1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2024 Intel Corporation 4 */ 5 6 #ifndef __I9XX_PLANE_REGS_H__ 7 #define __I9XX_PLANE_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 12 #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) 13 14 #define _DSPACNTR 0x70180 15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) 16 #define DISP_ENABLE REG_BIT(31) 17 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 18 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 19 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 20 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 21 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 22 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 23 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 24 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 25 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 26 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 27 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 28 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 29 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 30 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 31 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 32 #define DISP_STEREO_ENABLE REG_BIT(25) 33 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 34 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 35 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 36 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 37 #define DISP_LINE_DOUBLE REG_BIT(20) 38 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 39 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 40 #define DISP_ROTATE_180 REG_BIT(15) /* i965+ */ 41 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */ 42 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 43 #define DISP_TILED REG_BIT(10) /* i965+ */ 44 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 45 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 46 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) /* pre-g4x plane B/C */ 47 48 #define _DSPAADDR 0x70184 /* pre-i965 */ 49 #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) 50 51 #define _DSPALINOFF 0x70184 /* i965+ */ 52 #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) 53 54 #define _DSPASTRIDE 0x70188 55 #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) 56 57 #define _DSPAPOS 0x7018C /* pre-g4x */ 58 #define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) 59 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 60 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 61 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 62 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 63 64 #define _DSPASIZE 0x70190 /* pre-g4x */ 65 #define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) 66 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 67 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 68 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 69 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 70 71 #define _DSPASURF 0x7019C /* i965+ */ 72 #define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) 73 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 74 75 #define _DSPATILEOFF 0x701A4 /* i965+ */ 76 #define DSPTILEOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) 77 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 78 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 79 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 80 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 81 82 #define _DSPAOFFSET 0x701A4 /* hsw+ */ 83 #define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) 84 85 #define _DSPASURFLIVE 0x701AC /* g4x+ */ 86 #define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) 87 88 #define _DSPAGAMC 0x701E0 /* pre-g4x */ 89 #define DSPGAMC(dev_priv, plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 90 91 /* CHV pipe B primary plane */ 92 #define _PRIMPOS_A 0x60a08 93 #define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) 94 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 95 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 96 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 97 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 98 99 #define _PRIMSIZE_A 0x60a0c 100 #define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) 101 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 102 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 103 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 104 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 105 106 #define _PRIMCNSTALPHA_A 0x60a10 107 #define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) 108 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 109 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 110 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 111 112 #endif /* __I9XX_PLANE_REGS_H__ */ 113