1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2024 Intel Corporation */ 3 4 #ifndef _INTEL_THC_DMA_H_ 5 #define _INTEL_THC_DMA_H_ 6 7 #include <linux/bits.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/sizes.h> 10 #include <linux/time64.h> 11 #include <linux/types.h> 12 13 #define THC_POINTER_MASK GENMASK(6, 0) 14 #define THC_POINTER_WRAPAROUND 0x80 15 #define THC_WRAPAROUND_VALUE_ODD 0x10 16 #define THC_WRAPAROUND_VALUE_EVEN 0x90 17 #define THC_MIN_BYTES_PER_SG_LIST_ENTRY SZ_4K 18 19 #define THC_DEFAULT_RXDMA_POLLING_US_INTERVAL 100 20 #define THC_DEFAULT_RXDMA_POLLING_US_TIMEOUT (10 * USEC_PER_MSEC) 21 22 /* 23 * THC needs 1KB aligned address, dest_addr is 54 bits, not 64, 24 * so don't need to send the lower 10-bits of address. 25 */ 26 #define THC_ADDRESS_SHIFT 10 27 28 /** 29 * THC DMA channels: 30 * @THC_RXDMA1: Legacy channel, reserved for raw data reading 31 * @THC_RXDMA2: DMA to read HID data from touch device 32 * @THC_TXDMA: DMA to write to touch device 33 * @THC_SWDMA: SW triggered DMA to write and read from touch device 34 */ 35 enum thc_dma_channel { 36 THC_RXDMA1 = 0, 37 THC_RXDMA2 = 1, 38 THC_TXDMA = 2, 39 THC_SWDMA = 3, 40 MAX_THC_DMA_CHANNEL 41 }; 42 43 /** 44 * THC DMA Physical Memory Descriptor (PRD) 45 * @dest_addr: Bit[53:0], destination address in system memory 46 * @int_on_completion: Bit[63], if set, thc will trigger interrupt to driver 47 * @len: Bit[87:64], length of this entry 48 * @end_of_prd: Bit[88], if set, this entry is last one of current PRD table 49 * @hw_status: Bit[90:89], hardware status bits 50 */ 51 struct thc_prd_entry { 52 u64 dest_addr : 54; 53 u64 reserved1 : 9; 54 u64 int_on_completion : 1; 55 u64 len : 24; 56 u64 end_of_prd : 1; 57 u64 hw_status : 2; 58 u64 reserved2 : 37; 59 }; 60 61 /* 62 * Max OS memory fragmentation will be at a 4KB boundary, thus to address 1MB 63 * of virtually contiguous memory 256 PRD entries are required for a single 64 * PRD Table. SW writes the number of PRD Entries for each PRD table in the 65 * THC_M_PRT_RPRD_CNTRL.PTEC register field. The PRD entry's length must be 66 * multiple of 4KB except for the last entry in a PRD table. 67 * This is the max possible number of etries supported by HW, in practise we 68 * there will be less entries in each prd table(the actual number will be 69 * given by scatter-gather list allocation). 70 */ 71 #define PRD_ENTRIES_NUM 16 72 73 /* 74 * Number of PRD tables equals to number of data buffers. 75 * The max number of PRD tables supported by the HW is 128, 76 * but we allocate only 16. 77 */ 78 #define PRD_TABLES_NUM 16 79 80 /* THC DMA Physical Memory Descriptor Table */ 81 struct thc_prd_table { 82 struct thc_prd_entry entries[PRD_ENTRIES_NUM]; 83 }; 84 85 #define PRD_TABLE_SIZE sizeof(struct thc_prd_table) 86 87 /** 88 * struct thc_dma_configuration - THC DMA configure 89 * @dma_channel: DMA channel for current DMA configuration 90 * @prd_tbls_dma_handle: DMA buffer handle 91 * @dir: Direction of DMA for this config 92 * @prd_tbls: PRD tables for current DMA 93 * @sgls: Array of pointers to scatter-gather lists 94 * @sgls_nent_pages: Number of pages per scatter-gather list 95 * @sgls_nent: Actual number of entries per scatter-gather list 96 * @prd_tbl_num: Actual number of PRD tables 97 * @max_packet_size: Size of the buffer needed for 1 DMA message (1 PRD table) 98 * @prd_base_addr_high: High 32bits memory address where stores PRD table 99 * @prd_base_addr_low: Low 32bits memory address where stores PRD table 100 * @prd_cntrl: PRD control register value 101 * @dma_cntrl: DMA control register value 102 */ 103 struct thc_dma_configuration { 104 enum thc_dma_channel dma_channel; 105 dma_addr_t prd_tbls_dma_handle; 106 enum dma_data_direction dir; 107 bool is_enabled; 108 109 struct thc_prd_table *prd_tbls; 110 struct scatterlist *sgls[PRD_TABLES_NUM]; 111 u8 sgls_nent_pages[PRD_TABLES_NUM]; 112 u8 sgls_nent[PRD_TABLES_NUM]; 113 u8 prd_tbl_num; 114 115 size_t max_packet_size; 116 u32 prd_base_addr_high; 117 u32 prd_base_addr_low; 118 u32 prd_cntrl; 119 u32 dma_cntrl; 120 }; 121 122 /** 123 * struct thc_dma_context - THC DMA context 124 * @thc_dma_configuration: Array of all THC Channel configures 125 * @use_write_interrupts: Indicate TxDMA using interrupt or polling 126 * @rx_max_size_en: Temp flag to indicate THC I2C Rx max input size control feature 127 * enabled or not, only be used during SWDMA operation. 128 * @rx_int_delay_en: Temp flag to indicate THC I2C Rx interrupt delay feature 129 * enabled or not, only be used during SWDMA operation. 130 */ 131 struct thc_dma_context { 132 struct thc_dma_configuration dma_config[MAX_THC_DMA_CHANNEL]; 133 u8 use_write_interrupts; 134 135 bool rx_max_size_en; 136 bool rx_int_delay_en; 137 }; 138 139 struct thc_device; 140 141 int thc_dma_set_max_packet_sizes(struct thc_device *dev, 142 size_t mps_read1, size_t mps_read2, 143 size_t mps_write, size_t mps_swdma); 144 int thc_dma_allocate(struct thc_device *dev); 145 int thc_dma_configure(struct thc_device *dev); 146 void thc_dma_unconfigure(struct thc_device *dev); 147 void thc_dma_release(struct thc_device *dev); 148 int thc_rxdma_read(struct thc_device *dev, enum thc_dma_channel dma_channel, 149 void *read_buff, size_t *read_len, int *read_finished); 150 int thc_swdma_read(struct thc_device *dev, void *write_buff, size_t write_len, 151 u32 *prd_tbl_len, void *read_buff, size_t *read_len); 152 int thc_dma_write(struct thc_device *dev, void *buffer, size_t buf_len); 153 154 struct thc_dma_context *thc_dma_init(struct thc_device *dev); 155 156 #endif /* _INTEL_THC_DMA_H_ */ 157