1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 #include <linux/units.h> 28 29 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 32 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 33 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 34 extern const struct amdgpu_ip_block_version smu_v15_0_ip_block; 35 36 enum smu_temp_metric_type { 37 SMU_TEMP_METRIC_BASEBOARD, 38 SMU_TEMP_METRIC_GPUBOARD, 39 SMU_TEMP_METRIC_MAX, 40 }; 41 42 enum smu_event_type { 43 SMU_EVENT_RESET_COMPLETE = 0, 44 }; 45 46 struct amd_vce_state { 47 /* vce clocks */ 48 u32 evclk; 49 u32 ecclk; 50 /* gpu clocks */ 51 u32 sclk; 52 u32 mclk; 53 u8 clk_idx; 54 u8 pstate; 55 }; 56 57 58 enum amd_dpm_forced_level { 59 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 60 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 61 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 62 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 63 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 64 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 65 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 66 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 67 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 68 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 69 }; 70 71 enum amd_pm_state_type { 72 /* not used for dpm */ 73 POWER_STATE_TYPE_DEFAULT, 74 POWER_STATE_TYPE_POWERSAVE, 75 /* user selectable states */ 76 POWER_STATE_TYPE_BATTERY, 77 POWER_STATE_TYPE_BALANCED, 78 POWER_STATE_TYPE_PERFORMANCE, 79 /* internal states */ 80 POWER_STATE_TYPE_INTERNAL_UVD, 81 POWER_STATE_TYPE_INTERNAL_UVD_SD, 82 POWER_STATE_TYPE_INTERNAL_UVD_HD, 83 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 84 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 85 POWER_STATE_TYPE_INTERNAL_BOOT, 86 POWER_STATE_TYPE_INTERNAL_THERMAL, 87 POWER_STATE_TYPE_INTERNAL_ACPI, 88 POWER_STATE_TYPE_INTERNAL_ULV, 89 POWER_STATE_TYPE_INTERNAL_3DPERF, 90 }; 91 92 #define AMD_MAX_VCE_LEVELS 6 93 94 enum amd_vce_level { 95 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 96 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 97 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 98 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 99 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 100 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 101 }; 102 103 enum amd_fan_ctrl_mode { 104 AMD_FAN_CTRL_NONE = 0, 105 AMD_FAN_CTRL_MANUAL = 1, 106 AMD_FAN_CTRL_AUTO = 2, 107 }; 108 109 enum pp_clock_type { 110 PP_SCLK, 111 PP_MCLK, 112 PP_PCIE, 113 PP_SOCCLK, 114 PP_FCLK, 115 PP_DCEFCLK, 116 PP_VCLK, 117 PP_VCLK1, 118 PP_DCLK, 119 PP_DCLK1, 120 PP_ISPICLK, 121 PP_ISPXCLK, 122 OD_SCLK, 123 OD_MCLK, 124 OD_FCLK, 125 OD_VDDC_CURVE, 126 OD_RANGE, 127 OD_VDDGFX_OFFSET, 128 OD_CCLK, 129 OD_FAN_CURVE, 130 OD_ACOUSTIC_LIMIT, 131 OD_ACOUSTIC_TARGET, 132 OD_FAN_TARGET_TEMPERATURE, 133 OD_FAN_MINIMUM_PWM, 134 OD_FAN_ZERO_RPM_ENABLE, 135 OD_FAN_ZERO_RPM_STOP_TEMP, 136 }; 137 138 enum amd_pp_sensors { 139 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 140 AMDGPU_PP_SENSOR_CPU_CLK, 141 AMDGPU_PP_SENSOR_VDDNB, 142 AMDGPU_PP_SENSOR_VDDGFX, 143 AMDGPU_PP_SENSOR_UVD_VCLK, 144 AMDGPU_PP_SENSOR_UVD_DCLK, 145 AMDGPU_PP_SENSOR_VCE_ECCLK, 146 AMDGPU_PP_SENSOR_GPU_LOAD, 147 AMDGPU_PP_SENSOR_MEM_LOAD, 148 AMDGPU_PP_SENSOR_GFX_MCLK, 149 AMDGPU_PP_SENSOR_GPU_TEMP, 150 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 151 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 152 AMDGPU_PP_SENSOR_MEM_TEMP, 153 AMDGPU_PP_SENSOR_VCE_POWER, 154 AMDGPU_PP_SENSOR_UVD_POWER, 155 AMDGPU_PP_SENSOR_GPU_AVG_POWER, /* milliwatts */ 156 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, /* milliwatts */ 157 AMDGPU_PP_SENSOR_SS_APU_SHARE, 158 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 159 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 160 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 161 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 162 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 163 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 164 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 165 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 166 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 167 AMDGPU_PP_SENSOR_VCN_LOAD, 168 AMDGPU_PP_SENSOR_VDDBOARD, 169 AMDGPU_PP_SENSOR_NODEPOWERLIMIT, 170 AMDGPU_PP_SENSOR_NODEPOWER, 171 AMDGPU_PP_SENSOR_GPPTRESIDENCY, 172 AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, 173 AMDGPU_PP_SENSOR_UBB_POWER, 174 AMDGPU_PP_SENSOR_UBB_POWER_LIMIT, 175 AMDGPU_PP_SENSOR_NPMSTATUS, 176 }; 177 178 /* 179 * NPM sysfs capability bitmap: two bits per field, R then W. 180 * 00 = unsupported, 01 = read-only, 1x = writable (or RW). 181 */ 182 enum amdgpu_npm_cap_field { 183 AMDGPU_NPM_CAP_CUR_NODE_POWER_LIMIT, 184 AMDGPU_NPM_CAP_NODE_POWER, 185 AMDGPU_NPM_CAP_GLOBAL_PPT_RESID, 186 AMDGPU_NPM_CAP_MAX_NODE_POWER_LIMIT, 187 AMDGPU_NPM_CAP_NPM_STATUS, 188 }; 189 190 #define AMDGPU_NPM_CAP_R(field) BIT_ULL((field) * 2) 191 #define AMDGPU_NPM_CAP_W(field) BIT_ULL((field) * 2 + 1) 192 193 enum amd_pp_task { 194 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 195 AMD_PP_TASK_ENABLE_USER_STATE, 196 AMD_PP_TASK_READJUST_POWER_STATE, 197 AMD_PP_TASK_COMPLETE_INIT, 198 AMD_PP_TASK_MAX 199 }; 200 201 enum PP_SMC_POWER_PROFILE { 202 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 203 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 204 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 205 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 206 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 207 PP_SMC_POWER_PROFILE_VR = 0x4, 208 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 209 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 210 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 211 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 212 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 213 PP_SMC_POWER_PROFILE_COUNT, 214 }; 215 216 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 217 218 219 220 enum { 221 PP_GROUP_UNKNOWN = 0, 222 PP_GROUP_GFX = 1, 223 PP_GROUP_SYS, 224 PP_GROUP_MAX 225 }; 226 227 enum PP_OD_DPM_TABLE_COMMAND { 228 PP_OD_EDIT_SCLK_VDDC_TABLE, 229 PP_OD_EDIT_MCLK_VDDC_TABLE, 230 PP_OD_EDIT_FCLK_TABLE, 231 PP_OD_EDIT_CCLK_VDDC_TABLE, 232 PP_OD_EDIT_VDDC_CURVE, 233 PP_OD_RESTORE_DEFAULT_TABLE, 234 PP_OD_COMMIT_DPM_TABLE, 235 PP_OD_EDIT_VDDGFX_OFFSET, 236 PP_OD_EDIT_FAN_CURVE, 237 PP_OD_EDIT_ACOUSTIC_LIMIT, 238 PP_OD_EDIT_ACOUSTIC_TARGET, 239 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 240 PP_OD_EDIT_FAN_MINIMUM_PWM, 241 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 242 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 243 }; 244 245 struct pp_states_info { 246 uint32_t nums; 247 uint32_t states[16]; 248 }; 249 250 enum PP_HWMON_TEMP { 251 PP_TEMP_EDGE = 0, 252 PP_TEMP_JUNCTION, 253 PP_TEMP_MEM, 254 PP_TEMP_MAX 255 }; 256 257 enum pp_mp1_state { 258 PP_MP1_STATE_NONE, 259 PP_MP1_STATE_SHUTDOWN, 260 PP_MP1_STATE_UNLOAD, 261 PP_MP1_STATE_RESET, 262 PP_MP1_STATE_FLR, 263 }; 264 265 enum pp_df_cstate { 266 DF_CSTATE_DISALLOW = 0, 267 DF_CSTATE_ALLOW, 268 }; 269 270 /** 271 * DOC: amdgpu_pp_power 272 * 273 * APU power is managed to system-level requirements through the PPT 274 * (package power tracking) feature. PPT is intended to limit power to the 275 * requirements of the power source and could be dynamically updated to 276 * maximize APU performance within the system power budget. 277 * 278 * Two types of power measurement can be requested, where supported, with 279 * :c:type:`enum pp_power_type <pp_power_type>`. 280 */ 281 282 /** 283 * enum pp_power_limit_level - Used to query the power limits 284 * 285 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 286 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 287 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 288 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 289 */ 290 enum pp_power_limit_level { 291 PP_PWR_LIMIT_MIN = -1, 292 PP_PWR_LIMIT_CURRENT, 293 PP_PWR_LIMIT_DEFAULT, 294 PP_PWR_LIMIT_MAX, 295 }; 296 297 /** 298 * enum pp_power_type - Used to specify the type of the requested power 299 * 300 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 301 * moving average of APU power (default ~5000 ms). 302 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 303 * where supported. 304 */ 305 enum pp_power_type { 306 PP_PWR_TYPE_SUSTAINED, 307 PP_PWR_TYPE_FAST, 308 }; 309 310 enum pp_xgmi_plpd_mode { 311 XGMI_PLPD_NONE = -1, 312 XGMI_PLPD_DISALLOW, 313 XGMI_PLPD_DEFAULT, 314 XGMI_PLPD_OPTIMIZED, 315 XGMI_PLPD_COUNT, 316 }; 317 318 enum pp_pm_policy { 319 PP_PM_POLICY_NONE = -1, 320 PP_PM_POLICY_SOC_PSTATE = 0, 321 PP_PM_POLICY_XGMI_PLPD, 322 PP_PM_POLICY_NUM, 323 }; 324 325 enum pp_policy_soc_pstate { 326 SOC_PSTATE_DEFAULT = 0, 327 SOC_PSTATE_0, 328 SOC_PSTATE_1, 329 SOC_PSTATE_2, 330 SOC_PSTAT_COUNT, 331 }; 332 333 #define PP_POLICY_MAX_LEVELS 5 334 335 #define PP_GROUP_MASK 0xF0000000 336 #define PP_GROUP_SHIFT 28 337 338 #define PP_BLOCK_MASK 0x0FFFFF00 339 #define PP_BLOCK_SHIFT 8 340 341 #define PP_BLOCK_GFX_CG 0x01 342 #define PP_BLOCK_GFX_MG 0x02 343 #define PP_BLOCK_GFX_3D 0x04 344 #define PP_BLOCK_GFX_RLC 0x08 345 #define PP_BLOCK_GFX_CP 0x10 346 #define PP_BLOCK_SYS_BIF 0x01 347 #define PP_BLOCK_SYS_MC 0x02 348 #define PP_BLOCK_SYS_ROM 0x04 349 #define PP_BLOCK_SYS_DRM 0x08 350 #define PP_BLOCK_SYS_HDP 0x10 351 #define PP_BLOCK_SYS_SDMA 0x20 352 353 #define PP_STATE_MASK 0x0000000F 354 #define PP_STATE_SHIFT 0 355 #define PP_STATE_SUPPORT_MASK 0x000000F0 356 #define PP_STATE_SUPPORT_SHIFT 0 357 358 #define PP_STATE_CG 0x01 359 #define PP_STATE_LS 0x02 360 #define PP_STATE_DS 0x04 361 #define PP_STATE_SD 0x08 362 #define PP_STATE_SUPPORT_CG 0x10 363 #define PP_STATE_SUPPORT_LS 0x20 364 #define PP_STATE_SUPPORT_DS 0x40 365 #define PP_STATE_SUPPORT_SD 0x80 366 367 #define PP_CG_MSG_ID(group, block, support, state) \ 368 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 369 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 370 371 #define XGMI_MODE_PSTATE_D3 0 372 #define XGMI_MODE_PSTATE_D0 1 373 374 #define NUM_HBM_INSTANCES 4 375 #define NUM_XGMI_LINKS 8 376 #define MAX_GFX_CLKS 8 377 #define MAX_CLKS 4 378 #define NUM_VCN 4 379 #define NUM_JPEG_ENG 32 380 #define NUM_JPEG_ENG_V1 40 381 #define MAX_XCC 8 382 #define NUM_XCP 8 383 struct seq_file; 384 enum amd_pp_clock_type; 385 struct amd_pp_simple_clock_info; 386 struct amd_pp_display_configuration; 387 struct amd_pp_clock_info; 388 struct pp_display_clock_request; 389 struct pp_clock_levels_with_voltage; 390 struct pp_clock_levels_with_latency; 391 struct amd_pp_clocks; 392 struct pp_smu_wm_range_sets; 393 struct pp_smu_nv_clock_table; 394 struct dpm_clocks; 395 396 struct amdgpu_xcp_metrics { 397 /* Utilization Instantaneous (%) */ 398 uint32_t gfx_busy_inst[MAX_XCC]; 399 uint16_t jpeg_busy[NUM_JPEG_ENG]; 400 uint16_t vcn_busy[NUM_VCN]; 401 /* Utilization Accumulated (%) */ 402 uint64_t gfx_busy_acc[MAX_XCC]; 403 }; 404 405 struct amdgpu_xcp_metrics_v1_1 { 406 /* Utilization Instantaneous (%) */ 407 uint32_t gfx_busy_inst[MAX_XCC]; 408 uint16_t jpeg_busy[NUM_JPEG_ENG]; 409 uint16_t vcn_busy[NUM_VCN]; 410 /* Utilization Accumulated (%) */ 411 uint64_t gfx_busy_acc[MAX_XCC]; 412 /* Total App Clock Counter Accumulated */ 413 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 414 }; 415 416 struct amdgpu_xcp_metrics_v1_2 { 417 /* Utilization Instantaneous (%) */ 418 uint32_t gfx_busy_inst[MAX_XCC]; 419 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 420 uint16_t vcn_busy[NUM_VCN]; 421 /* Utilization Accumulated (%) */ 422 uint64_t gfx_busy_acc[MAX_XCC]; 423 /* Total App Clock Counter Accumulated */ 424 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 425 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 426 uint64_t gfx_low_utilization_acc[MAX_XCC]; 427 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 428 }; 429 430 struct amd_pm_funcs { 431 /* export for dpm on ci and si */ 432 int (*pre_set_power_state)(void *handle); 433 int (*set_power_state)(void *handle); 434 void (*post_set_power_state)(void *handle); 435 void (*display_configuration_changed)(void *handle); 436 void (*print_power_state)(void *handle, void *ps); 437 bool (*vblank_too_short)(void *handle); 438 void (*notify_ac_dc)(void *handle); 439 int (*check_state_equal)(void *handle, 440 void *cps, 441 void *rps, 442 bool *equal); 443 /* export for sysfs */ 444 int (*set_fan_control_mode)(void *handle, u32 mode); 445 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 446 int (*set_fan_speed_pwm)(void *handle, u32 speed); 447 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 448 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 449 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 450 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 451 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 452 int (*get_sclk_od)(void *handle); 453 int (*set_sclk_od)(void *handle, uint32_t value); 454 int (*get_mclk_od)(void *handle); 455 int (*set_mclk_od)(void *handle, uint32_t value); 456 int (*read_sensor)(void *handle, int idx, void *value, int *size); 457 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 458 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 459 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 460 enum amd_pm_state_type (*get_current_power_state)(void *handle); 461 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 462 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 463 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 464 int (*get_pp_table)(void *handle, char **table); 465 int (*set_pp_table)(void *handle, const char *buf, size_t size); 466 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 467 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 468 int (*pause_power_profile)(void *handle, bool pause); 469 /* export to amdgpu */ 470 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 471 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 472 enum amd_pm_state_type *user_state); 473 int (*load_firmware)(void *handle); 474 int (*wait_for_fw_loading_complete)(void *handle); 475 int (*set_powergating_by_smu)(void *handle, 476 uint32_t block_type, 477 bool gate, 478 int inst); 479 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 480 int (*set_power_limit)(void *handle, uint32_t limit_type, uint32_t n); 481 int (*get_power_limit)(void *handle, uint32_t *limit, 482 enum pp_power_limit_level pp_limit_level, 483 enum pp_power_type power_type); 484 int (*get_power_profile_mode)(void *handle, char *buf); 485 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 486 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 487 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 488 long *input, uint32_t size); 489 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 490 int (*smu_i2c_bus_access)(void *handle, bool acquire); 491 int (*gfx_state_change_set)(void *handle, uint32_t state); 492 /* export to DC */ 493 u32 (*get_sclk)(void *handle, bool low); 494 u32 (*get_mclk)(void *handle, bool low); 495 int (*display_configuration_change)(void *handle, 496 const struct amd_pp_display_configuration *input); 497 int (*get_current_clocks)(void *handle, 498 struct amd_pp_clock_info *clocks); 499 int (*get_clock_by_type)(void *handle, 500 enum amd_pp_clock_type type, 501 struct amd_pp_clocks *clocks); 502 int (*get_clock_by_type_with_latency)(void *handle, 503 enum amd_pp_clock_type type, 504 struct pp_clock_levels_with_latency *clocks); 505 int (*get_clock_by_type_with_voltage)(void *handle, 506 enum amd_pp_clock_type type, 507 struct pp_clock_levels_with_voltage *clocks); 508 int (*set_watermarks_for_clocks_ranges)(void *handle, 509 void *clock_ranges); 510 int (*display_clock_voltage_request)(void *handle, 511 struct pp_display_clock_request *clock); 512 int (*get_display_mode_validation_clocks)(void *handle, 513 struct amd_pp_simple_clock_info *clocks); 514 int (*notify_smu_enable_pwe)(void *handle); 515 int (*enable_mgpu_fan_boost)(void *handle); 516 int (*set_active_display_count)(void *handle, uint32_t count); 517 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 518 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 519 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 520 int (*get_asic_baco_capability)(void *handle); 521 int (*get_asic_baco_state)(void *handle, int *state); 522 int (*set_asic_baco_state)(void *handle, int state); 523 int (*get_ppfeature_status)(void *handle, char *buf); 524 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 525 int (*asic_reset_mode_2)(void *handle); 526 int (*asic_reset_enable_gfx_features)(void *handle); 527 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 528 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 529 ssize_t (*get_gpu_metrics)(void *handle, void **table); 530 ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table); 531 bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type); 532 u64 (*get_npm_cap)(void *handle); 533 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table); 534 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 535 int (*set_watermarks_for_clock_ranges)(void *handle, 536 struct pp_smu_wm_range_sets *ranges); 537 int (*display_disable_memory_clock_switch)(void *handle, 538 bool disable_memory_clock_switch); 539 int (*get_max_sustainable_clocks_by_dc)(void *handle, 540 struct pp_smu_nv_clock_table *max_clocks); 541 int (*get_uclk_dpm_states)(void *handle, 542 unsigned int *clock_values_in_khz, 543 unsigned int *num_states); 544 int (*get_dpm_clock_table)(void *handle, 545 struct dpm_clocks *clock_table); 546 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 547 void (*pm_compute_clocks)(void *handle); 548 int (*notify_rlc_state)(void *handle, bool en); 549 }; 550 551 struct metrics_table_header { 552 uint16_t structure_size; 553 uint8_t format_revision; 554 uint8_t content_revision; 555 }; 556 557 enum amdgpu_metrics_attr_id { 558 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HOTSPOT, 559 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MEM, 560 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_VRSOC, 561 AMDGPU_METRICS_ATTR_ID_CURR_SOCKET_POWER, 562 AMDGPU_METRICS_ATTR_ID_AVERAGE_GFX_ACTIVITY, 563 AMDGPU_METRICS_ATTR_ID_AVERAGE_UMC_ACTIVITY, 564 AMDGPU_METRICS_ATTR_ID_MEM_MAX_BANDWIDTH, 565 AMDGPU_METRICS_ATTR_ID_ENERGY_ACCUMULATOR, 566 AMDGPU_METRICS_ATTR_ID_SYSTEM_CLOCK_COUNTER, 567 AMDGPU_METRICS_ATTR_ID_ACCUMULATION_COUNTER, 568 AMDGPU_METRICS_ATTR_ID_PROCHOT_RESIDENCY_ACC, 569 AMDGPU_METRICS_ATTR_ID_PPT_RESIDENCY_ACC, 570 AMDGPU_METRICS_ATTR_ID_SOCKET_THM_RESIDENCY_ACC, 571 AMDGPU_METRICS_ATTR_ID_VR_THM_RESIDENCY_ACC, 572 AMDGPU_METRICS_ATTR_ID_HBM_THM_RESIDENCY_ACC, 573 AMDGPU_METRICS_ATTR_ID_GFXCLK_LOCK_STATUS, 574 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_WIDTH, 575 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_SPEED, 576 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_WIDTH, 577 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_SPEED, 578 AMDGPU_METRICS_ATTR_ID_GFX_ACTIVITY_ACC, 579 AMDGPU_METRICS_ATTR_ID_MEM_ACTIVITY_ACC, 580 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_ACC, 581 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_INST, 582 AMDGPU_METRICS_ATTR_ID_PCIE_L0_TO_RECOV_COUNT_ACC, 583 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_COUNT_ACC, 584 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_ROVER_COUNT_ACC, 585 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_SENT_COUNT_ACC, 586 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_RCVD_COUNT_ACC, 587 AMDGPU_METRICS_ATTR_ID_XGMI_READ_DATA_ACC, 588 AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_DATA_ACC, 589 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_STATUS, 590 AMDGPU_METRICS_ATTR_ID_FIRMWARE_TIMESTAMP, 591 AMDGPU_METRICS_ATTR_ID_CURRENT_GFXCLK, 592 AMDGPU_METRICS_ATTR_ID_CURRENT_SOCCLK, 593 AMDGPU_METRICS_ATTR_ID_CURRENT_VCLK0, 594 AMDGPU_METRICS_ATTR_ID_CURRENT_DCLK0, 595 AMDGPU_METRICS_ATTR_ID_CURRENT_UCLK, 596 AMDGPU_METRICS_ATTR_ID_NUM_PARTITION, 597 AMDGPU_METRICS_ATTR_ID_PCIE_LC_PERF_OTHER_END_RECOVERY, 598 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_INST, 599 AMDGPU_METRICS_ATTR_ID_JPEG_BUSY, 600 AMDGPU_METRICS_ATTR_ID_VCN_BUSY, 601 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_ACC, 602 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_PPT_ACC, 603 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC, 604 AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, 605 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, 606 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HBM, 607 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MID, 608 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_AID, 609 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_XCD, 610 AMDGPU_METRICS_ATTR_ID_LABEL_VERSION, 611 AMDGPU_METRICS_ATTR_ID_NODE_ID, 612 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_RETIMER, 613 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC, 614 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC_2, 615 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_VDD18_VR, 616 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_B_VR, 617 AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_D_VR, 618 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_A, 619 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_C, 620 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X0, 621 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X1, 622 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_B, 623 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_D, 624 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_B, 625 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_D, 626 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_B, 627 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_D, 628 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_B, 629 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_D, 630 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_A, 631 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_C, 632 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_A, 633 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_C, 634 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_UCIE, 635 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAA, 636 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_A, 637 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_C, 638 AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075, 639 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA, 640 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FRONT, 641 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_BACK, 642 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM7, 643 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_IBC, 644 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_UFPGA, 645 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM1, 646 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_HSC, 647 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_2_3_HSC, 648 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_HSC, 649 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_6_7_HSC, 650 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_0V72_VR, 651 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_3V3_VR, 652 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR, 653 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR, 654 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_0V9_VR, 655 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_0V9_VR, 656 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_2_3_0V9_VR, 657 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_6_7_0V9_VR, 658 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR, 659 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR, 660 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC_HSC, 661 AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC, 662 AMDGPU_METRICS_ATTR_ID_MAX, 663 }; 664 665 enum amdgpu_metrics_attr_type { 666 AMDGPU_METRICS_TYPE_U8, 667 AMDGPU_METRICS_TYPE_S8, 668 AMDGPU_METRICS_TYPE_U16, 669 AMDGPU_METRICS_TYPE_S16, 670 AMDGPU_METRICS_TYPE_U32, 671 AMDGPU_METRICS_TYPE_S32, 672 AMDGPU_METRICS_TYPE_U64, 673 AMDGPU_METRICS_TYPE_S64, 674 AMDGPU_METRICS_TYPE_MAX, 675 }; 676 677 enum amdgpu_metrics_attr_unit { 678 /* None */ 679 AMDGPU_METRICS_UNIT_NONE, 680 /* MHz*/ 681 AMDGPU_METRICS_UNIT_CLOCK_1, 682 /* Degree Celsius*/ 683 AMDGPU_METRICS_UNIT_TEMP_1, 684 /* Watts*/ 685 AMDGPU_METRICS_UNIT_POWER_1, 686 /* In nanoseconds*/ 687 AMDGPU_METRICS_UNIT_TIME_1, 688 /* In 10 nanoseconds*/ 689 AMDGPU_METRICS_UNIT_TIME_2, 690 /* Speed in GT/s */ 691 AMDGPU_METRICS_UNIT_SPEED_1, 692 /* Speed in 0.1 GT/s */ 693 AMDGPU_METRICS_UNIT_SPEED_2, 694 /* Bandwidth GB/s */ 695 AMDGPU_METRICS_UNIT_BW_1, 696 /* Data in KB */ 697 AMDGPU_METRICS_UNIT_DATA_1, 698 /* Percentage */ 699 AMDGPU_METRICS_UNIT_PERCENT, 700 AMDGPU_METRICS_UNIT_MAX, 701 }; 702 703 #define AMDGPU_METRICS_ATTR_UNIT_MASK 0xFF000000 704 #define AMDGPU_METRICS_ATTR_UNIT_SHIFT 24 705 #define AMDGPU_METRICS_ATTR_TYPE_MASK 0x00F00000 706 #define AMDGPU_METRICS_ATTR_TYPE_SHIFT 20 707 #define AMDGPU_METRICS_ATTR_ID_MASK 0x000FFC00 708 #define AMDGPU_METRICS_ATTR_ID_SHIFT 10 709 #define AMDGPU_METRICS_ATTR_INST_MASK 0x000003FF 710 #define AMDGPU_METRICS_ATTR_INST_SHIFT 0 711 712 #define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \ 713 (((u64)(unit) << AMDGPU_METRICS_ATTR_UNIT_SHIFT) | \ 714 ((u64)(type) << AMDGPU_METRICS_ATTR_TYPE_SHIFT) | \ 715 ((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst)) 716 717 /* 718 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 719 * Use gpu_metrics_v1_1 or later instead. 720 */ 721 struct gpu_metrics_v1_0 { 722 struct metrics_table_header common_header; 723 724 /* Driver attached timestamp (in ns) */ 725 uint64_t system_clock_counter; 726 727 /* Temperature */ 728 uint16_t temperature_edge; 729 uint16_t temperature_hotspot; 730 uint16_t temperature_mem; 731 uint16_t temperature_vrgfx; 732 uint16_t temperature_vrsoc; 733 uint16_t temperature_vrmem; 734 735 /* Utilization */ 736 uint16_t average_gfx_activity; 737 uint16_t average_umc_activity; // memory controller 738 uint16_t average_mm_activity; // UVD or VCN 739 740 /* Power/Energy */ 741 uint16_t average_socket_power; 742 uint32_t energy_accumulator; 743 744 /* Average clocks */ 745 uint16_t average_gfxclk_frequency; 746 uint16_t average_socclk_frequency; 747 uint16_t average_uclk_frequency; 748 uint16_t average_vclk0_frequency; 749 uint16_t average_dclk0_frequency; 750 uint16_t average_vclk1_frequency; 751 uint16_t average_dclk1_frequency; 752 753 /* Current clocks */ 754 uint16_t current_gfxclk; 755 uint16_t current_socclk; 756 uint16_t current_uclk; 757 uint16_t current_vclk0; 758 uint16_t current_dclk0; 759 uint16_t current_vclk1; 760 uint16_t current_dclk1; 761 762 /* Throttle status */ 763 uint32_t throttle_status; 764 765 /* Fans */ 766 uint16_t current_fan_speed; 767 768 /* Link width/speed */ 769 uint8_t pcie_link_width; 770 uint8_t pcie_link_speed; // in 0.1 GT/s 771 }; 772 773 struct gpu_metrics_v1_1 { 774 struct metrics_table_header common_header; 775 776 /* Temperature */ 777 uint16_t temperature_edge; 778 uint16_t temperature_hotspot; 779 uint16_t temperature_mem; 780 uint16_t temperature_vrgfx; 781 uint16_t temperature_vrsoc; 782 uint16_t temperature_vrmem; 783 784 /* Utilization */ 785 uint16_t average_gfx_activity; 786 uint16_t average_umc_activity; // memory controller 787 uint16_t average_mm_activity; // UVD or VCN 788 789 /* Power/Energy */ 790 uint16_t average_socket_power; 791 uint64_t energy_accumulator; 792 793 /* Driver attached timestamp (in ns) */ 794 uint64_t system_clock_counter; 795 796 /* Average clocks */ 797 uint16_t average_gfxclk_frequency; 798 uint16_t average_socclk_frequency; 799 uint16_t average_uclk_frequency; 800 uint16_t average_vclk0_frequency; 801 uint16_t average_dclk0_frequency; 802 uint16_t average_vclk1_frequency; 803 uint16_t average_dclk1_frequency; 804 805 /* Current clocks */ 806 uint16_t current_gfxclk; 807 uint16_t current_socclk; 808 uint16_t current_uclk; 809 uint16_t current_vclk0; 810 uint16_t current_dclk0; 811 uint16_t current_vclk1; 812 uint16_t current_dclk1; 813 814 /* Throttle status */ 815 uint32_t throttle_status; 816 817 /* Fans */ 818 uint16_t current_fan_speed; 819 820 /* Link width/speed */ 821 uint16_t pcie_link_width; 822 uint16_t pcie_link_speed; // in 0.1 GT/s 823 824 uint16_t padding; 825 826 uint32_t gfx_activity_acc; 827 uint32_t mem_activity_acc; 828 829 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 830 }; 831 832 struct gpu_metrics_v1_2 { 833 struct metrics_table_header common_header; 834 835 /* Temperature */ 836 uint16_t temperature_edge; 837 uint16_t temperature_hotspot; 838 uint16_t temperature_mem; 839 uint16_t temperature_vrgfx; 840 uint16_t temperature_vrsoc; 841 uint16_t temperature_vrmem; 842 843 /* Utilization */ 844 uint16_t average_gfx_activity; 845 uint16_t average_umc_activity; // memory controller 846 uint16_t average_mm_activity; // UVD or VCN 847 848 /* Power/Energy */ 849 uint16_t average_socket_power; 850 uint64_t energy_accumulator; 851 852 /* Driver attached timestamp (in ns) */ 853 uint64_t system_clock_counter; 854 855 /* Average clocks */ 856 uint16_t average_gfxclk_frequency; 857 uint16_t average_socclk_frequency; 858 uint16_t average_uclk_frequency; 859 uint16_t average_vclk0_frequency; 860 uint16_t average_dclk0_frequency; 861 uint16_t average_vclk1_frequency; 862 uint16_t average_dclk1_frequency; 863 864 /* Current clocks */ 865 uint16_t current_gfxclk; 866 uint16_t current_socclk; 867 uint16_t current_uclk; 868 uint16_t current_vclk0; 869 uint16_t current_dclk0; 870 uint16_t current_vclk1; 871 uint16_t current_dclk1; 872 873 /* Throttle status (ASIC dependent) */ 874 uint32_t throttle_status; 875 876 /* Fans */ 877 uint16_t current_fan_speed; 878 879 /* Link width/speed */ 880 uint16_t pcie_link_width; 881 uint16_t pcie_link_speed; // in 0.1 GT/s 882 883 uint16_t padding; 884 885 uint32_t gfx_activity_acc; 886 uint32_t mem_activity_acc; 887 888 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 889 890 /* PMFW attached timestamp (10ns resolution) */ 891 uint64_t firmware_timestamp; 892 }; 893 894 struct gpu_metrics_v1_3 { 895 struct metrics_table_header common_header; 896 897 /* Temperature */ 898 uint16_t temperature_edge; 899 uint16_t temperature_hotspot; 900 uint16_t temperature_mem; 901 uint16_t temperature_vrgfx; 902 uint16_t temperature_vrsoc; 903 uint16_t temperature_vrmem; 904 905 /* Utilization */ 906 uint16_t average_gfx_activity; 907 uint16_t average_umc_activity; // memory controller 908 uint16_t average_mm_activity; // UVD or VCN 909 910 /* Power/Energy */ 911 uint16_t average_socket_power; 912 uint64_t energy_accumulator; 913 914 /* Driver attached timestamp (in ns) */ 915 uint64_t system_clock_counter; 916 917 /* Average clocks */ 918 uint16_t average_gfxclk_frequency; 919 uint16_t average_socclk_frequency; 920 uint16_t average_uclk_frequency; 921 uint16_t average_vclk0_frequency; 922 uint16_t average_dclk0_frequency; 923 uint16_t average_vclk1_frequency; 924 uint16_t average_dclk1_frequency; 925 926 /* Current clocks */ 927 uint16_t current_gfxclk; 928 uint16_t current_socclk; 929 uint16_t current_uclk; 930 uint16_t current_vclk0; 931 uint16_t current_dclk0; 932 uint16_t current_vclk1; 933 uint16_t current_dclk1; 934 935 /* Throttle status */ 936 uint32_t throttle_status; 937 938 /* Fans */ 939 uint16_t current_fan_speed; 940 941 /* Link width/speed */ 942 uint16_t pcie_link_width; 943 uint16_t pcie_link_speed; // in 0.1 GT/s 944 945 uint16_t padding; 946 947 uint32_t gfx_activity_acc; 948 uint32_t mem_activity_acc; 949 950 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 951 952 /* PMFW attached timestamp (10ns resolution) */ 953 uint64_t firmware_timestamp; 954 955 /* Voltage (mV) */ 956 uint16_t voltage_soc; 957 uint16_t voltage_gfx; 958 uint16_t voltage_mem; 959 960 uint16_t padding1; 961 962 /* Throttle status (ASIC independent) */ 963 uint64_t indep_throttle_status; 964 }; 965 966 struct gpu_metrics_v1_4 { 967 struct metrics_table_header common_header; 968 969 /* Temperature (Celsius) */ 970 uint16_t temperature_hotspot; 971 uint16_t temperature_mem; 972 uint16_t temperature_vrsoc; 973 974 /* Power (Watts) */ 975 uint16_t curr_socket_power; 976 977 /* Utilization (%) */ 978 uint16_t average_gfx_activity; 979 uint16_t average_umc_activity; // memory controller 980 uint16_t vcn_activity[NUM_VCN]; 981 982 /* Energy (15.259uJ (2^-16) units) */ 983 uint64_t energy_accumulator; 984 985 /* Driver attached timestamp (in ns) */ 986 uint64_t system_clock_counter; 987 988 /* Throttle status */ 989 uint32_t throttle_status; 990 991 /* Clock Lock Status. Each bit corresponds to clock instance */ 992 uint32_t gfxclk_lock_status; 993 994 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 995 uint16_t pcie_link_width; 996 uint16_t pcie_link_speed; 997 998 /* XGMI bus width and bitrate (in Gbps) */ 999 uint16_t xgmi_link_width; 1000 uint16_t xgmi_link_speed; 1001 1002 /* Utilization Accumulated (%) */ 1003 uint32_t gfx_activity_acc; 1004 uint32_t mem_activity_acc; 1005 1006 /*PCIE accumulated bandwidth (GB/sec) */ 1007 uint64_t pcie_bandwidth_acc; 1008 1009 /*PCIE instantaneous bandwidth (GB/sec) */ 1010 uint64_t pcie_bandwidth_inst; 1011 1012 /* PCIE L0 to recovery state transition accumulated count */ 1013 uint64_t pcie_l0_to_recov_count_acc; 1014 1015 /* PCIE replay accumulated count */ 1016 uint64_t pcie_replay_count_acc; 1017 1018 /* PCIE replay rollover accumulated count */ 1019 uint64_t pcie_replay_rover_count_acc; 1020 1021 /* XGMI accumulated data transfer size(KiloBytes) */ 1022 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1023 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1024 1025 /* PMFW attached timestamp (10ns resolution) */ 1026 uint64_t firmware_timestamp; 1027 1028 /* Current clocks (Mhz) */ 1029 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1030 uint16_t current_socclk[MAX_CLKS]; 1031 uint16_t current_vclk0[MAX_CLKS]; 1032 uint16_t current_dclk0[MAX_CLKS]; 1033 uint16_t current_uclk; 1034 1035 uint16_t padding; 1036 }; 1037 1038 struct gpu_metrics_v1_5 { 1039 struct metrics_table_header common_header; 1040 1041 /* Temperature (Celsius) */ 1042 uint16_t temperature_hotspot; 1043 uint16_t temperature_mem; 1044 uint16_t temperature_vrsoc; 1045 1046 /* Power (Watts) */ 1047 uint16_t curr_socket_power; 1048 1049 /* Utilization (%) */ 1050 uint16_t average_gfx_activity; 1051 uint16_t average_umc_activity; // memory controller 1052 uint16_t vcn_activity[NUM_VCN]; 1053 uint16_t jpeg_activity[NUM_JPEG_ENG]; 1054 1055 /* Energy (15.259uJ (2^-16) units) */ 1056 uint64_t energy_accumulator; 1057 1058 /* Driver attached timestamp (in ns) */ 1059 uint64_t system_clock_counter; 1060 1061 /* Throttle status */ 1062 uint32_t throttle_status; 1063 1064 /* Clock Lock Status. Each bit corresponds to clock instance */ 1065 uint32_t gfxclk_lock_status; 1066 1067 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1068 uint16_t pcie_link_width; 1069 uint16_t pcie_link_speed; 1070 1071 /* XGMI bus width and bitrate (in Gbps) */ 1072 uint16_t xgmi_link_width; 1073 uint16_t xgmi_link_speed; 1074 1075 /* Utilization Accumulated (%) */ 1076 uint32_t gfx_activity_acc; 1077 uint32_t mem_activity_acc; 1078 1079 /*PCIE accumulated bandwidth (GB/sec) */ 1080 uint64_t pcie_bandwidth_acc; 1081 1082 /*PCIE instantaneous bandwidth (GB/sec) */ 1083 uint64_t pcie_bandwidth_inst; 1084 1085 /* PCIE L0 to recovery state transition accumulated count */ 1086 uint64_t pcie_l0_to_recov_count_acc; 1087 1088 /* PCIE replay accumulated count */ 1089 uint64_t pcie_replay_count_acc; 1090 1091 /* PCIE replay rollover accumulated count */ 1092 uint64_t pcie_replay_rover_count_acc; 1093 1094 /* PCIE NAK sent accumulated count */ 1095 uint32_t pcie_nak_sent_count_acc; 1096 1097 /* PCIE NAK received accumulated count */ 1098 uint32_t pcie_nak_rcvd_count_acc; 1099 1100 /* XGMI accumulated data transfer size(KiloBytes) */ 1101 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1102 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1103 1104 /* PMFW attached timestamp (10ns resolution) */ 1105 uint64_t firmware_timestamp; 1106 1107 /* Current clocks (Mhz) */ 1108 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1109 uint16_t current_socclk[MAX_CLKS]; 1110 uint16_t current_vclk0[MAX_CLKS]; 1111 uint16_t current_dclk0[MAX_CLKS]; 1112 uint16_t current_uclk; 1113 1114 uint16_t padding; 1115 }; 1116 1117 struct gpu_metrics_v1_6 { 1118 struct metrics_table_header common_header; 1119 1120 /* Temperature (Celsius) */ 1121 uint16_t temperature_hotspot; 1122 uint16_t temperature_mem; 1123 uint16_t temperature_vrsoc; 1124 1125 /* Power (Watts) */ 1126 uint16_t curr_socket_power; 1127 1128 /* Utilization (%) */ 1129 uint16_t average_gfx_activity; 1130 uint16_t average_umc_activity; // memory controller 1131 1132 /* Energy (15.259uJ (2^-16) units) */ 1133 uint64_t energy_accumulator; 1134 1135 /* Driver attached timestamp (in ns) */ 1136 uint64_t system_clock_counter; 1137 1138 /* Accumulation cycle counter */ 1139 uint32_t accumulation_counter; 1140 1141 /* Accumulated throttler residencies */ 1142 uint32_t prochot_residency_acc; 1143 uint32_t ppt_residency_acc; 1144 uint32_t socket_thm_residency_acc; 1145 uint32_t vr_thm_residency_acc; 1146 uint32_t hbm_thm_residency_acc; 1147 1148 /* Clock Lock Status. Each bit corresponds to clock instance */ 1149 uint32_t gfxclk_lock_status; 1150 1151 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1152 uint16_t pcie_link_width; 1153 uint16_t pcie_link_speed; 1154 1155 /* XGMI bus width and bitrate (in Gbps) */ 1156 uint16_t xgmi_link_width; 1157 uint16_t xgmi_link_speed; 1158 1159 /* Utilization Accumulated (%) */ 1160 uint32_t gfx_activity_acc; 1161 uint32_t mem_activity_acc; 1162 1163 /*PCIE accumulated bandwidth (GB/sec) */ 1164 uint64_t pcie_bandwidth_acc; 1165 1166 /*PCIE instantaneous bandwidth (GB/sec) */ 1167 uint64_t pcie_bandwidth_inst; 1168 1169 /* PCIE L0 to recovery state transition accumulated count */ 1170 uint64_t pcie_l0_to_recov_count_acc; 1171 1172 /* PCIE replay accumulated count */ 1173 uint64_t pcie_replay_count_acc; 1174 1175 /* PCIE replay rollover accumulated count */ 1176 uint64_t pcie_replay_rover_count_acc; 1177 1178 /* PCIE NAK sent accumulated count */ 1179 uint32_t pcie_nak_sent_count_acc; 1180 1181 /* PCIE NAK received accumulated count */ 1182 uint32_t pcie_nak_rcvd_count_acc; 1183 1184 /* XGMI accumulated data transfer size(KiloBytes) */ 1185 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1186 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1187 1188 /* PMFW attached timestamp (10ns resolution) */ 1189 uint64_t firmware_timestamp; 1190 1191 /* Current clocks (Mhz) */ 1192 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1193 uint16_t current_socclk[MAX_CLKS]; 1194 uint16_t current_vclk0[MAX_CLKS]; 1195 uint16_t current_dclk0[MAX_CLKS]; 1196 uint16_t current_uclk; 1197 1198 /* Number of current partition */ 1199 uint16_t num_partition; 1200 1201 /* XCP metrics stats */ 1202 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1203 1204 /* PCIE other end recovery counter */ 1205 uint32_t pcie_lc_perf_other_end_recovery; 1206 }; 1207 1208 struct gpu_metrics_v1_7 { 1209 struct metrics_table_header common_header; 1210 1211 /* Temperature (Celsius) */ 1212 uint16_t temperature_hotspot; 1213 uint16_t temperature_mem; 1214 uint16_t temperature_vrsoc; 1215 1216 /* Power (Watts) */ 1217 uint16_t curr_socket_power; 1218 1219 /* Utilization (%) */ 1220 uint16_t average_gfx_activity; 1221 uint16_t average_umc_activity; // memory controller 1222 1223 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1224 uint64_t mem_max_bandwidth; 1225 1226 /* Energy (15.259uJ (2^-16) units) */ 1227 uint64_t energy_accumulator; 1228 1229 /* Driver attached timestamp (in ns) */ 1230 uint64_t system_clock_counter; 1231 1232 /* Accumulation cycle counter */ 1233 uint32_t accumulation_counter; 1234 1235 /* Accumulated throttler residencies */ 1236 uint32_t prochot_residency_acc; 1237 uint32_t ppt_residency_acc; 1238 uint32_t socket_thm_residency_acc; 1239 uint32_t vr_thm_residency_acc; 1240 uint32_t hbm_thm_residency_acc; 1241 1242 /* Clock Lock Status. Each bit corresponds to clock instance */ 1243 uint32_t gfxclk_lock_status; 1244 1245 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1246 uint16_t pcie_link_width; 1247 uint16_t pcie_link_speed; 1248 1249 /* XGMI bus width and bitrate (in Gbps) */ 1250 uint16_t xgmi_link_width; 1251 uint16_t xgmi_link_speed; 1252 1253 /* Utilization Accumulated (%) */ 1254 uint32_t gfx_activity_acc; 1255 uint32_t mem_activity_acc; 1256 1257 /*PCIE accumulated bandwidth (GB/sec) */ 1258 uint64_t pcie_bandwidth_acc; 1259 1260 /*PCIE instantaneous bandwidth (GB/sec) */ 1261 uint64_t pcie_bandwidth_inst; 1262 1263 /* PCIE L0 to recovery state transition accumulated count */ 1264 uint64_t pcie_l0_to_recov_count_acc; 1265 1266 /* PCIE replay accumulated count */ 1267 uint64_t pcie_replay_count_acc; 1268 1269 /* PCIE replay rollover accumulated count */ 1270 uint64_t pcie_replay_rover_count_acc; 1271 1272 /* PCIE NAK sent accumulated count */ 1273 uint32_t pcie_nak_sent_count_acc; 1274 1275 /* PCIE NAK received accumulated count */ 1276 uint32_t pcie_nak_rcvd_count_acc; 1277 1278 /* XGMI accumulated data transfer size(KiloBytes) */ 1279 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1280 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1281 1282 /* XGMI link status(active/inactive) */ 1283 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1284 1285 uint16_t padding; 1286 1287 /* PMFW attached timestamp (10ns resolution) */ 1288 uint64_t firmware_timestamp; 1289 1290 /* Current clocks (Mhz) */ 1291 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1292 uint16_t current_socclk[MAX_CLKS]; 1293 uint16_t current_vclk0[MAX_CLKS]; 1294 uint16_t current_dclk0[MAX_CLKS]; 1295 uint16_t current_uclk; 1296 1297 /* Number of current partition */ 1298 uint16_t num_partition; 1299 1300 /* XCP metrics stats */ 1301 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1302 1303 /* PCIE other end recovery counter */ 1304 uint32_t pcie_lc_perf_other_end_recovery; 1305 }; 1306 1307 struct gpu_metrics_v1_8 { 1308 struct metrics_table_header common_header; 1309 1310 /* Temperature (Celsius) */ 1311 uint16_t temperature_hotspot; 1312 uint16_t temperature_mem; 1313 uint16_t temperature_vrsoc; 1314 1315 /* Power (Watts) */ 1316 uint16_t curr_socket_power; 1317 1318 /* Utilization (%) */ 1319 uint16_t average_gfx_activity; 1320 uint16_t average_umc_activity; // memory controller 1321 1322 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1323 uint64_t mem_max_bandwidth; 1324 1325 /* Energy (15.259uJ (2^-16) units) */ 1326 uint64_t energy_accumulator; 1327 1328 /* Driver attached timestamp (in ns) */ 1329 uint64_t system_clock_counter; 1330 1331 /* Accumulation cycle counter */ 1332 uint32_t accumulation_counter; 1333 1334 /* Accumulated throttler residencies */ 1335 uint32_t prochot_residency_acc; 1336 uint32_t ppt_residency_acc; 1337 uint32_t socket_thm_residency_acc; 1338 uint32_t vr_thm_residency_acc; 1339 uint32_t hbm_thm_residency_acc; 1340 1341 /* Clock Lock Status. Each bit corresponds to clock instance */ 1342 uint32_t gfxclk_lock_status; 1343 1344 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1345 uint16_t pcie_link_width; 1346 uint16_t pcie_link_speed; 1347 1348 /* XGMI bus width and bitrate (in Gbps) */ 1349 uint16_t xgmi_link_width; 1350 uint16_t xgmi_link_speed; 1351 1352 /* Utilization Accumulated (%) */ 1353 uint32_t gfx_activity_acc; 1354 uint32_t mem_activity_acc; 1355 1356 /*PCIE accumulated bandwidth (GB/sec) */ 1357 uint64_t pcie_bandwidth_acc; 1358 1359 /*PCIE instantaneous bandwidth (GB/sec) */ 1360 uint64_t pcie_bandwidth_inst; 1361 1362 /* PCIE L0 to recovery state transition accumulated count */ 1363 uint64_t pcie_l0_to_recov_count_acc; 1364 1365 /* PCIE replay accumulated count */ 1366 uint64_t pcie_replay_count_acc; 1367 1368 /* PCIE replay rollover accumulated count */ 1369 uint64_t pcie_replay_rover_count_acc; 1370 1371 /* PCIE NAK sent accumulated count */ 1372 uint32_t pcie_nak_sent_count_acc; 1373 1374 /* PCIE NAK received accumulated count */ 1375 uint32_t pcie_nak_rcvd_count_acc; 1376 1377 /* XGMI accumulated data transfer size(KiloBytes) */ 1378 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1379 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1380 1381 /* XGMI link status(active/inactive) */ 1382 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1383 1384 uint16_t padding; 1385 1386 /* PMFW attached timestamp (10ns resolution) */ 1387 uint64_t firmware_timestamp; 1388 1389 /* Current clocks (Mhz) */ 1390 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1391 uint16_t current_socclk[MAX_CLKS]; 1392 uint16_t current_vclk0[MAX_CLKS]; 1393 uint16_t current_dclk0[MAX_CLKS]; 1394 uint16_t current_uclk; 1395 1396 /* Number of current partition */ 1397 uint16_t num_partition; 1398 1399 /* XCP metrics stats */ 1400 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1401 1402 /* PCIE other end recovery counter */ 1403 uint32_t pcie_lc_perf_other_end_recovery; 1404 }; 1405 1406 struct gpu_metrics_attr { 1407 /* Field type encoded with AMDGPU_METRICS_ENC_ATTR */ 1408 uint64_t attr_encoding; 1409 /* Attribute value, depends on attr_encoding */ 1410 void *attr_value; 1411 }; 1412 1413 struct gpu_metrics_v1_9 { 1414 struct metrics_table_header common_header; 1415 int attr_count; 1416 struct gpu_metrics_attr metrics_attrs[]; 1417 }; 1418 1419 /* 1420 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1421 * Use gpu_metrics_v2_1 or later instead. 1422 */ 1423 struct gpu_metrics_v2_0 { 1424 struct metrics_table_header common_header; 1425 1426 /* Driver attached timestamp (in ns) */ 1427 uint64_t system_clock_counter; 1428 1429 /* Temperature */ 1430 uint16_t temperature_gfx; // gfx temperature on APUs 1431 uint16_t temperature_soc; // soc temperature on APUs 1432 uint16_t temperature_core[8]; // CPU core temperature on APUs 1433 uint16_t temperature_l3[2]; 1434 1435 /* Utilization */ 1436 uint16_t average_gfx_activity; 1437 uint16_t average_mm_activity; // UVD or VCN 1438 1439 /* Power/Energy */ 1440 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1441 uint16_t average_cpu_power; 1442 uint16_t average_soc_power; 1443 uint16_t average_gfx_power; 1444 uint16_t average_core_power[8]; // CPU core power on APUs 1445 1446 /* Average clocks */ 1447 uint16_t average_gfxclk_frequency; 1448 uint16_t average_socclk_frequency; 1449 uint16_t average_uclk_frequency; 1450 uint16_t average_fclk_frequency; 1451 uint16_t average_vclk_frequency; 1452 uint16_t average_dclk_frequency; 1453 1454 /* Current clocks */ 1455 uint16_t current_gfxclk; 1456 uint16_t current_socclk; 1457 uint16_t current_uclk; 1458 uint16_t current_fclk; 1459 uint16_t current_vclk; 1460 uint16_t current_dclk; 1461 uint16_t current_coreclk[8]; // CPU core clocks 1462 uint16_t current_l3clk[2]; 1463 1464 /* Throttle status */ 1465 uint32_t throttle_status; 1466 1467 /* Fans */ 1468 uint16_t fan_pwm; 1469 1470 uint16_t padding; 1471 }; 1472 1473 struct gpu_metrics_v2_1 { 1474 struct metrics_table_header common_header; 1475 1476 /* Temperature */ 1477 uint16_t temperature_gfx; // gfx temperature on APUs 1478 uint16_t temperature_soc; // soc temperature on APUs 1479 uint16_t temperature_core[8]; // CPU core temperature on APUs 1480 uint16_t temperature_l3[2]; 1481 1482 /* Utilization */ 1483 uint16_t average_gfx_activity; 1484 uint16_t average_mm_activity; // UVD or VCN 1485 1486 /* Driver attached timestamp (in ns) */ 1487 uint64_t system_clock_counter; 1488 1489 /* Power/Energy */ 1490 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1491 uint16_t average_cpu_power; 1492 uint16_t average_soc_power; 1493 uint16_t average_gfx_power; 1494 uint16_t average_core_power[8]; // CPU core power on APUs 1495 1496 /* Average clocks */ 1497 uint16_t average_gfxclk_frequency; 1498 uint16_t average_socclk_frequency; 1499 uint16_t average_uclk_frequency; 1500 uint16_t average_fclk_frequency; 1501 uint16_t average_vclk_frequency; 1502 uint16_t average_dclk_frequency; 1503 1504 /* Current clocks */ 1505 uint16_t current_gfxclk; 1506 uint16_t current_socclk; 1507 uint16_t current_uclk; 1508 uint16_t current_fclk; 1509 uint16_t current_vclk; 1510 uint16_t current_dclk; 1511 uint16_t current_coreclk[8]; // CPU core clocks 1512 uint16_t current_l3clk[2]; 1513 1514 /* Throttle status */ 1515 uint32_t throttle_status; 1516 1517 /* Fans */ 1518 uint16_t fan_pwm; 1519 1520 uint16_t padding[3]; 1521 }; 1522 1523 struct gpu_metrics_v2_2 { 1524 struct metrics_table_header common_header; 1525 1526 /* Temperature */ 1527 uint16_t temperature_gfx; // gfx temperature on APUs 1528 uint16_t temperature_soc; // soc temperature on APUs 1529 uint16_t temperature_core[8]; // CPU core temperature on APUs 1530 uint16_t temperature_l3[2]; 1531 1532 /* Utilization */ 1533 uint16_t average_gfx_activity; 1534 uint16_t average_mm_activity; // UVD or VCN 1535 1536 /* Driver attached timestamp (in ns) */ 1537 uint64_t system_clock_counter; 1538 1539 /* Power/Energy */ 1540 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1541 uint16_t average_cpu_power; 1542 uint16_t average_soc_power; 1543 uint16_t average_gfx_power; 1544 uint16_t average_core_power[8]; // CPU core power on APUs 1545 1546 /* Average clocks */ 1547 uint16_t average_gfxclk_frequency; 1548 uint16_t average_socclk_frequency; 1549 uint16_t average_uclk_frequency; 1550 uint16_t average_fclk_frequency; 1551 uint16_t average_vclk_frequency; 1552 uint16_t average_dclk_frequency; 1553 1554 /* Current clocks */ 1555 uint16_t current_gfxclk; 1556 uint16_t current_socclk; 1557 uint16_t current_uclk; 1558 uint16_t current_fclk; 1559 uint16_t current_vclk; 1560 uint16_t current_dclk; 1561 uint16_t current_coreclk[8]; // CPU core clocks 1562 uint16_t current_l3clk[2]; 1563 1564 /* Throttle status (ASIC dependent) */ 1565 uint32_t throttle_status; 1566 1567 /* Fans */ 1568 uint16_t fan_pwm; 1569 1570 uint16_t padding[3]; 1571 1572 /* Throttle status (ASIC independent) */ 1573 uint64_t indep_throttle_status; 1574 }; 1575 1576 struct gpu_metrics_v2_3 { 1577 struct metrics_table_header common_header; 1578 1579 /* Temperature */ 1580 uint16_t temperature_gfx; // gfx temperature on APUs 1581 uint16_t temperature_soc; // soc temperature on APUs 1582 uint16_t temperature_core[8]; // CPU core temperature on APUs 1583 uint16_t temperature_l3[2]; 1584 1585 /* Utilization */ 1586 uint16_t average_gfx_activity; 1587 uint16_t average_mm_activity; // UVD or VCN 1588 1589 /* Driver attached timestamp (in ns) */ 1590 uint64_t system_clock_counter; 1591 1592 /* Power/Energy */ 1593 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1594 uint16_t average_cpu_power; 1595 uint16_t average_soc_power; 1596 uint16_t average_gfx_power; 1597 uint16_t average_core_power[8]; // CPU core power on APUs 1598 1599 /* Average clocks */ 1600 uint16_t average_gfxclk_frequency; 1601 uint16_t average_socclk_frequency; 1602 uint16_t average_uclk_frequency; 1603 uint16_t average_fclk_frequency; 1604 uint16_t average_vclk_frequency; 1605 uint16_t average_dclk_frequency; 1606 1607 /* Current clocks */ 1608 uint16_t current_gfxclk; 1609 uint16_t current_socclk; 1610 uint16_t current_uclk; 1611 uint16_t current_fclk; 1612 uint16_t current_vclk; 1613 uint16_t current_dclk; 1614 uint16_t current_coreclk[8]; // CPU core clocks 1615 uint16_t current_l3clk[2]; 1616 1617 /* Throttle status (ASIC dependent) */ 1618 uint32_t throttle_status; 1619 1620 /* Fans */ 1621 uint16_t fan_pwm; 1622 1623 uint16_t padding[3]; 1624 1625 /* Throttle status (ASIC independent) */ 1626 uint64_t indep_throttle_status; 1627 1628 /* Average Temperature */ 1629 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1630 uint16_t average_temperature_soc; // average soc temperature on APUs 1631 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1632 uint16_t average_temperature_l3[2]; 1633 }; 1634 1635 struct gpu_metrics_v2_4 { 1636 struct metrics_table_header common_header; 1637 1638 /* Temperature (unit: centi-Celsius) */ 1639 uint16_t temperature_gfx; 1640 uint16_t temperature_soc; 1641 uint16_t temperature_core[8]; 1642 uint16_t temperature_l3[2]; 1643 1644 /* Utilization (unit: centi) */ 1645 uint16_t average_gfx_activity; 1646 uint16_t average_mm_activity; 1647 1648 /* Driver attached timestamp (in ns) */ 1649 uint64_t system_clock_counter; 1650 1651 /* Power/Energy (unit: mW) */ 1652 uint16_t average_socket_power; 1653 uint16_t average_cpu_power; 1654 uint16_t average_soc_power; 1655 uint16_t average_gfx_power; 1656 uint16_t average_core_power[8]; 1657 1658 /* Average clocks (unit: MHz) */ 1659 uint16_t average_gfxclk_frequency; 1660 uint16_t average_socclk_frequency; 1661 uint16_t average_uclk_frequency; 1662 uint16_t average_fclk_frequency; 1663 uint16_t average_vclk_frequency; 1664 uint16_t average_dclk_frequency; 1665 1666 /* Current clocks (unit: MHz) */ 1667 uint16_t current_gfxclk; 1668 uint16_t current_socclk; 1669 uint16_t current_uclk; 1670 uint16_t current_fclk; 1671 uint16_t current_vclk; 1672 uint16_t current_dclk; 1673 uint16_t current_coreclk[8]; 1674 uint16_t current_l3clk[2]; 1675 1676 /* Throttle status (ASIC dependent) */ 1677 uint32_t throttle_status; 1678 1679 /* Fans */ 1680 uint16_t fan_pwm; 1681 1682 uint16_t padding[3]; 1683 1684 /* Throttle status (ASIC independent) */ 1685 uint64_t indep_throttle_status; 1686 1687 /* Average Temperature (unit: centi-Celsius) */ 1688 uint16_t average_temperature_gfx; 1689 uint16_t average_temperature_soc; 1690 uint16_t average_temperature_core[8]; 1691 uint16_t average_temperature_l3[2]; 1692 1693 /* Power/Voltage (unit: mV) */ 1694 uint16_t average_cpu_voltage; 1695 uint16_t average_soc_voltage; 1696 uint16_t average_gfx_voltage; 1697 1698 /* Power/Current (unit: mA) */ 1699 uint16_t average_cpu_current; 1700 uint16_t average_soc_current; 1701 uint16_t average_gfx_current; 1702 }; 1703 1704 struct gpu_metrics_v3_0 { 1705 struct metrics_table_header common_header; 1706 1707 /* Temperature */ 1708 /* gfx temperature on APUs */ 1709 uint16_t temperature_gfx; 1710 /* soc temperature on APUs */ 1711 uint16_t temperature_soc; 1712 /* CPU core temperature on APUs */ 1713 uint16_t temperature_core[16]; 1714 /* skin temperature on APUs */ 1715 uint16_t temperature_skin; 1716 1717 /* Utilization */ 1718 /* time filtered GFX busy % [0-100] */ 1719 uint16_t average_gfx_activity; 1720 /* time filtered VCN busy % [0-100] */ 1721 uint16_t average_vcn_activity; 1722 /* time filtered IPU per-column busy % [0-100] */ 1723 uint16_t average_ipu_activity[8]; 1724 /* time filtered per-core C0 residency % [0-100]*/ 1725 uint16_t average_core_c0_activity[16]; 1726 /* time filtered DRAM read bandwidth [MB/sec] */ 1727 uint16_t average_dram_reads; 1728 /* time filtered DRAM write bandwidth [MB/sec] */ 1729 uint16_t average_dram_writes; 1730 /* time filtered IPU read bandwidth [MB/sec] */ 1731 uint16_t average_ipu_reads; 1732 /* time filtered IPU write bandwidth [MB/sec] */ 1733 uint16_t average_ipu_writes; 1734 1735 /* Driver attached timestamp (in ns) */ 1736 uint64_t system_clock_counter; 1737 1738 /* Power/Energy */ 1739 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1740 uint32_t average_socket_power; 1741 /* time filtered IPU power [mW] */ 1742 uint16_t average_ipu_power; 1743 /* time filtered APU power [mW] */ 1744 uint32_t average_apu_power; 1745 /* time filtered GFX power [mW] */ 1746 uint32_t average_gfx_power; 1747 /* time filtered dGPU power [mW] */ 1748 uint32_t average_dgpu_power; 1749 /* time filtered sum of core power across all cores in the socket [mW] */ 1750 uint32_t average_all_core_power; 1751 /* calculated core power [mW] */ 1752 uint16_t average_core_power[16]; 1753 /* time filtered total system power [mW] */ 1754 uint16_t average_sys_power; 1755 /* maximum IRM defined STAPM power limit [mW] */ 1756 uint16_t stapm_power_limit; 1757 /* time filtered STAPM power limit [mW] */ 1758 uint16_t current_stapm_power_limit; 1759 1760 /* time filtered clocks [MHz] */ 1761 uint16_t average_gfxclk_frequency; 1762 uint16_t average_socclk_frequency; 1763 uint16_t average_vpeclk_frequency; 1764 uint16_t average_ipuclk_frequency; 1765 uint16_t average_fclk_frequency; 1766 uint16_t average_vclk_frequency; 1767 uint16_t average_uclk_frequency; 1768 uint16_t average_mpipu_frequency; 1769 1770 /* Current clocks */ 1771 /* target core frequency [MHz] */ 1772 uint16_t current_coreclk[16]; 1773 /* CCLK frequency limit enforced on classic cores [MHz] */ 1774 uint16_t current_core_maxfreq; 1775 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1776 uint16_t current_gfx_maxfreq; 1777 1778 /* Throttle Residency (ASIC dependent) */ 1779 uint32_t throttle_residency_prochot; 1780 uint32_t throttle_residency_spl; 1781 uint32_t throttle_residency_fppt; 1782 uint32_t throttle_residency_sppt; 1783 uint32_t throttle_residency_thm_core; 1784 uint32_t throttle_residency_thm_gfx; 1785 uint32_t throttle_residency_thm_soc; 1786 1787 /* Metrics table alpha filter time constant [us] */ 1788 uint32_t time_filter_alphavalue; 1789 }; 1790 1791 struct amdgpu_pmmetrics_header { 1792 uint16_t structure_size; 1793 uint16_t pad; 1794 uint32_t mp1_ip_discovery_version; 1795 uint32_t pmfw_version; 1796 uint32_t pmmetrics_version; 1797 }; 1798 1799 struct amdgpu_pm_metrics { 1800 struct amdgpu_pmmetrics_header common_header; 1801 1802 uint8_t data[]; 1803 }; 1804 1805 enum amdgpu_vr_temp { 1806 AMDGPU_VDDCR_VDD0_TEMP, 1807 AMDGPU_VDDCR_VDD1_TEMP, 1808 AMDGPU_VDDCR_VDD2_TEMP, 1809 AMDGPU_VDDCR_VDD3_TEMP, 1810 AMDGPU_VDDCR_SOC_A_TEMP, 1811 AMDGPU_VDDCR_SOC_C_TEMP, 1812 AMDGPU_VDDCR_SOCIO_A_TEMP, 1813 AMDGPU_VDDCR_SOCIO_C_TEMP, 1814 AMDGPU_VDD_085_HBM_TEMP, 1815 AMDGPU_VDDCR_11_HBM_B_TEMP, 1816 AMDGPU_VDDCR_11_HBM_D_TEMP, 1817 AMDGPU_VDD_USR_TEMP, 1818 AMDGPU_VDDIO_11_E32_TEMP, 1819 AMDGPU_VR_MAX_TEMP_ENTRIES, 1820 }; 1821 1822 enum amdgpu_system_temp { 1823 AMDGPU_UBB_FPGA_TEMP, 1824 AMDGPU_UBB_FRONT_TEMP, 1825 AMDGPU_UBB_BACK_TEMP, 1826 AMDGPU_UBB_OAM7_TEMP, 1827 AMDGPU_UBB_IBC_TEMP, 1828 AMDGPU_UBB_UFPGA_TEMP, 1829 AMDGPU_UBB_OAM1_TEMP, 1830 AMDGPU_OAM_0_1_HSC_TEMP, 1831 AMDGPU_OAM_2_3_HSC_TEMP, 1832 AMDGPU_OAM_4_5_HSC_TEMP, 1833 AMDGPU_OAM_6_7_HSC_TEMP, 1834 AMDGPU_UBB_FPGA_0V72_VR_TEMP, 1835 AMDGPU_UBB_FPGA_3V3_VR_TEMP, 1836 AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP, 1837 AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP, 1838 AMDGPU_RETIMER_0_1_0V9_VR_TEMP, 1839 AMDGPU_RETIMER_4_5_0V9_VR_TEMP, 1840 AMDGPU_RETIMER_2_3_0V9_VR_TEMP, 1841 AMDGPU_RETIMER_6_7_0V9_VR_TEMP, 1842 AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP, 1843 AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP, 1844 AMDGPU_IBC_HSC_TEMP, 1845 AMDGPU_IBC_TEMP, 1846 AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32, 1847 }; 1848 1849 enum amdgpu_node_temp { 1850 AMDGPU_RETIMER_X_TEMP, 1851 AMDGPU_OAM_X_IBC_TEMP, 1852 AMDGPU_OAM_X_IBC_2_TEMP, 1853 AMDGPU_OAM_X_VDD18_VR_TEMP, 1854 AMDGPU_OAM_X_04_HBM_B_VR_TEMP, 1855 AMDGPU_OAM_X_04_HBM_D_VR_TEMP, 1856 AMDGPU_NODE_MAX_TEMP_ENTRIES = 12, 1857 }; 1858 1859 struct amdgpu_gpuboard_temp_metrics_v1_0 { 1860 struct metrics_table_header common_header; 1861 uint16_t label_version; 1862 uint16_t node_id; 1863 uint64_t accumulation_counter; 1864 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1865 uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES]; 1866 uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES]; 1867 }; 1868 1869 struct amdgpu_baseboard_temp_metrics_v1_0 { 1870 struct metrics_table_header common_header; 1871 uint16_t label_version; 1872 uint16_t node_id; 1873 uint64_t accumulation_counter; 1874 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1875 uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES]; 1876 }; 1877 1878 struct amdgpu_partition_metrics_v1_0 { 1879 struct metrics_table_header common_header; 1880 /* Current clocks (Mhz) */ 1881 uint16_t current_gfxclk[MAX_XCC]; 1882 uint16_t current_socclk[MAX_CLKS]; 1883 uint16_t current_vclk0[MAX_CLKS]; 1884 uint16_t current_dclk0[MAX_CLKS]; 1885 uint16_t current_uclk; 1886 uint16_t padding; 1887 1888 /* Utilization Instantaneous (%) */ 1889 uint32_t gfx_busy_inst[MAX_XCC]; 1890 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 1891 uint16_t vcn_busy[NUM_VCN]; 1892 /* Utilization Accumulated (%) */ 1893 uint64_t gfx_busy_acc[MAX_XCC]; 1894 /* Total App Clock Counter Accumulated */ 1895 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 1896 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 1897 uint64_t gfx_low_utilization_acc[MAX_XCC]; 1898 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 1899 }; 1900 1901 struct amdgpu_partition_metrics_v1_1 { 1902 struct metrics_table_header common_header; 1903 int attr_count; 1904 struct gpu_metrics_attr metrics_attrs[]; 1905 }; 1906 1907 enum amdgpu_xgmi_link_status { 1908 AMDGPU_XGMI_LINK_INACTIVE = 0, 1909 AMDGPU_XGMI_LINK_ACTIVE = 1, 1910 /* Status not available */ 1911 AMDGPU_XGMI_LINK_NA = 2, 1912 }; 1913 1914 struct amdgpu_gpuboard_temp_metrics_v1_1 { 1915 struct metrics_table_header common_header; 1916 int attr_count; 1917 struct gpu_metrics_attr metrics_attrs[]; 1918 }; 1919 1920 struct amdgpu_baseboard_temp_metrics_v1_1 { 1921 struct metrics_table_header common_header; 1922 int attr_count; 1923 struct gpu_metrics_attr metrics_attrs[]; 1924 }; 1925 1926 #endif 1927