1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. 4 */ 5 6 #ifndef _UAPI_AMDXDNA_ACCEL_H_ 7 #define _UAPI_AMDXDNA_ACCEL_H_ 8 9 #include <linux/stddef.h> 10 #include "drm.h" 11 12 #if defined(__cplusplus) 13 extern "C" { 14 #endif 15 16 #define AMDXDNA_INVALID_CMD_HANDLE (~0UL) 17 #define AMDXDNA_INVALID_ADDR (~0UL) 18 #define AMDXDNA_INVALID_CTX_HANDLE 0 19 #define AMDXDNA_INVALID_BO_HANDLE 0 20 #define AMDXDNA_INVALID_FENCE_HANDLE 0 21 22 enum amdxdna_device_type { 23 AMDXDNA_DEV_TYPE_UNKNOWN = -1, 24 AMDXDNA_DEV_TYPE_KMQ, 25 }; 26 27 enum amdxdna_drm_ioctl_id { 28 DRM_AMDXDNA_CREATE_HWCTX, 29 DRM_AMDXDNA_DESTROY_HWCTX, 30 DRM_AMDXDNA_CONFIG_HWCTX, 31 DRM_AMDXDNA_CREATE_BO, 32 DRM_AMDXDNA_GET_BO_INFO, 33 DRM_AMDXDNA_SYNC_BO, 34 DRM_AMDXDNA_EXEC_CMD, 35 DRM_AMDXDNA_GET_INFO, 36 DRM_AMDXDNA_SET_STATE, 37 }; 38 39 /** 40 * struct qos_info - QoS information for driver. 41 * @gops: Giga operations per second. 42 * @fps: Frames per second. 43 * @dma_bandwidth: DMA bandwidtha. 44 * @latency: Frame response latency. 45 * @frame_exec_time: Frame execution time. 46 * @priority: Request priority. 47 * 48 * User program can provide QoS hints to driver. 49 */ 50 struct amdxdna_qos_info { 51 __u32 gops; 52 __u32 fps; 53 __u32 dma_bandwidth; 54 __u32 latency; 55 __u32 frame_exec_time; 56 __u32 priority; 57 }; 58 59 /** 60 * struct amdxdna_drm_create_hwctx - Create hardware context. 61 * @ext: MBZ. 62 * @ext_flags: MBZ. 63 * @qos_p: Address of QoS info. 64 * @umq_bo: BO handle for user mode queue(UMQ). 65 * @log_buf_bo: BO handle for log buffer. 66 * @max_opc: Maximum operations per cycle. 67 * @num_tiles: Number of AIE tiles. 68 * @mem_size: Size of AIE tile memory. 69 * @umq_doorbell: Returned offset of doorbell associated with UMQ. 70 * @handle: Returned hardware context handle. 71 * @syncobj_handle: Returned syncobj handle for command completion. 72 */ 73 struct amdxdna_drm_create_hwctx { 74 __u64 ext; 75 __u64 ext_flags; 76 __u64 qos_p; 77 __u32 umq_bo; 78 __u32 log_buf_bo; 79 __u32 max_opc; 80 __u32 num_tiles; 81 __u32 mem_size; 82 __u32 umq_doorbell; 83 __u32 handle; 84 __u32 syncobj_handle; 85 }; 86 87 /** 88 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context. 89 * @handle: Hardware context handle. 90 * @pad: MBZ. 91 */ 92 struct amdxdna_drm_destroy_hwctx { 93 __u32 handle; 94 __u32 pad; 95 }; 96 97 /** 98 * struct amdxdna_cu_config - configuration for one CU 99 * @cu_bo: CU configuration buffer bo handle. 100 * @cu_func: Function of a CU. 101 * @pad: MBZ. 102 */ 103 struct amdxdna_cu_config { 104 __u32 cu_bo; 105 __u8 cu_func; 106 __u8 pad[3]; 107 }; 108 109 /** 110 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context 111 * @num_cus: Number of CUs to configure. 112 * @pad: MBZ. 113 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config. 114 */ 115 struct amdxdna_hwctx_param_config_cu { 116 __u16 num_cus; 117 __u16 pad[3]; 118 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus); 119 }; 120 121 enum amdxdna_drm_config_hwctx_param { 122 DRM_AMDXDNA_HWCTX_CONFIG_CU, 123 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF, 124 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF, 125 }; 126 127 /** 128 * struct amdxdna_drm_config_hwctx - Configure hardware context. 129 * @handle: hardware context handle. 130 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the 131 * structure passed in via param_val. 132 * @param_val: A structure specified by the param_type struct member. 133 * @param_val_size: Size of the parameter buffer pointed to by the param_val. 134 * If param_val is not a pointer, driver can ignore this. 135 * @pad: MBZ. 136 * 137 * Note: if the param_val is a pointer pointing to a buffer, the maximum size 138 * of the buffer is 4KiB(PAGE_SIZE). 139 */ 140 struct amdxdna_drm_config_hwctx { 141 __u32 handle; 142 __u32 param_type; 143 __u64 param_val; 144 __u32 param_val_size; 145 __u32 pad; 146 }; 147 148 enum amdxdna_bo_type { 149 AMDXDNA_BO_INVALID = 0, 150 AMDXDNA_BO_SHMEM, 151 AMDXDNA_BO_DEV_HEAP, 152 AMDXDNA_BO_DEV, 153 AMDXDNA_BO_CMD, 154 }; 155 156 /** 157 * struct amdxdna_drm_create_bo - Create a buffer object. 158 * @flags: Buffer flags. MBZ. 159 * @vaddr: User VA of buffer if applied. MBZ. 160 * @size: Size in bytes. 161 * @type: Buffer type. 162 * @handle: Returned DRM buffer object handle. 163 */ 164 struct amdxdna_drm_create_bo { 165 __u64 flags; 166 __u64 vaddr; 167 __u64 size; 168 __u32 type; 169 __u32 handle; 170 }; 171 172 /** 173 * struct amdxdna_drm_get_bo_info - Get buffer object information. 174 * @ext: MBZ. 175 * @ext_flags: MBZ. 176 * @handle: DRM buffer object handle. 177 * @pad: MBZ. 178 * @map_offset: Returned DRM fake offset for mmap(). 179 * @vaddr: Returned user VA of buffer. 0 in case user needs mmap(). 180 * @xdna_addr: Returned XDNA device virtual address. 181 */ 182 struct amdxdna_drm_get_bo_info { 183 __u64 ext; 184 __u64 ext_flags; 185 __u32 handle; 186 __u32 pad; 187 __u64 map_offset; 188 __u64 vaddr; 189 __u64 xdna_addr; 190 }; 191 192 /** 193 * struct amdxdna_drm_sync_bo - Sync buffer object. 194 * @handle: Buffer object handle. 195 * @direction: Direction of sync, can be from device or to device. 196 * @offset: Offset in the buffer to sync. 197 * @size: Size in bytes. 198 */ 199 struct amdxdna_drm_sync_bo { 200 __u32 handle; 201 #define SYNC_DIRECT_TO_DEVICE 0U 202 #define SYNC_DIRECT_FROM_DEVICE 1U 203 __u32 direction; 204 __u64 offset; 205 __u64 size; 206 }; 207 208 enum amdxdna_cmd_type { 209 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0, 210 AMDXDNA_CMD_SUBMIT_DEPENDENCY, 211 AMDXDNA_CMD_SUBMIT_SIGNAL, 212 }; 213 214 /** 215 * struct amdxdna_drm_exec_cmd - Execute command. 216 * @ext: MBZ. 217 * @ext_flags: MBZ. 218 * @hwctx: Hardware context handle. 219 * @type: One of command type in enum amdxdna_cmd_type. 220 * @cmd_handles: Array of command handles or the command handle itself 221 * in case of just one. 222 * @args: Array of arguments for all command handles. 223 * @cmd_count: Number of command handles in the cmd_handles array. 224 * @arg_count: Number of arguments in the args array. 225 * @seq: Returned sequence number for this command. 226 */ 227 struct amdxdna_drm_exec_cmd { 228 __u64 ext; 229 __u64 ext_flags; 230 __u32 hwctx; 231 __u32 type; 232 __u64 cmd_handles; 233 __u64 args; 234 __u32 cmd_count; 235 __u32 arg_count; 236 __u64 seq; 237 }; 238 239 /** 240 * struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware 241 * @buffer: The user space buffer that will return the AIE status. 242 * @buffer_size: The size of the user space buffer. 243 * @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer. 244 */ 245 struct amdxdna_drm_query_aie_status { 246 __u64 buffer; /* out */ 247 __u32 buffer_size; /* in */ 248 __u32 cols_filled; /* out */ 249 }; 250 251 /** 252 * struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware 253 * @major: The major version number. 254 * @minor: The minor version number. 255 */ 256 struct amdxdna_drm_query_aie_version { 257 __u32 major; /* out */ 258 __u32 minor; /* out */ 259 }; 260 261 /** 262 * struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim) 263 * @row_count: The number of rows. 264 * @row_start: The starting row number. 265 * @dma_channel_count: The number of dma channels. 266 * @lock_count: The number of locks. 267 * @event_reg_count: The number of events. 268 * @pad: Structure padding. 269 */ 270 struct amdxdna_drm_query_aie_tile_metadata { 271 __u16 row_count; 272 __u16 row_start; 273 __u16 dma_channel_count; 274 __u16 lock_count; 275 __u16 event_reg_count; 276 __u16 pad[3]; 277 }; 278 279 /** 280 * struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware 281 * @col_size: The size of a column in bytes. 282 * @cols: The total number of columns. 283 * @rows: The total number of rows. 284 * @version: The version of the AIE hardware. 285 * @core: The metadata for all core tiles. 286 * @mem: The metadata for all mem tiles. 287 * @shim: The metadata for all shim tiles. 288 */ 289 struct amdxdna_drm_query_aie_metadata { 290 __u32 col_size; 291 __u16 cols; 292 __u16 rows; 293 struct amdxdna_drm_query_aie_version version; 294 struct amdxdna_drm_query_aie_tile_metadata core; 295 struct amdxdna_drm_query_aie_tile_metadata mem; 296 struct amdxdna_drm_query_aie_tile_metadata shim; 297 }; 298 299 /** 300 * struct amdxdna_drm_query_clock - Metadata for a clock 301 * @name: The clock name. 302 * @freq_mhz: The clock frequency. 303 * @pad: Structure padding. 304 */ 305 struct amdxdna_drm_query_clock { 306 __u8 name[16]; 307 __u32 freq_mhz; 308 __u32 pad; 309 }; 310 311 /** 312 * struct amdxdna_drm_query_clock_metadata - Query metadata for clocks 313 * @mp_npu_clock: The metadata for MP-NPU clock. 314 * @h_clock: The metadata for H clock. 315 */ 316 struct amdxdna_drm_query_clock_metadata { 317 struct amdxdna_drm_query_clock mp_npu_clock; 318 struct amdxdna_drm_query_clock h_clock; 319 }; 320 321 enum amdxdna_sensor_type { 322 AMDXDNA_SENSOR_TYPE_POWER 323 }; 324 325 /** 326 * struct amdxdna_drm_query_sensor - The data for single sensor. 327 * @label: The name for a sensor. 328 * @input: The current value of the sensor. 329 * @max: The maximum value possible for the sensor. 330 * @average: The average value of the sensor. 331 * @highest: The highest recorded sensor value for this driver load for the sensor. 332 * @status: The sensor status. 333 * @units: The sensor units. 334 * @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value). 335 * @type: The sensor type from enum amdxdna_sensor_type. 336 * @pad: Structure padding. 337 */ 338 struct amdxdna_drm_query_sensor { 339 __u8 label[64]; 340 __u32 input; 341 __u32 max; 342 __u32 average; 343 __u32 highest; 344 __u8 status[64]; 345 __u8 units[16]; 346 __s8 unitm; 347 __u8 type; 348 __u8 pad[6]; 349 }; 350 351 /** 352 * struct amdxdna_drm_query_hwctx - The data for single context. 353 * @context_id: The ID for this context. 354 * @start_col: The starting column for the partition assigned to this context. 355 * @num_col: The number of columns in the partition assigned to this context. 356 * @pad: Structure padding. 357 * @pid: The Process ID of the process that created this context. 358 * @command_submissions: The number of commands submitted to this context. 359 * @command_completions: The number of commands completed by this context. 360 * @migrations: The number of times this context has been moved to a different partition. 361 * @preemptions: The number of times this context has been preempted by another context in the 362 * same partition. 363 * @errors: The errors for this context. 364 */ 365 struct amdxdna_drm_query_hwctx { 366 __u32 context_id; 367 __u32 start_col; 368 __u32 num_col; 369 __u32 pad; 370 __s64 pid; 371 __u64 command_submissions; 372 __u64 command_completions; 373 __u64 migrations; 374 __u64 preemptions; 375 __u64 errors; 376 }; 377 378 enum amdxdna_power_mode_type { 379 POWER_MODE_DEFAULT, /* Fallback to calculated DPM */ 380 POWER_MODE_LOW, /* Set frequency to lowest DPM */ 381 POWER_MODE_MEDIUM, /* Set frequency to medium DPM */ 382 POWER_MODE_HIGH, /* Set frequency to highest DPM */ 383 POWER_MODE_TURBO, /* Maximum power */ 384 }; 385 386 /** 387 * struct amdxdna_drm_get_power_mode - Get the configured power mode 388 * @power_mode: The mode type from enum amdxdna_power_mode_type 389 * @pad: Structure padding. 390 */ 391 struct amdxdna_drm_get_power_mode { 392 __u8 power_mode; 393 __u8 pad[7]; 394 }; 395 396 /** 397 * struct amdxdna_drm_query_firmware_version - Query the firmware version 398 * @major: The major version number 399 * @minor: The minor version number 400 * @patch: The patch level version number 401 * @build: The build ID 402 */ 403 struct amdxdna_drm_query_firmware_version { 404 __u32 major; /* out */ 405 __u32 minor; /* out */ 406 __u32 patch; /* out */ 407 __u32 build; /* out */ 408 }; 409 410 enum amdxdna_drm_get_param { 411 DRM_AMDXDNA_QUERY_AIE_STATUS, 412 DRM_AMDXDNA_QUERY_AIE_METADATA, 413 DRM_AMDXDNA_QUERY_AIE_VERSION, 414 DRM_AMDXDNA_QUERY_CLOCK_METADATA, 415 DRM_AMDXDNA_QUERY_SENSORS, 416 DRM_AMDXDNA_QUERY_HW_CONTEXTS, 417 DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8, 418 DRM_AMDXDNA_GET_POWER_MODE, 419 }; 420 421 /** 422 * struct amdxdna_drm_get_info - Get some information from the AIE hardware. 423 * @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer. 424 * @buffer_size: Size of the input buffer. Size needed/written by the kernel. 425 * @buffer: A structure specified by the param struct member. 426 */ 427 struct amdxdna_drm_get_info { 428 __u32 param; /* in */ 429 __u32 buffer_size; /* in/out */ 430 __u64 buffer; /* in/out */ 431 }; 432 433 enum amdxdna_drm_set_param { 434 DRM_AMDXDNA_SET_POWER_MODE, 435 DRM_AMDXDNA_WRITE_AIE_MEM, 436 DRM_AMDXDNA_WRITE_AIE_REG, 437 }; 438 439 /** 440 * struct amdxdna_drm_set_state - Set the state of the AIE hardware. 441 * @param: Value in enum amdxdna_drm_set_param. 442 * @buffer_size: Size of the input param. 443 * @buffer: Pointer to the input param. 444 */ 445 struct amdxdna_drm_set_state { 446 __u32 param; /* in */ 447 __u32 buffer_size; /* in */ 448 __u64 buffer; /* in */ 449 }; 450 451 /** 452 * struct amdxdna_drm_set_power_mode - Set the power mode of the AIE hardware 453 * @power_mode: The sensor type from enum amdxdna_power_mode_type 454 * @pad: MBZ. 455 */ 456 struct amdxdna_drm_set_power_mode { 457 __u8 power_mode; 458 __u8 pad[7]; 459 }; 460 461 #define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \ 462 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \ 463 struct amdxdna_drm_create_hwctx) 464 465 #define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \ 466 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \ 467 struct amdxdna_drm_destroy_hwctx) 468 469 #define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \ 470 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \ 471 struct amdxdna_drm_config_hwctx) 472 473 #define DRM_IOCTL_AMDXDNA_CREATE_BO \ 474 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \ 475 struct amdxdna_drm_create_bo) 476 477 #define DRM_IOCTL_AMDXDNA_GET_BO_INFO \ 478 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \ 479 struct amdxdna_drm_get_bo_info) 480 481 #define DRM_IOCTL_AMDXDNA_SYNC_BO \ 482 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \ 483 struct amdxdna_drm_sync_bo) 484 485 #define DRM_IOCTL_AMDXDNA_EXEC_CMD \ 486 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \ 487 struct amdxdna_drm_exec_cmd) 488 489 #define DRM_IOCTL_AMDXDNA_GET_INFO \ 490 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \ 491 struct amdxdna_drm_get_info) 492 493 #define DRM_IOCTL_AMDXDNA_SET_STATE \ 494 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \ 495 struct amdxdna_drm_set_state) 496 497 #if defined(__cplusplus) 498 } /* extern c end */ 499 #endif 500 501 #endif /* _UAPI_AMDXDNA_ACCEL_H_ */ 502