xref: /linux/drivers/usb/host/xhci-port.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 
3 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
4 /* true: device connected */
5 #define PORT_CONNECT	(1 << 0)
6 /* true: port enabled */
7 #define PORT_PE		(1 << 1)
8 /* bit 2 reserved and zeroed */
9 /* true: port has an over-current condition */
10 #define PORT_OC		(1 << 3)
11 /* true: port reset signaling asserted */
12 #define PORT_RESET	(1 << 4)
13 /* Port Link State - bits 5:8
14  * A read gives the current link PM state of the port,
15  * a write with Link State Write Strobe set sets the link state.
16  */
17 #define PORT_PLS_MASK	(0xf << 5)
18 #define XDEV_U0		(0x0 << 5)
19 #define XDEV_U1		(0x1 << 5)
20 #define XDEV_U2		(0x2 << 5)
21 #define XDEV_U3		(0x3 << 5)
22 #define XDEV_DISABLED	(0x4 << 5)
23 #define XDEV_RXDETECT	(0x5 << 5)
24 #define XDEV_INACTIVE	(0x6 << 5)
25 #define XDEV_POLLING	(0x7 << 5)
26 #define XDEV_RECOVERY	(0x8 << 5)
27 #define XDEV_HOT_RESET	(0x9 << 5)
28 #define XDEV_COMP_MODE	(0xa << 5)
29 #define XDEV_TEST_MODE	(0xb << 5)
30 #define XDEV_RESUME	(0xf << 5)
31 
32 /* true: port has power (see HCC_PPC) */
33 #define PORT_POWER	(1 << 9)
34 /* bits 10:13 indicate device speed:
35  * 0 - undefined speed - port hasn't be initialized by a reset yet
36  * 1 - full speed
37  * 2 - low speed
38  * 3 - high speed
39  * 4 - super speed
40  * 5-15 reserved
41  */
42 #define DEV_SPEED_MASK		(0xf << 10)
43 #define	XDEV_FS			(0x1 << 10)
44 #define	XDEV_LS			(0x2 << 10)
45 #define	XDEV_HS			(0x3 << 10)
46 #define	XDEV_SS			(0x4 << 10)
47 #define	XDEV_SSP		(0x5 << 10)
48 #define DEV_UNDEFSPEED(p)	(((p) & DEV_SPEED_MASK) == (0x0<<10))
49 #define DEV_FULLSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_FS)
50 #define DEV_LOWSPEED(p)		(((p) & DEV_SPEED_MASK) == XDEV_LS)
51 #define DEV_HIGHSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_HS)
52 #define DEV_SUPERSPEED(p)	(((p) & DEV_SPEED_MASK) == XDEV_SS)
53 #define DEV_SUPERSPEEDPLUS(p)	(((p) & DEV_SPEED_MASK) == XDEV_SSP)
54 #define DEV_SUPERSPEED_ANY(p)	(((p) & DEV_SPEED_MASK) >= XDEV_SS)
55 #define DEV_PORT_SPEED(p)	(((p) >> 10) & 0x0f)
56 
57 /* Bits 20:23 in the Slot Context are the speed for the device */
58 #define	SLOT_SPEED_FS		(XDEV_FS << 10)
59 #define	SLOT_SPEED_LS		(XDEV_LS << 10)
60 #define	SLOT_SPEED_HS		(XDEV_HS << 10)
61 #define	SLOT_SPEED_SS		(XDEV_SS << 10)
62 #define	SLOT_SPEED_SSP		(XDEV_SSP << 10)
63 /* Port Indicator Control */
64 #define PORT_LED_OFF	(0 << 14)
65 #define PORT_LED_AMBER	(1 << 14)
66 #define PORT_LED_GREEN	(2 << 14)
67 #define PORT_LED_MASK	(3 << 14)
68 /* Port Link State Write Strobe - set this when changing link state */
69 #define PORT_LINK_STROBE	(1 << 16)
70 /* true: connect status change */
71 #define PORT_CSC	(1 << 17)
72 /* true: port enable change */
73 #define PORT_PEC	(1 << 18)
74 /* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
75  * into an enabled state, and the device into the default state.  A "warm" reset
76  * also resets the link, forcing the device through the link training sequence.
77  * SW can also look at the Port Reset register to see when warm reset is done.
78  */
79 #define PORT_WRC	(1 << 19)
80 /* true: over-current change */
81 #define PORT_OCC	(1 << 20)
82 /* true: reset change - 1 to 0 transition of PORT_RESET */
83 #define PORT_RC		(1 << 21)
84 /* port link status change - set on some port link state transitions:
85  *  Transition				Reason
86  *  ------------------------------------------------------------------------------
87  *  - U3 to Resume			Wakeup signaling from a device
88  *  - Resume to Recovery to U0		USB 3.0 device resume
89  *  - Resume to U0			USB 2.0 device resume
90  *  - U3 to Recovery to U0		Software resume of USB 3.0 device complete
91  *  - U3 to U0				Software resume of USB 2.0 device complete
92  *  - U2 to U0				L1 resume of USB 2.1 device complete
93  *  - U0 to U0 (???)			L1 entry rejection by USB 2.1 device
94  *  - U0 to disabled			L1 entry error with USB 2.1 device
95  *  - Any state to inactive		Error on USB 3.0 port
96  */
97 #define PORT_PLC	(1 << 22)
98 /* port configure error change - port failed to configure its link partner */
99 #define PORT_CEC	(1 << 23)
100 #define PORT_CHANGE_MASK	(PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
101 				 PORT_RC | PORT_PLC | PORT_CEC)
102 
103 
104 /* Cold Attach Status - xHC can set this bit to report device attached during
105  * Sx state. Warm port reset should be perfomed to clear this bit and move port
106  * to connected state.
107  */
108 #define PORT_CAS	(1 << 24)
109 /* wake on connect (enable) */
110 #define PORT_WKCONN_E	(1 << 25)
111 /* wake on disconnect (enable) */
112 #define PORT_WKDISC_E	(1 << 26)
113 /* wake on over-current (enable) */
114 #define PORT_WKOC_E	(1 << 27)
115 /* bits 28:29 reserved */
116 /* true: device is non-removable - for USB 3.0 roothub emulation */
117 #define PORT_DEV_REMOVE	(1 << 30)
118 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
119 #define PORT_WR		(1 << 31)
120 
121 /* We mark duplicate entries with -1 */
122 #define DUPLICATE_ENTRY ((u8)(-1))
123 
124 /* Port Power Management Status and Control - port_power_base bitmasks */
125 /* Inactivity timer value for transitions into U1, in microseconds.
126  * Timeout can be up to 127us.  0xFF means an infinite timeout.
127  */
128 #define PORT_U1_TIMEOUT(p)	((p) & 0xff)
129 #define PORT_U1_TIMEOUT_MASK	0xff
130 /* Inactivity timer value for transitions into U2 */
131 #define PORT_U2_TIMEOUT(p)	(((p) & 0xff) << 8)
132 #define PORT_U2_TIMEOUT_MASK	(0xff << 8)
133 /* Bits 24:31 for port testing */
134 
135 /* USB2 Protocol PORTSPMSC */
136 #define	PORT_L1S_MASK		7
137 #define	PORT_L1S_SUCCESS	1
138 #define	PORT_RWE		(1 << 3)
139 #define	PORT_HIRD(p)		(((p) & 0xf) << 4)
140 #define	PORT_HIRD_MASK		(0xf << 4)
141 #define	PORT_L1DS_MASK		(0xff << 8)
142 #define	PORT_L1DS(p)		(((p) & 0xff) << 8)
143 #define	PORT_HLE		(1 << 16)
144 #define PORT_TEST_MODE_SHIFT	28
145 
146 /* USB3 Protocol PORTLI  Port Link Information */
147 #define PORT_RX_LANES(p)	(((p) >> 16) & 0xf)
148 #define PORT_TX_LANES(p)	(((p) >> 20) & 0xf)
149 
150 /* USB2 Protocol PORTHLPMC */
151 #define PORT_HIRDM(p)((p) & 3)
152 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
153 #define PORT_BESLD(p)(((p) & 0xf) << 10)
154 
155 /* use 512 microseconds as USB2 LPM L1 default timeout. */
156 #define XHCI_L1_TIMEOUT		512
157 
158 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
159  * Safe to use with mixed HIRD and BESL systems (host and device) and is used
160  * by other operating systems.
161  *
162  * XHCI 1.0 errata 8/14/12 Table 13 notes:
163  * "Software should choose xHC BESL/BESLD field values that do not violate a
164  * device's resume latency requirements,
165  * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
166  * or not program values < '4' if BLC = '0' and a BESL device is attached.
167  */
168 #define XHCI_DEFAULT_BESL	4
169 
170 /*
171  * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
172  * to complete link training. usually link trainig completes much faster
173  * so check status 10 times with 36ms sleep in places we need to wait for
174  * polling to complete.
175  */
176 #define XHCI_PORT_POLLING_LFPS_TIME  36
177