1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 *
5 * Copyright 2005 Tejun Heo
6 *
7 * Based on preview driver from Silicon Image.
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/gfp.h>
13 #include <linux/pci.h>
14 #include <linux/blkdev.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/device.h>
19 #include <scsi/scsi_host.h>
20 #include <scsi/scsi_cmnd.h>
21 #include <linux/libata.h>
22
23 #define DRV_NAME "sata_sil24"
24 #define DRV_VERSION "1.1"
25
26 /*
27 * Port request block (PRB) 32 bytes
28 */
29 struct sil24_prb {
30 __le16 ctrl;
31 __le16 prot;
32 __le32 rx_cnt;
33 u8 fis[6 * 4];
34 };
35
36 /*
37 * Scatter gather entry (SGE) 16 bytes
38 */
39 struct sil24_sge {
40 __le64 addr;
41 __le32 cnt;
42 __le32 flags;
43 };
44
45
46 enum {
47 SIL24_HOST_BAR = 0,
48 SIL24_PORT_BAR = 2,
49
50 /* sil24 fetches in chunks of 64bytes. The first block
51 * contains the PRB and two SGEs. From the second block, it's
52 * consisted of four SGEs and called SGT. Calculate the
53 * number of SGTs that fit into one page.
54 */
55 SIL24_PRB_SZ = sizeof(struct sil24_prb)
56 + 2 * sizeof(struct sil24_sge),
57 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
58 / (4 * sizeof(struct sil24_sge)),
59
60 /* This will give us one unused SGEs for ATA. This extra SGE
61 * will be used to store CDB for ATAPI devices.
62 */
63 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
64
65 /*
66 * Global controller registers (128 bytes @ BAR0)
67 */
68 /* 32 bit regs */
69 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
70 HOST_CTRL = 0x40,
71 HOST_IRQ_STAT = 0x44,
72 HOST_PHY_CFG = 0x48,
73 HOST_BIST_CTRL = 0x50,
74 HOST_BIST_PTRN = 0x54,
75 HOST_BIST_STAT = 0x58,
76 HOST_MEM_BIST_STAT = 0x5c,
77 HOST_FLASH_CMD = 0x70,
78 /* 8 bit regs */
79 HOST_FLASH_DATA = 0x74,
80 HOST_TRANSITION_DETECT = 0x75,
81 HOST_GPIO_CTRL = 0x76,
82 HOST_I2C_ADDR = 0x78, /* 32 bit */
83 HOST_I2C_DATA = 0x7c,
84 HOST_I2C_XFER_CNT = 0x7e,
85 HOST_I2C_CTRL = 0x7f,
86
87 /* HOST_SLOT_STAT bits */
88 HOST_SSTAT_ATTN = (1 << 31),
89
90 /* HOST_CTRL bits */
91 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
92 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
93 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
94 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
95 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
96 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
97
98 /*
99 * Port registers
100 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
101 */
102 PORT_REGS_SIZE = 0x2000,
103
104 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
105 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
106
107 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
108 PORT_PMP_STATUS = 0x0000, /* port device status offset */
109 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
110 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
111
112 /* 32 bit regs */
113 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
114 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
115 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
116 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
117 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
118 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
119 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
120 PORT_CMD_ERR = 0x1024, /* command error number */
121 PORT_FIS_CFG = 0x1028,
122 PORT_FIFO_THRES = 0x102c,
123 /* 16 bit regs */
124 PORT_DECODE_ERR_CNT = 0x1040,
125 PORT_DECODE_ERR_THRESH = 0x1042,
126 PORT_CRC_ERR_CNT = 0x1044,
127 PORT_CRC_ERR_THRESH = 0x1046,
128 PORT_HSHK_ERR_CNT = 0x1048,
129 PORT_HSHK_ERR_THRESH = 0x104a,
130 /* 32 bit regs */
131 PORT_PHY_CFG = 0x1050,
132 PORT_SLOT_STAT = 0x1800,
133 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
134 PORT_CONTEXT = 0x1e04,
135 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
136 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
137 PORT_SCONTROL = 0x1f00,
138 PORT_SSTATUS = 0x1f04,
139 PORT_SERROR = 0x1f08,
140 PORT_SACTIVE = 0x1f0c,
141
142 /* PORT_CTRL_STAT bits */
143 PORT_CS_PORT_RST = (1 << 0), /* port reset */
144 PORT_CS_DEV_RST = (1 << 1), /* device reset */
145 PORT_CS_INIT = (1 << 2), /* port initialize */
146 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
147 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
148 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
149 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
150 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
151 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
152
153 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
154 /* bits[11:0] are masked */
155 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
156 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
157 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
158 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
159 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
160 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
161 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
162 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
163 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
164 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
165 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
166 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
167
168 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
169 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
170 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
171
172 /* bits[27:16] are unmasked (raw) */
173 PORT_IRQ_RAW_SHIFT = 16,
174 PORT_IRQ_MASKED_MASK = 0x7ff,
175 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
176
177 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
178 PORT_IRQ_STEER_SHIFT = 30,
179 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
180
181 /* PORT_CMD_ERR constants */
182 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
183 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
184 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
185 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
186 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
187 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
188 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
189 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
190 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
191 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
192 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
193 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
194 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
195 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
196 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
197 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
198 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
199 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
200 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
201 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
202 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
203 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
204
205 /* bits of PRB control field */
206 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
207 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
208 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
209 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
210 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
211
212 /* PRB protocol field */
213 PRB_PROT_PACKET = (1 << 0),
214 PRB_PROT_TCQ = (1 << 1),
215 PRB_PROT_NCQ = (1 << 2),
216 PRB_PROT_READ = (1 << 3),
217 PRB_PROT_WRITE = (1 << 4),
218 PRB_PROT_TRANSPARENT = (1 << 5),
219
220 /*
221 * Other constants
222 */
223 SGE_TRM = (1 << 31), /* Last SGE in chain */
224 SGE_LNK = (1 << 30), /* linked list
225 Points to SGT, not SGE */
226 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
227 data address ignored */
228
229 SIL24_MAX_CMDS = 31,
230
231 /* board id */
232 BID_SIL3124 = 0,
233 BID_SIL3132 = 1,
234 BID_SIL3131 = 2,
235
236 /* host flags */
237 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
238 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
239 ATA_FLAG_AN | ATA_FLAG_PMP,
240 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
241
242 IRQ_STAT_4PORTS = 0xf,
243 };
244
245 struct sil24_ata_block {
246 struct sil24_prb prb;
247 struct sil24_sge sge[SIL24_MAX_SGE];
248 };
249
250 struct sil24_atapi_block {
251 struct sil24_prb prb;
252 u8 cdb[16];
253 struct sil24_sge sge[SIL24_MAX_SGE];
254 };
255
256 union sil24_cmd_block {
257 struct sil24_ata_block ata;
258 struct sil24_atapi_block atapi;
259 };
260
261 static const struct sil24_cerr_info {
262 unsigned int err_mask, action;
263 const char *desc;
264 } sil24_cerr_db[] = {
265 [0] = { AC_ERR_DEV, 0,
266 "device error" },
267 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
268 "device error via D2H FIS" },
269 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
270 "device error via SDB FIS" },
271 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
272 "error in data FIS" },
273 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
274 "failed to transmit command FIS" },
275 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
276 "protocol mismatch" },
277 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
278 "data direction mismatch" },
279 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
280 "ran out of SGEs while writing" },
281 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
282 "ran out of SGEs while reading" },
283 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
284 "invalid data direction for ATAPI CDB" },
285 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
286 "SGT not on qword boundary" },
287 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
288 "PCI target abort while fetching SGT" },
289 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
290 "PCI master abort while fetching SGT" },
291 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
292 "PCI parity error while fetching SGT" },
293 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
294 "PRB not on qword boundary" },
295 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
296 "PCI target abort while fetching PRB" },
297 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
298 "PCI master abort while fetching PRB" },
299 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
300 "PCI parity error while fetching PRB" },
301 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
302 "undefined error while transferring data" },
303 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
304 "PCI target abort while transferring data" },
305 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
306 "PCI master abort while transferring data" },
307 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
308 "PCI parity error while transferring data" },
309 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
310 "FIS received while sending service FIS" },
311 };
312
313 /*
314 * ap->private_data
315 *
316 * The preview driver always returned 0 for status. We emulate it
317 * here from the previous interrupt.
318 */
319 struct sil24_port_priv {
320 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
321 dma_addr_t cmd_block_dma; /* DMA base addr for them */
322 int do_port_rst;
323 };
324
325 static void sil24_dev_config(struct ata_device *dev);
326 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
327 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
328 static int sil24_qc_defer(struct ata_queued_cmd *qc);
329 static enum ata_completion_errors sil24_qc_prep(struct ata_queued_cmd *qc);
330 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
331 static void sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
332 static void sil24_pmp_attach(struct ata_port *ap);
333 static void sil24_pmp_detach(struct ata_port *ap);
334 static void sil24_freeze(struct ata_port *ap);
335 static void sil24_thaw(struct ata_port *ap);
336 static int sil24_softreset(struct ata_link *link, unsigned int *class,
337 unsigned long deadline);
338 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
339 unsigned long deadline);
340 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
341 unsigned long deadline);
342 static void sil24_error_handler(struct ata_port *ap);
343 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
344 static int sil24_port_start(struct ata_port *ap);
345 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
346 #ifdef CONFIG_PM_SLEEP
347 static int sil24_pci_device_resume(struct pci_dev *pdev);
348 #endif
349 #ifdef CONFIG_PM
350 static int sil24_port_resume(struct ata_port *ap);
351 #endif
352
353 static const struct pci_device_id sil24_pci_tbl[] = {
354 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
355 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
356 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
357 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
358 { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
359 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
360 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
361
362 { } /* terminate list */
363 };
364
365 static struct pci_driver sil24_pci_driver = {
366 .name = DRV_NAME,
367 .id_table = sil24_pci_tbl,
368 .probe = sil24_init_one,
369 .remove = ata_pci_remove_one,
370 #ifdef CONFIG_PM_SLEEP
371 .suspend = ata_pci_device_suspend,
372 .resume = sil24_pci_device_resume,
373 #endif
374 };
375
376 static const struct scsi_host_template sil24_sht = {
377 __ATA_BASE_SHT(DRV_NAME),
378 .can_queue = SIL24_MAX_CMDS,
379 .sg_tablesize = SIL24_MAX_SGE,
380 .dma_boundary = ATA_DMA_BOUNDARY,
381 .sdev_groups = ata_ncq_sdev_groups,
382 .change_queue_depth = ata_scsi_change_queue_depth,
383 .sdev_configure = ata_scsi_sdev_configure
384 };
385
386 static struct ata_port_operations sil24_ops = {
387 .inherits = &sata_pmp_port_ops,
388
389 .qc_defer = sil24_qc_defer,
390 .qc_prep = sil24_qc_prep,
391 .qc_issue = sil24_qc_issue,
392 .qc_fill_rtf = sil24_qc_fill_rtf,
393
394 .freeze = sil24_freeze,
395 .thaw = sil24_thaw,
396 .reset.softreset = sil24_softreset,
397 .reset.hardreset = sil24_hardreset,
398 .pmp_reset.softreset = sil24_softreset,
399 .pmp_reset.hardreset = sil24_pmp_hardreset,
400 .error_handler = sil24_error_handler,
401 .post_internal_cmd = sil24_post_internal_cmd,
402 .dev_config = sil24_dev_config,
403
404 .scr_read = sil24_scr_read,
405 .scr_write = sil24_scr_write,
406 .pmp_attach = sil24_pmp_attach,
407 .pmp_detach = sil24_pmp_detach,
408
409 .port_start = sil24_port_start,
410 #ifdef CONFIG_PM
411 .port_resume = sil24_port_resume,
412 #endif
413 };
414
415 static bool sata_sil24_msi; /* Disable MSI */
416 module_param_named(msi, sata_sil24_msi, bool, S_IRUGO);
417 MODULE_PARM_DESC(msi, "Enable MSI (Default: false)");
418
419 /*
420 * Use bits 30-31 of port_flags to encode available port numbers.
421 * Current maxium is 4.
422 */
423 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
424 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
425
426 static const struct ata_port_info sil24_port_info[] = {
427 /* sil_3124 */
428 {
429 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
430 SIL24_FLAG_PCIX_IRQ_WOC,
431 .pio_mask = ATA_PIO4,
432 .mwdma_mask = ATA_MWDMA2,
433 .udma_mask = ATA_UDMA5,
434 .port_ops = &sil24_ops,
435 },
436 /* sil_3132 */
437 {
438 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
439 .pio_mask = ATA_PIO4,
440 .mwdma_mask = ATA_MWDMA2,
441 .udma_mask = ATA_UDMA5,
442 .port_ops = &sil24_ops,
443 },
444 /* sil_3131/sil_3531 */
445 {
446 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
447 .pio_mask = ATA_PIO4,
448 .mwdma_mask = ATA_MWDMA2,
449 .udma_mask = ATA_UDMA5,
450 .port_ops = &sil24_ops,
451 },
452 };
453
sil24_tag(int tag)454 static int sil24_tag(int tag)
455 {
456 if (unlikely(ata_tag_internal(tag)))
457 return 0;
458 return tag;
459 }
460
sil24_port_offset(struct ata_port * ap)461 static unsigned long sil24_port_offset(struct ata_port *ap)
462 {
463 return ap->port_no * PORT_REGS_SIZE;
464 }
465
sil24_port_base(struct ata_port * ap)466 static void __iomem *sil24_port_base(struct ata_port *ap)
467 {
468 return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
469 }
470
sil24_dev_config(struct ata_device * dev)471 static void sil24_dev_config(struct ata_device *dev)
472 {
473 void __iomem *port = sil24_port_base(dev->link->ap);
474
475 if (dev->cdb_len == 16)
476 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
477 else
478 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
479 }
480
sil24_read_tf(struct ata_port * ap,int tag,struct ata_taskfile * tf)481 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
482 {
483 void __iomem *port = sil24_port_base(ap);
484 struct sil24_prb __iomem *prb;
485 u8 fis[6 * 4];
486
487 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
488 memcpy_fromio(fis, prb->fis, sizeof(fis));
489 ata_tf_from_fis(fis, tf);
490 }
491
492 static int sil24_scr_map[] = {
493 [SCR_CONTROL] = 0,
494 [SCR_STATUS] = 1,
495 [SCR_ERROR] = 2,
496 [SCR_ACTIVE] = 3,
497 };
498
sil24_scr_read(struct ata_link * link,unsigned sc_reg,u32 * val)499 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
500 {
501 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
502
503 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
504 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
505 return 0;
506 }
507 return -EINVAL;
508 }
509
sil24_scr_write(struct ata_link * link,unsigned sc_reg,u32 val)510 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
511 {
512 void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
513
514 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
515 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
516 return 0;
517 }
518 return -EINVAL;
519 }
520
sil24_config_port(struct ata_port * ap)521 static void sil24_config_port(struct ata_port *ap)
522 {
523 void __iomem *port = sil24_port_base(ap);
524
525 /* configure IRQ WoC */
526 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
527 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
528 else
529 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
530
531 /* zero error counters. */
532 writew(0x8000, port + PORT_DECODE_ERR_THRESH);
533 writew(0x8000, port + PORT_CRC_ERR_THRESH);
534 writew(0x8000, port + PORT_HSHK_ERR_THRESH);
535 writew(0x0000, port + PORT_DECODE_ERR_CNT);
536 writew(0x0000, port + PORT_CRC_ERR_CNT);
537 writew(0x0000, port + PORT_HSHK_ERR_CNT);
538
539 /* always use 64bit activation */
540 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
541
542 /* clear port multiplier enable and resume bits */
543 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
544 }
545
sil24_config_pmp(struct ata_port * ap,int attached)546 static void sil24_config_pmp(struct ata_port *ap, int attached)
547 {
548 void __iomem *port = sil24_port_base(ap);
549
550 if (attached)
551 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
552 else
553 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
554 }
555
sil24_clear_pmp(struct ata_port * ap)556 static void sil24_clear_pmp(struct ata_port *ap)
557 {
558 void __iomem *port = sil24_port_base(ap);
559 int i;
560
561 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
562
563 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
564 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
565
566 writel(0, pmp_base + PORT_PMP_STATUS);
567 writel(0, pmp_base + PORT_PMP_QACTIVE);
568 }
569 }
570
sil24_init_port(struct ata_port * ap)571 static int sil24_init_port(struct ata_port *ap)
572 {
573 void __iomem *port = sil24_port_base(ap);
574 struct sil24_port_priv *pp = ap->private_data;
575 u32 tmp;
576
577 /* clear PMP error status */
578 if (sata_pmp_attached(ap))
579 sil24_clear_pmp(ap);
580
581 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
582 ata_wait_register(ap, port + PORT_CTRL_STAT,
583 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
584 tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
585 PORT_CS_RDY, 0, 10, 100);
586
587 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
588 pp->do_port_rst = 1;
589 ap->link.eh_context.i.action |= ATA_EH_RESET;
590 return -EIO;
591 }
592
593 return 0;
594 }
595
sil24_exec_polled_cmd(struct ata_port * ap,int pmp,const struct ata_taskfile * tf,int is_cmd,u32 ctrl,unsigned int timeout_msec)596 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
597 const struct ata_taskfile *tf,
598 int is_cmd, u32 ctrl,
599 unsigned int timeout_msec)
600 {
601 void __iomem *port = sil24_port_base(ap);
602 struct sil24_port_priv *pp = ap->private_data;
603 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
604 dma_addr_t paddr = pp->cmd_block_dma;
605 u32 irq_enabled, irq_mask, irq_stat;
606 int rc;
607
608 prb->ctrl = cpu_to_le16(ctrl);
609 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
610
611 /* temporarily plug completion and error interrupts */
612 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
613 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
614
615 /*
616 * The barrier is required to ensure that writes to cmd_block reach
617 * the memory before the write to PORT_CMD_ACTIVATE.
618 */
619 wmb();
620 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
621 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
622
623 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
624 irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
625 10, timeout_msec);
626
627 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
628 irq_stat >>= PORT_IRQ_RAW_SHIFT;
629
630 if (irq_stat & PORT_IRQ_COMPLETE)
631 rc = 0;
632 else {
633 /* force port into known state */
634 sil24_init_port(ap);
635
636 if (irq_stat & PORT_IRQ_ERROR)
637 rc = -EIO;
638 else
639 rc = -EBUSY;
640 }
641
642 /* restore IRQ enabled */
643 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
644
645 return rc;
646 }
647
sil24_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)648 static int sil24_softreset(struct ata_link *link, unsigned int *class,
649 unsigned long deadline)
650 {
651 struct ata_port *ap = link->ap;
652 int pmp = sata_srst_pmp(link);
653 unsigned int timeout_msec = 0;
654 struct ata_taskfile tf;
655 const char *reason;
656 int rc;
657
658 /* put the port into known state */
659 if (sil24_init_port(ap)) {
660 reason = "port not ready";
661 goto err;
662 }
663
664 /* do SRST */
665 if (time_after(deadline, jiffies))
666 timeout_msec = jiffies_to_msecs(deadline - jiffies);
667
668 ata_tf_init(link->device, &tf); /* doesn't really matter */
669 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
670 timeout_msec);
671 if (rc == -EBUSY) {
672 reason = "timeout";
673 goto err;
674 } else if (rc) {
675 reason = "SRST command error";
676 goto err;
677 }
678
679 sil24_read_tf(ap, 0, &tf);
680 *class = ata_port_classify(ap, &tf);
681
682 return 0;
683
684 err:
685 ata_link_err(link, "softreset failed (%s)\n", reason);
686 return -EIO;
687 }
688
sil24_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)689 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
690 unsigned long deadline)
691 {
692 struct ata_port *ap = link->ap;
693 void __iomem *port = sil24_port_base(ap);
694 struct sil24_port_priv *pp = ap->private_data;
695 int did_port_rst = 0;
696 const char *reason;
697 int tout_msec, rc;
698 u32 tmp;
699
700 retry:
701 /* Sometimes, DEV_RST is not enough to recover the controller.
702 * This happens often after PM DMA CS errata.
703 */
704 if (pp->do_port_rst) {
705 ata_port_warn(ap,
706 "controller in dubious state, performing PORT_RST\n");
707
708 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
709 ata_msleep(ap, 10);
710 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
711 ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
712 10, 5000);
713
714 /* restore port configuration */
715 sil24_config_port(ap);
716 sil24_config_pmp(ap, ap->nr_pmp_links);
717
718 pp->do_port_rst = 0;
719 did_port_rst = 1;
720 }
721
722 /* sil24 does the right thing(tm) without any protection */
723 sata_set_spd(link);
724
725 tout_msec = 100;
726 if (ata_link_online(link))
727 tout_msec = 5000;
728
729 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
730 tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
731 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
732 tout_msec);
733
734 /* SStatus oscillates between zero and valid status after
735 * DEV_RST, debounce it.
736 */
737 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
738 if (rc) {
739 reason = "PHY debouncing failed";
740 goto err;
741 }
742
743 if (tmp & PORT_CS_DEV_RST) {
744 if (ata_link_offline(link))
745 return 0;
746 reason = "link not ready";
747 goto err;
748 }
749
750 /* Sil24 doesn't store signature FIS after hardreset, so we
751 * can't wait for BSY to clear. Some devices take a long time
752 * to get ready and those devices will choke if we don't wait
753 * for BSY clearance here. Tell libata to perform follow-up
754 * softreset.
755 */
756 return -EAGAIN;
757
758 err:
759 if (!did_port_rst) {
760 pp->do_port_rst = 1;
761 goto retry;
762 }
763
764 ata_link_err(link, "hardreset failed (%s)\n", reason);
765 return -EIO;
766 }
767
sil24_fill_sg(struct ata_queued_cmd * qc,struct sil24_sge * sge)768 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
769 struct sil24_sge *sge)
770 {
771 struct scatterlist *sg;
772 struct sil24_sge *last_sge = NULL;
773 unsigned int si;
774
775 for_each_sg(qc->sg, sg, qc->n_elem, si) {
776 sge->addr = cpu_to_le64(sg_dma_address(sg));
777 sge->cnt = cpu_to_le32(sg_dma_len(sg));
778 sge->flags = 0;
779
780 last_sge = sge;
781 sge++;
782 }
783
784 last_sge->flags = cpu_to_le32(SGE_TRM);
785 }
786
sil24_qc_defer(struct ata_queued_cmd * qc)787 static int sil24_qc_defer(struct ata_queued_cmd *qc)
788 {
789 struct ata_link *link = qc->dev->link;
790 struct ata_port *ap = link->ap;
791 u8 prot = qc->tf.protocol;
792 int ret;
793
794 /*
795 * There is a bug in the chip:
796 * Port LRAM Causes the PRB/SGT Data to be Corrupted
797 * If the host issues a read request for LRAM and SActive registers
798 * while active commands are available in the port, PRB/SGT data in
799 * the LRAM can become corrupted. This issue applies only when
800 * reading from, but not writing to, the LRAM.
801 *
802 * Therefore, reading LRAM when there is no particular error [and
803 * other commands may be outstanding] is prohibited.
804 *
805 * To avoid this bug there are two situations where a command must run
806 * exclusive of any other commands on the port:
807 *
808 * - ATAPI commands which check the sense data
809 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
810 * set.
811 *
812 */
813 int is_excl = (ata_is_atapi(prot) ||
814 (qc->flags & ATA_QCFLAG_RESULT_TF));
815
816 if (unlikely(ap->excl_link)) {
817 if (link == ap->excl_link) {
818 if (ap->nr_active_links)
819 return ATA_DEFER_PORT;
820 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
821 } else
822 return ATA_DEFER_PORT;
823 } else if (unlikely(is_excl)) {
824 ap->excl_link = link;
825 if (ap->nr_active_links)
826 return ATA_DEFER_PORT;
827 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
828 }
829
830 ret = ata_std_qc_defer(qc);
831 if (ret == ATA_DEFER_LINK)
832 return ATA_DEFER_LINK_EXCL;
833 return ret;
834 }
835
sil24_qc_prep(struct ata_queued_cmd * qc)836 static enum ata_completion_errors sil24_qc_prep(struct ata_queued_cmd *qc)
837 {
838 struct ata_port *ap = qc->ap;
839 struct sil24_port_priv *pp = ap->private_data;
840 union sil24_cmd_block *cb;
841 struct sil24_prb *prb;
842 struct sil24_sge *sge;
843 u16 ctrl = 0;
844
845 cb = &pp->cmd_block[sil24_tag(qc->hw_tag)];
846
847 if (!ata_is_atapi(qc->tf.protocol)) {
848 prb = &cb->ata.prb;
849 sge = cb->ata.sge;
850 if (ata_is_data(qc->tf.protocol)) {
851 u16 prot = 0;
852 ctrl = PRB_CTRL_PROTOCOL;
853 if (ata_is_ncq(qc->tf.protocol))
854 prot |= PRB_PROT_NCQ;
855 if (qc->tf.flags & ATA_TFLAG_WRITE)
856 prot |= PRB_PROT_WRITE;
857 else
858 prot |= PRB_PROT_READ;
859 prb->prot = cpu_to_le16(prot);
860 }
861 } else {
862 prb = &cb->atapi.prb;
863 sge = cb->atapi.sge;
864 memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));
865 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
866
867 if (ata_is_data(qc->tf.protocol)) {
868 if (qc->tf.flags & ATA_TFLAG_WRITE)
869 ctrl = PRB_CTRL_PACKET_WRITE;
870 else
871 ctrl = PRB_CTRL_PACKET_READ;
872 }
873 }
874
875 prb->ctrl = cpu_to_le16(ctrl);
876 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
877
878 if (qc->flags & ATA_QCFLAG_DMAMAP)
879 sil24_fill_sg(qc, sge);
880
881 return AC_ERR_OK;
882 }
883
sil24_qc_issue(struct ata_queued_cmd * qc)884 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
885 {
886 struct ata_port *ap = qc->ap;
887 struct sil24_port_priv *pp = ap->private_data;
888 void __iomem *port = sil24_port_base(ap);
889 unsigned int tag = sil24_tag(qc->hw_tag);
890 dma_addr_t paddr;
891 void __iomem *activate;
892
893 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
894 activate = port + PORT_CMD_ACTIVATE + tag * 8;
895
896 /*
897 * The barrier is required to ensure that writes to cmd_block reach
898 * the memory before the write to PORT_CMD_ACTIVATE.
899 */
900 wmb();
901 writel((u32)paddr, activate);
902 writel((u64)paddr >> 32, activate + 4);
903
904 return 0;
905 }
906
sil24_qc_fill_rtf(struct ata_queued_cmd * qc)907 static void sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
908 {
909 sil24_read_tf(qc->ap, qc->hw_tag, &qc->result_tf);
910 }
911
sil24_pmp_attach(struct ata_port * ap)912 static void sil24_pmp_attach(struct ata_port *ap)
913 {
914 u32 *gscr = ap->link.device->gscr;
915
916 sil24_config_pmp(ap, 1);
917 sil24_init_port(ap);
918
919 if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
920 sata_pmp_gscr_devid(gscr) == 0x4140) {
921 ata_port_info(ap,
922 "disabling NCQ support due to sil24-mv4140 quirk\n");
923 ap->flags &= ~ATA_FLAG_NCQ;
924 }
925 }
926
sil24_pmp_detach(struct ata_port * ap)927 static void sil24_pmp_detach(struct ata_port *ap)
928 {
929 sil24_init_port(ap);
930 sil24_config_pmp(ap, 0);
931
932 ap->flags |= ATA_FLAG_NCQ;
933 }
934
sil24_pmp_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)935 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
936 unsigned long deadline)
937 {
938 int rc;
939
940 rc = sil24_init_port(link->ap);
941 if (rc) {
942 ata_link_err(link, "hardreset failed (port not ready)\n");
943 return rc;
944 }
945
946 return sata_std_hardreset(link, class, deadline);
947 }
948
sil24_freeze(struct ata_port * ap)949 static void sil24_freeze(struct ata_port *ap)
950 {
951 void __iomem *port = sil24_port_base(ap);
952
953 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
954 * PORT_IRQ_ENABLE instead.
955 */
956 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
957 }
958
sil24_thaw(struct ata_port * ap)959 static void sil24_thaw(struct ata_port *ap)
960 {
961 void __iomem *port = sil24_port_base(ap);
962 u32 tmp;
963
964 /* clear IRQ */
965 tmp = readl(port + PORT_IRQ_STAT);
966 writel(tmp, port + PORT_IRQ_STAT);
967
968 /* turn IRQ back on */
969 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
970 }
971
sil24_error_intr(struct ata_port * ap)972 static void sil24_error_intr(struct ata_port *ap)
973 {
974 void __iomem *port = sil24_port_base(ap);
975 struct sil24_port_priv *pp = ap->private_data;
976 struct ata_queued_cmd *qc = NULL;
977 struct ata_link *link;
978 struct ata_eh_info *ehi;
979 int abort = 0, freeze = 0;
980 u32 irq_stat;
981
982 /* on error, we need to clear IRQ explicitly */
983 irq_stat = readl(port + PORT_IRQ_STAT);
984 writel(irq_stat, port + PORT_IRQ_STAT);
985
986 /* first, analyze and record host port events */
987 link = &ap->link;
988 ehi = &link->eh_info;
989 ata_ehi_clear_desc(ehi);
990
991 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
992
993 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
994 ata_ehi_push_desc(ehi, "SDB notify");
995 sata_async_notification(ap);
996 }
997
998 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
999 ata_ehi_hotplugged(ehi);
1000 ata_ehi_push_desc(ehi, "%s",
1001 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1002 "PHY RDY changed" : "device exchanged");
1003 freeze = 1;
1004 }
1005
1006 if (irq_stat & PORT_IRQ_UNK_FIS) {
1007 ehi->err_mask |= AC_ERR_HSM;
1008 ehi->action |= ATA_EH_RESET;
1009 ata_ehi_push_desc(ehi, "unknown FIS");
1010 freeze = 1;
1011 }
1012
1013 /* deal with command error */
1014 if (irq_stat & PORT_IRQ_ERROR) {
1015 const struct sil24_cerr_info *ci = NULL;
1016 unsigned int err_mask = 0, action = 0;
1017 u32 context, cerr;
1018 int pmp;
1019
1020 abort = 1;
1021
1022 /* DMA Context Switch Failure in Port Multiplier Mode
1023 * errata. If we have active commands to 3 or more
1024 * devices, any error condition on active devices can
1025 * corrupt DMA context switching.
1026 */
1027 if (ap->nr_active_links >= 3) {
1028 ehi->err_mask |= AC_ERR_OTHER;
1029 ehi->action |= ATA_EH_RESET;
1030 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1031 pp->do_port_rst = 1;
1032 freeze = 1;
1033 }
1034
1035 /* find out the offending link and qc */
1036 if (sata_pmp_attached(ap)) {
1037 context = readl(port + PORT_CONTEXT);
1038 pmp = (context >> 5) & 0xf;
1039
1040 if (pmp < ap->nr_pmp_links) {
1041 link = &ap->pmp_link[pmp];
1042 ehi = &link->eh_info;
1043 qc = ata_qc_from_tag(ap, link->active_tag);
1044
1045 ata_ehi_clear_desc(ehi);
1046 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1047 irq_stat);
1048 } else {
1049 err_mask |= AC_ERR_HSM;
1050 action |= ATA_EH_RESET;
1051 freeze = 1;
1052 }
1053 } else
1054 qc = ata_qc_from_tag(ap, link->active_tag);
1055
1056 /* analyze CMD_ERR */
1057 cerr = readl(port + PORT_CMD_ERR);
1058 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1059 ci = &sil24_cerr_db[cerr];
1060
1061 if (ci && ci->desc) {
1062 err_mask |= ci->err_mask;
1063 action |= ci->action;
1064 if (action & ATA_EH_RESET)
1065 freeze = 1;
1066 ata_ehi_push_desc(ehi, "%s", ci->desc);
1067 } else {
1068 err_mask |= AC_ERR_OTHER;
1069 action |= ATA_EH_RESET;
1070 freeze = 1;
1071 ata_ehi_push_desc(ehi, "unknown command error %d",
1072 cerr);
1073 }
1074
1075 /* record error info */
1076 if (qc)
1077 qc->err_mask |= err_mask;
1078 else
1079 ehi->err_mask |= err_mask;
1080
1081 ehi->action |= action;
1082
1083 /* if PMP, resume */
1084 if (sata_pmp_attached(ap))
1085 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1086 }
1087
1088 /* freeze or abort */
1089 if (freeze)
1090 ata_port_freeze(ap);
1091 else if (abort) {
1092 if (qc)
1093 ata_link_abort(qc->dev->link);
1094 else
1095 ata_port_abort(ap);
1096 }
1097 }
1098
sil24_host_intr(struct ata_port * ap)1099 static inline void sil24_host_intr(struct ata_port *ap)
1100 {
1101 void __iomem *port = sil24_port_base(ap);
1102 u32 slot_stat, qc_active;
1103 int rc;
1104
1105 /* If PCIX_IRQ_WOC, there's an inherent race window between
1106 * clearing IRQ pending status and reading PORT_SLOT_STAT
1107 * which may cause spurious interrupts afterwards. This is
1108 * unavoidable and much better than losing interrupts which
1109 * happens if IRQ pending is cleared after reading
1110 * PORT_SLOT_STAT.
1111 */
1112 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1113 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1114
1115 slot_stat = readl(port + PORT_SLOT_STAT);
1116
1117 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1118 sil24_error_intr(ap);
1119 return;
1120 }
1121
1122 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1123 rc = ata_qc_complete_multiple(ap, qc_active);
1124 if (rc > 0)
1125 return;
1126 if (rc < 0) {
1127 struct ata_eh_info *ehi = &ap->link.eh_info;
1128 ehi->err_mask |= AC_ERR_HSM;
1129 ehi->action |= ATA_EH_RESET;
1130 ata_port_freeze(ap);
1131 return;
1132 }
1133
1134 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1135 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1136 ata_port_info(ap,
1137 "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1138 slot_stat, ap->link.active_tag, ap->link.sactive);
1139 }
1140
sil24_interrupt(int irq,void * dev_instance)1141 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1142 {
1143 struct ata_host *host = dev_instance;
1144 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1145 unsigned handled = 0;
1146 u32 status;
1147 int i;
1148
1149 status = readl(host_base + HOST_IRQ_STAT);
1150
1151 if (status == 0xffffffff) {
1152 dev_err(host->dev, "IRQ status == 0xffffffff, "
1153 "PCI fault or device removal?\n");
1154 goto out;
1155 }
1156
1157 if (!(status & IRQ_STAT_4PORTS))
1158 goto out;
1159
1160 spin_lock(&host->lock);
1161
1162 for (i = 0; i < host->n_ports; i++)
1163 if (status & (1 << i)) {
1164 sil24_host_intr(host->ports[i]);
1165 handled++;
1166 }
1167
1168 spin_unlock(&host->lock);
1169 out:
1170 return IRQ_RETVAL(handled);
1171 }
1172
sil24_error_handler(struct ata_port * ap)1173 static void sil24_error_handler(struct ata_port *ap)
1174 {
1175 struct sil24_port_priv *pp = ap->private_data;
1176
1177 if (sil24_init_port(ap))
1178 ata_eh_freeze_port(ap);
1179
1180 sata_pmp_error_handler(ap);
1181
1182 pp->do_port_rst = 0;
1183 }
1184
sil24_post_internal_cmd(struct ata_queued_cmd * qc)1185 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1186 {
1187 struct ata_port *ap = qc->ap;
1188
1189 /* make DMA engine forget about the failed command */
1190 if ((qc->flags & ATA_QCFLAG_EH) && sil24_init_port(ap))
1191 ata_eh_freeze_port(ap);
1192 }
1193
sil24_port_start(struct ata_port * ap)1194 static int sil24_port_start(struct ata_port *ap)
1195 {
1196 struct device *dev = ap->host->dev;
1197 struct sil24_port_priv *pp;
1198 union sil24_cmd_block *cb;
1199 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1200 dma_addr_t cb_dma;
1201
1202 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1203 if (!pp)
1204 return -ENOMEM;
1205
1206 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1207 if (!cb)
1208 return -ENOMEM;
1209
1210 pp->cmd_block = cb;
1211 pp->cmd_block_dma = cb_dma;
1212
1213 ap->private_data = pp;
1214
1215 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1216 ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
1217
1218 return 0;
1219 }
1220
sil24_init_controller(struct ata_host * host)1221 static void sil24_init_controller(struct ata_host *host)
1222 {
1223 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1224 u32 tmp;
1225 int i;
1226
1227 /* GPIO off */
1228 writel(0, host_base + HOST_FLASH_CMD);
1229
1230 /* clear global reset & mask interrupts during initialization */
1231 writel(0, host_base + HOST_CTRL);
1232
1233 /* init ports */
1234 for (i = 0; i < host->n_ports; i++) {
1235 struct ata_port *ap = host->ports[i];
1236 void __iomem *port = sil24_port_base(ap);
1237
1238
1239 /* Initial PHY setting */
1240 writel(0x20c, port + PORT_PHY_CFG);
1241
1242 /* Clear port RST */
1243 tmp = readl(port + PORT_CTRL_STAT);
1244 if (tmp & PORT_CS_PORT_RST) {
1245 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1246 tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
1247 PORT_CS_PORT_RST,
1248 PORT_CS_PORT_RST, 10, 100);
1249 if (tmp & PORT_CS_PORT_RST)
1250 dev_err(host->dev,
1251 "failed to clear port RST\n");
1252 }
1253
1254 /* configure port */
1255 sil24_config_port(ap);
1256 }
1257
1258 /* Turn on interrupts */
1259 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1260 }
1261
sil24_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1262 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1263 {
1264 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1265 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1266 const struct ata_port_info *ppi[] = { &pi, NULL };
1267 void __iomem * const *iomap;
1268 struct ata_host *host;
1269 int rc;
1270 u32 tmp;
1271
1272 /* cause link error if sil24_cmd_block is sized wrongly */
1273 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1274 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1275
1276 ata_print_version_once(&pdev->dev, DRV_VERSION);
1277
1278 /* acquire resources */
1279 rc = pcim_enable_device(pdev);
1280 if (rc)
1281 return rc;
1282
1283 rc = pcim_iomap_regions(pdev,
1284 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1285 DRV_NAME);
1286 if (rc)
1287 return rc;
1288 iomap = pcim_iomap_table(pdev);
1289
1290 /* apply workaround for completion IRQ loss on PCI-X errata */
1291 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1292 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1293 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1294 dev_info(&pdev->dev,
1295 "Applying completion IRQ loss on PCI-X errata fix\n");
1296 else
1297 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1298 }
1299
1300 /* allocate and fill host */
1301 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1302 SIL24_FLAG2NPORTS(ppi[0]->flags));
1303 if (!host)
1304 return -ENOMEM;
1305 host->iomap = iomap;
1306
1307 /* configure and activate the device */
1308 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1309 if (rc) {
1310 dev_err(&pdev->dev, "DMA enable failed\n");
1311 return rc;
1312 }
1313
1314 /* Set max read request size to 4096. This slightly increases
1315 * write throughput for pci-e variants.
1316 */
1317 pcie_set_readrq(pdev, 4096);
1318
1319 sil24_init_controller(host);
1320
1321 if (sata_sil24_msi && !pci_enable_msi(pdev)) {
1322 dev_info(&pdev->dev, "Using MSI\n");
1323 pcim_intx(pdev, 0);
1324 }
1325
1326 pci_set_master(pdev);
1327 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1328 &sil24_sht);
1329 }
1330
1331 #ifdef CONFIG_PM_SLEEP
sil24_pci_device_resume(struct pci_dev * pdev)1332 static int sil24_pci_device_resume(struct pci_dev *pdev)
1333 {
1334 struct ata_host *host = pci_get_drvdata(pdev);
1335 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1336 int rc;
1337
1338 rc = ata_pci_device_do_resume(pdev);
1339 if (rc)
1340 return rc;
1341
1342 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1343 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1344
1345 sil24_init_controller(host);
1346
1347 ata_host_resume(host);
1348
1349 return 0;
1350 }
1351 #endif
1352
1353 #ifdef CONFIG_PM
sil24_port_resume(struct ata_port * ap)1354 static int sil24_port_resume(struct ata_port *ap)
1355 {
1356 sil24_config_pmp(ap, ap->nr_pmp_links);
1357 return 0;
1358 }
1359 #endif
1360
1361 module_pci_driver(sil24_pci_driver);
1362
1363 MODULE_AUTHOR("Tejun Heo");
1364 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1365 MODULE_LICENSE("GPL");
1366 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1367