1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2021 Xilinx
6 * Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 * Davorin Mista <davorin.mista@aggios.com>
10 * Jolly Shah <jollys@xilinx.com>
11 * Rajan Vaja <rajanv@xilinx.com>
12 */
13
14 #ifndef __FIRMWARE_ZYNQMP_H__
15 #define __FIRMWARE_ZYNQMP_H__
16 #include <linux/types.h>
17
18 #include <linux/err.h>
19 #include <linux/firmware/xlnx-zynqmp-ufs.h>
20
21 #define ZYNQMP_PM_VERSION_MAJOR 1
22 #define ZYNQMP_PM_VERSION_MINOR 0
23
24 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
25 ZYNQMP_PM_VERSION_MINOR)
26
27 #define ZYNQMP_TZ_VERSION_MAJOR 1
28 #define ZYNQMP_TZ_VERSION_MINOR 0
29
30 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
31 ZYNQMP_TZ_VERSION_MINOR)
32
33 /* SMC SIP service Call Function Identifier Prefix */
34 #define PM_SIP_SVC 0xC2000000
35
36 /* SMC function ID to get SiP SVC version */
37 #define GET_SIP_SVC_VERSION (0x8200ff03U)
38
39 /* SiP Service Calls version numbers */
40 #define SIP_SVC_VERSION_MAJOR (0U)
41 #define SIP_SVC_VERSION_MINOR (2U)
42
43 #define SIP_SVC_PASSTHROUGH_VERSION ((SIP_SVC_VERSION_MAJOR << 16) | \
44 SIP_SVC_VERSION_MINOR)
45
46 /* Fixed ID for FW specific APIs */
47 #define PASS_THROUGH_FW_CMD_ID GENMASK(11, 0)
48
49 /* PM API versions */
50 #define PM_API_VERSION_1 1
51 #define PM_API_VERSION_2 2
52
53 #define PM_PINCTRL_PARAM_SET_VERSION 2
54
55 /* Family codes */
56 #define PM_ZYNQMP_FAMILY_CODE 0x1 /* ZynqMP family code */
57 #define PM_VERSAL_FAMILY_CODE 0x2 /* Versal family code */
58 #define PM_VERSAL_NET_FAMILY_CODE 0x3 /* Versal NET family code */
59
60 #define API_ID_MASK GENMASK(7, 0)
61 #define MODULE_ID_MASK GENMASK(11, 8)
62 #define PLM_MODULE_ID_MASK GENMASK(15, 8)
63
64 /* Firmware feature check version mask */
65 #define FIRMWARE_VERSION_MASK 0xFFFFU
66
67 /* ATF only commands */
68 #define TF_A_PM_REGISTER_SGI 0xa04
69 #define PM_GET_TRUSTZONE_VERSION 0xa03
70 #define PM_SET_SUSPEND_MODE 0xa02
71 #define GET_CALLBACK_DATA 0xa01
72
73 /* Number of 32bits values in payload */
74 #define PAYLOAD_ARG_CNT 7U
75
76 /* Number of 64bits arguments for SMC call */
77 #define SMC_ARG_CNT_64 8U
78
79 /* Number of 32bits arguments for SMC call */
80 #define SMC_ARG_CNT_32 13U
81
82 /* Number of arguments for a callback */
83 #define CB_ARG_CNT 4
84
85 /* Payload size (consists of callback API ID + arguments) */
86 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
87
88 #define ZYNQMP_PM_MAX_QOS 100U
89
90 #define GSS_NUM_REGS (4)
91
92 /* Node capabilities */
93 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
94 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
95 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
96 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
97
98 /* Loader commands */
99 #define PM_LOAD_PDI 0x701
100 #define PDI_SRC_DDR 0xF
101
102 /*
103 * Firmware FPGA Manager flags
104 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
105 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
106 */
107 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
108 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
109
110 /* FPGA Status Reg */
111 #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
112 #define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U
113
114 /*
115 * Node IDs for the Error Events.
116 */
117 #define VERSAL_EVENT_ERROR_PMC_ERR1 (0x28100000U)
118 #define VERSAL_EVENT_ERROR_PMC_ERR2 (0x28104000U)
119 #define VERSAL_EVENT_ERROR_PSM_ERR1 (0x28108000U)
120 #define VERSAL_EVENT_ERROR_PSM_ERR2 (0x2810C000U)
121
122 #define VERSAL_NET_EVENT_ERROR_PMC_ERR1 (0x28100000U)
123 #define VERSAL_NET_EVENT_ERROR_PMC_ERR2 (0x28104000U)
124 #define VERSAL_NET_EVENT_ERROR_PMC_ERR3 (0x28108000U)
125 #define VERSAL_NET_EVENT_ERROR_PSM_ERR1 (0x2810C000U)
126 #define VERSAL_NET_EVENT_ERROR_PSM_ERR2 (0x28110000U)
127 #define VERSAL_NET_EVENT_ERROR_PSM_ERR3 (0x28114000U)
128 #define VERSAL_NET_EVENT_ERROR_PSM_ERR4 (0x28118000U)
129
130 /* ZynqMP SD tap delay tuning */
131 #define SD_ITAPDLY 0xFF180314
132 #define SD_OTAPDLYSEL 0xFF180318
133
134 /**
135 * XPM_EVENT_ERROR_MASK_DDRMC_CR: Error event mask for DDRMC MC Correctable ECC Error.
136 */
137 #define XPM_EVENT_ERROR_MASK_DDRMC_CR BIT(18)
138
139 /**
140 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error.
141 */
142 #define XPM_EVENT_ERROR_MASK_DDRMC_NCR BIT(19)
143 #define XPM_EVENT_ERROR_MASK_NOC_NCR BIT(13)
144 #define XPM_EVENT_ERROR_MASK_NOC_CR BIT(12)
145
146 enum pm_module_id {
147 PM_MODULE_ID = 0x0,
148 XPM_MODULE_ID = 0x2,
149 XSEM_MODULE_ID = 0x3,
150 TF_A_MODULE_ID = 0xa,
151 };
152
153 enum pm_api_cb_id {
154 PM_INIT_SUSPEND_CB = 30,
155 PM_ACKNOWLEDGE_CB = 31,
156 PM_NOTIFY_CB = 32,
157 };
158
159 enum pm_api_id {
160 PM_API_FEATURES = 0,
161 PM_GET_API_VERSION = 1,
162 PM_GET_NODE_STATUS = 3,
163 PM_REGISTER_NOTIFIER = 5,
164 PM_FORCE_POWERDOWN = 8,
165 PM_REQUEST_WAKEUP = 10,
166 PM_SYSTEM_SHUTDOWN = 12,
167 PM_REQUEST_NODE = 13,
168 PM_RELEASE_NODE = 14,
169 PM_SET_REQUIREMENT = 15,
170 PM_RESET_ASSERT = 17,
171 PM_RESET_GET_STATUS = 18,
172 PM_MMIO_WRITE = 19,
173 PM_MMIO_READ = 20,
174 PM_PM_INIT_FINALIZE = 21,
175 PM_FPGA_LOAD = 22,
176 PM_FPGA_GET_STATUS = 23,
177 PM_GET_CHIPID = 24,
178 PM_SECURE_SHA = 26,
179 PM_PINCTRL_REQUEST = 28,
180 PM_PINCTRL_RELEASE = 29,
181 PM_PINCTRL_SET_FUNCTION = 31,
182 PM_PINCTRL_CONFIG_PARAM_GET = 32,
183 PM_PINCTRL_CONFIG_PARAM_SET = 33,
184 PM_IOCTL = 34,
185 PM_QUERY_DATA = 35,
186 PM_CLOCK_ENABLE = 36,
187 PM_CLOCK_DISABLE = 37,
188 PM_CLOCK_GETSTATE = 38,
189 PM_CLOCK_SETDIVIDER = 39,
190 PM_CLOCK_GETDIVIDER = 40,
191 PM_CLOCK_SETPARENT = 43,
192 PM_CLOCK_GETPARENT = 44,
193 PM_FPGA_READ = 46,
194 PM_SECURE_AES = 47,
195 PM_EFUSE_ACCESS = 53,
196 PM_FEATURE_CHECK = 63,
197 };
198
199 /* PMU-FW return status codes */
200 enum pm_ret_status {
201 XST_PM_SUCCESS = 0,
202 XST_PM_INVALID_VERSION = 4,
203 XST_PM_NO_FEATURE = 19,
204 XST_PM_INVALID_CRC = 301,
205 XST_PM_INTERNAL = 2000,
206 XST_PM_CONFLICT = 2001,
207 XST_PM_NO_ACCESS = 2002,
208 XST_PM_INVALID_NODE = 2003,
209 XST_PM_DOUBLE_REQ = 2004,
210 XST_PM_ABORT_SUSPEND = 2005,
211 XST_PM_MULT_USER = 2008,
212 };
213
214 enum pm_ioctl_id {
215 IOCTL_GET_RPU_OPER_MODE = 0,
216 IOCTL_SET_RPU_OPER_MODE = 1,
217 IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
218 IOCTL_TCM_COMB_CONFIG = 3,
219 IOCTL_SET_TAPDELAY_BYPASS = 4,
220 IOCTL_SD_DLL_RESET = 6,
221 IOCTL_SET_SD_TAPDELAY = 7,
222 IOCTL_SET_PLL_FRAC_MODE = 8,
223 IOCTL_GET_PLL_FRAC_MODE = 9,
224 IOCTL_SET_PLL_FRAC_DATA = 10,
225 IOCTL_GET_PLL_FRAC_DATA = 11,
226 IOCTL_WRITE_GGS = 12,
227 IOCTL_READ_GGS = 13,
228 IOCTL_WRITE_PGGS = 14,
229 IOCTL_READ_PGGS = 15,
230 /* Set healthy bit value */
231 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
232 IOCTL_OSPI_MUX_SELECT = 21,
233 /* Register SGI to ATF */
234 IOCTL_REGISTER_SGI = 25,
235 /* Runtime feature configuration */
236 IOCTL_SET_FEATURE_CONFIG = 26,
237 IOCTL_GET_FEATURE_CONFIG = 27,
238 /* IOCTL for Secure Read/Write Interface */
239 IOCTL_READ_REG = 28,
240 IOCTL_MASK_WRITE_REG = 29,
241 /* Dynamic SD/GEM configuration */
242 IOCTL_SET_SD_CONFIG = 30,
243 IOCTL_SET_GEM_CONFIG = 31,
244 /* IOCTL to get default/current QoS */
245 IOCTL_GET_QOS = 34,
246 };
247
248 enum pm_query_id {
249 PM_QID_INVALID = 0,
250 PM_QID_CLOCK_GET_NAME = 1,
251 PM_QID_CLOCK_GET_TOPOLOGY = 2,
252 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
253 PM_QID_CLOCK_GET_PARENTS = 4,
254 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
255 PM_QID_PINCTRL_GET_NUM_PINS = 6,
256 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
257 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
258 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
259 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
260 PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
261 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
262 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
263 PM_QID_PINCTRL_GET_ATTRIBUTES = 15,
264 };
265
266 enum rpu_oper_mode {
267 PM_RPU_MODE_LOCKSTEP = 0,
268 PM_RPU_MODE_SPLIT = 1,
269 };
270
271 enum rpu_boot_mem {
272 PM_RPU_BOOTMEM_LOVEC = 0,
273 PM_RPU_BOOTMEM_HIVEC = 1,
274 };
275
276 enum rpu_tcm_comb {
277 PM_RPU_TCM_SPLIT = 0,
278 PM_RPU_TCM_COMB = 1,
279 };
280
281 enum zynqmp_pm_reset_action {
282 PM_RESET_ACTION_RELEASE = 0,
283 PM_RESET_ACTION_ASSERT = 1,
284 PM_RESET_ACTION_PULSE = 2,
285 };
286
287 enum zynqmp_pm_reset {
288 ZYNQMP_PM_RESET_START = 1000,
289 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
290 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
291 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
292 ZYNQMP_PM_RESET_DP = 1003,
293 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
294 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
295 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
296 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
297 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
298 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
299 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
300 ZYNQMP_PM_RESET_GDMA = 1011,
301 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
302 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
303 ZYNQMP_PM_RESET_GPU = 1014,
304 ZYNQMP_PM_RESET_GT = 1015,
305 ZYNQMP_PM_RESET_SATA = 1016,
306 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
307 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
308 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
309 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
310 ZYNQMP_PM_RESET_APU_L2 = 1021,
311 ZYNQMP_PM_RESET_ACPU3 = 1022,
312 ZYNQMP_PM_RESET_ACPU2 = 1023,
313 ZYNQMP_PM_RESET_ACPU1 = 1024,
314 ZYNQMP_PM_RESET_ACPU0 = 1025,
315 ZYNQMP_PM_RESET_DDR = 1026,
316 ZYNQMP_PM_RESET_APM_FPD = 1027,
317 ZYNQMP_PM_RESET_SOFT = 1028,
318 ZYNQMP_PM_RESET_GEM0 = 1029,
319 ZYNQMP_PM_RESET_GEM1 = 1030,
320 ZYNQMP_PM_RESET_GEM2 = 1031,
321 ZYNQMP_PM_RESET_GEM3 = 1032,
322 ZYNQMP_PM_RESET_QSPI = 1033,
323 ZYNQMP_PM_RESET_UART0 = 1034,
324 ZYNQMP_PM_RESET_UART1 = 1035,
325 ZYNQMP_PM_RESET_SPI0 = 1036,
326 ZYNQMP_PM_RESET_SPI1 = 1037,
327 ZYNQMP_PM_RESET_SDIO0 = 1038,
328 ZYNQMP_PM_RESET_SDIO1 = 1039,
329 ZYNQMP_PM_RESET_CAN0 = 1040,
330 ZYNQMP_PM_RESET_CAN1 = 1041,
331 ZYNQMP_PM_RESET_I2C0 = 1042,
332 ZYNQMP_PM_RESET_I2C1 = 1043,
333 ZYNQMP_PM_RESET_TTC0 = 1044,
334 ZYNQMP_PM_RESET_TTC1 = 1045,
335 ZYNQMP_PM_RESET_TTC2 = 1046,
336 ZYNQMP_PM_RESET_TTC3 = 1047,
337 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
338 ZYNQMP_PM_RESET_NAND = 1049,
339 ZYNQMP_PM_RESET_ADMA = 1050,
340 ZYNQMP_PM_RESET_GPIO = 1051,
341 ZYNQMP_PM_RESET_IOU_CC = 1052,
342 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
343 ZYNQMP_PM_RESET_RPU_R50 = 1054,
344 ZYNQMP_PM_RESET_RPU_R51 = 1055,
345 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
346 ZYNQMP_PM_RESET_OCM = 1057,
347 ZYNQMP_PM_RESET_RPU_PGE = 1058,
348 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
349 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
350 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
351 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
352 ZYNQMP_PM_RESET_USB0_APB = 1063,
353 ZYNQMP_PM_RESET_USB1_APB = 1064,
354 ZYNQMP_PM_RESET_IPI = 1065,
355 ZYNQMP_PM_RESET_APM_LPD = 1066,
356 ZYNQMP_PM_RESET_RTC = 1067,
357 ZYNQMP_PM_RESET_SYSMON = 1068,
358 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
359 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
360 ZYNQMP_PM_RESET_FPD = 1071,
361 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
362 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
363 ZYNQMP_PM_RESET_DBG_LPD = 1074,
364 ZYNQMP_PM_RESET_DBG_FPD = 1075,
365 ZYNQMP_PM_RESET_APLL = 1076,
366 ZYNQMP_PM_RESET_DPLL = 1077,
367 ZYNQMP_PM_RESET_VPLL = 1078,
368 ZYNQMP_PM_RESET_IOPLL = 1079,
369 ZYNQMP_PM_RESET_RPLL = 1080,
370 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
371 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
372 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
373 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
374 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
375 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
376 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
377 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
378 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
379 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
380 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
381 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
382 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
383 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
384 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
385 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
386 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
387 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
388 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
389 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
390 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
391 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
392 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
393 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
394 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
395 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
396 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
397 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
398 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
399 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
400 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
401 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
402 ZYNQMP_PM_RESET_RPU_LS = 1113,
403 ZYNQMP_PM_RESET_PS_ONLY = 1114,
404 ZYNQMP_PM_RESET_PL = 1115,
405 ZYNQMP_PM_RESET_PS_PL0 = 1116,
406 ZYNQMP_PM_RESET_PS_PL1 = 1117,
407 ZYNQMP_PM_RESET_PS_PL2 = 1118,
408 ZYNQMP_PM_RESET_PS_PL3 = 1119,
409 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
410 };
411
412 enum zynqmp_pm_suspend_reason {
413 SUSPEND_POWER_REQUEST = 201,
414 SUSPEND_ALERT = 202,
415 SUSPEND_SYSTEM_SHUTDOWN = 203,
416 };
417
418 enum zynqmp_pm_request_ack {
419 ZYNQMP_PM_REQUEST_ACK_NO = 1,
420 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
421 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
422 };
423
424 enum pm_node_id {
425 NODE_SD_0 = 39,
426 NODE_SD_1 = 40,
427 };
428
429 enum tap_delay_type {
430 PM_TAPDELAY_INPUT = 0,
431 PM_TAPDELAY_OUTPUT = 1,
432 };
433
434 enum dll_reset_type {
435 PM_DLL_RESET_ASSERT = 0,
436 PM_DLL_RESET_RELEASE = 1,
437 PM_DLL_RESET_PULSE = 2,
438 };
439
440 enum pm_pinctrl_config_param {
441 PM_PINCTRL_CONFIG_SLEW_RATE = 0,
442 PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
443 PM_PINCTRL_CONFIG_PULL_CTRL = 2,
444 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
445 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
446 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
447 PM_PINCTRL_CONFIG_TRI_STATE = 6,
448 PM_PINCTRL_CONFIG_MAX = 7,
449 };
450
451 enum pm_pinctrl_slew_rate {
452 PM_PINCTRL_SLEW_RATE_FAST = 0,
453 PM_PINCTRL_SLEW_RATE_SLOW = 1,
454 };
455
456 enum pm_pinctrl_bias_status {
457 PM_PINCTRL_BIAS_DISABLE = 0,
458 PM_PINCTRL_BIAS_ENABLE = 1,
459 };
460
461 enum pm_pinctrl_pull_ctrl {
462 PM_PINCTRL_BIAS_PULL_DOWN = 0,
463 PM_PINCTRL_BIAS_PULL_UP = 1,
464 };
465
466 enum pm_pinctrl_schmitt_cmos {
467 PM_PINCTRL_INPUT_TYPE_CMOS = 0,
468 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
469 };
470
471 enum pm_pinctrl_drive_strength {
472 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
473 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
474 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
475 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
476 };
477
478 enum pm_pinctrl_tri_state {
479 PM_PINCTRL_TRI_STATE_DISABLE = 0,
480 PM_PINCTRL_TRI_STATE_ENABLE = 1,
481 };
482
483 enum zynqmp_pm_shutdown_type {
484 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
485 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
486 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
487 };
488
489 enum zynqmp_pm_shutdown_subtype {
490 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
491 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
492 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
493 };
494
495 enum tap_delay_signal_type {
496 PM_TAPDELAY_NAND_DQS_IN = 0,
497 PM_TAPDELAY_NAND_DQS_OUT = 1,
498 PM_TAPDELAY_QSPI = 2,
499 PM_TAPDELAY_MAX = 3,
500 };
501
502 enum tap_delay_bypass_ctrl {
503 PM_TAPDELAY_BYPASS_DISABLE = 0,
504 PM_TAPDELAY_BYPASS_ENABLE = 1,
505 };
506
507 enum ospi_mux_select_type {
508 PM_OSPI_MUX_SEL_DMA = 0,
509 PM_OSPI_MUX_SEL_LINEAR = 1,
510 };
511
512 enum pm_feature_config_id {
513 PM_FEATURE_INVALID = 0,
514 PM_FEATURE_OVERTEMP_STATUS = 1,
515 PM_FEATURE_OVERTEMP_VALUE = 2,
516 PM_FEATURE_EXTWDT_STATUS = 3,
517 PM_FEATURE_EXTWDT_VALUE = 4,
518 };
519
520 /**
521 * enum pm_sd_config_type - PM SD configuration.
522 * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
523 * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
524 * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
525 * @SD_CONFIG_FIXED: To set fixed config registers
526 */
527 enum pm_sd_config_type {
528 SD_CONFIG_EMMC_SEL = 1,
529 SD_CONFIG_BASECLK = 2,
530 SD_CONFIG_8BIT = 3,
531 SD_CONFIG_FIXED = 4,
532 };
533
534 /**
535 * enum pm_gem_config_type - PM GEM configuration.
536 * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
537 * @GEM_CONFIG_FIXED: To set fixed config registers
538 */
539 enum pm_gem_config_type {
540 GEM_CONFIG_SGMII_MODE = 1,
541 GEM_CONFIG_FIXED = 2,
542 };
543
544 /**
545 * struct zynqmp_pm_query_data - PM query data
546 * @qid: query ID
547 * @arg1: Argument 1 of query data
548 * @arg2: Argument 2 of query data
549 * @arg3: Argument 3 of query data
550 */
551 struct zynqmp_pm_query_data {
552 u32 qid;
553 u32 arg1;
554 u32 arg2;
555 u32 arg3;
556 };
557
558 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...);
559 int zynqmp_pm_invoke_fw_fn(u32 pm_api_id, u32 *ret_payload, u32 num_args, ...);
560
561 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
562 int zynqmp_pm_get_api_version(u32 *version);
563 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
564 int zynqmp_pm_get_family_info(u32 *family);
565 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
566 int zynqmp_pm_clock_enable(u32 clock_id);
567 int zynqmp_pm_clock_disable(u32 clock_id);
568 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
569 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
570 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
571 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
572 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
573 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
574 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
575 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
576 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
577 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
578 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
579 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
580 int zynqmp_pm_reset_assert(const u32 reset,
581 const enum zynqmp_pm_reset_action assert_flag);
582 int zynqmp_pm_reset_get_status(const u32 reset, u32 *status);
583 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
584 int zynqmp_pm_bootmode_write(u32 ps_mode);
585 int zynqmp_pm_set_suspend_mode(u32 mode);
586 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
587 const u32 qos, const enum zynqmp_pm_request_ack ack);
588 int zynqmp_pm_release_node(const u32 node);
589 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
590 const u32 qos,
591 const enum zynqmp_pm_request_ack ack);
592 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
593 int zynqmp_pm_efuse_access(const u64 address, u32 *out);
594 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
595 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
596 int zynqmp_pm_fpga_get_status(u32 *value);
597 int zynqmp_pm_fpga_get_config_status(u32 *value);
598 int zynqmp_pm_write_ggs(u32 index, u32 value);
599 int zynqmp_pm_read_ggs(u32 index, u32 *value);
600 int zynqmp_pm_write_pggs(u32 index, u32 value);
601 int zynqmp_pm_read_pggs(u32 index, u32 *value);
602 int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value);
603 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
604 int zynqmp_pm_set_boot_health_status(u32 value);
605 int zynqmp_pm_pinctrl_request(const u32 pin);
606 int zynqmp_pm_pinctrl_release(const u32 pin);
607 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
608 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
609 u32 *value);
610 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
611 u32 value);
612 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
613 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
614 const u32 wake, const u32 enable);
615 int zynqmp_pm_feature(const u32 api_id);
616 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
617 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
618 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
619 int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value);
620 int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset,
621 u32 mask, u32 value);
622 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
623 int zynqmp_pm_force_pwrdwn(const u32 target,
624 const enum zynqmp_pm_request_ack ack);
625 int zynqmp_pm_request_wake(const u32 node,
626 const bool set_addr,
627 const u64 address,
628 const enum zynqmp_pm_request_ack ack);
629 int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode);
630 int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode);
631 int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode);
632 int zynqmp_pm_get_node_status(const u32 node, u32 *const status,
633 u32 *const requirements, u32 *const usage);
634 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
635 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
636 u32 value);
637 #else
zynqmp_pm_get_api_version(u32 * version)638 static inline int zynqmp_pm_get_api_version(u32 *version)
639 {
640 return -ENODEV;
641 }
642
zynqmp_pm_get_chipid(u32 * idcode,u32 * version)643 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
644 {
645 return -ENODEV;
646 }
647
zynqmp_pm_get_family_info(u32 * family)648 static inline int zynqmp_pm_get_family_info(u32 *family)
649 {
650 return -ENODEV;
651 }
652
zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,u32 * out)653 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
654 u32 *out)
655 {
656 return -ENODEV;
657 }
658
zynqmp_pm_clock_enable(u32 clock_id)659 static inline int zynqmp_pm_clock_enable(u32 clock_id)
660 {
661 return -ENODEV;
662 }
663
zynqmp_pm_clock_disable(u32 clock_id)664 static inline int zynqmp_pm_clock_disable(u32 clock_id)
665 {
666 return -ENODEV;
667 }
668
zynqmp_pm_clock_getstate(u32 clock_id,u32 * state)669 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
670 {
671 return -ENODEV;
672 }
673
zynqmp_pm_clock_setdivider(u32 clock_id,u32 divider)674 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
675 {
676 return -ENODEV;
677 }
678
zynqmp_pm_clock_getdivider(u32 clock_id,u32 * divider)679 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
680 {
681 return -ENODEV;
682 }
683
zynqmp_pm_clock_setparent(u32 clock_id,u32 parent_id)684 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
685 {
686 return -ENODEV;
687 }
688
zynqmp_pm_clock_getparent(u32 clock_id,u32 * parent_id)689 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
690 {
691 return -ENODEV;
692 }
693
zynqmp_pm_set_pll_frac_mode(u32 clk_id,u32 mode)694 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
695 {
696 return -ENODEV;
697 }
698
zynqmp_pm_get_pll_frac_mode(u32 clk_id,u32 * mode)699 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
700 {
701 return -ENODEV;
702 }
703
zynqmp_pm_set_pll_frac_data(u32 clk_id,u32 data)704 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
705 {
706 return -ENODEV;
707 }
708
zynqmp_pm_get_pll_frac_data(u32 clk_id,u32 * data)709 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
710 {
711 return -ENODEV;
712 }
713
zynqmp_pm_set_sd_tapdelay(u32 node_id,u32 type,u32 value)714 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
715 {
716 return -ENODEV;
717 }
718
zynqmp_pm_sd_dll_reset(u32 node_id,u32 type)719 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
720 {
721 return -ENODEV;
722 }
723
zynqmp_pm_ospi_mux_select(u32 dev_id,u32 select)724 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
725 {
726 return -ENODEV;
727 }
728
zynqmp_pm_reset_assert(const u32 reset,const enum zynqmp_pm_reset_action assert_flag)729 static inline int zynqmp_pm_reset_assert(const u32 reset,
730 const enum zynqmp_pm_reset_action assert_flag)
731 {
732 return -ENODEV;
733 }
734
zynqmp_pm_reset_get_status(const u32 reset,u32 * status)735 static inline int zynqmp_pm_reset_get_status(const u32 reset, u32 *status)
736 {
737 return -ENODEV;
738 }
739
zynqmp_pm_bootmode_read(u32 * ps_mode)740 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
741 {
742 return -ENODEV;
743 }
744
zynqmp_pm_bootmode_write(u32 ps_mode)745 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
746 {
747 return -ENODEV;
748 }
749
zynqmp_pm_set_suspend_mode(u32 mode)750 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
751 {
752 return -ENODEV;
753 }
754
zynqmp_pm_request_node(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)755 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
756 const u32 qos,
757 const enum zynqmp_pm_request_ack ack)
758 {
759 return -ENODEV;
760 }
761
zynqmp_pm_release_node(const u32 node)762 static inline int zynqmp_pm_release_node(const u32 node)
763 {
764 return -ENODEV;
765 }
766
zynqmp_pm_set_requirement(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)767 static inline int zynqmp_pm_set_requirement(const u32 node,
768 const u32 capabilities,
769 const u32 qos,
770 const enum zynqmp_pm_request_ack ack)
771 {
772 return -ENODEV;
773 }
774
zynqmp_pm_aes_engine(const u64 address,u32 * out)775 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
776 {
777 return -ENODEV;
778 }
779
zynqmp_pm_efuse_access(const u64 address,u32 * out)780 static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out)
781 {
782 return -ENODEV;
783 }
784
zynqmp_pm_sha_hash(const u64 address,const u32 size,const u32 flags)785 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
786 const u32 flags)
787 {
788 return -ENODEV;
789 }
790
zynqmp_pm_fpga_load(const u64 address,const u32 size,const u32 flags)791 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
792 const u32 flags)
793 {
794 return -ENODEV;
795 }
796
zynqmp_pm_fpga_get_status(u32 * value)797 static inline int zynqmp_pm_fpga_get_status(u32 *value)
798 {
799 return -ENODEV;
800 }
801
zynqmp_pm_fpga_get_config_status(u32 * value)802 static inline int zynqmp_pm_fpga_get_config_status(u32 *value)
803 {
804 return -ENODEV;
805 }
806
zynqmp_pm_write_ggs(u32 index,u32 value)807 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
808 {
809 return -ENODEV;
810 }
811
zynqmp_pm_read_ggs(u32 index,u32 * value)812 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
813 {
814 return -ENODEV;
815 }
816
zynqmp_pm_write_pggs(u32 index,u32 value)817 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
818 {
819 return -ENODEV;
820 }
821
zynqmp_pm_read_pggs(u32 index,u32 * value)822 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
823 {
824 return -ENODEV;
825 }
826
zynqmp_pm_set_tapdelay_bypass(u32 index,u32 value)827 static inline int zynqmp_pm_set_tapdelay_bypass(u32 index, u32 value)
828 {
829 return -ENODEV;
830 }
831
zynqmp_pm_system_shutdown(const u32 type,const u32 subtype)832 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
833 {
834 return -ENODEV;
835 }
836
zynqmp_pm_set_boot_health_status(u32 value)837 static inline int zynqmp_pm_set_boot_health_status(u32 value)
838 {
839 return -ENODEV;
840 }
841
zynqmp_pm_pinctrl_request(const u32 pin)842 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
843 {
844 return -ENODEV;
845 }
846
zynqmp_pm_pinctrl_release(const u32 pin)847 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
848 {
849 return -ENODEV;
850 }
851
zynqmp_pm_is_function_supported(const u32 api_id,const u32 id)852 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
853 {
854 return -ENODEV;
855 }
856
zynqmp_pm_pinctrl_set_function(const u32 pin,const u32 id)857 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
858 {
859 return -ENODEV;
860 }
861
zynqmp_pm_pinctrl_get_config(const u32 pin,const u32 param,u32 * value)862 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
863 u32 *value)
864 {
865 return -ENODEV;
866 }
867
zynqmp_pm_pinctrl_set_config(const u32 pin,const u32 param,u32 value)868 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
869 u32 value)
870 {
871 return -ENODEV;
872 }
873
zynqmp_pm_load_pdi(const u32 src,const u64 address)874 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
875 {
876 return -ENODEV;
877 }
878
zynqmp_pm_register_notifier(const u32 node,const u32 event,const u32 wake,const u32 enable)879 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
880 const u32 wake, const u32 enable)
881 {
882 return -ENODEV;
883 }
884
zynqmp_pm_feature(const u32 api_id)885 static inline int zynqmp_pm_feature(const u32 api_id)
886 {
887 return -ENODEV;
888 }
889
zynqmp_pm_set_feature_config(enum pm_feature_config_id id,u32 value)890 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
891 u32 value)
892 {
893 return -ENODEV;
894 }
895
zynqmp_pm_get_feature_config(enum pm_feature_config_id id,u32 * payload)896 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
897 u32 *payload)
898 {
899 return -ENODEV;
900 }
901
zynqmp_pm_register_sgi(u32 sgi_num,u32 reset)902 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
903 {
904 return -ENODEV;
905 }
906
zynqmp_pm_force_pwrdwn(const u32 target,const enum zynqmp_pm_request_ack ack)907 static inline int zynqmp_pm_force_pwrdwn(const u32 target,
908 const enum zynqmp_pm_request_ack ack)
909 {
910 return -ENODEV;
911 }
912
zynqmp_pm_request_wake(const u32 node,const bool set_addr,const u64 address,const enum zynqmp_pm_request_ack ack)913 static inline int zynqmp_pm_request_wake(const u32 node,
914 const bool set_addr,
915 const u64 address,
916 const enum zynqmp_pm_request_ack ack)
917 {
918 return -ENODEV;
919 }
920
zynqmp_pm_sec_read_reg(u32 node_id,u32 offset,u32 * ret_value)921 static inline int zynqmp_pm_sec_read_reg(u32 node_id, u32 offset, u32 *ret_value)
922 {
923 return -ENODEV;
924 }
925
zynqmp_pm_sec_mask_write_reg(const u32 node_id,const u32 offset,u32 mask,u32 value)926 static inline int zynqmp_pm_sec_mask_write_reg(const u32 node_id, const u32 offset,
927 u32 mask, u32 value)
928 {
929 return -ENODEV;
930 }
931
zynqmp_pm_get_rpu_mode(u32 node_id,enum rpu_oper_mode * rpu_mode)932 static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode)
933 {
934 return -ENODEV;
935 }
936
zynqmp_pm_set_rpu_mode(u32 node_id,enum rpu_oper_mode rpu_mode)937 static inline int zynqmp_pm_set_rpu_mode(u32 node_id, enum rpu_oper_mode rpu_mode)
938 {
939 return -ENODEV;
940 }
941
zynqmp_pm_set_tcm_config(u32 node_id,enum rpu_tcm_comb tcm_mode)942 static inline int zynqmp_pm_set_tcm_config(u32 node_id, enum rpu_tcm_comb tcm_mode)
943 {
944 return -ENODEV;
945 }
946
zynqmp_pm_get_node_status(const u32 node,u32 * const status,u32 * const requirements,u32 * const usage)947 static inline int zynqmp_pm_get_node_status(const u32 node, u32 *const status,
948 u32 *const requirements,
949 u32 *const usage)
950 {
951 return -ENODEV;
952 }
953
zynqmp_pm_set_sd_config(u32 node,enum pm_sd_config_type config,u32 value)954 static inline int zynqmp_pm_set_sd_config(u32 node,
955 enum pm_sd_config_type config,
956 u32 value)
957 {
958 return -ENODEV;
959 }
960
zynqmp_pm_set_gem_config(u32 node,enum pm_gem_config_type config,u32 value)961 static inline int zynqmp_pm_set_gem_config(u32 node,
962 enum pm_gem_config_type config,
963 u32 value)
964 {
965 return -ENODEV;
966 }
967
968 #endif
969
970 #endif /* __FIRMWARE_ZYNQMP_H__ */
971