1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/gpio/driver.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_irq.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/seq_file.h>
15 #include <linux/slab.h>
16 #include <linux/spmi.h>
17 #include <linux/string_choices.h>
18 #include <linux/types.h>
19
20 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/pinctrl/pinconf.h>
22 #include <linux/pinctrl/pinmux.h>
23
24 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
25
26 #include "../core.h"
27 #include "../pinctrl-utils.h"
28
29 #define PMIC_GPIO_ADDRESS_RANGE 0x100
30
31 /* type and subtype registers base address offsets */
32 #define PMIC_GPIO_REG_TYPE 0x4
33 #define PMIC_GPIO_REG_SUBTYPE 0x5
34
35 /* GPIO peripheral type and subtype out_values */
36 #define PMIC_GPIO_TYPE 0x10
37 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
38 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
39 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
40 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
41 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
42 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
43 #define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2 0x12
44 #define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3 0x13
45 #define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK 0x14
46 #define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK 0x15
47
48 #define PMIC_MPP_REG_RT_STS 0x10
49 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
50
51 /* control register base address offsets */
52 #define PMIC_GPIO_REG_MODE_CTL 0x40
53 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
54 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
55 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
56 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
57 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
58 #define PMIC_GPIO_REG_EN_CTL 0x46
59 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
60
61 /* PMIC_GPIO_REG_MODE_CTL */
62 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
63 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
64 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
65 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
66 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
67
68 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
69 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
70 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
71 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
72 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
73
74 /* PMIC_GPIO_REG_DIG_VIN_CTL */
75 #define PMIC_GPIO_REG_VIN_SHIFT 0
76 #define PMIC_GPIO_REG_VIN_MASK 0x7
77
78 /* PMIC_GPIO_REG_DIG_PULL_CTL */
79 #define PMIC_GPIO_REG_PULL_SHIFT 0
80 #define PMIC_GPIO_REG_PULL_MASK 0x7
81
82 #define PMIC_GPIO_PULL_DOWN 4
83 #define PMIC_GPIO_PULL_DISABLE 5
84
85 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
86 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
87 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
88 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
89
90 /* PMIC_GPIO_REG_DIG_IN_CTL */
91 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
92 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
93 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
94
95 /* PMIC_GPIO_REG_DIG_OUT_CTL */
96 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
97 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
98 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
99 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
100
101 /*
102 * Output type - indicates pin should be configured as push-pull,
103 * open drain or open source.
104 */
105 #define PMIC_GPIO_OUT_BUF_CMOS 0
106 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
107 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
108
109 #define PMIC_GPIO_OUT_STRENGTH_LOW 1
110 #define PMIC_GPIO_OUT_STRENGTH_HIGH 3
111
112 /* PMIC_GPIO_REG_EN_CTL */
113 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
114
115 #define PMIC_GPIO_PHYSICAL_OFFSET 1
116
117 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
118 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
119
120 /* Qualcomm specific pin configurations */
121 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
122 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
123 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
124 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
125 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
126
127 /* The index of each function in pmic_gpio_functions[] array */
128 enum pmic_gpio_func_index {
129 PMIC_GPIO_FUNC_INDEX_NORMAL,
130 PMIC_GPIO_FUNC_INDEX_PAIRED,
131 PMIC_GPIO_FUNC_INDEX_FUNC1,
132 PMIC_GPIO_FUNC_INDEX_FUNC2,
133 PMIC_GPIO_FUNC_INDEX_FUNC3,
134 PMIC_GPIO_FUNC_INDEX_FUNC4,
135 PMIC_GPIO_FUNC_INDEX_DTEST1,
136 PMIC_GPIO_FUNC_INDEX_DTEST2,
137 PMIC_GPIO_FUNC_INDEX_DTEST3,
138 PMIC_GPIO_FUNC_INDEX_DTEST4,
139 };
140
141 /**
142 * struct pmic_gpio_pad - keep current GPIO settings
143 * @base: Address base in SPMI device.
144 * @is_enabled: Set to false when GPIO should be put in high Z state.
145 * @out_value: Cached pin output value
146 * @have_buffer: Set to true if GPIO output could be configured in push-pull,
147 * open-drain or open-source mode.
148 * @output_enabled: Set to true if GPIO output logic is enabled.
149 * @input_enabled: Set to true if GPIO input buffer logic is enabled.
150 * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
151 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
152 * @num_sources: Number of power-sources supported by this GPIO.
153 * @power_source: Current power-source used.
154 * @buffer_type: Push-pull, open-drain or open-source.
155 * @pullup: Constant current which flow trough GPIO output buffer.
156 * @strength: No, Low, Medium, High
157 * @function: See pmic_gpio_functions[]
158 * @atest: the ATEST selection for GPIO analog-pass-through mode
159 * @dtest_buffer: the DTEST buffer selection for digital input mode.
160 */
161 struct pmic_gpio_pad {
162 u16 base;
163 bool is_enabled;
164 bool out_value;
165 bool have_buffer;
166 bool output_enabled;
167 bool input_enabled;
168 bool analog_pass;
169 bool lv_mv_type;
170 unsigned int num_sources;
171 unsigned int power_source;
172 unsigned int buffer_type;
173 unsigned int pullup;
174 unsigned int strength;
175 unsigned int function;
176 unsigned int atest;
177 unsigned int dtest_buffer;
178 };
179
180 struct pmic_gpio_state {
181 struct device *dev;
182 struct regmap *map;
183 struct pinctrl_dev *ctrl;
184 struct gpio_chip chip;
185 u8 usid;
186 u8 pid_base;
187 };
188
189 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
190 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
191 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
192 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
193 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
194 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
195 };
196
197 #ifdef CONFIG_DEBUG_FS
198 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
199 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
200 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
201 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
202 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
203 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
204 };
205 #endif
206
207 static const char *const pmic_gpio_groups[] = {
208 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
209 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
210 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
211 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
212 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
213 };
214
215 static const char *const pmic_gpio_functions[] = {
216 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
217 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
218 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
219 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
220 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
221 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
222 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
223 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
224 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
225 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
226 };
227
pmic_gpio_read(struct pmic_gpio_state * state,struct pmic_gpio_pad * pad,unsigned int addr)228 static int pmic_gpio_read(struct pmic_gpio_state *state,
229 struct pmic_gpio_pad *pad, unsigned int addr)
230 {
231 unsigned int val;
232 int ret;
233
234 ret = regmap_read(state->map, pad->base + addr, &val);
235 if (ret < 0)
236 dev_err(state->dev, "read 0x%x failed\n", addr);
237 else
238 ret = val;
239
240 return ret;
241 }
242
pmic_gpio_write(struct pmic_gpio_state * state,struct pmic_gpio_pad * pad,unsigned int addr,unsigned int val)243 static int pmic_gpio_write(struct pmic_gpio_state *state,
244 struct pmic_gpio_pad *pad, unsigned int addr,
245 unsigned int val)
246 {
247 int ret;
248
249 ret = regmap_write(state->map, pad->base + addr, val);
250 if (ret < 0)
251 dev_err(state->dev, "write 0x%x failed\n", addr);
252
253 return ret;
254 }
255
pmic_gpio_get_groups_count(struct pinctrl_dev * pctldev)256 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
257 {
258 /* Every PIN is a group */
259 return pctldev->desc->npins;
260 }
261
pmic_gpio_get_group_name(struct pinctrl_dev * pctldev,unsigned pin)262 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
263 unsigned pin)
264 {
265 return pctldev->desc->pins[pin].name;
266 }
267
pmic_gpio_get_group_pins(struct pinctrl_dev * pctldev,unsigned pin,const unsigned ** pins,unsigned * num_pins)268 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
269 const unsigned **pins, unsigned *num_pins)
270 {
271 *pins = &pctldev->desc->pins[pin].number;
272 *num_pins = 1;
273 return 0;
274 }
275
276 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
277 .get_groups_count = pmic_gpio_get_groups_count,
278 .get_group_name = pmic_gpio_get_group_name,
279 .get_group_pins = pmic_gpio_get_group_pins,
280 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
281 .dt_free_map = pinctrl_utils_free_map,
282 };
283
pmic_gpio_get_functions_count(struct pinctrl_dev * pctldev)284 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
285 {
286 return ARRAY_SIZE(pmic_gpio_functions);
287 }
288
pmic_gpio_get_function_name(struct pinctrl_dev * pctldev,unsigned function)289 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
290 unsigned function)
291 {
292 return pmic_gpio_functions[function];
293 }
294
pmic_gpio_get_function_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_qgroups)295 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
296 unsigned function,
297 const char *const **groups,
298 unsigned *const num_qgroups)
299 {
300 *groups = pmic_gpio_groups;
301 *num_qgroups = pctldev->desc->npins;
302 return 0;
303 }
304
pmic_gpio_set_mux(struct pinctrl_dev * pctldev,unsigned function,unsigned pin)305 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
306 unsigned pin)
307 {
308 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
309 struct pmic_gpio_pad *pad;
310 unsigned int val;
311 int ret;
312
313 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
314 pr_err("function: %d is not defined\n", function);
315 return -EINVAL;
316 }
317
318 pad = pctldev->desc->pins[pin].drv_data;
319 /*
320 * Non-LV/MV subtypes only support 2 special functions,
321 * offsetting the dtestx function values by 2
322 */
323 if (!pad->lv_mv_type) {
324 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
325 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
326 pr_err("LV/MV subtype doesn't have func3/func4\n");
327 return -EINVAL;
328 }
329 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
330 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
331 PMIC_GPIO_FUNC_INDEX_FUNC3);
332 }
333
334 pad->function = function;
335
336 if (pad->analog_pass)
337 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
338 else if (pad->output_enabled && pad->input_enabled)
339 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
340 else if (pad->output_enabled)
341 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
342 else
343 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
344
345 if (pad->lv_mv_type) {
346 ret = pmic_gpio_write(state, pad,
347 PMIC_GPIO_REG_MODE_CTL, val);
348 if (ret < 0)
349 return ret;
350
351 val = pad->atest - 1;
352 ret = pmic_gpio_write(state, pad,
353 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
354 if (ret < 0)
355 return ret;
356
357 val = pad->out_value
358 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
359 val |= pad->function
360 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
361 ret = pmic_gpio_write(state, pad,
362 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
363 if (ret < 0)
364 return ret;
365 } else {
366 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
367 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
368 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
369
370 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
371 if (ret < 0)
372 return ret;
373 }
374
375 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
376
377 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
378 }
379
380 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
381 .get_functions_count = pmic_gpio_get_functions_count,
382 .get_function_name = pmic_gpio_get_function_name,
383 .get_function_groups = pmic_gpio_get_function_groups,
384 .set_mux = pmic_gpio_set_mux,
385 };
386
pmic_gpio_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)387 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
388 unsigned int pin, unsigned long *config)
389 {
390 unsigned param = pinconf_to_config_param(*config);
391 struct pmic_gpio_pad *pad;
392 unsigned arg;
393
394 pad = pctldev->desc->pins[pin].drv_data;
395
396 switch (param) {
397 case PIN_CONFIG_DRIVE_PUSH_PULL:
398 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
399 return -EINVAL;
400 arg = 1;
401 break;
402 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
403 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
404 return -EINVAL;
405 arg = 1;
406 break;
407 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
408 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
409 return -EINVAL;
410 arg = 1;
411 break;
412 case PIN_CONFIG_BIAS_PULL_DOWN:
413 if (pad->pullup != PMIC_GPIO_PULL_DOWN)
414 return -EINVAL;
415 arg = 1;
416 break;
417 case PIN_CONFIG_BIAS_DISABLE:
418 if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
419 return -EINVAL;
420 arg = 1;
421 break;
422 case PIN_CONFIG_BIAS_PULL_UP:
423 if (pad->pullup != PMIC_GPIO_PULL_UP_30)
424 return -EINVAL;
425 arg = 1;
426 break;
427 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
428 if (pad->is_enabled)
429 return -EINVAL;
430 arg = 1;
431 break;
432 case PIN_CONFIG_POWER_SOURCE:
433 arg = pad->power_source;
434 break;
435 case PIN_CONFIG_INPUT_ENABLE:
436 if (!pad->input_enabled)
437 return -EINVAL;
438 arg = 1;
439 break;
440 case PIN_CONFIG_OUTPUT_ENABLE:
441 arg = pad->output_enabled;
442 break;
443 case PIN_CONFIG_LEVEL:
444 arg = pad->out_value;
445 break;
446 case PMIC_GPIO_CONF_PULL_UP:
447 arg = pad->pullup;
448 break;
449 case PMIC_GPIO_CONF_STRENGTH:
450 switch (pad->strength) {
451 case PMIC_GPIO_OUT_STRENGTH_HIGH:
452 arg = PMIC_GPIO_STRENGTH_HIGH;
453 break;
454 case PMIC_GPIO_OUT_STRENGTH_LOW:
455 arg = PMIC_GPIO_STRENGTH_LOW;
456 break;
457 default:
458 arg = pad->strength;
459 break;
460 }
461 break;
462 case PMIC_GPIO_CONF_ATEST:
463 arg = pad->atest;
464 break;
465 case PMIC_GPIO_CONF_ANALOG_PASS:
466 arg = pad->analog_pass;
467 break;
468 case PMIC_GPIO_CONF_DTEST_BUFFER:
469 arg = pad->dtest_buffer;
470 break;
471 default:
472 return -EINVAL;
473 }
474
475 *config = pinconf_to_config_packed(param, arg);
476 return 0;
477 }
478
pmic_gpio_config_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned nconfs)479 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
480 unsigned long *configs, unsigned nconfs)
481 {
482 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
483 struct pmic_gpio_pad *pad;
484 unsigned param, arg;
485 unsigned int val;
486 int i, ret;
487
488 pad = pctldev->desc->pins[pin].drv_data;
489
490 pad->is_enabled = true;
491 for (i = 0; i < nconfs; i++) {
492 param = pinconf_to_config_param(configs[i]);
493 arg = pinconf_to_config_argument(configs[i]);
494
495 switch (param) {
496 case PIN_CONFIG_DRIVE_PUSH_PULL:
497 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
498 break;
499 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
500 if (!pad->have_buffer)
501 return -EINVAL;
502 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
503 break;
504 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
505 if (!pad->have_buffer)
506 return -EINVAL;
507 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
508 break;
509 case PIN_CONFIG_BIAS_DISABLE:
510 pad->pullup = PMIC_GPIO_PULL_DISABLE;
511 break;
512 case PIN_CONFIG_BIAS_PULL_UP:
513 pad->pullup = PMIC_GPIO_PULL_UP_30;
514 break;
515 case PIN_CONFIG_BIAS_PULL_DOWN:
516 if (arg)
517 pad->pullup = PMIC_GPIO_PULL_DOWN;
518 else
519 pad->pullup = PMIC_GPIO_PULL_DISABLE;
520 break;
521 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
522 pad->is_enabled = false;
523 break;
524 case PIN_CONFIG_POWER_SOURCE:
525 if (arg >= pad->num_sources)
526 return -EINVAL;
527 pad->power_source = arg;
528 break;
529 case PIN_CONFIG_INPUT_ENABLE:
530 pad->input_enabled = arg ? true : false;
531 break;
532 case PIN_CONFIG_OUTPUT_ENABLE:
533 pad->output_enabled = arg ? true : false;
534 break;
535 case PIN_CONFIG_LEVEL:
536 pad->output_enabled = true;
537 pad->out_value = arg;
538 break;
539 case PMIC_GPIO_CONF_PULL_UP:
540 if (arg > PMIC_GPIO_PULL_UP_1P5_30)
541 return -EINVAL;
542 pad->pullup = arg;
543 break;
544 case PMIC_GPIO_CONF_STRENGTH:
545 if (arg > PMIC_GPIO_STRENGTH_LOW)
546 return -EINVAL;
547 switch (arg) {
548 case PMIC_GPIO_STRENGTH_HIGH:
549 pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH;
550 break;
551 case PMIC_GPIO_STRENGTH_LOW:
552 pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW;
553 break;
554 default:
555 pad->strength = arg;
556 break;
557 }
558 break;
559 case PMIC_GPIO_CONF_ATEST:
560 if (!pad->lv_mv_type || arg > 4)
561 return -EINVAL;
562 pad->atest = arg;
563 break;
564 case PMIC_GPIO_CONF_ANALOG_PASS:
565 if (!pad->lv_mv_type)
566 return -EINVAL;
567 pad->analog_pass = true;
568 break;
569 case PMIC_GPIO_CONF_DTEST_BUFFER:
570 if (arg > 4)
571 return -EINVAL;
572 pad->dtest_buffer = arg;
573 break;
574 default:
575 return -EINVAL;
576 }
577 }
578
579 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
580
581 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
582 if (ret < 0)
583 return ret;
584
585 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
586
587 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
588 if (ret < 0)
589 return ret;
590
591 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
592 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
593
594 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
595 if (ret < 0)
596 return ret;
597
598 if (pad->dtest_buffer == 0) {
599 val = 0;
600 } else {
601 if (pad->lv_mv_type) {
602 val = pad->dtest_buffer - 1;
603 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
604 } else {
605 val = BIT(pad->dtest_buffer - 1);
606 }
607 }
608 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
609 if (ret < 0)
610 return ret;
611
612 if (pad->analog_pass)
613 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
614 else if (pad->output_enabled && pad->input_enabled)
615 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
616 else if (pad->output_enabled)
617 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
618 else
619 val = PMIC_GPIO_MODE_DIGITAL_INPUT;
620
621 if (pad->lv_mv_type) {
622 ret = pmic_gpio_write(state, pad,
623 PMIC_GPIO_REG_MODE_CTL, val);
624 if (ret < 0)
625 return ret;
626
627 val = pad->atest - 1;
628 ret = pmic_gpio_write(state, pad,
629 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
630 if (ret < 0)
631 return ret;
632
633 val = pad->out_value
634 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
635 val |= pad->function
636 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
637 ret = pmic_gpio_write(state, pad,
638 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
639 if (ret < 0)
640 return ret;
641 } else {
642 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
643 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
644 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
645
646 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
647 if (ret < 0)
648 return ret;
649 }
650
651 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
652
653 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
654
655 return ret;
656 }
657
pmic_gpio_config_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned pin)658 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
659 struct seq_file *s, unsigned pin)
660 {
661 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
662 struct pmic_gpio_pad *pad;
663 int ret, val, function;
664
665 static const char *const biases[] = {
666 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
667 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
668 };
669 static const char *const buffer_types[] = {
670 "push-pull", "open-drain", "open-source"
671 };
672 static const char *const strengths[] = {
673 "no", "low", "medium", "high"
674 };
675
676 pad = pctldev->desc->pins[pin].drv_data;
677
678 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
679
680 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
681
682 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
683 seq_puts(s, " ---");
684 } else {
685 if (pad->input_enabled) {
686 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
687 if (ret < 0)
688 return;
689
690 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
691 pad->out_value = ret;
692 }
693 /*
694 * For the non-LV/MV subtypes only 2 special functions are
695 * available, offsetting the dtest function values by 2.
696 */
697 function = pad->function;
698 if (!pad->lv_mv_type &&
699 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
700 function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
701 PMIC_GPIO_FUNC_INDEX_FUNC3;
702
703 if (pad->analog_pass)
704 seq_puts(s, " analog-pass");
705 else
706 seq_printf(s, " %-4s",
707 pad->output_enabled ? "out" : "in");
708 seq_printf(s, " %-4s", str_high_low(pad->out_value));
709 seq_printf(s, " %-7s", pmic_gpio_functions[function]);
710 seq_printf(s, " vin-%d", pad->power_source);
711 seq_printf(s, " %-27s", biases[pad->pullup]);
712 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
713 seq_printf(s, " %-7s", strengths[pad->strength]);
714 seq_printf(s, " atest-%d", pad->atest);
715 seq_printf(s, " dtest-%d", pad->dtest_buffer);
716 }
717 }
718
719 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
720 .is_generic = true,
721 .pin_config_group_get = pmic_gpio_config_get,
722 .pin_config_group_set = pmic_gpio_config_set,
723 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
724 };
725
pmic_gpio_direction_input(struct gpio_chip * chip,unsigned pin)726 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
727 {
728 struct pmic_gpio_state *state = gpiochip_get_data(chip);
729 unsigned long config;
730
731 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
732
733 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
734 }
735
pmic_gpio_direction_output(struct gpio_chip * chip,unsigned pin,int val)736 static int pmic_gpio_direction_output(struct gpio_chip *chip,
737 unsigned pin, int val)
738 {
739 struct pmic_gpio_state *state = gpiochip_get_data(chip);
740 unsigned long config;
741
742 config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, val);
743
744 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
745 }
746
pmic_gpio_get(struct gpio_chip * chip,unsigned pin)747 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
748 {
749 struct pmic_gpio_state *state = gpiochip_get_data(chip);
750 struct pmic_gpio_pad *pad;
751 int ret;
752
753 pad = state->ctrl->desc->pins[pin].drv_data;
754
755 if (!pad->is_enabled)
756 return -EINVAL;
757
758 if (pad->input_enabled) {
759 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
760 if (ret < 0)
761 return ret;
762
763 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
764 }
765
766 return !!pad->out_value;
767 }
768
pmic_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)769 static int pmic_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
770 {
771 struct pmic_gpio_state *state = gpiochip_get_data(chip);
772 unsigned long config;
773
774 config = pinconf_to_config_packed(PIN_CONFIG_LEVEL, value);
775
776 return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
777 }
778
pmic_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpio_desc,u32 * flags)779 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
780 const struct of_phandle_args *gpio_desc,
781 u32 *flags)
782 {
783 if (chip->of_gpio_n_cells < 2)
784 return -EINVAL;
785
786 if (flags)
787 *flags = gpio_desc->args[1];
788
789 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
790 }
791
pmic_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)792 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
793 {
794 struct pmic_gpio_state *state = gpiochip_get_data(chip);
795 unsigned i;
796
797 for (i = 0; i < chip->ngpio; i++) {
798 pmic_gpio_config_dbg_show(state->ctrl, s, i);
799 seq_puts(s, "\n");
800 }
801 }
802
803 static const struct gpio_chip pmic_gpio_gpio_template = {
804 .direction_input = pmic_gpio_direction_input,
805 .direction_output = pmic_gpio_direction_output,
806 .get = pmic_gpio_get,
807 .set = pmic_gpio_set,
808 .request = gpiochip_generic_request,
809 .free = gpiochip_generic_free,
810 .of_xlate = pmic_gpio_of_xlate,
811 .dbg_show = pmic_gpio_dbg_show,
812 };
813
pmic_gpio_populate(struct pmic_gpio_state * state,struct pmic_gpio_pad * pad)814 static int pmic_gpio_populate(struct pmic_gpio_state *state,
815 struct pmic_gpio_pad *pad)
816 {
817 int type, subtype, val, dir;
818
819 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
820 if (type < 0)
821 return type;
822
823 if (type != PMIC_GPIO_TYPE) {
824 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
825 type, pad->base);
826 return -ENODEV;
827 }
828
829 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
830 if (subtype < 0)
831 return subtype;
832
833 switch (subtype) {
834 case PMIC_GPIO_SUBTYPE_GPIO_4CH:
835 pad->have_buffer = true;
836 fallthrough;
837 case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
838 pad->num_sources = 4;
839 break;
840 case PMIC_GPIO_SUBTYPE_GPIO_8CH:
841 pad->have_buffer = true;
842 fallthrough;
843 case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
844 pad->num_sources = 8;
845 break;
846 case PMIC_GPIO_SUBTYPE_GPIO_LV:
847 pad->num_sources = 1;
848 pad->have_buffer = true;
849 pad->lv_mv_type = true;
850 break;
851 case PMIC_GPIO_SUBTYPE_GPIO_MV:
852 pad->num_sources = 2;
853 pad->have_buffer = true;
854 pad->lv_mv_type = true;
855 break;
856 case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2:
857 case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2_CLK:
858 pad->num_sources = 2;
859 pad->have_buffer = true;
860 pad->lv_mv_type = true;
861 break;
862 case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3:
863 case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3_CLK:
864 pad->num_sources = 3;
865 pad->have_buffer = true;
866 pad->lv_mv_type = true;
867 break;
868 default:
869 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
870 return -ENODEV;
871 }
872
873 if (pad->lv_mv_type) {
874 val = pmic_gpio_read(state, pad,
875 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
876 if (val < 0)
877 return val;
878
879 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
880 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
881
882 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
883 if (val < 0)
884 return val;
885
886 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
887 } else {
888 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
889 if (val < 0)
890 return val;
891
892 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
893
894 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
895 dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
896 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
897 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
898 }
899
900 switch (dir) {
901 case PMIC_GPIO_MODE_DIGITAL_INPUT:
902 pad->input_enabled = true;
903 pad->output_enabled = false;
904 break;
905 case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
906 pad->input_enabled = false;
907 pad->output_enabled = true;
908 break;
909 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
910 pad->input_enabled = true;
911 pad->output_enabled = true;
912 break;
913 case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
914 if (!pad->lv_mv_type)
915 return -ENODEV;
916 pad->analog_pass = true;
917 break;
918 default:
919 dev_err(state->dev, "unknown GPIO direction\n");
920 return -ENODEV;
921 }
922
923 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
924 if (val < 0)
925 return val;
926
927 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
928 pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
929
930 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
931 if (val < 0)
932 return val;
933
934 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
935 pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
936
937 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
938 if (val < 0)
939 return val;
940
941 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
942 pad->dtest_buffer =
943 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
944 else if (!pad->lv_mv_type)
945 pad->dtest_buffer = ffs(val);
946 else
947 pad->dtest_buffer = 0;
948
949 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
950 if (val < 0)
951 return val;
952
953 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
954 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
955
956 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
957 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
958
959 if (pad->lv_mv_type) {
960 val = pmic_gpio_read(state, pad,
961 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
962 if (val < 0)
963 return val;
964 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
965 }
966
967 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
968 pad->is_enabled = true;
969 return 0;
970 }
971
pmic_gpio_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)972 static int pmic_gpio_domain_translate(struct irq_domain *domain,
973 struct irq_fwspec *fwspec,
974 unsigned long *hwirq,
975 unsigned int *type)
976 {
977 struct pmic_gpio_state *state = container_of(domain->host_data,
978 struct pmic_gpio_state,
979 chip);
980
981 if (fwspec->param_count != 2 ||
982 fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
983 return -EINVAL;
984
985 *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
986 *type = fwspec->param[1];
987
988 return 0;
989 }
990
pmic_gpio_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)991 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
992 unsigned int offset)
993 {
994 return offset + PMIC_GPIO_PHYSICAL_OFFSET;
995 }
996
pmic_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int child_hwirq,unsigned int child_type,unsigned int * parent_hwirq,unsigned int * parent_type)997 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
998 unsigned int child_hwirq,
999 unsigned int child_type,
1000 unsigned int *parent_hwirq,
1001 unsigned int *parent_type)
1002 {
1003 struct pmic_gpio_state *state = gpiochip_get_data(chip);
1004
1005 *parent_hwirq = child_hwirq + state->pid_base;
1006 *parent_type = child_type;
1007
1008 return 0;
1009 }
1010
pmic_gpio_populate_parent_fwspec(struct gpio_chip * chip,union gpio_irq_fwspec * gfwspec,unsigned int parent_hwirq,unsigned int parent_type)1011 static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
1012 union gpio_irq_fwspec *gfwspec,
1013 unsigned int parent_hwirq,
1014 unsigned int parent_type)
1015 {
1016 struct pmic_gpio_state *state = gpiochip_get_data(chip);
1017 struct irq_fwspec *fwspec = &gfwspec->fwspec;
1018
1019 fwspec->fwnode = chip->irq.parent_domain->fwnode;
1020
1021 fwspec->param_count = 4;
1022 fwspec->param[0] = state->usid;
1023 fwspec->param[1] = parent_hwirq;
1024 /* param[2] must be left as 0 */
1025 fwspec->param[3] = parent_type;
1026
1027 return 0;
1028 }
1029
pmic_gpio_irq_mask(struct irq_data * data)1030 static void pmic_gpio_irq_mask(struct irq_data *data)
1031 {
1032 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1033
1034 irq_chip_mask_parent(data);
1035 gpiochip_disable_irq(gc, data->hwirq);
1036 }
1037
pmic_gpio_irq_unmask(struct irq_data * data)1038 static void pmic_gpio_irq_unmask(struct irq_data *data)
1039 {
1040 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1041
1042 gpiochip_enable_irq(gc, data->hwirq);
1043 irq_chip_unmask_parent(data);
1044 }
1045
1046 static const struct irq_chip spmi_gpio_irq_chip = {
1047 .name = "spmi-gpio",
1048 .irq_ack = irq_chip_ack_parent,
1049 .irq_mask = pmic_gpio_irq_mask,
1050 .irq_unmask = pmic_gpio_irq_unmask,
1051 .irq_set_type = irq_chip_set_type_parent,
1052 .irq_set_wake = irq_chip_set_wake_parent,
1053 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
1054 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1055 };
1056
pmic_gpio_probe(struct platform_device * pdev)1057 static int pmic_gpio_probe(struct platform_device *pdev)
1058 {
1059 struct irq_domain *parent_domain;
1060 struct device_node *parent_node;
1061 struct device *dev = &pdev->dev;
1062 struct pinctrl_pin_desc *pindesc;
1063 struct pinctrl_desc *pctrldesc;
1064 struct pmic_gpio_pad *pad, *pads;
1065 struct pmic_gpio_state *state;
1066 struct gpio_irq_chip *girq;
1067 const struct spmi_device *parent_spmi_dev;
1068 int ret, npins, i;
1069 u32 reg;
1070
1071 ret = of_property_read_u32(dev->of_node, "reg", ®);
1072 if (ret < 0) {
1073 dev_err(dev, "missing base address");
1074 return ret;
1075 }
1076
1077 npins = (uintptr_t) device_get_match_data(&pdev->dev);
1078
1079 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1080 if (!state)
1081 return -ENOMEM;
1082
1083 platform_set_drvdata(pdev, state);
1084
1085 state->dev = &pdev->dev;
1086 state->map = dev_get_regmap(dev->parent, NULL);
1087 parent_spmi_dev = to_spmi_device(dev->parent);
1088 state->usid = parent_spmi_dev->usid;
1089 state->pid_base = reg >> 8;
1090
1091 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1092 if (!pindesc)
1093 return -ENOMEM;
1094
1095 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1096 if (!pads)
1097 return -ENOMEM;
1098
1099 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1100 if (!pctrldesc)
1101 return -ENOMEM;
1102
1103 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1104 pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1105 pctrldesc->confops = &pmic_gpio_pinconf_ops;
1106 pctrldesc->owner = THIS_MODULE;
1107 pctrldesc->name = dev_name(dev);
1108 pctrldesc->pins = pindesc;
1109 pctrldesc->npins = npins;
1110 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1111 pctrldesc->custom_params = pmic_gpio_bindings;
1112 #ifdef CONFIG_DEBUG_FS
1113 pctrldesc->custom_conf_items = pmic_conf_items;
1114 #endif
1115
1116 for (i = 0; i < npins; i++, pindesc++) {
1117 pad = &pads[i];
1118 pindesc->drv_data = pad;
1119 pindesc->number = i;
1120 pindesc->name = pmic_gpio_groups[i];
1121
1122 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1123
1124 ret = pmic_gpio_populate(state, pad);
1125 if (ret < 0)
1126 return ret;
1127 }
1128
1129 state->chip = pmic_gpio_gpio_template;
1130 state->chip.parent = dev;
1131 state->chip.base = -1;
1132 state->chip.ngpio = npins;
1133 state->chip.label = dev_name(dev);
1134 state->chip.of_gpio_n_cells = 2;
1135 state->chip.can_sleep = false;
1136
1137 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1138 if (IS_ERR(state->ctrl))
1139 return PTR_ERR(state->ctrl);
1140
1141 parent_node = of_irq_find_parent(state->dev->of_node);
1142 if (!parent_node)
1143 return -ENXIO;
1144
1145 parent_domain = irq_find_host(parent_node);
1146 of_node_put(parent_node);
1147 if (!parent_domain)
1148 return -ENXIO;
1149
1150 girq = &state->chip.irq;
1151 gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip);
1152 girq->default_type = IRQ_TYPE_NONE;
1153 girq->handler = handle_level_irq;
1154 girq->fwnode = dev_fwnode(state->dev);
1155 girq->parent_domain = parent_domain;
1156 girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1157 girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec;
1158 girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1159 girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1160
1161 ret = gpiochip_add_data(&state->chip, state);
1162 if (ret) {
1163 dev_err(state->dev, "can't add gpio chip\n");
1164 return ret;
1165 }
1166
1167 /*
1168 * For DeviceTree-supported systems, the gpio core checks the
1169 * pinctrl's device node for the "gpio-ranges" property.
1170 * If it is present, it takes care of adding the pin ranges
1171 * for the driver. In this case the driver can skip ahead.
1172 *
1173 * In order to remain compatible with older, existing DeviceTree
1174 * files which don't set the "gpio-ranges" property or systems that
1175 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1176 */
1177 if (!of_property_present(dev->of_node, "gpio-ranges")) {
1178 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1179 npins);
1180 if (ret) {
1181 dev_err(dev, "failed to add pin range\n");
1182 goto err_range;
1183 }
1184 }
1185
1186 return 0;
1187
1188 err_range:
1189 gpiochip_remove(&state->chip);
1190 return ret;
1191 }
1192
pmic_gpio_remove(struct platform_device * pdev)1193 static void pmic_gpio_remove(struct platform_device *pdev)
1194 {
1195 struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1196
1197 gpiochip_remove(&state->chip);
1198 }
1199
1200 static const struct of_device_id pmic_gpio_of_match[] = {
1201 { .compatible = "qcom,pm2250-gpio", .data = (void *) 10 },
1202 /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1203 { .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1204 /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1205 { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1206 { .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
1207 { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1208 { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1209 { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
1210 { .compatible = "qcom,pm6450-gpio", .data = (void *) 9 },
1211 { .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 },
1212 { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1213 { .compatible = "qcom,pm7550-gpio", .data = (void *) 12 },
1214 { .compatible = "qcom,pm7550ba-gpio", .data = (void *) 8},
1215 { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1216 { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
1217 /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1218 { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1219 { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
1220 /* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1221 { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1222 /* pm8150l has 12 GPIOs with holes on 7 */
1223 { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1224 { .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
1225 { .compatible = "qcom,pm8226-gpio", .data = (void *) 8 },
1226 { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1227 { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1228 { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1229 { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
1230 { .compatible = "qcom,pm8550-gpio", .data = (void *) 12 },
1231 { .compatible = "qcom,pm8550b-gpio", .data = (void *) 12 },
1232 { .compatible = "qcom,pm8550ve-gpio", .data = (void *) 8 },
1233 { .compatible = "qcom,pm8550vs-gpio", .data = (void *) 6 },
1234 { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1235 /* pm8937 has 8 GPIOs with holes on 3, 4 and 6 */
1236 { .compatible = "qcom,pm8937-gpio", .data = (void *) 8 },
1237 { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1238 /* pm8950 has 8 GPIOs with holes on 3 */
1239 { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1240 /* pm8953 has 8 GPIOs with holes on 3 and 6 */
1241 { .compatible = "qcom,pm8953-gpio", .data = (void *) 8 },
1242 { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1243 { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1244 { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1245 { .compatible = "qcom,pmc8380-gpio", .data = (void *) 10 },
1246 { .compatible = "qcom,pmcx0102-gpio", .data = (void *)14 },
1247 { .compatible = "qcom,pmd8028-gpio", .data = (void *) 4 },
1248 { .compatible = "qcom,pmh0101-gpio", .data = (void *)18 },
1249 { .compatible = "qcom,pmh0104-gpio", .data = (void *)8 },
1250 { .compatible = "qcom,pmh0110-gpio", .data = (void *)14 },
1251 { .compatible = "qcom,pmi632-gpio", .data = (void *) 8 },
1252 { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1253 { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1254 { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1255 { .compatible = "qcom,pmih0108-gpio", .data = (void *) 18 },
1256 { .compatible = "qcom,pmiv0104-gpio", .data = (void *) 10 },
1257 { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1258 { .compatible = "qcom,pmk8550-gpio", .data = (void *) 6 },
1259 { .compatible = "qcom,pmk8850-gpio", .data = (void *)8 },
1260 { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
1261 { .compatible = "qcom,pmm8654au-gpio", .data = (void *) 12 },
1262 /* pmp8074 has 12 GPIOs with holes on 1 and 12 */
1263 { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
1264 { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1265 { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1266 { .compatible = "qcom,pmr735d-gpio", .data = (void *) 2 },
1267 /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1268 { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1269 /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1270 { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1271 { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 },
1272 { .compatible = "qcom,pmx75-gpio", .data = (void *) 16 },
1273 { .compatible = "qcom,pmxr2230-gpio", .data = (void *) 12 },
1274 { },
1275 };
1276
1277 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1278
1279 static struct platform_driver pmic_gpio_driver = {
1280 .driver = {
1281 .name = "qcom-spmi-gpio",
1282 .of_match_table = pmic_gpio_of_match,
1283 },
1284 .probe = pmic_gpio_probe,
1285 .remove = pmic_gpio_remove,
1286 };
1287
1288 module_platform_driver(pmic_gpio_driver);
1289
1290 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1291 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1292 MODULE_ALIAS("platform:qcom-spmi-gpio");
1293 MODULE_LICENSE("GPL v2");
1294