xref: /linux/include/linux/platform_data/x86/pmc_atom.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80) 
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Intel Atom SoC Power Management Controller Header File
4  * Copyright (c) 2014-2015,2022 Intel Corporation.
5  */
6 
7 #ifndef PMC_ATOM_H
8 #define PMC_ATOM_H
9 
10 #include <linux/bits.h>
11 
12 /* ValleyView Power Control Unit PCI Device ID */
13 #define	PCI_DEVICE_ID_VLV_PMC	0x0F1C
14 /* CherryTrail Power Control Unit PCI Device ID */
15 #define	PCI_DEVICE_ID_CHT_PMC	0x229C
16 
17 /* PMC Memory mapped IO registers */
18 #define	PMC_BASE_ADDR_OFFSET	0x44
19 #define	PMC_BASE_ADDR_MASK	0xFFFFFE00
20 #define	PMC_MMIO_REG_LEN	0x100
21 #define	PMC_REG_BIT_WIDTH	32
22 
23 /* BIOS uses FUNC_DIS to disable specific function */
24 #define	PMC_FUNC_DIS		0x34
25 #define	PMC_FUNC_DIS_2		0x38
26 
27 /* CHT specific bits in FUNC_DIS2 register */
28 #define	BIT_FD_GMM		BIT(3)
29 #define	BIT_FD_ISH		BIT(4)
30 
31 /* S0ix wake event control */
32 #define	PMC_S0IX_WAKE_EN	0x3C
33 
34 #define	BIT_LPC_CLOCK_RUN		BIT(4)
35 #define	BIT_SHARED_IRQ_GPSC		BIT(5)
36 #define	BIT_ORED_DEDICATED_IRQ_GPSS	BIT(18)
37 #define	BIT_ORED_DEDICATED_IRQ_GPSC	BIT(19)
38 #define	BIT_SHARED_IRQ_GPSS		BIT(20)
39 
40 #define	PMC_WAKE_EN_SETTING	~(BIT_LPC_CLOCK_RUN | \
41 				BIT_SHARED_IRQ_GPSC | \
42 				BIT_ORED_DEDICATED_IRQ_GPSS | \
43 				BIT_ORED_DEDICATED_IRQ_GPSC | \
44 				BIT_SHARED_IRQ_GPSS)
45 
46 /* External clk generator settings */
47 #define PMC_CLK_CTL_OFFSET		0x60
48 #define PMC_CLK_CTL_SIZE		4
49 #define PMC_CLK_NUM			6
50 #define PMC_CLK_CTL_GATED_ON_D3		0x0
51 #define PMC_CLK_CTL_FORCE_ON		0x1
52 #define PMC_CLK_CTL_FORCE_OFF		0x2
53 #define PMC_CLK_CTL_RESERVED		0x3
54 #define PMC_MASK_CLK_CTL		GENMASK(1, 0)
55 #define PMC_MASK_CLK_FREQ		BIT(2)
56 #define PMC_CLK_FREQ_XTAL		(0 << 2)	/* 25 MHz */
57 #define PMC_CLK_FREQ_PLL		(1 << 2)	/* 19.2 MHz */
58 
59 /* The timers accumulate time spent in sleep state */
60 #define	PMC_S0IR_TMR		0x80
61 #define	PMC_S0I1_TMR		0x84
62 #define	PMC_S0I2_TMR		0x88
63 #define	PMC_S0I3_TMR		0x8C
64 #define	PMC_S0_TMR		0x90
65 /* Sleep state counter is in units of 32us */
66 #define	PMC_TMR_SHIFT		5
67 
68 /* Power status of power islands */
69 #define	PMC_PSS			0x98
70 
71 #define PMC_PSS_BIT_GBE			BIT(0)
72 #define PMC_PSS_BIT_SATA		BIT(1)
73 #define PMC_PSS_BIT_HDA			BIT(2)
74 #define PMC_PSS_BIT_SEC			BIT(3)
75 #define PMC_PSS_BIT_PCIE		BIT(4)
76 #define PMC_PSS_BIT_LPSS		BIT(5)
77 #define PMC_PSS_BIT_LPE			BIT(6)
78 #define PMC_PSS_BIT_DFX			BIT(7)
79 #define PMC_PSS_BIT_USH_CTRL		BIT(8)
80 #define PMC_PSS_BIT_USH_SUS		BIT(9)
81 #define PMC_PSS_BIT_USH_VCCS		BIT(10)
82 #define PMC_PSS_BIT_USH_VCCA		BIT(11)
83 #define PMC_PSS_BIT_OTG_CTRL		BIT(12)
84 #define PMC_PSS_BIT_OTG_VCCS		BIT(13)
85 #define PMC_PSS_BIT_OTG_VCCA_CLK	BIT(14)
86 #define PMC_PSS_BIT_OTG_VCCA		BIT(15)
87 #define PMC_PSS_BIT_USB			BIT(16)
88 #define PMC_PSS_BIT_USB_SUS		BIT(17)
89 
90 /* CHT specific bits in PSS register */
91 #define	PMC_PSS_BIT_CHT_UFS		BIT(7)
92 #define	PMC_PSS_BIT_CHT_UXD		BIT(11)
93 #define	PMC_PSS_BIT_CHT_UXD_FD		BIT(12)
94 #define	PMC_PSS_BIT_CHT_UX_ENG		BIT(15)
95 #define	PMC_PSS_BIT_CHT_USB_SUS		BIT(16)
96 #define	PMC_PSS_BIT_CHT_GMM		BIT(17)
97 #define	PMC_PSS_BIT_CHT_ISH		BIT(18)
98 #define	PMC_PSS_BIT_CHT_DFX_MASTER	BIT(26)
99 #define	PMC_PSS_BIT_CHT_DFX_CLUSTER1	BIT(27)
100 #define	PMC_PSS_BIT_CHT_DFX_CLUSTER2	BIT(28)
101 #define	PMC_PSS_BIT_CHT_DFX_CLUSTER3	BIT(29)
102 #define	PMC_PSS_BIT_CHT_DFX_CLUSTER4	BIT(30)
103 #define	PMC_PSS_BIT_CHT_DFX_CLUSTER5	BIT(31)
104 
105 /* These registers reflect D3 status of functions */
106 #define	PMC_D3_STS_0		0xA0
107 
108 #define	BIT_LPSS1_F0_DMA	BIT(0)
109 #define	BIT_LPSS1_F1_PWM1	BIT(1)
110 #define	BIT_LPSS1_F2_PWM2	BIT(2)
111 #define	BIT_LPSS1_F3_HSUART1	BIT(3)
112 #define	BIT_LPSS1_F4_HSUART2	BIT(4)
113 #define	BIT_LPSS1_F5_SPI	BIT(5)
114 #define	BIT_LPSS1_F6_XXX	BIT(6)
115 #define	BIT_LPSS1_F7_XXX	BIT(7)
116 #define	BIT_SCC_EMMC		BIT(8)
117 #define	BIT_SCC_SDIO		BIT(9)
118 #define	BIT_SCC_SDCARD		BIT(10)
119 #define	BIT_SCC_MIPI		BIT(11)
120 #define	BIT_HDA			BIT(12) /* CHT datasheet: reserved */
121 #define	BIT_LPE			BIT(13)
122 #define	BIT_OTG			BIT(14)
123 #define	BIT_USH			BIT(15) /* CHT datasheet: reserved */
124 #define	BIT_GBE			BIT(16) /* CHT datasheet: reserved */
125 #define	BIT_SATA		BIT(17) /* CHT datasheet: reserved */
126 #define	BIT_USB_EHCI		BIT(18) /* CHT datasheet: XHCI!    */
127 #define	BIT_SEC			BIT(19) /* BYT datasheet: reserved */
128 #define	BIT_PCIE_PORT0		BIT(20)
129 #define	BIT_PCIE_PORT1		BIT(21)
130 #define	BIT_PCIE_PORT2		BIT(22)
131 #define	BIT_PCIE_PORT3		BIT(23)
132 #define	BIT_LPSS2_F0_DMA	BIT(24)
133 #define	BIT_LPSS2_F1_I2C1	BIT(25)
134 #define	BIT_LPSS2_F2_I2C2	BIT(26)
135 #define	BIT_LPSS2_F3_I2C3	BIT(27)
136 #define	BIT_LPSS2_F4_I2C4	BIT(28)
137 #define	BIT_LPSS2_F5_I2C5	BIT(29)
138 #define	BIT_LPSS2_F6_I2C6	BIT(30)
139 #define	BIT_LPSS2_F7_I2C7	BIT(31)
140 
141 #define	PMC_D3_STS_1		0xA4
142 #define	BIT_SMB			BIT(0)
143 #define	BIT_OTG_SS_PHY		BIT(1)
144 #define	BIT_USH_SS_PHY		BIT(2)
145 #define	BIT_DFX			BIT(3)
146 
147 /* CHT specific bits in PMC_D3_STS_1 register */
148 #define	BIT_STS_GMM		BIT(1)
149 #define	BIT_STS_ISH		BIT(2)
150 
151 /* PMC I/O Registers */
152 #define	ACPI_BASE_ADDR_OFFSET	0x40
153 #define	ACPI_BASE_ADDR_MASK	0xFFFFFE00
154 #define	ACPI_MMIO_REG_LEN	0x100
155 
156 #define	PM1_CNT			0x4
157 #define	SLEEP_TYPE_MASK		GENMASK(12, 10)
158 #define	SLEEP_TYPE_S5		0x1C00
159 #define	SLEEP_ENABLE		BIT(13)
160 
161 extern int pmc_atom_read(int offset, u32 *value);
162 
163 #endif /* PMC_ATOM_H */
164