1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su> 4 * 5 * Derived from the ems_pci.c driver: 6 * Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com> 7 * Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com> 8 * Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/netdevice.h> 15 #include <linux/delay.h> 16 #include <linux/slab.h> 17 #include <linux/pci.h> 18 #include <linux/can/dev.h> 19 #include <linux/io.h> 20 21 #include "sja1000.h" 22 23 #define DRV_NAME "sja1000_plx_pci" 24 25 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>"); 26 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with " 27 "the SJA1000 chips"); 28 MODULE_LICENSE("GPL v2"); 29 30 #define PLX_PCI_MAX_CHAN 2 31 32 struct plx_pci_card { 33 int channels; /* detected channels count */ 34 struct net_device *net_dev[PLX_PCI_MAX_CHAN]; 35 void __iomem *conf_addr; 36 37 /* Pointer to device-dependent reset function */ 38 void (*reset_func)(struct pci_dev *pdev); 39 }; 40 41 #define PLX_PCI_CAN_CLOCK (16000000 / 2) 42 43 /* PLX9030/9050/9052 registers */ 44 #define PLX_INTCSR 0x4c /* Interrupt Control/Status */ 45 #define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response, 46 * Serial EEPROM, and Initialization 47 * Control register 48 */ 49 50 #define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */ 51 #define PLX_LINT1_POL (1 << 1) /* Local interrupt 1 polarity */ 52 #define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */ 53 #define PLX_LINT2_POL (1 << 4) /* Local interrupt 2 polarity */ 54 #define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */ 55 #define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */ 56 57 /* PLX9056 registers */ 58 #define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */ 59 #define PLX9056_CNTRL 0x6c /* Control / Software Reset */ 60 61 #define PLX9056_LINTI (1 << 11) 62 #define PLX9056_PCI_INT_EN (1 << 8) 63 #define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */ 64 65 /* 66 * The board configuration is probably following: 67 * RX1 is connected to ground. 68 * TX1 is not connected. 69 * CLKO is not connected. 70 * Setting the OCR register to 0xDA is a good idea. 71 * This means normal output mode, push-pull and the correct polarity. 72 */ 73 #define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL) 74 75 /* OCR setting for ASEM Dual CAN raw */ 76 #define ASEM_PCI_OCR 0xfe 77 78 /* 79 * In the CDR register, you should set CBP to 1. 80 * You will probably also want to set the clock divider value to 7 81 * (meaning direct oscillator output) because the second SJA1000 chip 82 * is driven by the first one CLKOUT output. 83 */ 84 #define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK) 85 86 /* SJA1000 Control Register in the BasicCAN Mode */ 87 #define REG_CR 0x00 88 89 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/ 90 #define REG_CR_BASICCAN_INITIAL 0x21 91 #define REG_CR_BASICCAN_INITIAL_MASK 0xa1 92 #define REG_SR_BASICCAN_INITIAL 0x0c 93 #define REG_IR_BASICCAN_INITIAL 0xe0 94 95 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/ 96 #define REG_MOD_PELICAN_INITIAL 0x01 97 #define REG_SR_PELICAN_INITIAL 0x3c 98 #define REG_IR_PELICAN_INITIAL 0x00 99 100 #define ADLINK_PCI_VENDOR_ID 0x144A 101 #define ADLINK_PCI_DEVICE_ID 0x7841 102 103 #define ESD_PCI_SUB_SYS_ID_PCI200 0x0004 104 #define ESD_PCI_SUB_SYS_ID_PCI266 0x0009 105 #define ESD_PCI_SUB_SYS_ID_PMC266 0x000e 106 #define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b 107 #define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200 108 #define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501 109 110 #define CAN200PCI_DEVICE_ID 0x9030 111 #define CAN200PCI_VENDOR_ID 0x10b5 112 #define CAN200PCI_SUB_DEVICE_ID 0x0301 113 #define CAN200PCI_SUB_VENDOR_ID 0xe1c5 114 115 #define IXXAT_PCI_VENDOR_ID 0x10b5 116 #define IXXAT_PCI_DEVICE_ID 0x9050 117 #define IXXAT_PCI_SUB_SYS_ID 0x2540 118 119 #define MARATHON_PCI_DEVICE_ID 0x2715 120 #define MARATHON_PCIE_DEVICE_ID 0x3432 121 122 #define TEWS_PCI_VENDOR_ID 0x1498 123 #define TEWS_PCI_DEVICE_ID_TMPC810 0x032A 124 125 #define CTI_PCI_DEVICE_ID_CRG001 0x0900 126 127 #define MOXA_PCI_VENDOR_ID 0x1393 128 #define MOXA_PCI_DEVICE_ID 0x0100 129 130 #define ASEM_RAW_CAN_VENDOR_ID 0x10b5 131 #define ASEM_RAW_CAN_DEVICE_ID 0x9030 132 #define ASEM_RAW_CAN_SUB_VENDOR_ID 0x3000 133 #define ASEM_RAW_CAN_SUB_DEVICE_ID 0x1001 134 #define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS 0x1002 135 #define ASEM_RAW_CAN_RST_REGISTER 0x54 136 #define ASEM_RAW_CAN_RST_MASK_CAN1 0x20 137 #define ASEM_RAW_CAN_RST_MASK_CAN2 0x04 138 139 static void plx_pci_reset_common(struct pci_dev *pdev); 140 static void plx9056_pci_reset_common(struct pci_dev *pdev); 141 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev); 142 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev); 143 static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev); 144 145 struct plx_pci_channel_map { 146 u32 bar; 147 u32 offset; 148 u32 size; /* 0x00 - auto, e.g. length of entire bar */ 149 }; 150 151 struct plx_pci_card_info { 152 const char *name; 153 int channel_count; 154 u32 can_clock; 155 u8 ocr; /* output control register */ 156 u8 cdr; /* clock divider register */ 157 158 /* Parameters for mapping local configuration space */ 159 struct plx_pci_channel_map conf_map; 160 161 /* Parameters for mapping the SJA1000 chips */ 162 struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN]; 163 164 /* Pointer to device-dependent reset function */ 165 void (*reset_func)(struct pci_dev *pdev); 166 }; 167 168 static struct plx_pci_card_info plx_pci_card_info_adlink = { 169 "Adlink PCI-7841/cPCI-7841", 2, 170 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 171 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 172 &plx_pci_reset_common 173 /* based on PLX9052 */ 174 }; 175 176 static struct plx_pci_card_info plx_pci_card_info_adlink_se = { 177 "Adlink PCI-7841/cPCI-7841 SE", 2, 178 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 179 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} }, 180 &plx_pci_reset_common 181 /* based on PLX9052 */ 182 }; 183 184 static struct plx_pci_card_info plx_pci_card_info_esd200 = { 185 "esd CAN-PCI/CPCI/PCI104/200", 2, 186 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 187 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 188 &plx_pci_reset_common 189 /* based on PLX9030/9050 */ 190 }; 191 192 static struct plx_pci_card_info plx_pci_card_info_esd266 = { 193 "esd CAN-PCI/PMC/266", 2, 194 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 195 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 196 &plx9056_pci_reset_common 197 /* based on PLX9056 */ 198 }; 199 200 static struct plx_pci_card_info plx_pci_card_info_esd2000 = { 201 "esd CAN-PCIe/2000", 2, 202 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 203 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} }, 204 &plx9056_pci_reset_common 205 /* based on PEX8311 */ 206 }; 207 208 static struct plx_pci_card_info plx_pci_card_info_ixxat = { 209 "IXXAT PC-I 04/PCI", 2, 210 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 211 {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} }, 212 &plx_pci_reset_common 213 /* based on PLX9050 */ 214 }; 215 216 static struct plx_pci_card_info plx_pci_card_info_marathon_pci = { 217 "Marathon CAN-bus-PCI", 2, 218 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 219 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 220 &plx_pci_reset_marathon_pci 221 /* based on PLX9052 */ 222 }; 223 224 static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = { 225 "Marathon CAN-bus-PCIe", 2, 226 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 227 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} }, 228 &plx_pci_reset_marathon_pcie 229 /* based on PEX8311 */ 230 }; 231 232 static struct plx_pci_card_info plx_pci_card_info_tews = { 233 "TEWS TECHNOLOGIES TPMC810", 2, 234 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 235 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 236 &plx_pci_reset_common 237 /* based on PLX9030 */ 238 }; 239 240 static struct plx_pci_card_info plx_pci_card_info_cti = { 241 "Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2, 242 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 243 {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} }, 244 &plx_pci_reset_common 245 /* based on PLX9030 */ 246 }; 247 248 static struct plx_pci_card_info plx_pci_card_info_elcus = { 249 "Eclus CAN-200-PCI", 2, 250 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 251 {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} }, 252 &plx_pci_reset_common 253 /* based on PLX9030 */ 254 }; 255 256 static struct plx_pci_card_info plx_pci_card_info_moxa = { 257 "MOXA", 2, 258 PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR, 259 {0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} }, 260 &plx_pci_reset_common 261 /* based on PLX9052 */ 262 }; 263 264 static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = { 265 "ASEM Dual CAN raw PCI", 2, 266 PLX_PCI_CAN_CLOCK, ASEM_PCI_OCR, PLX_PCI_CDR, 267 {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} }, 268 &plx_pci_reset_asem_dual_can_raw 269 /* based on PLX9030 */ 270 }; 271 272 static const struct pci_device_id plx_pci_tbl[] = { 273 { 274 /* Adlink PCI-7841/cPCI-7841 */ 275 PCI_DEVICE(ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID), 276 .class = PCI_CLASS_NETWORK_OTHER << 8, 277 .class_mask = ~0, 278 .driver_data = (kernel_ulong_t)&plx_pci_card_info_adlink, 279 }, { 280 /* Adlink PCI-7841/cPCI-7841 SE */ 281 PCI_DEVICE(ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID), 282 .class = PCI_CLASS_COMMUNICATION_OTHER << 8, 283 .class_mask = ~0, 284 .driver_data = (kernel_ulong_t)&plx_pci_card_info_adlink_se, 285 }, { 286 /* esd CAN-PCI/200 */ 287 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 288 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200), 289 .driver_data = (kernel_ulong_t)&plx_pci_card_info_esd200, 290 }, { 291 /* esd CAN-CPCI/200 */ 292 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030, 293 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200), 294 .driver_data = (kernel_ulong_t)&plx_pci_card_info_esd200, 295 }, { 296 /* esd CAN-PCI104/200 */ 297 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030, 298 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200), 299 .driver_data = (kernel_ulong_t)&plx_pci_card_info_esd200, 300 }, { 301 /* esd CAN-PCI/266 */ 302 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9056, 303 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266), 304 .driver_data = (kernel_ulong_t)&plx_pci_card_info_esd266, 305 }, { 306 /* esd CAN-PMC/266 */ 307 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9056, 308 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266), 309 .driver_data = (kernel_ulong_t)&plx_pci_card_info_esd266, 310 }, { 311 /* esd CAN-PCIE/2000 */ 312 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9056, 313 PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000), 314 .driver_data = (kernel_ulong_t)&plx_pci_card_info_esd2000, 315 }, { 316 /* IXXAT PC-I 04/PCI card */ 317 PCI_DEVICE_SUB(IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID, 318 PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID), 319 .driver_data = (kernel_ulong_t)&plx_pci_card_info_ixxat, 320 }, { 321 /* Marathon CAN-bus-PCI card */ 322 PCI_VDEVICE(PLX, MARATHON_PCI_DEVICE_ID), 323 .driver_data = (kernel_ulong_t)&plx_pci_card_info_marathon_pci, 324 }, { 325 /* Marathon CAN-bus-PCIe card */ 326 PCI_VDEVICE(PLX, MARATHON_PCIE_DEVICE_ID), 327 .driver_data = (kernel_ulong_t)&plx_pci_card_info_marathon_pcie, 328 }, { 329 /* TEWS TECHNOLOGIES TPMC810 card */ 330 PCI_DEVICE(TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810), 331 .driver_data = (kernel_ulong_t)&plx_pci_card_info_tews, 332 }, { 333 /* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */ 334 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030, 335 PCI_SUBVENDOR_ID_CONNECT_TECH, CTI_PCI_DEVICE_ID_CRG001), 336 .driver_data = (kernel_ulong_t)&plx_pci_card_info_cti, 337 }, { 338 /* Elcus CAN-200-PCI */ 339 PCI_DEVICE_SUB(CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID, 340 CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID), 341 .driver_data = (kernel_ulong_t)&plx_pci_card_info_elcus, 342 }, { 343 /* moxa */ 344 PCI_DEVICE(MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID), 345 .driver_data = (kernel_ulong_t)&plx_pci_card_info_moxa, 346 }, { 347 /* ASEM Dual CAN raw */ 348 PCI_DEVICE_SUB(ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID, 349 ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID), 350 .driver_data = (kernel_ulong_t)&plx_pci_card_info_asem_dual_can, 351 }, { 352 /* ASEM Dual CAN raw -new model */ 353 PCI_DEVICE_SUB(ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID, 354 ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID_BIS), 355 .driver_data = (kernel_ulong_t)&plx_pci_card_info_asem_dual_can, 356 }, 357 { } 358 }; 359 MODULE_DEVICE_TABLE(pci, plx_pci_tbl); 360 361 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port) 362 { 363 return ioread8(priv->reg_base + port); 364 } 365 366 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val) 367 { 368 iowrite8(val, priv->reg_base + port); 369 } 370 371 /* 372 * Check if a CAN controller is present at the specified location 373 * by trying to switch 'em from the Basic mode into the PeliCAN mode. 374 * Also check states of some registers in reset mode. 375 */ 376 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv) 377 { 378 int flag = 0; 379 380 /* 381 * Check registers after hardware reset (the Basic mode) 382 * See states on p. 10 of the Datasheet. 383 */ 384 if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) == 385 REG_CR_BASICCAN_INITIAL && 386 (priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) && 387 (priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL)) 388 flag = 1; 389 390 /* Bring the SJA1000 into the PeliCAN mode*/ 391 priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN); 392 393 /* 394 * Check registers after reset in the PeliCAN mode. 395 * See states on p. 23 of the Datasheet. 396 */ 397 if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL && 398 priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL && 399 priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL) 400 return flag; 401 402 return 0; 403 } 404 405 /* 406 * PLX9030/50/52 software reset 407 * Also LRESET# asserts and brings to reset device on the Local Bus (if wired). 408 * For most cards it's enough for reset the SJA1000 chips. 409 */ 410 static void plx_pci_reset_common(struct pci_dev *pdev) 411 { 412 struct plx_pci_card *card = pci_get_drvdata(pdev); 413 u32 cntrl; 414 415 cntrl = ioread32(card->conf_addr + PLX_CNTRL); 416 cntrl |= PLX_PCI_RESET; 417 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 418 udelay(100); 419 cntrl ^= PLX_PCI_RESET; 420 iowrite32(cntrl, card->conf_addr + PLX_CNTRL); 421 }; 422 423 /* 424 * PLX9056 software reset 425 * Assert LRESET# and reset device(s) on the Local Bus (if wired). 426 */ 427 static void plx9056_pci_reset_common(struct pci_dev *pdev) 428 { 429 struct plx_pci_card *card = pci_get_drvdata(pdev); 430 u32 cntrl; 431 432 /* issue a local bus reset */ 433 cntrl = ioread32(card->conf_addr + PLX9056_CNTRL); 434 cntrl |= PLX_PCI_RESET; 435 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 436 udelay(100); 437 cntrl ^= PLX_PCI_RESET; 438 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 439 440 /* reload local configuration from EEPROM */ 441 cntrl |= PLX9056_PCI_RCR; 442 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 443 444 /* 445 * There is no safe way to poll for the end 446 * of reconfiguration process. Waiting for 10ms 447 * is safe. 448 */ 449 mdelay(10); 450 451 cntrl ^= PLX9056_PCI_RCR; 452 iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL); 453 }; 454 455 /* Special reset function for Marathon CAN-bus-PCI card */ 456 static void plx_pci_reset_marathon_pci(struct pci_dev *pdev) 457 { 458 void __iomem *reset_addr; 459 int i; 460 static const int reset_bar[2] = {3, 5}; 461 462 plx_pci_reset_common(pdev); 463 464 for (i = 0; i < 2; i++) { 465 reset_addr = pci_iomap(pdev, reset_bar[i], 0); 466 if (!reset_addr) { 467 dev_err(&pdev->dev, "Failed to remap reset " 468 "space %d (BAR%d)\n", i, reset_bar[i]); 469 } else { 470 /* reset the SJA1000 chip */ 471 iowrite8(0x1, reset_addr); 472 udelay(100); 473 pci_iounmap(pdev, reset_addr); 474 } 475 } 476 } 477 478 /* Special reset function for Marathon CAN-bus-PCIe card */ 479 static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev) 480 { 481 void __iomem *addr; 482 void __iomem *reset_addr; 483 int i; 484 485 plx9056_pci_reset_common(pdev); 486 487 for (i = 0; i < 2; i++) { 488 struct plx_pci_channel_map *chan_map = 489 &plx_pci_card_info_marathon_pcie.chan_map_tbl[i]; 490 addr = pci_iomap(pdev, chan_map->bar, chan_map->size); 491 if (!addr) { 492 dev_err(&pdev->dev, "Failed to remap reset " 493 "space %d (BAR%d)\n", i, chan_map->bar); 494 } else { 495 /* reset the SJA1000 chip */ 496 #define MARATHON_PCIE_RESET_OFFSET 32 497 reset_addr = addr + chan_map->offset + 498 MARATHON_PCIE_RESET_OFFSET; 499 iowrite8(0x1, reset_addr); 500 udelay(100); 501 pci_iounmap(pdev, addr); 502 } 503 } 504 } 505 506 /* Special reset function for ASEM Dual CAN raw card */ 507 static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev) 508 { 509 void __iomem *bar0_addr; 510 u8 tmpval; 511 512 plx_pci_reset_common(pdev); 513 514 bar0_addr = pci_iomap(pdev, 0, 0); 515 if (!bar0_addr) { 516 dev_err(&pdev->dev, "Failed to remap reset space 0 (BAR0)\n"); 517 return; 518 } 519 520 /* reset the two SJA1000 chips */ 521 tmpval = ioread8(bar0_addr + ASEM_RAW_CAN_RST_REGISTER); 522 tmpval &= ~(ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2); 523 iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER); 524 usleep_range(300, 400); 525 tmpval |= ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2; 526 iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER); 527 usleep_range(300, 400); 528 pci_iounmap(pdev, bar0_addr); 529 } 530 531 static void plx_pci_del_card(struct pci_dev *pdev) 532 { 533 struct plx_pci_card *card = pci_get_drvdata(pdev); 534 struct net_device *dev; 535 struct sja1000_priv *priv; 536 int i = 0; 537 538 for (i = 0; i < PLX_PCI_MAX_CHAN; i++) { 539 dev = card->net_dev[i]; 540 if (!dev) 541 continue; 542 543 dev_info(&pdev->dev, "Removing %s\n", dev->name); 544 unregister_sja1000dev(dev); 545 priv = netdev_priv(dev); 546 if (priv->reg_base) 547 pci_iounmap(pdev, priv->reg_base); 548 free_sja1000dev(dev); 549 } 550 551 card->reset_func(pdev); 552 553 /* 554 * Disable interrupts from PCI-card and disable local 555 * interrupts 556 */ 557 if (pdev->device != PCI_DEVICE_ID_PLX_9056 && 558 pdev->device != MARATHON_PCIE_DEVICE_ID) 559 iowrite32(0x0, card->conf_addr + PLX_INTCSR); 560 else 561 iowrite32(0x0, card->conf_addr + PLX9056_INTCSR); 562 563 if (card->conf_addr) 564 pci_iounmap(pdev, card->conf_addr); 565 566 kfree(card); 567 568 pci_disable_device(pdev); 569 } 570 571 /* 572 * Probe PLX90xx based device for the SJA1000 chips and register each 573 * available CAN channel to SJA1000 Socket-CAN subsystem. 574 */ 575 static int plx_pci_add_card(struct pci_dev *pdev, 576 const struct pci_device_id *ent) 577 { 578 struct sja1000_priv *priv; 579 struct net_device *dev; 580 struct plx_pci_card *card; 581 struct plx_pci_card_info *ci; 582 int err, i; 583 u32 val; 584 void __iomem *addr; 585 586 ci = (struct plx_pci_card_info *)ent->driver_data; 587 588 if (pci_enable_device(pdev) < 0) { 589 dev_err(&pdev->dev, "Failed to enable PCI device\n"); 590 return -ENODEV; 591 } 592 593 dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n", 594 ci->name, PCI_SLOT(pdev->devfn)); 595 596 /* Allocate card structures to hold addresses, ... */ 597 card = kzalloc_obj(*card); 598 if (!card) { 599 pci_disable_device(pdev); 600 return -ENOMEM; 601 } 602 603 pci_set_drvdata(pdev, card); 604 605 card->channels = 0; 606 607 /* Remap PLX90xx configuration space */ 608 addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size); 609 if (!addr) { 610 err = -ENOMEM; 611 dev_err(&pdev->dev, "Failed to remap configuration space " 612 "(BAR%d)\n", ci->conf_map.bar); 613 goto failure_cleanup; 614 } 615 card->conf_addr = addr + ci->conf_map.offset; 616 617 ci->reset_func(pdev); 618 card->reset_func = ci->reset_func; 619 620 /* Detect available channels */ 621 for (i = 0; i < ci->channel_count; i++) { 622 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i]; 623 624 dev = alloc_sja1000dev(0); 625 if (!dev) { 626 err = -ENOMEM; 627 goto failure_cleanup; 628 } 629 630 card->net_dev[i] = dev; 631 priv = netdev_priv(dev); 632 priv->priv = card; 633 priv->irq_flags = IRQF_SHARED; 634 635 dev->irq = pdev->irq; 636 637 /* 638 * Remap IO space of the SJA1000 chips 639 * This is device-dependent mapping 640 */ 641 addr = pci_iomap(pdev, cm->bar, cm->size); 642 if (!addr) { 643 err = -ENOMEM; 644 dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar); 645 goto failure_cleanup; 646 } 647 648 priv->reg_base = addr + cm->offset; 649 priv->read_reg = plx_pci_read_reg; 650 priv->write_reg = plx_pci_write_reg; 651 652 /* Check if channel is present */ 653 if (plx_pci_check_sja1000(priv)) { 654 priv->can.clock.freq = ci->can_clock; 655 priv->ocr = ci->ocr; 656 priv->cdr = ci->cdr; 657 658 SET_NETDEV_DEV(dev, &pdev->dev); 659 dev->dev_id = i; 660 661 /* Register SJA1000 device */ 662 err = register_sja1000dev(dev); 663 if (err) { 664 dev_err(&pdev->dev, "Registering device failed " 665 "(err=%d)\n", err); 666 goto failure_cleanup; 667 } 668 669 card->channels++; 670 671 dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d " 672 "registered as %s\n", i + 1, priv->reg_base, 673 dev->irq, dev->name); 674 } else { 675 dev_err(&pdev->dev, "Channel #%d not detected\n", 676 i + 1); 677 free_sja1000dev(dev); 678 card->net_dev[i] = NULL; 679 } 680 } 681 682 if (!card->channels) { 683 err = -ENODEV; 684 goto failure_cleanup; 685 } 686 687 /* 688 * Enable interrupts from PCI-card (PLX90xx) and enable Local_1, 689 * Local_2 interrupts from the SJA1000 chips 690 */ 691 if (pdev->device != PCI_DEVICE_ID_PLX_9056 && 692 pdev->device != MARATHON_PCIE_DEVICE_ID) { 693 val = ioread32(card->conf_addr + PLX_INTCSR); 694 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH) 695 val |= PLX_LINT1_EN | PLX_PCI_INT_EN; 696 else 697 val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN; 698 iowrite32(val, card->conf_addr + PLX_INTCSR); 699 } else { 700 iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN, 701 card->conf_addr + PLX9056_INTCSR); 702 } 703 return 0; 704 705 failure_cleanup: 706 dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err); 707 708 plx_pci_del_card(pdev); 709 710 return err; 711 } 712 713 static struct pci_driver plx_pci_driver = { 714 .name = DRV_NAME, 715 .id_table = plx_pci_tbl, 716 .probe = plx_pci_add_card, 717 .remove = plx_pci_del_card, 718 }; 719 720 module_pci_driver(plx_pci_driver); 721