1 // SPDX-License-Identifier: GPL-2.0 2 // tscs42xx.c -- TSCS42xx ALSA SoC Audio driver 3 // Copyright 2017 Tempo Semiconductor, Inc. 4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> 5 6 #include <linux/kernel.h> 7 #include <linux/device.h> 8 #include <linux/regmap.h> 9 #include <linux/i2c.h> 10 #include <linux/err.h> 11 #include <linux/string.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/mutex.h> 15 #include <linux/clk.h> 16 #include <sound/tlv.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc.h> 19 #include <sound/soc-dapm.h> 20 21 #include "tscs42xx.h" 22 23 #define COEFF_SIZE 3 24 #define BIQUAD_COEFF_COUNT 5 25 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT) 26 27 #define COEFF_RAM_MAX_ADDR 0xcd 28 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1) 29 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT) 30 31 struct tscs42xx { 32 33 int bclk_ratio; 34 int samplerate; 35 struct mutex audio_params_lock; 36 37 u8 coeff_ram[COEFF_RAM_SIZE]; 38 bool coeff_ram_synced; 39 struct mutex coeff_ram_lock; 40 41 struct mutex pll_lock; 42 43 struct regmap *regmap; 44 45 struct clk *sysclk; 46 int sysclk_src_id; 47 }; 48 49 struct coeff_ram_ctl { 50 unsigned int addr; 51 struct soc_bytes_ext bytes_ext; 52 }; 53 54 static bool tscs42xx_volatile(struct device *dev, unsigned int reg) 55 { 56 switch (reg) { 57 case R_DACCRWRL: 58 case R_DACCRWRM: 59 case R_DACCRWRH: 60 case R_DACCRRDL: 61 case R_DACCRRDM: 62 case R_DACCRRDH: 63 case R_DACCRSTAT: 64 case R_DACCRADDR: 65 case R_PLLCTL0: 66 return true; 67 default: 68 return false; 69 } 70 } 71 72 static bool tscs42xx_precious(struct device *dev, unsigned int reg) 73 { 74 switch (reg) { 75 case R_DACCRWRL: 76 case R_DACCRWRM: 77 case R_DACCRWRH: 78 case R_DACCRRDL: 79 case R_DACCRRDM: 80 case R_DACCRRDH: 81 return true; 82 default: 83 return false; 84 } 85 } 86 87 static const struct regmap_config tscs42xx_regmap = { 88 .reg_bits = 8, 89 .val_bits = 8, 90 91 .volatile_reg = tscs42xx_volatile, 92 .precious_reg = tscs42xx_precious, 93 .max_register = R_DACMBCREL3H, 94 95 .cache_type = REGCACHE_RBTREE, 96 .can_multi_write = true, 97 }; 98 99 #define MAX_PLL_LOCK_20MS_WAITS 1 100 static bool plls_locked(struct snd_soc_component *component) 101 { 102 int ret; 103 int count = MAX_PLL_LOCK_20MS_WAITS; 104 105 do { 106 ret = snd_soc_component_read(component, R_PLLCTL0); 107 if (ret < 0) { 108 dev_err(component->dev, 109 "Failed to read PLL lock status (%d)\n", ret); 110 return false; 111 } else if (ret > 0) { 112 return true; 113 } 114 msleep(20); 115 } while (count--); 116 117 return false; 118 } 119 120 static int sample_rate_to_pll_freq_out(int sample_rate) 121 { 122 switch (sample_rate) { 123 case 11025: 124 case 22050: 125 case 44100: 126 case 88200: 127 return 112896000; 128 case 8000: 129 case 16000: 130 case 32000: 131 case 48000: 132 case 96000: 133 return 122880000; 134 default: 135 return -EINVAL; 136 } 137 } 138 139 #define DACCRSTAT_MAX_TRYS 10 140 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram, 141 unsigned int addr, unsigned int coeff_cnt) 142 { 143 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 144 int cnt; 145 int trys; 146 int ret; 147 148 for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) { 149 150 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) { 151 ret = snd_soc_component_read(component, R_DACCRSTAT); 152 if (ret < 0) { 153 dev_err(component->dev, 154 "Failed to read stat (%d)\n", ret); 155 return ret; 156 } 157 if (!ret) 158 break; 159 } 160 161 if (trys == DACCRSTAT_MAX_TRYS) { 162 ret = -EIO; 163 dev_err(component->dev, 164 "dac coefficient write error (%d)\n", ret); 165 return ret; 166 } 167 168 ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr); 169 if (ret < 0) { 170 dev_err(component->dev, 171 "Failed to write dac ram address (%d)\n", ret); 172 return ret; 173 } 174 175 ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL, 176 &coeff_ram[addr * COEFF_SIZE], 177 COEFF_SIZE); 178 if (ret < 0) { 179 dev_err(component->dev, 180 "Failed to write dac ram (%d)\n", ret); 181 return ret; 182 } 183 } 184 185 return 0; 186 } 187 188 static int power_up_audio_plls(struct snd_soc_component *component) 189 { 190 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 191 int freq_out; 192 int ret; 193 unsigned int mask; 194 unsigned int val; 195 196 freq_out = sample_rate_to_pll_freq_out(tscs42xx->samplerate); 197 switch (freq_out) { 198 case 122880000: /* 48k */ 199 mask = RM_PLLCTL1C_PDB_PLL1; 200 val = RV_PLLCTL1C_PDB_PLL1_ENABLE; 201 break; 202 case 112896000: /* 44.1k */ 203 mask = RM_PLLCTL1C_PDB_PLL2; 204 val = RV_PLLCTL1C_PDB_PLL2_ENABLE; 205 break; 206 default: 207 ret = -EINVAL; 208 dev_err(component->dev, 209 "Unrecognized PLL output freq (%d)\n", ret); 210 return ret; 211 } 212 213 mutex_lock(&tscs42xx->pll_lock); 214 215 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val); 216 if (ret < 0) { 217 dev_err(component->dev, "Failed to turn PLL on (%d)\n", ret); 218 goto exit; 219 } 220 221 if (!plls_locked(component)) { 222 dev_err(component->dev, "Failed to lock plls\n"); 223 ret = -ENOMSG; 224 goto exit; 225 } 226 227 ret = 0; 228 exit: 229 mutex_unlock(&tscs42xx->pll_lock); 230 231 return ret; 232 } 233 234 static int power_down_audio_plls(struct snd_soc_component *component) 235 { 236 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 237 int ret; 238 239 mutex_lock(&tscs42xx->pll_lock); 240 241 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, 242 RM_PLLCTL1C_PDB_PLL1, 243 RV_PLLCTL1C_PDB_PLL1_DISABLE); 244 if (ret < 0) { 245 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret); 246 goto exit; 247 } 248 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, 249 RM_PLLCTL1C_PDB_PLL2, 250 RV_PLLCTL1C_PDB_PLL2_DISABLE); 251 if (ret < 0) { 252 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret); 253 goto exit; 254 } 255 256 ret = 0; 257 exit: 258 mutex_unlock(&tscs42xx->pll_lock); 259 260 return ret; 261 } 262 263 static int coeff_ram_get(struct snd_kcontrol *kcontrol, 264 struct snd_ctl_elem_value *ucontrol) 265 { 266 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 267 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 268 struct coeff_ram_ctl *ctl = 269 (struct coeff_ram_ctl *)kcontrol->private_value; 270 struct soc_bytes_ext *params = &ctl->bytes_ext; 271 272 mutex_lock(&tscs42xx->coeff_ram_lock); 273 274 memcpy(ucontrol->value.bytes.data, 275 &tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], params->max); 276 277 mutex_unlock(&tscs42xx->coeff_ram_lock); 278 279 return 0; 280 } 281 282 static int coeff_ram_put(struct snd_kcontrol *kcontrol, 283 struct snd_ctl_elem_value *ucontrol) 284 { 285 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 286 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 287 struct coeff_ram_ctl *ctl = 288 (struct coeff_ram_ctl *)kcontrol->private_value; 289 struct soc_bytes_ext *params = &ctl->bytes_ext; 290 unsigned int coeff_cnt = params->max / COEFF_SIZE; 291 int ret; 292 293 mutex_lock(&tscs42xx->coeff_ram_lock); 294 295 tscs42xx->coeff_ram_synced = false; 296 297 memcpy(&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], 298 ucontrol->value.bytes.data, params->max); 299 300 mutex_lock(&tscs42xx->pll_lock); 301 302 if (plls_locked(component)) { 303 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 304 ctl->addr, coeff_cnt); 305 if (ret < 0) { 306 dev_err(component->dev, 307 "Failed to flush coeff ram cache (%d)\n", ret); 308 goto exit; 309 } 310 tscs42xx->coeff_ram_synced = true; 311 } 312 313 ret = 0; 314 exit: 315 mutex_unlock(&tscs42xx->pll_lock); 316 317 mutex_unlock(&tscs42xx->coeff_ram_lock); 318 319 return ret; 320 } 321 322 /* Input L Capture Route */ 323 static char const * const input_select_text[] = { 324 "Line 1", "Line 2", "Line 3", "D2S" 325 }; 326 327 static const struct soc_enum left_input_select_enum = 328 SOC_ENUM_SINGLE(R_INSELL, FB_INSELL, ARRAY_SIZE(input_select_text), 329 input_select_text); 330 331 static const struct snd_kcontrol_new left_input_select = 332 SOC_DAPM_ENUM("LEFT_INPUT_SELECT_ENUM", left_input_select_enum); 333 334 /* Input R Capture Route */ 335 static const struct soc_enum right_input_select_enum = 336 SOC_ENUM_SINGLE(R_INSELR, FB_INSELR, ARRAY_SIZE(input_select_text), 337 input_select_text); 338 339 static const struct snd_kcontrol_new right_input_select = 340 SOC_DAPM_ENUM("RIGHT_INPUT_SELECT_ENUM", right_input_select_enum); 341 342 /* Input Channel Mapping */ 343 static char const * const ch_map_select_text[] = { 344 "Normal", "Left to Right", "Right to Left", "Swap" 345 }; 346 347 static const struct soc_enum ch_map_select_enum = 348 SOC_ENUM_SINGLE(R_AIC2, FB_AIC2_ADCDSEL, ARRAY_SIZE(ch_map_select_text), 349 ch_map_select_text); 350 351 static int dapm_vref_event(struct snd_soc_dapm_widget *w, 352 struct snd_kcontrol *kcontrol, int event) 353 { 354 msleep(20); 355 return 0; 356 } 357 358 static int dapm_micb_event(struct snd_soc_dapm_widget *w, 359 struct snd_kcontrol *kcontrol, int event) 360 { 361 msleep(20); 362 return 0; 363 } 364 365 static int pll_event(struct snd_soc_dapm_widget *w, 366 struct snd_kcontrol *kcontrol, int event) 367 { 368 struct snd_soc_component *component = 369 snd_soc_dapm_to_component(w->dapm); 370 int ret; 371 372 if (SND_SOC_DAPM_EVENT_ON(event)) 373 ret = power_up_audio_plls(component); 374 else 375 ret = power_down_audio_plls(component); 376 377 return ret; 378 } 379 380 static int dac_event(struct snd_soc_dapm_widget *w, 381 struct snd_kcontrol *kcontrol, int event) 382 { 383 struct snd_soc_component *component = 384 snd_soc_dapm_to_component(w->dapm); 385 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 386 int ret; 387 388 mutex_lock(&tscs42xx->coeff_ram_lock); 389 390 if (!tscs42xx->coeff_ram_synced) { 391 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 0x00, 392 COEFF_RAM_COEFF_COUNT); 393 if (ret < 0) 394 goto exit; 395 tscs42xx->coeff_ram_synced = true; 396 } 397 398 ret = 0; 399 exit: 400 mutex_unlock(&tscs42xx->coeff_ram_lock); 401 402 return ret; 403 } 404 405 static const struct snd_soc_dapm_widget tscs42xx_dapm_widgets[] = { 406 /* Vref */ 407 SND_SOC_DAPM_SUPPLY_S("Vref", 1, R_PWRM2, FB_PWRM2_VREF, 0, 408 dapm_vref_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 409 410 /* PLL */ 411 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, pll_event, 412 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 413 414 /* Headphone */ 415 SND_SOC_DAPM_DAC_E("DAC L", "HiFi Playback", R_PWRM2, FB_PWRM2_HPL, 0, 416 dac_event, SND_SOC_DAPM_POST_PMU), 417 SND_SOC_DAPM_DAC_E("DAC R", "HiFi Playback", R_PWRM2, FB_PWRM2_HPR, 0, 418 dac_event, SND_SOC_DAPM_POST_PMU), 419 SND_SOC_DAPM_OUTPUT("Headphone L"), 420 SND_SOC_DAPM_OUTPUT("Headphone R"), 421 422 /* Speaker */ 423 SND_SOC_DAPM_DAC_E("ClassD L", "HiFi Playback", 424 R_PWRM2, FB_PWRM2_SPKL, 0, 425 dac_event, SND_SOC_DAPM_POST_PMU), 426 SND_SOC_DAPM_DAC_E("ClassD R", "HiFi Playback", 427 R_PWRM2, FB_PWRM2_SPKR, 0, 428 dac_event, SND_SOC_DAPM_POST_PMU), 429 SND_SOC_DAPM_OUTPUT("Speaker L"), 430 SND_SOC_DAPM_OUTPUT("Speaker R"), 431 432 /* Capture */ 433 SND_SOC_DAPM_PGA("Analog In PGA L", R_PWRM1, FB_PWRM1_PGAL, 0, NULL, 0), 434 SND_SOC_DAPM_PGA("Analog In PGA R", R_PWRM1, FB_PWRM1_PGAR, 0, NULL, 0), 435 SND_SOC_DAPM_PGA("Analog Boost L", R_PWRM1, FB_PWRM1_BSTL, 0, NULL, 0), 436 SND_SOC_DAPM_PGA("Analog Boost R", R_PWRM1, FB_PWRM1_BSTR, 0, NULL, 0), 437 SND_SOC_DAPM_PGA("ADC Mute", R_CNVRTR0, FB_CNVRTR0_HPOR, true, NULL, 0), 438 SND_SOC_DAPM_ADC("ADC L", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCL, 0), 439 SND_SOC_DAPM_ADC("ADC R", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCR, 0), 440 441 /* Capture Input */ 442 SND_SOC_DAPM_MUX("Input L Capture Route", R_PWRM2, 443 FB_PWRM2_INSELL, 0, &left_input_select), 444 SND_SOC_DAPM_MUX("Input R Capture Route", R_PWRM2, 445 FB_PWRM2_INSELR, 0, &right_input_select), 446 447 /* Digital Mic */ 448 SND_SOC_DAPM_SUPPLY_S("Digital Mic Enable", 2, R_DMICCTL, 449 FB_DMICCTL_DMICEN, 0, NULL, 450 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 451 452 /* Analog Mic */ 453 SND_SOC_DAPM_SUPPLY_S("Mic Bias", 2, R_PWRM1, FB_PWRM1_MICB, 454 0, dapm_micb_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 455 456 /* Line In */ 457 SND_SOC_DAPM_INPUT("Line In 1 L"), 458 SND_SOC_DAPM_INPUT("Line In 1 R"), 459 SND_SOC_DAPM_INPUT("Line In 2 L"), 460 SND_SOC_DAPM_INPUT("Line In 2 R"), 461 SND_SOC_DAPM_INPUT("Line In 3 L"), 462 SND_SOC_DAPM_INPUT("Line In 3 R"), 463 }; 464 465 static const struct snd_soc_dapm_route tscs42xx_intercon[] = { 466 {"DAC L", NULL, "PLL"}, 467 {"DAC R", NULL, "PLL"}, 468 {"DAC L", NULL, "Vref"}, 469 {"DAC R", NULL, "Vref"}, 470 {"Headphone L", NULL, "DAC L"}, 471 {"Headphone R", NULL, "DAC R"}, 472 473 {"ClassD L", NULL, "PLL"}, 474 {"ClassD R", NULL, "PLL"}, 475 {"ClassD L", NULL, "Vref"}, 476 {"ClassD R", NULL, "Vref"}, 477 {"Speaker L", NULL, "ClassD L"}, 478 {"Speaker R", NULL, "ClassD R"}, 479 480 {"Input L Capture Route", NULL, "Vref"}, 481 {"Input R Capture Route", NULL, "Vref"}, 482 483 {"Mic Bias", NULL, "Vref"}, 484 485 {"Input L Capture Route", "Line 1", "Line In 1 L"}, 486 {"Input R Capture Route", "Line 1", "Line In 1 R"}, 487 {"Input L Capture Route", "Line 2", "Line In 2 L"}, 488 {"Input R Capture Route", "Line 2", "Line In 2 R"}, 489 {"Input L Capture Route", "Line 3", "Line In 3 L"}, 490 {"Input R Capture Route", "Line 3", "Line In 3 R"}, 491 492 {"Analog In PGA L", NULL, "Input L Capture Route"}, 493 {"Analog In PGA R", NULL, "Input R Capture Route"}, 494 {"Analog Boost L", NULL, "Analog In PGA L"}, 495 {"Analog Boost R", NULL, "Analog In PGA R"}, 496 {"ADC Mute", NULL, "Analog Boost L"}, 497 {"ADC Mute", NULL, "Analog Boost R"}, 498 {"ADC L", NULL, "PLL"}, 499 {"ADC R", NULL, "PLL"}, 500 {"ADC L", NULL, "ADC Mute"}, 501 {"ADC R", NULL, "ADC Mute"}, 502 }; 503 504 /************ 505 * CONTROLS * 506 ************/ 507 508 static char const * const eq_band_enable_text[] = { 509 "Prescale only", 510 "Band1", 511 "Band1:2", 512 "Band1:3", 513 "Band1:4", 514 "Band1:5", 515 "Band1:6", 516 }; 517 518 static char const * const level_detection_text[] = { 519 "Average", 520 "Peak", 521 }; 522 523 static char const * const level_detection_window_text[] = { 524 "512 Samples", 525 "64 Samples", 526 }; 527 528 static char const * const compressor_ratio_text[] = { 529 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1", 530 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1", 531 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1", 532 }; 533 534 static DECLARE_TLV_DB_SCALE(hpvol_scale, -8850, 75, 0); 535 static DECLARE_TLV_DB_SCALE(spkvol_scale, -7725, 75, 0); 536 static DECLARE_TLV_DB_SCALE(dacvol_scale, -9563, 38, 0); 537 static DECLARE_TLV_DB_SCALE(adcvol_scale, -7125, 38, 0); 538 static DECLARE_TLV_DB_SCALE(invol_scale, -1725, 75, 0); 539 static DECLARE_TLV_DB_SCALE(mic_boost_scale, 0, 1000, 0); 540 static DECLARE_TLV_DB_MINMAX(mugain_scale, 0, 4650); 541 static DECLARE_TLV_DB_MINMAX(compth_scale, -9562, 0); 542 543 static const struct soc_enum eq1_band_enable_enum = 544 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ1_BE, 545 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 546 547 static const struct soc_enum eq2_band_enable_enum = 548 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ2_BE, 549 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 550 551 static const struct soc_enum cle_level_detection_enum = 552 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_LVL_MODE, 553 ARRAY_SIZE(level_detection_text), 554 level_detection_text); 555 556 static const struct soc_enum cle_level_detection_window_enum = 557 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_WINDOWSEL, 558 ARRAY_SIZE(level_detection_window_text), 559 level_detection_window_text); 560 561 static const struct soc_enum mbc_level_detection_enums[] = { 562 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1, 563 ARRAY_SIZE(level_detection_text), 564 level_detection_text), 565 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2, 566 ARRAY_SIZE(level_detection_text), 567 level_detection_text), 568 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3, 569 ARRAY_SIZE(level_detection_text), 570 level_detection_text), 571 }; 572 573 static const struct soc_enum mbc_level_detection_window_enums[] = { 574 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1, 575 ARRAY_SIZE(level_detection_window_text), 576 level_detection_window_text), 577 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2, 578 ARRAY_SIZE(level_detection_window_text), 579 level_detection_window_text), 580 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3, 581 ARRAY_SIZE(level_detection_window_text), 582 level_detection_window_text), 583 }; 584 585 static const struct soc_enum compressor_ratio_enum = 586 SOC_ENUM_SINGLE(R_CMPRAT, FB_CMPRAT, 587 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 588 589 static const struct soc_enum dac_mbc1_compressor_ratio_enum = 590 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT1_RATIO, 591 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 592 593 static const struct soc_enum dac_mbc2_compressor_ratio_enum = 594 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT2_RATIO, 595 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 596 597 static const struct soc_enum dac_mbc3_compressor_ratio_enum = 598 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT3_RATIO, 599 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 600 601 static int bytes_info_ext(struct snd_kcontrol *kcontrol, 602 struct snd_ctl_elem_info *ucontrol) 603 { 604 struct coeff_ram_ctl *ctl = 605 (struct coeff_ram_ctl *)kcontrol->private_value; 606 struct soc_bytes_ext *params = &ctl->bytes_ext; 607 608 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 609 ucontrol->count = params->max; 610 611 return 0; 612 } 613 614 #define COEFF_RAM_CTL(xname, xcount, xaddr) \ 615 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 616 .info = bytes_info_ext, \ 617 .get = coeff_ram_get, .put = coeff_ram_put, \ 618 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \ 619 .addr = xaddr, \ 620 .bytes_ext = {.max = xcount, }, \ 621 } \ 622 } 623 624 static const struct snd_kcontrol_new tscs42xx_snd_controls[] = { 625 /* Volumes */ 626 SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR, 627 FB_HPVOLL, 0x7F, 0, hpvol_scale), 628 SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR, 629 FB_SPKVOLL, 0x7F, 0, spkvol_scale), 630 SOC_DOUBLE_R_TLV("Master Volume", R_DACVOLL, R_DACVOLR, 631 FB_DACVOLL, 0xFF, 0, dacvol_scale), 632 SOC_DOUBLE_R_TLV("PCM Volume", R_ADCVOLL, R_ADCVOLR, 633 FB_ADCVOLL, 0xFF, 0, adcvol_scale), 634 SOC_DOUBLE_R_TLV("Input Volume", R_INVOLL, R_INVOLR, 635 FB_INVOLL, 0x3F, 0, invol_scale), 636 637 /* INSEL */ 638 SOC_DOUBLE_R_TLV("Mic Boost Volume", R_INSELL, R_INSELR, 639 FB_INSELL_MICBSTL, FV_INSELL_MICBSTL_30DB, 640 0, mic_boost_scale), 641 642 /* Input Channel Map */ 643 SOC_ENUM("Input Channel Map", ch_map_select_enum), 644 645 /* Mic Bias */ 646 SOC_SINGLE("Mic Bias Boost Switch", 0x71, 0x07, 1, 0), 647 648 /* Headphone Auto Switching */ 649 SOC_SINGLE("Headphone Auto Switching Switch", 650 R_CTL, FB_CTL_HPSWEN, 1, 0), 651 SOC_SINGLE("Headphone Detect Polarity Toggle Switch", 652 R_CTL, FB_CTL_HPSWPOL, 1, 0), 653 654 /* Coefficient Ram */ 655 COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00), 656 COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05), 657 COEFF_RAM_CTL("Cascade1L BiQuad3", BIQUAD_SIZE, 0x0a), 658 COEFF_RAM_CTL("Cascade1L BiQuad4", BIQUAD_SIZE, 0x0f), 659 COEFF_RAM_CTL("Cascade1L BiQuad5", BIQUAD_SIZE, 0x14), 660 COEFF_RAM_CTL("Cascade1L BiQuad6", BIQUAD_SIZE, 0x19), 661 662 COEFF_RAM_CTL("Cascade1R BiQuad1", BIQUAD_SIZE, 0x20), 663 COEFF_RAM_CTL("Cascade1R BiQuad2", BIQUAD_SIZE, 0x25), 664 COEFF_RAM_CTL("Cascade1R BiQuad3", BIQUAD_SIZE, 0x2a), 665 COEFF_RAM_CTL("Cascade1R BiQuad4", BIQUAD_SIZE, 0x2f), 666 COEFF_RAM_CTL("Cascade1R BiQuad5", BIQUAD_SIZE, 0x34), 667 COEFF_RAM_CTL("Cascade1R BiQuad6", BIQUAD_SIZE, 0x39), 668 669 COEFF_RAM_CTL("Cascade1L Prescale", COEFF_SIZE, 0x1f), 670 COEFF_RAM_CTL("Cascade1R Prescale", COEFF_SIZE, 0x3f), 671 672 COEFF_RAM_CTL("Cascade2L BiQuad1", BIQUAD_SIZE, 0x40), 673 COEFF_RAM_CTL("Cascade2L BiQuad2", BIQUAD_SIZE, 0x45), 674 COEFF_RAM_CTL("Cascade2L BiQuad3", BIQUAD_SIZE, 0x4a), 675 COEFF_RAM_CTL("Cascade2L BiQuad4", BIQUAD_SIZE, 0x4f), 676 COEFF_RAM_CTL("Cascade2L BiQuad5", BIQUAD_SIZE, 0x54), 677 COEFF_RAM_CTL("Cascade2L BiQuad6", BIQUAD_SIZE, 0x59), 678 679 COEFF_RAM_CTL("Cascade2R BiQuad1", BIQUAD_SIZE, 0x60), 680 COEFF_RAM_CTL("Cascade2R BiQuad2", BIQUAD_SIZE, 0x65), 681 COEFF_RAM_CTL("Cascade2R BiQuad3", BIQUAD_SIZE, 0x6a), 682 COEFF_RAM_CTL("Cascade2R BiQuad4", BIQUAD_SIZE, 0x6f), 683 COEFF_RAM_CTL("Cascade2R BiQuad5", BIQUAD_SIZE, 0x74), 684 COEFF_RAM_CTL("Cascade2R BiQuad6", BIQUAD_SIZE, 0x79), 685 686 COEFF_RAM_CTL("Cascade2L Prescale", COEFF_SIZE, 0x5f), 687 COEFF_RAM_CTL("Cascade2R Prescale", COEFF_SIZE, 0x7f), 688 689 COEFF_RAM_CTL("Bass Extraction BiQuad1", BIQUAD_SIZE, 0x80), 690 COEFF_RAM_CTL("Bass Extraction BiQuad2", BIQUAD_SIZE, 0x85), 691 692 COEFF_RAM_CTL("Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 693 COEFF_RAM_CTL("Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 694 695 COEFF_RAM_CTL("Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 696 697 COEFF_RAM_CTL("Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 698 699 COEFF_RAM_CTL("Bass Mix", COEFF_SIZE, 0x96), 700 701 COEFF_RAM_CTL("Treb Extraction BiQuad1", BIQUAD_SIZE, 0x97), 702 COEFF_RAM_CTL("Treb Extraction BiQuad2", BIQUAD_SIZE, 0x9c), 703 704 COEFF_RAM_CTL("Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 705 COEFF_RAM_CTL("Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 706 707 COEFF_RAM_CTL("Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 708 709 COEFF_RAM_CTL("Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 710 711 COEFF_RAM_CTL("Treb Mix", COEFF_SIZE, 0xad), 712 713 COEFF_RAM_CTL("3D", COEFF_SIZE, 0xae), 714 715 COEFF_RAM_CTL("3D Mix", COEFF_SIZE, 0xaf), 716 717 COEFF_RAM_CTL("MBC1 BiQuad1", BIQUAD_SIZE, 0xb0), 718 COEFF_RAM_CTL("MBC1 BiQuad2", BIQUAD_SIZE, 0xb5), 719 720 COEFF_RAM_CTL("MBC2 BiQuad1", BIQUAD_SIZE, 0xba), 721 COEFF_RAM_CTL("MBC2 BiQuad2", BIQUAD_SIZE, 0xbf), 722 723 COEFF_RAM_CTL("MBC3 BiQuad1", BIQUAD_SIZE, 0xc4), 724 COEFF_RAM_CTL("MBC3 BiQuad2", BIQUAD_SIZE, 0xc9), 725 726 /* EQ */ 727 SOC_SINGLE("EQ1 Switch", R_CONFIG1, FB_CONFIG1_EQ1_EN, 1, 0), 728 SOC_SINGLE("EQ2 Switch", R_CONFIG1, FB_CONFIG1_EQ2_EN, 1, 0), 729 SOC_ENUM("EQ1 Band Enable", eq1_band_enable_enum), 730 SOC_ENUM("EQ2 Band Enable", eq2_band_enable_enum), 731 732 /* CLE */ 733 SOC_ENUM("CLE Level Detect", 734 cle_level_detection_enum), 735 SOC_ENUM("CLE Level Detect Win", 736 cle_level_detection_window_enum), 737 SOC_SINGLE("Expander Switch", 738 R_CLECTL, FB_CLECTL_EXP_EN, 1, 0), 739 SOC_SINGLE("Limiter Switch", 740 R_CLECTL, FB_CLECTL_LIMIT_EN, 1, 0), 741 SOC_SINGLE("Comp Switch", 742 R_CLECTL, FB_CLECTL_COMP_EN, 1, 0), 743 SOC_SINGLE_TLV("CLE Make-Up Gain Volume", 744 R_MUGAIN, FB_MUGAIN_CLEMUG, 0x1f, 0, mugain_scale), 745 SOC_SINGLE_TLV("Comp Thresh Volume", 746 R_COMPTH, FB_COMPTH, 0xff, 0, compth_scale), 747 SOC_ENUM("Comp Ratio", compressor_ratio_enum), 748 SND_SOC_BYTES("Comp Atk Time", R_CATKTCL, 2), 749 750 /* Effects */ 751 SOC_SINGLE("3D Switch", R_FXCTL, FB_FXCTL_3DEN, 1, 0), 752 SOC_SINGLE("Treble Switch", R_FXCTL, FB_FXCTL_TEEN, 1, 0), 753 SOC_SINGLE("Treble Bypass Switch", R_FXCTL, FB_FXCTL_TNLFBYPASS, 1, 0), 754 SOC_SINGLE("Bass Switch", R_FXCTL, FB_FXCTL_BEEN, 1, 0), 755 SOC_SINGLE("Bass Bypass Switch", R_FXCTL, FB_FXCTL_BNLFBYPASS, 1, 0), 756 757 /* MBC */ 758 SOC_SINGLE("MBC Band1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0), 759 SOC_SINGLE("MBC Band2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0), 760 SOC_SINGLE("MBC Band3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0), 761 SOC_ENUM("MBC Band1 Level Detect", 762 mbc_level_detection_enums[0]), 763 SOC_ENUM("MBC Band2 Level Detect", 764 mbc_level_detection_enums[1]), 765 SOC_ENUM("MBC Band3 Level Detect", 766 mbc_level_detection_enums[2]), 767 SOC_ENUM("MBC Band1 Level Detect Win", 768 mbc_level_detection_window_enums[0]), 769 SOC_ENUM("MBC Band2 Level Detect Win", 770 mbc_level_detection_window_enums[1]), 771 SOC_ENUM("MBC Band3 Level Detect Win", 772 mbc_level_detection_window_enums[2]), 773 774 SOC_SINGLE("MBC1 Phase Invert Switch", 775 R_DACMBCMUG1, FB_DACMBCMUG1_PHASE, 1, 0), 776 SOC_SINGLE_TLV("DAC MBC1 Make-Up Gain Volume", 777 R_DACMBCMUG1, FB_DACMBCMUG1_MUGAIN, 0x1f, 0, mugain_scale), 778 SOC_SINGLE_TLV("DAC MBC1 Comp Thresh Volume", 779 R_DACMBCTHR1, FB_DACMBCTHR1_THRESH, 0xff, 0, compth_scale), 780 SOC_ENUM("DAC MBC1 Comp Ratio", 781 dac_mbc1_compressor_ratio_enum), 782 SND_SOC_BYTES("DAC MBC1 Comp Atk Time", R_DACMBCATK1L, 2), 783 SND_SOC_BYTES("DAC MBC1 Comp Rel Time Const", 784 R_DACMBCREL1L, 2), 785 786 SOC_SINGLE("MBC2 Phase Invert Switch", 787 R_DACMBCMUG2, FB_DACMBCMUG2_PHASE, 1, 0), 788 SOC_SINGLE_TLV("DAC MBC2 Make-Up Gain Volume", 789 R_DACMBCMUG2, FB_DACMBCMUG2_MUGAIN, 0x1f, 0, mugain_scale), 790 SOC_SINGLE_TLV("DAC MBC2 Comp Thresh Volume", 791 R_DACMBCTHR2, FB_DACMBCTHR2_THRESH, 0xff, 0, compth_scale), 792 SOC_ENUM("DAC MBC2 Comp Ratio", 793 dac_mbc2_compressor_ratio_enum), 794 SND_SOC_BYTES("DAC MBC2 Comp Atk Time", R_DACMBCATK2L, 2), 795 SND_SOC_BYTES("DAC MBC2 Comp Rel Time Const", 796 R_DACMBCREL2L, 2), 797 798 SOC_SINGLE("MBC3 Phase Invert Switch", 799 R_DACMBCMUG3, FB_DACMBCMUG3_PHASE, 1, 0), 800 SOC_SINGLE_TLV("DAC MBC3 Make-Up Gain Volume", 801 R_DACMBCMUG3, FB_DACMBCMUG3_MUGAIN, 0x1f, 0, mugain_scale), 802 SOC_SINGLE_TLV("DAC MBC3 Comp Thresh Volume", 803 R_DACMBCTHR3, FB_DACMBCTHR3_THRESH, 0xff, 0, compth_scale), 804 SOC_ENUM("DAC MBC3 Comp Ratio", 805 dac_mbc3_compressor_ratio_enum), 806 SND_SOC_BYTES("DAC MBC3 Comp Atk Time", R_DACMBCATK3L, 2), 807 SND_SOC_BYTES("DAC MBC3 Comp Rel Time Const", 808 R_DACMBCREL3L, 2), 809 }; 810 811 static int setup_sample_format(struct snd_soc_component *component, 812 snd_pcm_format_t format) 813 { 814 unsigned int width; 815 int ret; 816 817 switch (format) { 818 case SNDRV_PCM_FORMAT_S16_LE: 819 width = RV_AIC1_WL_16; 820 break; 821 case SNDRV_PCM_FORMAT_S20_3LE: 822 width = RV_AIC1_WL_20; 823 break; 824 case SNDRV_PCM_FORMAT_S24_LE: 825 width = RV_AIC1_WL_24; 826 break; 827 case SNDRV_PCM_FORMAT_S32_LE: 828 width = RV_AIC1_WL_32; 829 break; 830 default: 831 ret = -EINVAL; 832 dev_err(component->dev, "Unsupported format width (%d)\n", ret); 833 return ret; 834 } 835 ret = snd_soc_component_update_bits(component, 836 R_AIC1, RM_AIC1_WL, width); 837 if (ret < 0) { 838 dev_err(component->dev, 839 "Failed to set sample width (%d)\n", ret); 840 return ret; 841 } 842 843 return 0; 844 } 845 846 static int setup_sample_rate(struct snd_soc_component *component, 847 unsigned int rate) 848 { 849 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 850 unsigned int br, bm; 851 int ret; 852 853 switch (rate) { 854 case 8000: 855 br = RV_DACSR_DBR_32; 856 bm = RV_DACSR_DBM_PT25; 857 break; 858 case 16000: 859 br = RV_DACSR_DBR_32; 860 bm = RV_DACSR_DBM_PT5; 861 break; 862 case 24000: 863 br = RV_DACSR_DBR_48; 864 bm = RV_DACSR_DBM_PT5; 865 break; 866 case 32000: 867 br = RV_DACSR_DBR_32; 868 bm = RV_DACSR_DBM_1; 869 break; 870 case 48000: 871 br = RV_DACSR_DBR_48; 872 bm = RV_DACSR_DBM_1; 873 break; 874 case 96000: 875 br = RV_DACSR_DBR_48; 876 bm = RV_DACSR_DBM_2; 877 break; 878 case 11025: 879 br = RV_DACSR_DBR_44_1; 880 bm = RV_DACSR_DBM_PT25; 881 break; 882 case 22050: 883 br = RV_DACSR_DBR_44_1; 884 bm = RV_DACSR_DBM_PT5; 885 break; 886 case 44100: 887 br = RV_DACSR_DBR_44_1; 888 bm = RV_DACSR_DBM_1; 889 break; 890 case 88200: 891 br = RV_DACSR_DBR_44_1; 892 bm = RV_DACSR_DBM_2; 893 break; 894 default: 895 dev_err(component->dev, "Unsupported sample rate %d\n", rate); 896 return -EINVAL; 897 } 898 899 /* DAC and ADC share bit and frame clock */ 900 ret = snd_soc_component_update_bits(component, 901 R_DACSR, RM_DACSR_DBR, br); 902 if (ret < 0) { 903 dev_err(component->dev, 904 "Failed to update register (%d)\n", ret); 905 return ret; 906 } 907 ret = snd_soc_component_update_bits(component, 908 R_DACSR, RM_DACSR_DBM, bm); 909 if (ret < 0) { 910 dev_err(component->dev, 911 "Failed to update register (%d)\n", ret); 912 return ret; 913 } 914 ret = snd_soc_component_update_bits(component, 915 R_ADCSR, RM_DACSR_DBR, br); 916 if (ret < 0) { 917 dev_err(component->dev, 918 "Failed to update register (%d)\n", ret); 919 return ret; 920 } 921 ret = snd_soc_component_update_bits(component, 922 R_ADCSR, RM_DACSR_DBM, bm); 923 if (ret < 0) { 924 dev_err(component->dev, 925 "Failed to update register (%d)\n", ret); 926 return ret; 927 } 928 929 mutex_lock(&tscs42xx->audio_params_lock); 930 931 tscs42xx->samplerate = rate; 932 933 mutex_unlock(&tscs42xx->audio_params_lock); 934 935 return 0; 936 } 937 938 struct reg_setting { 939 unsigned int addr; 940 unsigned int val; 941 unsigned int mask; 942 }; 943 944 #define PLL_REG_SETTINGS_COUNT 13 945 struct pll_ctl { 946 int input_freq; 947 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; 948 }; 949 950 #define PLL_CTL(f, rt, rd, r1b_l, r9, ra, rb, \ 951 rc, r12, r1b_h, re, rf, r10, r11) \ 952 { \ 953 .input_freq = f, \ 954 .settings = { \ 955 {R_TIMEBASE, rt, 0xFF}, \ 956 {R_PLLCTLD, rd, 0xFF}, \ 957 {R_PLLCTL1B, r1b_l, 0x0F}, \ 958 {R_PLLCTL9, r9, 0xFF}, \ 959 {R_PLLCTLA, ra, 0xFF}, \ 960 {R_PLLCTLB, rb, 0xFF}, \ 961 {R_PLLCTLC, rc, 0xFF}, \ 962 {R_PLLCTL12, r12, 0xFF}, \ 963 {R_PLLCTL1B, r1b_h, 0xF0}, \ 964 {R_PLLCTLE, re, 0xFF}, \ 965 {R_PLLCTLF, rf, 0xFF}, \ 966 {R_PLLCTL10, r10, 0xFF}, \ 967 {R_PLLCTL11, r11, 0xFF}, \ 968 }, \ 969 } 970 971 static const struct pll_ctl pll_ctls[] = { 972 PLL_CTL(1411200, 0x05, 973 0x39, 0x04, 0x07, 0x02, 0xC3, 0x04, 974 0x1B, 0x10, 0x03, 0x03, 0xD0, 0x02), 975 PLL_CTL(1536000, 0x05, 976 0x1A, 0x04, 0x02, 0x03, 0xE0, 0x01, 977 0x1A, 0x10, 0x02, 0x03, 0xB9, 0x01), 978 PLL_CTL(2822400, 0x0A, 979 0x23, 0x04, 0x07, 0x04, 0xC3, 0x04, 980 0x22, 0x10, 0x05, 0x03, 0x58, 0x02), 981 PLL_CTL(3072000, 0x0B, 982 0x22, 0x04, 0x07, 0x03, 0x48, 0x03, 983 0x1A, 0x10, 0x04, 0x03, 0xB9, 0x01), 984 PLL_CTL(5644800, 0x15, 985 0x23, 0x04, 0x0E, 0x04, 0xC3, 0x04, 986 0x1A, 0x10, 0x08, 0x03, 0xE0, 0x01), 987 PLL_CTL(6144000, 0x17, 988 0x1A, 0x04, 0x08, 0x03, 0xE0, 0x01, 989 0x1A, 0x10, 0x08, 0x03, 0xB9, 0x01), 990 PLL_CTL(12000000, 0x2E, 991 0x1B, 0x04, 0x19, 0x03, 0x00, 0x03, 992 0x2A, 0x10, 0x19, 0x05, 0x98, 0x04), 993 PLL_CTL(19200000, 0x4A, 994 0x13, 0x04, 0x14, 0x03, 0x80, 0x01, 995 0x1A, 0x10, 0x19, 0x03, 0xB9, 0x01), 996 PLL_CTL(22000000, 0x55, 997 0x2A, 0x04, 0x37, 0x05, 0x00, 0x06, 998 0x22, 0x10, 0x26, 0x03, 0x49, 0x02), 999 PLL_CTL(22579200, 0x57, 1000 0x22, 0x04, 0x31, 0x03, 0x20, 0x03, 1001 0x1A, 0x10, 0x1D, 0x03, 0xB3, 0x01), 1002 PLL_CTL(24000000, 0x5D, 1003 0x13, 0x04, 0x19, 0x03, 0x80, 0x01, 1004 0x1B, 0x10, 0x19, 0x05, 0x4C, 0x02), 1005 PLL_CTL(24576000, 0x5F, 1006 0x13, 0x04, 0x1D, 0x03, 0xB3, 0x01, 1007 0x22, 0x10, 0x40, 0x03, 0x72, 0x03), 1008 PLL_CTL(27000000, 0x68, 1009 0x22, 0x04, 0x4B, 0x03, 0x00, 0x04, 1010 0x2A, 0x10, 0x7D, 0x03, 0x20, 0x06), 1011 PLL_CTL(36000000, 0x8C, 1012 0x1B, 0x04, 0x4B, 0x03, 0x00, 0x03, 1013 0x2A, 0x10, 0x7D, 0x03, 0x98, 0x04), 1014 PLL_CTL(25000000, 0x61, 1015 0x1B, 0x04, 0x37, 0x03, 0x2B, 0x03, 1016 0x1A, 0x10, 0x2A, 0x03, 0x39, 0x02), 1017 PLL_CTL(26000000, 0x65, 1018 0x23, 0x04, 0x41, 0x05, 0x00, 0x06, 1019 0x1A, 0x10, 0x26, 0x03, 0xEF, 0x01), 1020 PLL_CTL(12288000, 0x2F, 1021 0x1A, 0x04, 0x12, 0x03, 0x1C, 0x02, 1022 0x22, 0x10, 0x20, 0x03, 0x72, 0x03), 1023 PLL_CTL(40000000, 0x9B, 1024 0x22, 0x08, 0x7D, 0x03, 0x80, 0x04, 1025 0x23, 0x10, 0x7D, 0x05, 0xE4, 0x06), 1026 PLL_CTL(512000, 0x01, 1027 0x22, 0x04, 0x01, 0x03, 0xD0, 0x02, 1028 0x1B, 0x10, 0x01, 0x04, 0x72, 0x03), 1029 PLL_CTL(705600, 0x02, 1030 0x22, 0x04, 0x02, 0x03, 0x15, 0x04, 1031 0x22, 0x10, 0x01, 0x04, 0x80, 0x02), 1032 PLL_CTL(1024000, 0x03, 1033 0x22, 0x04, 0x02, 0x03, 0xD0, 0x02, 1034 0x1B, 0x10, 0x02, 0x04, 0x72, 0x03), 1035 PLL_CTL(2048000, 0x07, 1036 0x22, 0x04, 0x04, 0x03, 0xD0, 0x02, 1037 0x1B, 0x10, 0x04, 0x04, 0x72, 0x03), 1038 PLL_CTL(2400000, 0x08, 1039 0x22, 0x04, 0x05, 0x03, 0x00, 0x03, 1040 0x23, 0x10, 0x05, 0x05, 0x98, 0x04), 1041 }; 1042 1043 static const struct pll_ctl *get_pll_ctl(int input_freq) 1044 { 1045 int i; 1046 const struct pll_ctl *pll_ctl = NULL; 1047 1048 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i) 1049 if (input_freq == pll_ctls[i].input_freq) { 1050 pll_ctl = &pll_ctls[i]; 1051 break; 1052 } 1053 1054 return pll_ctl; 1055 } 1056 1057 static int set_pll_ctl_from_input_freq(struct snd_soc_component *component, 1058 const int input_freq) 1059 { 1060 int ret; 1061 int i; 1062 const struct pll_ctl *pll_ctl; 1063 1064 pll_ctl = get_pll_ctl(input_freq); 1065 if (!pll_ctl) { 1066 ret = -EINVAL; 1067 dev_err(component->dev, "No PLL input entry for %d (%d)\n", 1068 input_freq, ret); 1069 return ret; 1070 } 1071 1072 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) { 1073 ret = snd_soc_component_update_bits(component, 1074 pll_ctl->settings[i].addr, 1075 pll_ctl->settings[i].mask, 1076 pll_ctl->settings[i].val); 1077 if (ret < 0) { 1078 dev_err(component->dev, "Failed to set pll ctl (%d)\n", 1079 ret); 1080 return ret; 1081 } 1082 } 1083 1084 return 0; 1085 } 1086 1087 static int tscs42xx_hw_params(struct snd_pcm_substream *substream, 1088 struct snd_pcm_hw_params *params, 1089 struct snd_soc_dai *codec_dai) 1090 { 1091 struct snd_soc_component *component = codec_dai->component; 1092 int ret; 1093 1094 ret = setup_sample_format(component, params_format(params)); 1095 if (ret < 0) { 1096 dev_err(component->dev, "Failed to setup sample format (%d)\n", 1097 ret); 1098 return ret; 1099 } 1100 1101 ret = setup_sample_rate(component, params_rate(params)); 1102 if (ret < 0) { 1103 dev_err(component->dev, 1104 "Failed to setup sample rate (%d)\n", ret); 1105 return ret; 1106 } 1107 1108 return 0; 1109 } 1110 1111 static inline int dac_mute(struct snd_soc_component *component) 1112 { 1113 int ret; 1114 1115 ret = snd_soc_component_update_bits(component, 1116 R_CNVRTR1, RM_CNVRTR1_DACMU, 1117 RV_CNVRTR1_DACMU_ENABLE); 1118 if (ret < 0) { 1119 dev_err(component->dev, "Failed to mute DAC (%d)\n", 1120 ret); 1121 return ret; 1122 } 1123 1124 return 0; 1125 } 1126 1127 static inline int dac_unmute(struct snd_soc_component *component) 1128 { 1129 int ret; 1130 1131 ret = snd_soc_component_update_bits(component, 1132 R_CNVRTR1, RM_CNVRTR1_DACMU, 1133 RV_CNVRTR1_DACMU_DISABLE); 1134 if (ret < 0) { 1135 dev_err(component->dev, "Failed to unmute DAC (%d)\n", 1136 ret); 1137 return ret; 1138 } 1139 1140 return 0; 1141 } 1142 1143 static inline int adc_mute(struct snd_soc_component *component) 1144 { 1145 int ret; 1146 1147 ret = snd_soc_component_update_bits(component, 1148 R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_ENABLE); 1149 if (ret < 0) { 1150 dev_err(component->dev, "Failed to mute ADC (%d)\n", 1151 ret); 1152 return ret; 1153 } 1154 1155 return 0; 1156 } 1157 1158 static inline int adc_unmute(struct snd_soc_component *component) 1159 { 1160 int ret; 1161 1162 ret = snd_soc_component_update_bits(component, 1163 R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_DISABLE); 1164 if (ret < 0) { 1165 dev_err(component->dev, "Failed to unmute ADC (%d)\n", 1166 ret); 1167 return ret; 1168 } 1169 1170 return 0; 1171 } 1172 1173 static int tscs42xx_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1174 { 1175 struct snd_soc_component *component = dai->component; 1176 int ret; 1177 1178 if (mute) 1179 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1180 ret = dac_mute(component); 1181 else 1182 ret = adc_mute(component); 1183 else 1184 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1185 ret = dac_unmute(component); 1186 else 1187 ret = adc_unmute(component); 1188 1189 return ret; 1190 } 1191 1192 static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1193 unsigned int fmt) 1194 { 1195 struct snd_soc_component *component = codec_dai->component; 1196 int ret; 1197 1198 /* Consumer mode not supported since it needs always-on frame clock */ 1199 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1200 case SND_SOC_DAIFMT_CBP_CFP: 1201 ret = snd_soc_component_update_bits(component, 1202 R_AIC1, RM_AIC1_MS, RV_AIC1_MS_MASTER); 1203 if (ret < 0) { 1204 dev_err(component->dev, 1205 "Failed to set codec DAI master (%d)\n", ret); 1206 return ret; 1207 } 1208 break; 1209 default: 1210 ret = -EINVAL; 1211 dev_err(component->dev, "Unsupported format (%d)\n", ret); 1212 return ret; 1213 } 1214 1215 return 0; 1216 } 1217 1218 static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai, 1219 unsigned int ratio) 1220 { 1221 struct snd_soc_component *component = codec_dai->component; 1222 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 1223 unsigned int value; 1224 int ret = 0; 1225 1226 switch (ratio) { 1227 case 32: 1228 value = RV_DACSR_DBCM_32; 1229 break; 1230 case 40: 1231 value = RV_DACSR_DBCM_40; 1232 break; 1233 case 64: 1234 value = RV_DACSR_DBCM_64; 1235 break; 1236 default: 1237 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); 1238 return -EINVAL; 1239 } 1240 1241 ret = snd_soc_component_update_bits(component, 1242 R_DACSR, RM_DACSR_DBCM, value); 1243 if (ret < 0) { 1244 dev_err(component->dev, 1245 "Failed to set DAC BCLK ratio (%d)\n", ret); 1246 return ret; 1247 } 1248 ret = snd_soc_component_update_bits(component, 1249 R_ADCSR, RM_ADCSR_ABCM, value); 1250 if (ret < 0) { 1251 dev_err(component->dev, 1252 "Failed to set ADC BCLK ratio (%d)\n", ret); 1253 return ret; 1254 } 1255 1256 mutex_lock(&tscs42xx->audio_params_lock); 1257 1258 tscs42xx->bclk_ratio = ratio; 1259 1260 mutex_unlock(&tscs42xx->audio_params_lock); 1261 1262 return 0; 1263 } 1264 1265 static const struct snd_soc_dai_ops tscs42xx_dai_ops = { 1266 .hw_params = tscs42xx_hw_params, 1267 .mute_stream = tscs42xx_mute_stream, 1268 .set_fmt = tscs42xx_set_dai_fmt, 1269 .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio, 1270 }; 1271 1272 static int part_is_valid(struct tscs42xx *tscs42xx) 1273 { 1274 int val; 1275 int ret; 1276 unsigned int reg; 1277 1278 ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®); 1279 if (ret < 0) 1280 return ret; 1281 1282 val = reg << 8; 1283 ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®); 1284 if (ret < 0) 1285 return ret; 1286 1287 val |= reg; 1288 1289 switch (val) { 1290 case 0x4A74: 1291 case 0x4A73: 1292 return true; 1293 default: 1294 return false; 1295 } 1296 } 1297 1298 static int set_sysclk(struct snd_soc_component *component) 1299 { 1300 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 1301 unsigned long freq; 1302 int ret; 1303 1304 switch (tscs42xx->sysclk_src_id) { 1305 case TSCS42XX_PLL_SRC_XTAL: 1306 case TSCS42XX_PLL_SRC_MCLK1: 1307 ret = snd_soc_component_write(component, R_PLLREFSEL, 1308 RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 | 1309 RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1); 1310 if (ret < 0) { 1311 dev_err(component->dev, 1312 "Failed to set pll reference input (%d)\n", 1313 ret); 1314 return ret; 1315 } 1316 break; 1317 case TSCS42XX_PLL_SRC_MCLK2: 1318 ret = snd_soc_component_write(component, R_PLLREFSEL, 1319 RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 | 1320 RV_PLLREFSEL_PLL2_REF_SEL_MCLK2); 1321 if (ret < 0) { 1322 dev_err(component->dev, 1323 "Failed to set PLL reference (%d)\n", ret); 1324 return ret; 1325 } 1326 break; 1327 default: 1328 dev_err(component->dev, "pll src is unsupported\n"); 1329 return -EINVAL; 1330 } 1331 1332 freq = clk_get_rate(tscs42xx->sysclk); 1333 ret = set_pll_ctl_from_input_freq(component, freq); 1334 if (ret < 0) { 1335 dev_err(component->dev, 1336 "Failed to setup PLL input freq (%d)\n", ret); 1337 return ret; 1338 } 1339 1340 return 0; 1341 } 1342 1343 static int tscs42xx_probe(struct snd_soc_component *component) 1344 { 1345 return set_sysclk(component); 1346 } 1347 1348 static const struct snd_soc_component_driver soc_codec_dev_tscs42xx = { 1349 .probe = tscs42xx_probe, 1350 .dapm_widgets = tscs42xx_dapm_widgets, 1351 .num_dapm_widgets = ARRAY_SIZE(tscs42xx_dapm_widgets), 1352 .dapm_routes = tscs42xx_intercon, 1353 .num_dapm_routes = ARRAY_SIZE(tscs42xx_intercon), 1354 .controls = tscs42xx_snd_controls, 1355 .num_controls = ARRAY_SIZE(tscs42xx_snd_controls), 1356 .idle_bias_on = 1, 1357 .use_pmdown_time = 1, 1358 .endianness = 1, 1359 }; 1360 1361 static inline void init_coeff_ram_cache(struct tscs42xx *tscs42xx) 1362 { 1363 static const u8 norm_addrs[] = { 1364 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1f, 0x20, 0x25, 0x2a, 1365 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59, 1366 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7f, 0x80, 0x85, 1367 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 0xa8, 0xad, 0xaf, 0xb0, 1368 0xb5, 0xba, 0xbf, 0xc4, 0xc9, 1369 }; 1370 u8 *coeff_ram = tscs42xx->coeff_ram; 1371 int i; 1372 1373 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++) 1374 coeff_ram[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; 1375 } 1376 1377 #define TSCS42XX_RATES SNDRV_PCM_RATE_8000_96000 1378 1379 #define TSCS42XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1380 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1381 1382 static struct snd_soc_dai_driver tscs42xx_dai = { 1383 .name = "tscs42xx-HiFi", 1384 .playback = { 1385 .stream_name = "HiFi Playback", 1386 .channels_min = 2, 1387 .channels_max = 2, 1388 .rates = TSCS42XX_RATES, 1389 .formats = TSCS42XX_FORMATS,}, 1390 .capture = { 1391 .stream_name = "HiFi Capture", 1392 .channels_min = 2, 1393 .channels_max = 2, 1394 .rates = TSCS42XX_RATES, 1395 .formats = TSCS42XX_FORMATS,}, 1396 .ops = &tscs42xx_dai_ops, 1397 .symmetric_rate = 1, 1398 .symmetric_channels = 1, 1399 .symmetric_sample_bits = 1, 1400 }; 1401 1402 static const struct reg_sequence tscs42xx_patch[] = { 1403 { R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED }, 1404 }; 1405 1406 static char const * const src_names[TSCS42XX_PLL_SRC_CNT] = { 1407 "xtal", "mclk1", "mclk2"}; 1408 1409 static int tscs42xx_i2c_probe(struct i2c_client *i2c) 1410 { 1411 struct tscs42xx *tscs42xx; 1412 int src; 1413 int ret; 1414 1415 tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL); 1416 if (!tscs42xx) { 1417 ret = -ENOMEM; 1418 dev_err(&i2c->dev, 1419 "Failed to allocate memory for data (%d)\n", ret); 1420 return ret; 1421 } 1422 i2c_set_clientdata(i2c, tscs42xx); 1423 1424 for (src = TSCS42XX_PLL_SRC_XTAL; src < TSCS42XX_PLL_SRC_CNT; src++) { 1425 tscs42xx->sysclk = devm_clk_get(&i2c->dev, src_names[src]); 1426 if (!IS_ERR(tscs42xx->sysclk)) { 1427 break; 1428 } else if (PTR_ERR(tscs42xx->sysclk) != -ENOENT) { 1429 ret = PTR_ERR(tscs42xx->sysclk); 1430 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); 1431 return ret; 1432 } 1433 } 1434 if (src == TSCS42XX_PLL_SRC_CNT) { 1435 ret = -EINVAL; 1436 dev_err(&i2c->dev, "Failed to get a valid clock name (%d)\n", 1437 ret); 1438 return ret; 1439 } 1440 tscs42xx->sysclk_src_id = src; 1441 1442 tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap); 1443 if (IS_ERR(tscs42xx->regmap)) { 1444 ret = PTR_ERR(tscs42xx->regmap); 1445 dev_err(&i2c->dev, "Failed to allocate regmap (%d)\n", ret); 1446 return ret; 1447 } 1448 1449 init_coeff_ram_cache(tscs42xx); 1450 1451 ret = part_is_valid(tscs42xx); 1452 if (ret <= 0) { 1453 dev_err(&i2c->dev, "No valid part (%d)\n", ret); 1454 ret = -ENODEV; 1455 return ret; 1456 } 1457 1458 ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE); 1459 if (ret < 0) { 1460 dev_err(&i2c->dev, "Failed to reset device (%d)\n", ret); 1461 return ret; 1462 } 1463 1464 ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch, 1465 ARRAY_SIZE(tscs42xx_patch)); 1466 if (ret < 0) { 1467 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); 1468 return ret; 1469 } 1470 1471 mutex_init(&tscs42xx->audio_params_lock); 1472 mutex_init(&tscs42xx->coeff_ram_lock); 1473 mutex_init(&tscs42xx->pll_lock); 1474 1475 ret = devm_snd_soc_register_component(&i2c->dev, 1476 &soc_codec_dev_tscs42xx, &tscs42xx_dai, 1); 1477 if (ret) { 1478 dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret); 1479 return ret; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static const struct i2c_device_id tscs42xx_i2c_id[] = { 1486 { "tscs42A1" }, 1487 { "tscs42A2" }, 1488 { } 1489 }; 1490 MODULE_DEVICE_TABLE(i2c, tscs42xx_i2c_id); 1491 1492 static const struct of_device_id tscs42xx_of_match[] = { 1493 { .compatible = "tempo,tscs42A1", }, 1494 { .compatible = "tempo,tscs42A2", }, 1495 { } 1496 }; 1497 MODULE_DEVICE_TABLE(of, tscs42xx_of_match); 1498 1499 static struct i2c_driver tscs42xx_i2c_driver = { 1500 .driver = { 1501 .name = "tscs42xx", 1502 .of_match_table = tscs42xx_of_match, 1503 }, 1504 .probe = tscs42xx_i2c_probe, 1505 .id_table = tscs42xx_i2c_id, 1506 }; 1507 1508 module_i2c_driver(tscs42xx_i2c_driver); 1509 1510 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com"); 1511 MODULE_DESCRIPTION("ASoC TSCS42xx driver"); 1512 MODULE_LICENSE("GPL"); 1513