1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 8 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 9 #define __QCOM_CLK_ALPHA_PLL_H__ 10 11 #include <linux/clk-provider.h> 12 #include "clk-regmap.h" 13 14 /* Alpha PLL types */ 15 enum { 16 CLK_ALPHA_PLL_TYPE_DEFAULT, 17 CLK_ALPHA_PLL_TYPE_HUAYRA, 18 CLK_ALPHA_PLL_TYPE_HUAYRA_APSS, 19 CLK_ALPHA_PLL_TYPE_HUAYRA_2290, 20 CLK_ALPHA_PLL_TYPE_BRAMMO, 21 CLK_ALPHA_PLL_TYPE_FABIA, 22 CLK_ALPHA_PLL_TYPE_TRION, 23 CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, 24 CLK_ALPHA_PLL_TYPE_AGERA, 25 CLK_ALPHA_PLL_TYPE_ZONDA, 26 CLK_ALPHA_PLL_TYPE_REGERA = CLK_ALPHA_PLL_TYPE_ZONDA, 27 CLK_ALPHA_PLL_TYPE_ZONDA_OLE, 28 CLK_ALPHA_PLL_TYPE_LUCID_EVO, 29 CLK_ALPHA_PLL_TYPE_LUCID_OLE, 30 CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, 31 CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, 32 CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, 33 CLK_ALPHA_PLL_TYPE_STROMER, 34 CLK_ALPHA_PLL_TYPE_STROMER_PLUS, 35 CLK_ALPHA_PLL_TYPE_NSS_HUAYRA, 36 CLK_ALPHA_PLL_TYPE_MAX, 37 }; 38 39 enum { 40 PLL_OFF_L_VAL, 41 PLL_OFF_CAL_L_VAL, 42 PLL_OFF_ALPHA_VAL, 43 PLL_OFF_ALPHA_VAL_U, 44 PLL_OFF_USER_CTL, 45 PLL_OFF_USER_CTL_U, 46 PLL_OFF_USER_CTL_U1, 47 PLL_OFF_CONFIG_CTL, 48 PLL_OFF_CONFIG_CTL_U, 49 PLL_OFF_CONFIG_CTL_U1, 50 PLL_OFF_CONFIG_CTL_U2, 51 PLL_OFF_TEST_CTL, 52 PLL_OFF_TEST_CTL_U, 53 PLL_OFF_TEST_CTL_U1, 54 PLL_OFF_TEST_CTL_U2, 55 PLL_OFF_STATE, 56 PLL_OFF_STATUS, 57 PLL_OFF_OPMODE, 58 PLL_OFF_FRAC, 59 PLL_OFF_CAL_VAL, 60 PLL_OFF_MAX_REGS 61 }; 62 63 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 64 65 struct pll_vco { 66 unsigned long min_freq; 67 unsigned long max_freq; 68 u32 val; 69 }; 70 71 #define VCO(a, b, c) { \ 72 .val = a,\ 73 .min_freq = b,\ 74 .max_freq = c,\ 75 } 76 77 /** 78 * struct clk_alpha_pll - phase locked loop (PLL) 79 * @offset: base address of registers 80 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 81 * @vco_table: array of VCO settings 82 * @num_vco: number of VCO settings in @vco_table 83 * @flags: bitmask to indicate features supported by the hardware 84 * @clkr: regmap clock handle 85 */ 86 struct clk_alpha_pll { 87 u32 offset; 88 const u8 *regs; 89 90 const struct pll_vco *vco_table; 91 size_t num_vco; 92 #define SUPPORTS_OFFLINE_REQ BIT(0) 93 #define SUPPORTS_FSM_MODE BIT(2) 94 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 95 #define SUPPORTS_FSM_LEGACY_MODE BIT(4) 96 u8 flags; 97 98 struct clk_regmap clkr; 99 }; 100 101 /** 102 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 103 * @offset: base address of registers 104 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 105 * @width: width of post-divider 106 * @post_div_shift: shift to differentiate between odd & even post-divider 107 * @post_div_table: table with PLL odd and even post-divider settings 108 * @num_post_div: Number of PLL post-divider settings 109 * 110 * @clkr: regmap clock handle 111 */ 112 struct clk_alpha_pll_postdiv { 113 u32 offset; 114 u8 width; 115 const u8 *regs; 116 117 struct clk_regmap clkr; 118 int post_div_shift; 119 const struct clk_div_table *post_div_table; 120 size_t num_post_div; 121 }; 122 123 struct alpha_pll_config { 124 u32 l; 125 u32 alpha; 126 u32 alpha_hi; 127 u32 config_ctl_val; 128 u32 config_ctl_hi_val; 129 u32 config_ctl_hi1_val; 130 u32 config_ctl_hi2_val; 131 u32 user_ctl_val; 132 u32 user_ctl_hi_val; 133 u32 user_ctl_hi1_val; 134 u32 test_ctl_val; 135 u32 test_ctl_mask; 136 u32 test_ctl_hi_val; 137 u32 test_ctl_hi_mask; 138 u32 test_ctl_hi1_val; 139 u32 test_ctl_hi2_val; 140 u32 main_output_mask; 141 u32 aux_output_mask; 142 u32 aux2_output_mask; 143 u32 early_output_mask; 144 u32 alpha_en_mask; 145 u32 alpha_mode_mask; 146 u32 pre_div_val; 147 u32 pre_div_mask; 148 u32 post_div_val; 149 u32 post_div_mask; 150 u32 vco_val; 151 u32 vco_mask; 152 u32 status_val; 153 u32 status_mask; 154 u32 lock_det; 155 }; 156 157 extern const struct clk_ops clk_alpha_pll_ops; 158 extern const struct clk_ops clk_alpha_pll_fixed_ops; 159 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 160 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 161 extern const struct clk_ops clk_alpha_pll_huayra_ops; 162 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 163 extern const struct clk_ops clk_alpha_pll_stromer_ops; 164 extern const struct clk_ops clk_alpha_pll_stromer_plus_ops; 165 166 extern const struct clk_ops clk_alpha_pll_fabia_ops; 167 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 168 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 169 170 extern const struct clk_ops clk_alpha_pll_trion_ops; 171 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops; 172 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops; 173 174 extern const struct clk_ops clk_alpha_pll_lucid_ops; 175 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops 176 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 177 extern const struct clk_ops clk_alpha_pll_agera_ops; 178 179 extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops; 180 extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops; 181 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops; 182 183 extern const struct clk_ops clk_alpha_pll_zonda_ops; 184 #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops 185 #define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops 186 187 extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; 188 extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; 189 #define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops 190 extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; 191 #define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops 192 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops; 193 #define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops 194 195 extern const struct clk_ops clk_alpha_pll_rivian_evo_ops; 196 #define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops 197 198 extern const struct clk_ops clk_alpha_pll_regera_ops; 199 200 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 201 const struct alpha_pll_config *config); 202 void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 203 const struct alpha_pll_config *config); 204 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 205 const struct alpha_pll_config *config); 206 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 207 const struct alpha_pll_config *config); 208 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 209 const struct alpha_pll_config *config); 210 #define clk_lucid_pll_configure(pll, regmap, config) \ 211 clk_trion_pll_configure(pll, regmap, config) 212 213 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 214 const struct alpha_pll_config *config); 215 void clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 216 const struct alpha_pll_config *config); 217 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 218 const struct alpha_pll_config *config); 219 void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 220 const struct alpha_pll_config *config); 221 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 222 const struct alpha_pll_config *config); 223 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 224 const struct alpha_pll_config *config); 225 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 226 const struct alpha_pll_config *config); 227 228 #endif 229