1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe SERDES driver for AM654x SoC
4 *
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <dt-bindings/phy/phy.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/mux/consumer.h>
17 #include <linux/of_address.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22
23 #define CMU_R004 0x4
24 #define CMU_R060 0x60
25 #define CMU_R07C 0x7c
26 #define CMU_R088 0x88
27 #define CMU_R0D0 0xd0
28 #define CMU_R0E8 0xe8
29
30 #define LANE_R048 0x248
31 #define LANE_R058 0x258
32 #define LANE_R06c 0x26c
33 #define LANE_R070 0x270
34 #define LANE_R19C 0x39c
35
36 #define COMLANE_R004 0xa04
37 #define COMLANE_R138 0xb38
38 #define VERSION_VAL 0x70
39
40 #define COMLANE_R190 0xb90
41 #define COMLANE_R194 0xb94
42
43 #define COMRXEQ_R004 0x1404
44 #define COMRXEQ_R008 0x1408
45 #define COMRXEQ_R00C 0x140c
46 #define COMRXEQ_R014 0x1414
47 #define COMRXEQ_R018 0x1418
48 #define COMRXEQ_R01C 0x141c
49 #define COMRXEQ_R04C 0x144c
50 #define COMRXEQ_R088 0x1488
51 #define COMRXEQ_R094 0x1494
52 #define COMRXEQ_R098 0x1498
53
54 #define SERDES_CTRL 0x1fd0
55
56 #define WIZ_LANEXCTL_STS 0x1fe0
57 #define TX0_DISABLE_STATE 0x4
58 #define TX0_SLEEP_STATE 0x5
59 #define TX0_SNOOZE_STATE 0x6
60 #define TX0_ENABLE_STATE 0x7
61
62 #define RX0_DISABLE_STATE 0x4
63 #define RX0_SLEEP_STATE 0x5
64 #define RX0_SNOOZE_STATE 0x6
65 #define RX0_ENABLE_STATE 0x7
66
67 #define WIZ_PLL_CTRL 0x1ff4
68 #define PLL_DISABLE_STATE 0x4
69 #define PLL_SLEEP_STATE 0x5
70 #define PLL_SNOOZE_STATE 0x6
71 #define PLL_ENABLE_STATE 0x7
72
73 #define PLL_LOCK_TIME 100000 /* in microseconds */
74 #define SLEEP_TIME 100 /* in microseconds */
75
76 #define LANE_USB3 0x0
77 #define LANE_PCIE0_LANE0 0x1
78
79 #define LANE_PCIE1_LANE0 0x0
80 #define LANE_PCIE0_LANE1 0x1
81
82 #define SERDES_NUM_CLOCKS 3
83
84 #define AM654_SERDES_CTRL_CLKSEL_MASK GENMASK(7, 4)
85 #define AM654_SERDES_CTRL_CLKSEL_SHIFT 4
86
87 struct serdes_am654_clk_mux {
88 struct clk_hw hw;
89 struct regmap *regmap;
90 unsigned int reg;
91 int clk_id;
92 struct clk_init_data clk_data;
93 };
94
95 #define to_serdes_am654_clk_mux(_hw) \
96 container_of(_hw, struct serdes_am654_clk_mux, hw)
97
98 static const struct regmap_config serdes_am654_regmap_config = {
99 .reg_bits = 32,
100 .val_bits = 32,
101 .reg_stride = 4,
102 .max_register = 0x1ffc,
103 };
104
105 enum serdes_am654_fields {
106 /* CMU PLL Control */
107 CMU_PLL_CTRL,
108
109 LANE_PLL_CTRL_RXEQ_RXIDLE,
110
111 /* CMU VCO bias current and VREG setting */
112 AHB_PMA_CM_VCO_VBIAS_VREG,
113 AHB_PMA_CM_VCO_BIAS_VREG,
114
115 AHB_PMA_CM_SR,
116 AHB_SSC_GEN_Z_O_20_13,
117
118 /* AHB PMA Lane Configuration */
119 AHB_PMA_LN_AGC_THSEL_VREGH,
120
121 /* AGC and Signal detect threshold for Gen3 */
122 AHB_PMA_LN_GEN3_AGC_SD_THSEL,
123
124 AHB_PMA_LN_RX_SELR_GEN3,
125 AHB_PMA_LN_TX_DRV,
126
127 /* CMU Master Reset */
128 CMU_MASTER_CDN,
129
130 /* P2S ring buffer initial startup pointer difference */
131 P2S_RBUF_PTR_DIFF,
132
133 CONFIG_VERSION,
134
135 /* Lane 1 Master Reset */
136 L1_MASTER_CDN,
137
138 /* CMU OK Status */
139 CMU_OK_I_0,
140
141 /* Mid-speed initial calibration control */
142 COMRXEQ_MS_INIT_CTRL_7_0,
143
144 /* High-speed initial calibration control */
145 COMRXEQ_HS_INIT_CAL_7_0,
146
147 /* Mid-speed recalibration control */
148 COMRXEQ_MS_RECAL_CTRL_7_0,
149
150 /* High-speed recalibration control */
151 COMRXEQ_HS_RECAL_CTRL_7_0,
152
153 /* ATT configuration */
154 COMRXEQ_CSR_ATT_CONFIG,
155
156 /* Edge based boost adaptation window length */
157 COMRXEQ_CSR_EBSTADAPT_WIN_LEN,
158
159 /* COMRXEQ control 3 & 4 */
160 COMRXEQ_CTRL_3_4,
161
162 /* COMRXEQ control 14, 15 and 16*/
163 COMRXEQ_CTRL_14_15_16,
164
165 /* Threshold for errors in pattern data */
166 COMRXEQ_CSR_DLEV_ERR_THRESH,
167
168 /* COMRXEQ control 25 */
169 COMRXEQ_CTRL_25,
170
171 /* Mid-speed rate change calibration control */
172 CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O,
173
174 /* High-speed rate change calibration control */
175 COMRXEQ_HS_RCHANGE_CTRL_7_0,
176
177 /* Serdes reset */
178 POR_EN,
179
180 /* Tx Enable Value */
181 TX0_ENABLE,
182
183 /* Rx Enable Value */
184 RX0_ENABLE,
185
186 /* PLL Enable Value */
187 PLL_ENABLE,
188
189 /* PLL ready for use */
190 PLL_OK,
191
192 /* sentinel */
193 MAX_FIELDS
194
195 };
196
197 static const struct reg_field serdes_am654_reg_fields[] = {
198 [CMU_PLL_CTRL] = REG_FIELD(CMU_R004, 8, 15),
199 [AHB_PMA_CM_VCO_VBIAS_VREG] = REG_FIELD(CMU_R060, 8, 15),
200 [CMU_MASTER_CDN] = REG_FIELD(CMU_R07C, 24, 31),
201 [AHB_PMA_CM_VCO_BIAS_VREG] = REG_FIELD(CMU_R088, 24, 31),
202 [AHB_PMA_CM_SR] = REG_FIELD(CMU_R0D0, 24, 31),
203 [AHB_SSC_GEN_Z_O_20_13] = REG_FIELD(CMU_R0E8, 8, 15),
204 [LANE_PLL_CTRL_RXEQ_RXIDLE] = REG_FIELD(LANE_R048, 8, 15),
205 [AHB_PMA_LN_AGC_THSEL_VREGH] = REG_FIELD(LANE_R058, 16, 23),
206 [AHB_PMA_LN_GEN3_AGC_SD_THSEL] = REG_FIELD(LANE_R06c, 0, 7),
207 [AHB_PMA_LN_RX_SELR_GEN3] = REG_FIELD(LANE_R070, 16, 23),
208 [AHB_PMA_LN_TX_DRV] = REG_FIELD(LANE_R19C, 16, 23),
209 [P2S_RBUF_PTR_DIFF] = REG_FIELD(COMLANE_R004, 0, 7),
210 [CONFIG_VERSION] = REG_FIELD(COMLANE_R138, 16, 23),
211 [L1_MASTER_CDN] = REG_FIELD(COMLANE_R190, 8, 15),
212 [CMU_OK_I_0] = REG_FIELD(COMLANE_R194, 19, 19),
213 [COMRXEQ_MS_INIT_CTRL_7_0] = REG_FIELD(COMRXEQ_R004, 24, 31),
214 [COMRXEQ_HS_INIT_CAL_7_0] = REG_FIELD(COMRXEQ_R008, 0, 7),
215 [COMRXEQ_MS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 8, 15),
216 [COMRXEQ_HS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 16, 23),
217 [COMRXEQ_CSR_ATT_CONFIG] = REG_FIELD(COMRXEQ_R014, 16, 23),
218 [COMRXEQ_CSR_EBSTADAPT_WIN_LEN] = REG_FIELD(COMRXEQ_R018, 16, 23),
219 [COMRXEQ_CTRL_3_4] = REG_FIELD(COMRXEQ_R01C, 8, 15),
220 [COMRXEQ_CTRL_14_15_16] = REG_FIELD(COMRXEQ_R04C, 0, 7),
221 [COMRXEQ_CSR_DLEV_ERR_THRESH] = REG_FIELD(COMRXEQ_R088, 16, 23),
222 [COMRXEQ_CTRL_25] = REG_FIELD(COMRXEQ_R094, 24, 31),
223 [CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O] = REG_FIELD(COMRXEQ_R098, 8, 15),
224 [COMRXEQ_HS_RCHANGE_CTRL_7_0] = REG_FIELD(COMRXEQ_R098, 16, 23),
225 [POR_EN] = REG_FIELD(SERDES_CTRL, 29, 29),
226 [TX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31),
227 [RX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15),
228 [PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
229 [PLL_OK] = REG_FIELD(WIZ_PLL_CTRL, 28, 28),
230 };
231
232 struct serdes_am654 {
233 struct regmap *regmap;
234 struct regmap_field *fields[MAX_FIELDS];
235
236 struct device *dev;
237 struct mux_control *control;
238 bool busy;
239 u32 type;
240 struct device_node *of_node;
241 struct clk_onecell_data clk_data;
242 struct clk *clks[SERDES_NUM_CLOCKS];
243 };
244
serdes_am654_enable_pll(struct serdes_am654 * phy)245 static int serdes_am654_enable_pll(struct serdes_am654 *phy)
246 {
247 int ret;
248 u32 val;
249
250 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE);
251 if (ret)
252 return ret;
253
254 return regmap_field_read_poll_timeout(phy->fields[PLL_OK], val, val,
255 1000, PLL_LOCK_TIME);
256 }
257
serdes_am654_disable_pll(struct serdes_am654 * phy)258 static void serdes_am654_disable_pll(struct serdes_am654 *phy)
259 {
260 struct device *dev = phy->dev;
261 int ret;
262
263 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE);
264 if (ret)
265 dev_err(dev, "Failed to disable PLL\n");
266 }
267
serdes_am654_enable_txrx(struct serdes_am654 * phy)268 static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
269 {
270 int ret = 0;
271
272 /* Enable TX */
273 ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_ENABLE_STATE);
274
275 /* Enable RX */
276 ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_ENABLE_STATE);
277
278 if (ret)
279 return -EIO;
280
281 return 0;
282 }
283
serdes_am654_disable_txrx(struct serdes_am654 * phy)284 static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
285 {
286 int ret = 0;
287
288 /* Disable TX */
289 ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_DISABLE_STATE);
290
291 /* Disable RX */
292 ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_DISABLE_STATE);
293
294 if (ret)
295 return -EIO;
296
297 return 0;
298 }
299
serdes_am654_power_on(struct phy * x)300 static int serdes_am654_power_on(struct phy *x)
301 {
302 struct serdes_am654 *phy = phy_get_drvdata(x);
303 struct device *dev = phy->dev;
304 int ret;
305 u32 val;
306
307 ret = serdes_am654_enable_pll(phy);
308 if (ret) {
309 dev_err(dev, "Failed to enable PLL\n");
310 return ret;
311 }
312
313 ret = serdes_am654_enable_txrx(phy);
314 if (ret) {
315 dev_err(dev, "Failed to enable TX RX\n");
316 return ret;
317 }
318
319 return regmap_field_read_poll_timeout(phy->fields[CMU_OK_I_0], val,
320 val, SLEEP_TIME, PLL_LOCK_TIME);
321 }
322
serdes_am654_power_off(struct phy * x)323 static int serdes_am654_power_off(struct phy *x)
324 {
325 struct serdes_am654 *phy = phy_get_drvdata(x);
326
327 serdes_am654_disable_txrx(phy);
328 serdes_am654_disable_pll(phy);
329
330 return 0;
331 }
332
333 #define SERDES_AM654_CFG(offset, a, b, val) \
334 regmap_update_bits(phy->regmap, (offset),\
335 GENMASK((a), (b)), (val) << (b))
336
serdes_am654_usb3_init(struct serdes_am654 * phy)337 static int serdes_am654_usb3_init(struct serdes_am654 *phy)
338 {
339 SERDES_AM654_CFG(0x0000, 31, 24, 0x17);
340 SERDES_AM654_CFG(0x0004, 15, 8, 0x02);
341 SERDES_AM654_CFG(0x0004, 7, 0, 0x0e);
342 SERDES_AM654_CFG(0x0008, 23, 16, 0x2e);
343 SERDES_AM654_CFG(0x0008, 31, 24, 0x2e);
344 SERDES_AM654_CFG(0x0060, 7, 0, 0x4b);
345 SERDES_AM654_CFG(0x0060, 15, 8, 0x98);
346 SERDES_AM654_CFG(0x0060, 23, 16, 0x60);
347 SERDES_AM654_CFG(0x00d0, 31, 24, 0x45);
348 SERDES_AM654_CFG(0x00e8, 15, 8, 0x0e);
349 SERDES_AM654_CFG(0x0220, 7, 0, 0x34);
350 SERDES_AM654_CFG(0x0220, 15, 8, 0x34);
351 SERDES_AM654_CFG(0x0220, 31, 24, 0x37);
352 SERDES_AM654_CFG(0x0224, 7, 0, 0x37);
353 SERDES_AM654_CFG(0x0224, 15, 8, 0x37);
354 SERDES_AM654_CFG(0x0228, 23, 16, 0x37);
355 SERDES_AM654_CFG(0x0228, 31, 24, 0x37);
356 SERDES_AM654_CFG(0x022c, 7, 0, 0x37);
357 SERDES_AM654_CFG(0x022c, 15, 8, 0x37);
358 SERDES_AM654_CFG(0x0230, 15, 8, 0x2a);
359 SERDES_AM654_CFG(0x0230, 23, 16, 0x2a);
360 SERDES_AM654_CFG(0x0240, 23, 16, 0x10);
361 SERDES_AM654_CFG(0x0240, 31, 24, 0x34);
362 SERDES_AM654_CFG(0x0244, 7, 0, 0x40);
363 SERDES_AM654_CFG(0x0244, 23, 16, 0x34);
364 SERDES_AM654_CFG(0x0248, 15, 8, 0x0d);
365 SERDES_AM654_CFG(0x0258, 15, 8, 0x16);
366 SERDES_AM654_CFG(0x0258, 23, 16, 0x84);
367 SERDES_AM654_CFG(0x0258, 31, 24, 0xf2);
368 SERDES_AM654_CFG(0x025c, 7, 0, 0x21);
369 SERDES_AM654_CFG(0x0260, 7, 0, 0x27);
370 SERDES_AM654_CFG(0x0260, 15, 8, 0x04);
371 SERDES_AM654_CFG(0x0268, 15, 8, 0x04);
372 SERDES_AM654_CFG(0x0288, 15, 8, 0x2c);
373 SERDES_AM654_CFG(0x0330, 31, 24, 0xa0);
374 SERDES_AM654_CFG(0x0338, 23, 16, 0x03);
375 SERDES_AM654_CFG(0x0338, 31, 24, 0x00);
376 SERDES_AM654_CFG(0x033c, 7, 0, 0x00);
377 SERDES_AM654_CFG(0x0344, 31, 24, 0x18);
378 SERDES_AM654_CFG(0x034c, 7, 0, 0x18);
379 SERDES_AM654_CFG(0x039c, 23, 16, 0x3b);
380 SERDES_AM654_CFG(0x0a04, 7, 0, 0x03);
381 SERDES_AM654_CFG(0x0a14, 31, 24, 0x3c);
382 SERDES_AM654_CFG(0x0a18, 15, 8, 0x3c);
383 SERDES_AM654_CFG(0x0a38, 7, 0, 0x3e);
384 SERDES_AM654_CFG(0x0a38, 15, 8, 0x3e);
385 SERDES_AM654_CFG(0x0ae0, 7, 0, 0x07);
386 SERDES_AM654_CFG(0x0b6c, 23, 16, 0xcd);
387 SERDES_AM654_CFG(0x0b6c, 31, 24, 0x04);
388 SERDES_AM654_CFG(0x0b98, 23, 16, 0x03);
389 SERDES_AM654_CFG(0x1400, 7, 0, 0x3f);
390 SERDES_AM654_CFG(0x1404, 23, 16, 0x6f);
391 SERDES_AM654_CFG(0x1404, 31, 24, 0x6f);
392 SERDES_AM654_CFG(0x140c, 7, 0, 0x6f);
393 SERDES_AM654_CFG(0x140c, 15, 8, 0x6f);
394 SERDES_AM654_CFG(0x1410, 15, 8, 0x27);
395 SERDES_AM654_CFG(0x1414, 7, 0, 0x0c);
396 SERDES_AM654_CFG(0x1414, 23, 16, 0x07);
397 SERDES_AM654_CFG(0x1418, 23, 16, 0x40);
398 SERDES_AM654_CFG(0x141c, 7, 0, 0x00);
399 SERDES_AM654_CFG(0x141c, 15, 8, 0x1f);
400 SERDES_AM654_CFG(0x1428, 31, 24, 0x08);
401 SERDES_AM654_CFG(0x1434, 31, 24, 0x00);
402 SERDES_AM654_CFG(0x1444, 7, 0, 0x94);
403 SERDES_AM654_CFG(0x1460, 31, 24, 0x7f);
404 SERDES_AM654_CFG(0x1464, 7, 0, 0x43);
405 SERDES_AM654_CFG(0x1464, 23, 16, 0x6f);
406 SERDES_AM654_CFG(0x1464, 31, 24, 0x43);
407 SERDES_AM654_CFG(0x1484, 23, 16, 0x8f);
408 SERDES_AM654_CFG(0x1498, 7, 0, 0x4f);
409 SERDES_AM654_CFG(0x1498, 23, 16, 0x4f);
410 SERDES_AM654_CFG(0x007c, 31, 24, 0x0d);
411 SERDES_AM654_CFG(0x0b90, 15, 8, 0x0f);
412
413 return 0;
414 }
415
serdes_am654_pcie_init(struct serdes_am654 * phy)416 static int serdes_am654_pcie_init(struct serdes_am654 *phy)
417 {
418 int ret = 0;
419
420 ret |= regmap_field_write(phy->fields[CMU_PLL_CTRL], 0x2);
421 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_VBIAS_VREG], 0x98);
422 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_BIAS_VREG], 0x98);
423 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_SR], 0x45);
424 ret |= regmap_field_write(phy->fields[AHB_SSC_GEN_Z_O_20_13], 0xe);
425 ret |= regmap_field_write(phy->fields[LANE_PLL_CTRL_RXEQ_RXIDLE], 0x5);
426 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_AGC_THSEL_VREGH], 0x83);
427 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_GEN3_AGC_SD_THSEL], 0x83);
428 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_RX_SELR_GEN3], 0x81);
429 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_TX_DRV], 0x3b);
430 ret |= regmap_field_write(phy->fields[P2S_RBUF_PTR_DIFF], 0x3);
431 ret |= regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL);
432 ret |= regmap_field_write(phy->fields[COMRXEQ_MS_INIT_CTRL_7_0], 0xf);
433 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_INIT_CAL_7_0], 0x4f);
434 ret |= regmap_field_write(phy->fields[COMRXEQ_MS_RECAL_CTRL_7_0], 0xf);
435 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RECAL_CTRL_7_0], 0x4f);
436 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_ATT_CONFIG], 0x7);
437 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_EBSTADAPT_WIN_LEN], 0x7f);
438 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_3_4], 0xf);
439 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_14_15_16], 0x9a);
440 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_DLEV_ERR_THRESH], 0x32);
441 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_25], 0x80);
442 ret |= regmap_field_write(phy->fields[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O], 0xf);
443 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RCHANGE_CTRL_7_0], 0x4f);
444 ret |= regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1);
445 ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x2);
446
447 if (ret)
448 return -EIO;
449
450 return 0;
451 }
452
serdes_am654_init(struct phy * x)453 static int serdes_am654_init(struct phy *x)
454 {
455 struct serdes_am654 *phy = phy_get_drvdata(x);
456
457 switch (phy->type) {
458 case PHY_TYPE_PCIE:
459 return serdes_am654_pcie_init(phy);
460 case PHY_TYPE_USB3:
461 return serdes_am654_usb3_init(phy);
462 default:
463 return -EINVAL;
464 }
465 }
466
serdes_am654_reset(struct phy * x)467 static int serdes_am654_reset(struct phy *x)
468 {
469 struct serdes_am654 *phy = phy_get_drvdata(x);
470 int ret = 0;
471
472 serdes_am654_disable_pll(phy);
473 serdes_am654_disable_txrx(phy);
474
475 ret |= regmap_field_write(phy->fields[POR_EN], 0x1);
476
477 mdelay(1);
478
479 ret |= regmap_field_write(phy->fields[POR_EN], 0x0);
480
481 if (ret)
482 return -EIO;
483
484 return 0;
485 }
486
serdes_am654_release(struct phy * x)487 static void serdes_am654_release(struct phy *x)
488 {
489 struct serdes_am654 *phy = phy_get_drvdata(x);
490
491 phy->type = PHY_NONE;
492 phy->busy = false;
493 mux_control_deselect(phy->control);
494 }
495
serdes_am654_xlate(struct device * dev,const struct of_phandle_args * args)496 static struct phy *serdes_am654_xlate(struct device *dev,
497 const struct of_phandle_args *args)
498 {
499 struct serdes_am654 *am654_phy;
500 struct phy *phy;
501 int ret;
502
503 phy = of_phy_simple_xlate(dev, args);
504 if (IS_ERR(phy))
505 return phy;
506
507 am654_phy = phy_get_drvdata(phy);
508 if (am654_phy->busy)
509 return ERR_PTR(-EBUSY);
510
511 ret = mux_control_select(am654_phy->control, args->args[1]);
512 if (ret) {
513 dev_err(dev, "Failed to select SERDES Lane Function\n");
514 return ERR_PTR(ret);
515 }
516
517 am654_phy->busy = true;
518 am654_phy->type = args->args[0];
519
520 return phy;
521 }
522
523 static const struct phy_ops ops = {
524 .reset = serdes_am654_reset,
525 .init = serdes_am654_init,
526 .power_on = serdes_am654_power_on,
527 .power_off = serdes_am654_power_off,
528 .release = serdes_am654_release,
529 .owner = THIS_MODULE,
530 };
531
532 #define SERDES_NUM_MUX_COMBINATIONS 16
533
534 #define LICLK 0
535 #define EXT_REFCLK 1
536 #define RICLK 2
537
538 static const int
539 serdes_am654_mux_table[SERDES_NUM_MUX_COMBINATIONS][SERDES_NUM_CLOCKS] = {
540 /*
541 * Each combination maps to one of
542 * "Figure 12-1986. SerDes Reference Clock Distribution"
543 * in TRM.
544 */
545 /* Parent of CMU refclk, Left output, Right output
546 * either of EXT_REFCLK, LICLK, RICLK
547 */
548 { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0000 */
549 { RICLK, EXT_REFCLK, EXT_REFCLK }, /* 0001 */
550 { EXT_REFCLK, RICLK, LICLK }, /* 0010 */
551 { RICLK, RICLK, EXT_REFCLK }, /* 0011 */
552 { LICLK, EXT_REFCLK, EXT_REFCLK }, /* 0100 */
553 { EXT_REFCLK, EXT_REFCLK, EXT_REFCLK }, /* 0101 */
554 { LICLK, RICLK, LICLK }, /* 0110 */
555 { EXT_REFCLK, RICLK, LICLK }, /* 0111 */
556 { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1000 */
557 { RICLK, EXT_REFCLK, LICLK }, /* 1001 */
558 { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1010 */
559 { RICLK, RICLK, EXT_REFCLK }, /* 1011 */
560 { LICLK, EXT_REFCLK, LICLK }, /* 1100 */
561 { EXT_REFCLK, EXT_REFCLK, LICLK }, /* 1101 */
562 { LICLK, RICLK, EXT_REFCLK }, /* 1110 */
563 { EXT_REFCLK, RICLK, EXT_REFCLK }, /* 1111 */
564 };
565
serdes_am654_clk_mux_get_parent(struct clk_hw * hw)566 static u8 serdes_am654_clk_mux_get_parent(struct clk_hw *hw)
567 {
568 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
569 struct regmap *regmap = mux->regmap;
570 unsigned int reg = mux->reg;
571 unsigned int val;
572
573 regmap_read(regmap, reg, &val);
574 val &= AM654_SERDES_CTRL_CLKSEL_MASK;
575 val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
576
577 return serdes_am654_mux_table[val][mux->clk_id];
578 }
579
serdes_am654_clk_mux_set_parent(struct clk_hw * hw,u8 index)580 static int serdes_am654_clk_mux_set_parent(struct clk_hw *hw, u8 index)
581 {
582 struct serdes_am654_clk_mux *mux = to_serdes_am654_clk_mux(hw);
583 struct regmap *regmap = mux->regmap;
584 const char *name = clk_hw_get_name(hw);
585 unsigned int reg = mux->reg;
586 int clk_id = mux->clk_id;
587 int parents[SERDES_NUM_CLOCKS];
588 const int *p;
589 u32 val;
590 int found, i;
591 int ret;
592
593 /* get existing setting */
594 regmap_read(regmap, reg, &val);
595 val &= AM654_SERDES_CTRL_CLKSEL_MASK;
596 val >>= AM654_SERDES_CTRL_CLKSEL_SHIFT;
597
598 for (i = 0; i < SERDES_NUM_CLOCKS; i++)
599 parents[i] = serdes_am654_mux_table[val][i];
600
601 /* change parent of this clock. others left intact */
602 parents[clk_id] = index;
603
604 /* Find the match */
605 for (val = 0; val < SERDES_NUM_MUX_COMBINATIONS; val++) {
606 p = serdes_am654_mux_table[val];
607 found = 1;
608 for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
609 if (parents[i] != p[i]) {
610 found = 0;
611 break;
612 }
613 }
614
615 if (found)
616 break;
617 }
618
619 if (!found) {
620 /*
621 * This can never happen, unless we missed
622 * a valid combination in serdes_am654_mux_table.
623 */
624 WARN(1, "Failed to find the parent of %s clock\n", name);
625 return -EINVAL;
626 }
627
628 val <<= AM654_SERDES_CTRL_CLKSEL_SHIFT;
629 ret = regmap_update_bits(regmap, reg, AM654_SERDES_CTRL_CLKSEL_MASK,
630 val);
631
632 return ret;
633 }
634
635 static const struct clk_ops serdes_am654_clk_mux_ops = {
636 .determine_rate = __clk_mux_determine_rate,
637 .set_parent = serdes_am654_clk_mux_set_parent,
638 .get_parent = serdes_am654_clk_mux_get_parent,
639 };
640
serdes_am654_clk_register(struct serdes_am654 * am654_phy,const char * clock_name,int clock_num)641 static int serdes_am654_clk_register(struct serdes_am654 *am654_phy,
642 const char *clock_name, int clock_num)
643 {
644 struct device_node *node = am654_phy->of_node;
645 struct device *dev = am654_phy->dev;
646 struct serdes_am654_clk_mux *mux;
647 const char **parent_names;
648 struct clk_init_data *init;
649 unsigned int num_parents;
650 struct regmap *regmap;
651 const __be32 *addr;
652 unsigned int reg;
653 struct clk *clk;
654
655 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
656 if (!mux)
657 return -ENOMEM;
658
659 init = &mux->clk_data;
660
661 struct device_node *regmap_node __free(device_node) =
662 of_parse_phandle(node, "ti,serdes-clk", 0);
663 if (!regmap_node)
664 return dev_err_probe(dev, -ENODEV, "Fail to get serdes-clk node\n");
665
666 regmap = syscon_node_to_regmap(regmap_node->parent);
667 if (IS_ERR(regmap))
668 return dev_err_probe(dev, PTR_ERR(regmap),
669 "Fail to get Syscon regmap\n");
670
671 num_parents = of_clk_get_parent_count(node);
672 if (num_parents < 2)
673 return dev_err_probe(dev, -EINVAL, "SERDES clock must have parents\n");
674
675 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
676 GFP_KERNEL);
677 if (!parent_names)
678 return -ENOMEM;
679
680 of_clk_parent_fill(node, parent_names, num_parents);
681
682 addr = of_get_address(regmap_node, 0, NULL, NULL);
683 if (!addr)
684 return -EINVAL;
685
686 reg = be32_to_cpu(*addr);
687
688 init->ops = &serdes_am654_clk_mux_ops;
689 init->flags = CLK_SET_RATE_NO_REPARENT;
690 init->parent_names = parent_names;
691 init->num_parents = num_parents;
692 init->name = clock_name;
693
694 mux->regmap = regmap;
695 mux->reg = reg;
696 mux->clk_id = clock_num;
697 mux->hw.init = init;
698
699 clk = devm_clk_register(dev, &mux->hw);
700 if (IS_ERR(clk))
701 return PTR_ERR(clk);
702
703 am654_phy->clks[clock_num] = clk;
704
705 return 0;
706 }
707
708 static const struct of_device_id serdes_am654_id_table[] = {
709 {
710 .compatible = "ti,phy-am654-serdes",
711 },
712 {}
713 };
714 MODULE_DEVICE_TABLE(of, serdes_am654_id_table);
715
serdes_am654_regfield_init(struct serdes_am654 * am654_phy)716 static int serdes_am654_regfield_init(struct serdes_am654 *am654_phy)
717 {
718 struct regmap *regmap = am654_phy->regmap;
719 struct device *dev = am654_phy->dev;
720 int i;
721
722 for (i = 0; i < MAX_FIELDS; i++) {
723 am654_phy->fields[i] = devm_regmap_field_alloc(dev,
724 regmap,
725 serdes_am654_reg_fields[i]);
726 if (IS_ERR(am654_phy->fields[i])) {
727 dev_err(dev, "Unable to allocate regmap field %d\n", i);
728 return PTR_ERR(am654_phy->fields[i]);
729 }
730 }
731
732 return 0;
733 }
734
serdes_am654_probe(struct platform_device * pdev)735 static int serdes_am654_probe(struct platform_device *pdev)
736 {
737 struct phy_provider *phy_provider;
738 struct device *dev = &pdev->dev;
739 struct device_node *node = dev->of_node;
740 struct clk_onecell_data *clk_data;
741 struct serdes_am654 *am654_phy;
742 struct mux_control *control;
743 const char *clock_name;
744 struct regmap *regmap;
745 void __iomem *base;
746 struct phy *phy;
747 int ret;
748 int i;
749
750 am654_phy = devm_kzalloc(dev, sizeof(*am654_phy), GFP_KERNEL);
751 if (!am654_phy)
752 return -ENOMEM;
753
754 base = devm_platform_ioremap_resource(pdev, 0);
755 if (IS_ERR(base))
756 return PTR_ERR(base);
757
758 regmap = devm_regmap_init_mmio(dev, base, &serdes_am654_regmap_config);
759 if (IS_ERR(regmap)) {
760 dev_err(dev, "Failed to initialize regmap\n");
761 return PTR_ERR(regmap);
762 }
763
764 control = devm_mux_control_get(dev, NULL);
765 if (IS_ERR(control))
766 return PTR_ERR(control);
767
768 am654_phy->dev = dev;
769 am654_phy->of_node = node;
770 am654_phy->regmap = regmap;
771 am654_phy->control = control;
772 am654_phy->type = PHY_NONE;
773
774 ret = serdes_am654_regfield_init(am654_phy);
775 if (ret) {
776 dev_err(dev, "Failed to initialize regfields\n");
777 return ret;
778 }
779
780 platform_set_drvdata(pdev, am654_phy);
781
782 for (i = 0; i < SERDES_NUM_CLOCKS; i++) {
783 ret = of_property_read_string_index(node, "clock-output-names",
784 i, &clock_name);
785 if (ret) {
786 dev_err(dev, "Failed to get clock name\n");
787 return ret;
788 }
789
790 ret = serdes_am654_clk_register(am654_phy, clock_name, i);
791 if (ret) {
792 dev_err(dev, "Failed to initialize clock %s\n",
793 clock_name);
794 return ret;
795 }
796 }
797
798 clk_data = &am654_phy->clk_data;
799 clk_data->clks = am654_phy->clks;
800 clk_data->clk_num = SERDES_NUM_CLOCKS;
801 ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
802 if (ret)
803 return ret;
804
805 pm_runtime_enable(dev);
806
807 phy = devm_phy_create(dev, NULL, &ops);
808 if (IS_ERR(phy)) {
809 ret = PTR_ERR(phy);
810 goto clk_err;
811 }
812
813 phy_set_drvdata(phy, am654_phy);
814 phy_provider = devm_of_phy_provider_register(dev, serdes_am654_xlate);
815 if (IS_ERR(phy_provider)) {
816 ret = PTR_ERR(phy_provider);
817 goto clk_err;
818 }
819
820 return 0;
821
822 clk_err:
823 of_clk_del_provider(node);
824 pm_runtime_disable(dev);
825 return ret;
826 }
827
serdes_am654_remove(struct platform_device * pdev)828 static void serdes_am654_remove(struct platform_device *pdev)
829 {
830 struct serdes_am654 *am654_phy = platform_get_drvdata(pdev);
831 struct device_node *node = am654_phy->of_node;
832
833 pm_runtime_disable(&pdev->dev);
834 of_clk_del_provider(node);
835 }
836
837 static struct platform_driver serdes_am654_driver = {
838 .probe = serdes_am654_probe,
839 .remove = serdes_am654_remove,
840 .driver = {
841 .name = "phy-am654",
842 .of_match_table = serdes_am654_id_table,
843 },
844 };
845 module_platform_driver(serdes_am654_driver);
846
847 MODULE_AUTHOR("Texas Instruments Inc.");
848 MODULE_DESCRIPTION("TI AM654x SERDES driver");
849 MODULE_LICENSE("GPL v2");
850