1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Samsung Electronics Co., Ltd.
4 * Author: Sunyeal Hong <sunyeal.hong@samsung.com>
5 *
6 * Common Clock Framework support for ExynosAuto v920 SoC.
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13
14 #include <dt-bindings/clock/samsung,exynosautov920.h>
15
16 #include "clk.h"
17 #include "clk-exynos-arm64.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
21 #define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1)
22 #define CLKS_NR_CPUCL1 (CLK_DOUT_CPUCL1_NOCP + 1)
23 #define CLKS_NR_CPUCL2 (CLK_DOUT_CPUCL2_NOCP + 1)
24 #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
25 #define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
26 #define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
27 #define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1)
28 #define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1)
29
30 /* ---- CMU_TOP ------------------------------------------------------------ */
31
32 /* Register Offset definitions for CMU_TOP (0x11000000) */
33 #define PLL_LOCKTIME_PLL_MMC 0x0004
34 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
35 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
36 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
37 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
38 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
39 #define PLL_LOCKTIME_PLL_SHARED5 0x0018
40 #define PLL_CON0_PLL_MMC 0x0140
41 #define PLL_CON3_PLL_MMC 0x014c
42 #define PLL_CON0_PLL_SHARED0 0x0180
43 #define PLL_CON3_PLL_SHARED0 0x018c
44 #define PLL_CON0_PLL_SHARED1 0x01c0
45 #define PLL_CON3_PLL_SHARED1 0x01cc
46 #define PLL_CON0_PLL_SHARED2 0x0200
47 #define PLL_CON3_PLL_SHARED2 0x020c
48 #define PLL_CON0_PLL_SHARED3 0x0240
49 #define PLL_CON3_PLL_SHARED3 0x024c
50 #define PLL_CON0_PLL_SHARED4 0x0280
51 #define PLL_CON3_PLL_SHARED4 0x028c
52 #define PLL_CON0_PLL_SHARED5 0x02c0
53 #define PLL_CON3_PLL_SHARED5 0x02cc
54
55 /* MUX */
56 #define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC 0x1000
57 #define CLK_CON_MUX_MUX_CLKCMU_APM_NOC 0x1004
58 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
59 #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x100c
60 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 0x1010
61 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 0x1014
62 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 0x1018
63 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 0x101c
64 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1020
65 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
66 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1028
67 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
68 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
69 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
70 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER 0x1038
71 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x103c
72 #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x1040
73 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
74 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC 0x1048
75 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC 0x104c
76 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x1050
77 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC 0x1054
78 #define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC 0x1058
79 #define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC 0x105c
80 #define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC 0x1060
81 #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x1064
82 #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1068
83 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x106c
84 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x1070
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x1074
86 #define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB 0x1078
87 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA 0x107c
88 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x1080
89 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1084
90 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD 0x1088
91 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET 0x108c
92 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC 0x1090
93 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS 0x1094
94 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x1098
95 #define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC 0x109c
96 #define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG 0x10a0
97 #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x10a4
98 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10a8
99 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x10ac
100 #define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC 0x10b0
101 #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x10b4
102 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10b8
103 #define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC 0x10bc
104 #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x10c0
105 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC 0x10c4
106 #define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC 0x10c8
107 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10cc
108 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x10d0
109 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d4
110 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x10d8
111 #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x10dc
112 #define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC 0x10e0
113 #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x10e4
114 #define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC 0x10e8
115 #define CLK_CON_MUX_MUX_CLK_CMU_NOCP 0x10ec
116 #define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT 0x10f0
117 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
118
119 /* DIV */
120 #define CLK_CON_DIV_CLKCMU_ACC_NOC 0x1800
121 #define CLK_CON_DIV_CLKCMU_APM_NOC 0x1804
122 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1808
123 #define CLK_CON_DIV_CLKCMU_AUD_NOC 0x180c
124 #define CLK_CON_DIV_CLKCMU_CIS_MCLK0 0x1810
125 #define CLK_CON_DIV_CLKCMU_CIS_MCLK1 0x1814
126 #define CLK_CON_DIV_CLKCMU_CIS_MCLK2 0x1818
127 #define CLK_CON_DIV_CLKCMU_CIS_MCLK3 0x181c
128 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
129 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1824
130 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
131 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
132 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
133 #define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER 0x1834
134 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1838
135 #define CLK_CON_DIV_CLKCMU_DNC_NOC 0x183c
136 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
137 #define CLK_CON_DIV_CLKCMU_DPTX_DPOSC 0x1844
138 #define CLK_CON_DIV_CLKCMU_DPTX_NOC 0x1848
139 #define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x184c
140 #define CLK_CON_DIV_CLKCMU_DPUB_NOC 0x1850
141 #define CLK_CON_DIV_CLKCMU_DPUF0_NOC 0x1854
142 #define CLK_CON_DIV_CLKCMU_DPUF1_NOC 0x1858
143 #define CLK_CON_DIV_CLKCMU_DPUF2_NOC 0x185c
144 #define CLK_CON_DIV_CLKCMU_DSP_NOC 0x1860
145 #define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1864
146 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
147 #define CLK_CON_DIV_CLKCMU_GNPU_NOC 0x186c
148 #define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1870
149 #define CLK_CON_DIV_CLKCMU_ACC_ORB 0x1874
150 #define CLK_CON_DIV_CLKCMU_GNPU_XMAA 0x1878
151 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x187c
152 #define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1880
153 #define CLK_CON_DIV_CLKCMU_HSI1_USBDRD 0x1884
154 #define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET 0x1888
155 #define CLK_CON_DIV_CLKCMU_HSI2_NOC 0x188c
156 #define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS 0x1890
157 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x1894
158 #define CLK_CON_DIV_CLKCMU_ISP_NOC 0x1898
159 #define CLK_CON_DIV_CLKCMU_M2M_JPEG 0x189c
160 #define CLK_CON_DIV_CLKCMU_M2M_NOC 0x18a0
161 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18a4
162 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x18a8
163 #define CLK_CON_DIV_CLKCMU_MFD_NOC 0x18ac
164 #define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x18b0
165 #define CLK_CON_DIV_CLKCMU_MISC_NOC 0x18b4
166 #define CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x18b8
167 #define CLK_CON_DIV_CLKCMU_NOCL1_NOC 0x18bc
168 #define CLK_CON_DIV_CLKCMU_NOCL2_NOC 0x18c0
169 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c4
170 #define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x18c8
171 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18cc
172 #define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x18d0
173 #define CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18d4
174 #define CLK_CON_DIV_CLKCMU_SNW_NOC 0x18d8
175 #define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18dc
176 #define CLK_CON_DIV_CLKCMU_TAA_NOC 0x18e0
177 #define CLK_CON_DIV_CLK_ADD_CH_CLK 0x18e4
178 #define CLK_CON_DIV_CLK_CMU_PLLCLKOUT 0x18e8
179 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18ec
180 #define CLK_CON_DIV_DIV_CLK_CMU_NOCP 0x18f0
181
182 static const unsigned long top_clk_regs[] __initconst = {
183 PLL_LOCKTIME_PLL_MMC,
184 PLL_LOCKTIME_PLL_SHARED0,
185 PLL_LOCKTIME_PLL_SHARED1,
186 PLL_LOCKTIME_PLL_SHARED2,
187 PLL_LOCKTIME_PLL_SHARED3,
188 PLL_LOCKTIME_PLL_SHARED4,
189 PLL_LOCKTIME_PLL_SHARED5,
190 PLL_CON0_PLL_MMC,
191 PLL_CON3_PLL_MMC,
192 PLL_CON0_PLL_SHARED0,
193 PLL_CON3_PLL_SHARED0,
194 PLL_CON0_PLL_SHARED1,
195 PLL_CON3_PLL_SHARED1,
196 PLL_CON0_PLL_SHARED2,
197 PLL_CON3_PLL_SHARED2,
198 PLL_CON0_PLL_SHARED3,
199 PLL_CON3_PLL_SHARED3,
200 PLL_CON0_PLL_SHARED4,
201 PLL_CON3_PLL_SHARED4,
202 PLL_CON0_PLL_SHARED5,
203 PLL_CON3_PLL_SHARED5,
204 CLK_CON_MUX_MUX_CLKCMU_ACC_NOC,
205 CLK_CON_MUX_MUX_CLKCMU_APM_NOC,
206 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
207 CLK_CON_MUX_MUX_CLKCMU_AUD_NOC,
208 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0,
209 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1,
210 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2,
211 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3,
212 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
213 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
214 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
215 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
216 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
217 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
218 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER,
219 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
220 CLK_CON_MUX_MUX_CLKCMU_DNC_NOC,
221 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC,
222 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC,
223 CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC,
224 CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM,
225 CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC,
226 CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC,
227 CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC,
228 CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC,
229 CLK_CON_MUX_MUX_CLKCMU_DSP_NOC,
230 CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP,
231 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
232 CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC,
233 CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC,
234 CLK_CON_MUX_MUX_CLKCMU_ACC_ORB,
235 CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA,
236 CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
237 CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
238 CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD,
239 CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET,
240 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC,
241 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS,
242 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
243 CLK_CON_MUX_MUX_CLKCMU_ISP_NOC,
244 CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG,
245 CLK_CON_MUX_MUX_CLKCMU_M2M_NOC,
246 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
247 CLK_CON_MUX_MUX_CLKCMU_MFC_WFD,
248 CLK_CON_MUX_MUX_CLKCMU_MFD_NOC,
249 CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP,
250 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
251 CLK_CON_MUX_MUX_CLKCMU_MISC_NOC,
252 CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC,
253 CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC,
254 CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC,
255 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
256 CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC,
257 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
258 CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC,
259 CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC,
260 CLK_CON_MUX_MUX_CLKCMU_SNW_NOC,
261 CLK_CON_MUX_MUX_CLKCMU_SSP_NOC,
262 CLK_CON_MUX_MUX_CLKCMU_TAA_NOC,
263 CLK_CON_MUX_MUX_CLK_CMU_NOCP,
264 CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT,
265 CLK_CON_MUX_MUX_CMU_CMUREF,
266 CLK_CON_DIV_CLKCMU_ACC_NOC,
267 CLK_CON_DIV_CLKCMU_APM_NOC,
268 CLK_CON_DIV_CLKCMU_AUD_CPU,
269 CLK_CON_DIV_CLKCMU_AUD_NOC,
270 CLK_CON_DIV_CLKCMU_CIS_MCLK0,
271 CLK_CON_DIV_CLKCMU_CIS_MCLK1,
272 CLK_CON_DIV_CLKCMU_CIS_MCLK2,
273 CLK_CON_DIV_CLKCMU_CIS_MCLK3,
274 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER,
275 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
276 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
277 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER,
278 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
279 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER,
280 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
281 CLK_CON_DIV_CLKCMU_DNC_NOC,
282 CLK_CON_DIV_CLKCMU_DPTX_DPGTC,
283 CLK_CON_DIV_CLKCMU_DPTX_DPOSC,
284 CLK_CON_DIV_CLKCMU_DPTX_NOC,
285 CLK_CON_DIV_CLKCMU_DPUB_DSIM,
286 CLK_CON_DIV_CLKCMU_DPUB_NOC,
287 CLK_CON_DIV_CLKCMU_DPUF0_NOC,
288 CLK_CON_DIV_CLKCMU_DPUF1_NOC,
289 CLK_CON_DIV_CLKCMU_DPUF2_NOC,
290 CLK_CON_DIV_CLKCMU_DSP_NOC,
291 CLK_CON_DIV_CLKCMU_G3D_NOCP,
292 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
293 CLK_CON_DIV_CLKCMU_GNPU_NOC,
294 CLK_CON_DIV_CLKCMU_HSI0_NOC,
295 CLK_CON_DIV_CLKCMU_ACC_ORB,
296 CLK_CON_DIV_CLKCMU_GNPU_XMAA,
297 CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
298 CLK_CON_DIV_CLKCMU_HSI1_NOC,
299 CLK_CON_DIV_CLKCMU_HSI1_USBDRD,
300 CLK_CON_DIV_CLKCMU_HSI2_ETHERNET,
301 CLK_CON_DIV_CLKCMU_HSI2_NOC,
302 CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS,
303 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
304 CLK_CON_DIV_CLKCMU_ISP_NOC,
305 CLK_CON_DIV_CLKCMU_M2M_JPEG,
306 CLK_CON_DIV_CLKCMU_M2M_NOC,
307 CLK_CON_DIV_CLKCMU_MFC_MFC,
308 CLK_CON_DIV_CLKCMU_MFC_WFD,
309 CLK_CON_DIV_CLKCMU_MFD_NOC,
310 CLK_CON_DIV_CLKCMU_MIF_NOCP,
311 CLK_CON_DIV_CLKCMU_MISC_NOC,
312 CLK_CON_DIV_CLKCMU_NOCL0_NOC,
313 CLK_CON_DIV_CLKCMU_NOCL1_NOC,
314 CLK_CON_DIV_CLKCMU_NOCL2_NOC,
315 CLK_CON_DIV_CLKCMU_PERIC0_IP,
316 CLK_CON_DIV_CLKCMU_PERIC0_NOC,
317 CLK_CON_DIV_CLKCMU_PERIC1_IP,
318 CLK_CON_DIV_CLKCMU_PERIC1_NOC,
319 CLK_CON_DIV_CLKCMU_SDMA_NOC,
320 CLK_CON_DIV_CLKCMU_SNW_NOC,
321 CLK_CON_DIV_CLKCMU_SSP_NOC,
322 CLK_CON_DIV_CLKCMU_TAA_NOC,
323 CLK_CON_DIV_CLK_ADD_CH_CLK,
324 CLK_CON_DIV_CLK_CMU_PLLCLKOUT,
325 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
326 CLK_CON_DIV_DIV_CLK_CMU_NOCP,
327 };
328
329 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
330 /* CMU_TOP_PURECLKCOMP */
331 PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
332 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
333 PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
334 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
335 PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
336 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
337 PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
338 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
339 PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
340 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
341 PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk",
342 PLL_LOCKTIME_PLL_SHARED5, PLL_CON3_PLL_SHARED5, NULL),
343 PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
344 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
345 };
346
347 /* List of parent clocks for Muxes in CMU_TOP */
348 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
349 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
350 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
351 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
352 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
353 PNAME(mout_shared5_pll_p) = { "oscclk", "fout_shared5_pll" };
354 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
355
356 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
357 "dout_shared2_div4", "dout_shared4_div4" };
358
359 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
360
361 PNAME(mout_clkcmu_acc_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
362 "dout_shared4_div2", "dout_shared1_div3",
363 "dout_shared2_div3", "dout_shared5_div1",
364 "dout_shared3_div1", "oscclk" };
365
366 PNAME(mout_clkcmu_acc_orb_p) = { "dout_shared2_div2", "dout_shared0_div3",
367 "dout_shared1_div2", "dout_shared1_div3",
368 "dout_shared2_div3", "fout_shared5_pll",
369 "fout_shared3_pll", "oscclk" };
370
371 PNAME(mout_clkcmu_apm_noc_p) = { "dout_shared2_div2", "dout_shared1_div4",
372 "dout_shared2_div4", "dout_shared4_div4" };
373
374 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
375 "dout_shared2_div2", "dout_shared0_div3",
376 "dout_shared4_div2", "dout_shared1_div3",
377 "dout_shared2_div3", "dout_shared4_div3" };
378
379 PNAME(mout_clkcmu_aud_noc_p) = { "dout_shared2_div2", "dout_shared4_div2",
380 "dout_shared1_div2", "dout_shared2_div3" };
381
382 PNAME(mout_clkcmu_cpucl0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
383 "dout_shared2_div2", "dout_shared4_div2" };
384
385 PNAME(mout_clkcmu_cpucl0_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
386 "dout_shared0_div2", "dout_shared1_div2",
387 "dout_shared2_div2", "dout_shared4_div2",
388 "dout_shared2_div3", "fout_shared3_pll" };
389
390 PNAME(mout_clkcmu_cpucl0_dbg_p) = { "dout_shared2_div2", "dout_shared0_div3",
391 "dout_shared4_div2", "dout_shared0_div4" };
392
393 PNAME(mout_clkcmu_cpucl1_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
394 "dout_shared2_div2", "dout_shared4_div2" };
395
396 PNAME(mout_clkcmu_cpucl1_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
397 "dout_shared0_div2", "dout_shared1_div2",
398 "dout_shared2_div2", "dout_shared4_div2",
399 "dout_shared2_div3", "fout_shared3_pll" };
400
401 PNAME(mout_clkcmu_cpucl2_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
402 "dout_shared2_div2", "dout_shared4_div2" };
403
404 PNAME(mout_clkcmu_cpucl2_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll",
405 "dout_shared0_div2", "dout_shared1_div2",
406 "dout_shared2_div2", "dout_shared4_div2",
407 "dout_shared2_div3", "fout_shared3_pll" };
408
409 PNAME(mout_clkcmu_dnc_noc_p) = { "dout_shared1_div2", "dout_shared2_div2",
410 "dout_shared0_div3", "dout_shared4_div2",
411 "dout_shared1_div3", "dout_shared2_div3",
412 "dout_shared1_div4", "fout_shared3_pll" };
413
414 PNAME(mout_clkcmu_dptx_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
415 "dout_shared1_div4", "dout_shared2_div4" };
416
417 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3",
418 "dout_shared2_div4", "dout_shared4_div4" };
419
420 PNAME(mout_clkcmu_dptx_dposc_p) = { "oscclk", "dout_shared2_div4" };
421
422 PNAME(mout_clkcmu_dpub_noc_p) = { "dout_shared4_div2", "dout_shared1_div3",
423 "dout_shared2_div3", "dout_shared1_div4",
424 "dout_shared2_div4", "dout_shared4_div4",
425 "fout_shared3_pll" };
426
427 PNAME(mout_clkcmu_dpub_dsim_p) = { "dout_shared2_div3", "dout_shared2_div4" };
428
429 PNAME(mout_clkcmu_dpuf_noc_p) = { "dout_shared4_div2", "dout_shared1_div3",
430 "dout_shared2_div3", "dout_shared1_div4",
431 "dout_shared2_div4", "dout_shared4_div4",
432 "fout_shared3_pll" };
433
434 PNAME(mout_clkcmu_dsp_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
435 "dout_shared2_div2", "dout_shared0_div3",
436 "dout_shared4_div2", "dout_shared1_div3",
437 "fout_shared5_pll", "fout_shared3_pll" };
438
439 PNAME(mout_clkcmu_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
440 "dout_shared2_div2", "dout_shared4_div2" };
441
442 PNAME(mout_clkcmu_g3d_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4",
443 "dout_shared2_div4", "dout_shared4_div4" };
444
445 PNAME(mout_clkcmu_gnpu_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
446 "dout_shared2_div2", "dout_shared0_div3",
447 "dout_shared4_div2", "dout_shared2_div3",
448 "fout_shared5_pll", "fout_shared3_pll" };
449
450 PNAME(mout_clkcmu_hsi0_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
451 "dout_shared1_div4", "dout_shared2_div4" };
452
453 PNAME(mout_clkcmu_hsi1_noc_p) = { "dout_shared2_div3", "dout_shared1_div4",
454 "dout_shared2_div4", "dout_shared4_div4" };
455
456 PNAME(mout_clkcmu_hsi1_usbdrd_p) = { "oscclk", "dout_shared2_div3",
457 "dout_shared2_div4", "dout_shared4_div4" };
458
459 PNAME(mout_clkcmu_hsi1_mmc_card_p) = { "oscclk", "dout_shared2_div2",
460 "dout_shared4_div2", "fout_mmc_pll" };
461
462 PNAME(mout_clkcmu_hsi2_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
463 "dout_shared1_div4", "dout_shared2_div4" };
464
465 PNAME(mout_clkcmu_hsi2_noc_ufs_p) = { "dout_shared4_div2", "dout_shared2_div3",
466 "dout_shared1_div4", "dout_shared2_div2" };
467
468 PNAME(mout_clkcmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared2_div3",
469 "dout_shared2_div4", "dout_shared4_div4" };
470
471 PNAME(mout_clkcmu_hsi2_ethernet_p) = { "oscclk", "dout_shared2_div2",
472 "dout_shared0_div3", "dout_shared1_div3" };
473
474 PNAME(mout_clkcmu_isp_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
475 "dout_shared4_div2", "dout_shared1_div3",
476 "dout_shared2_div3", "fout_shared5_pll",
477 "fout_shared3_pll", "oscclk" };
478
479 PNAME(mout_clkcmu_m2m_noc_p) = { "dout_shared0_div3", "dout_shared4_div2",
480 "dout_shared2_div3", "dout_shared1_div4" };
481
482 PNAME(mout_clkcmu_m2m_jpeg_p) = { "dout_shared0_div3", "dout_shared4_div2",
483 "dout_shared2_div3", "dout_shared1_div4" };
484
485 PNAME(mout_clkcmu_mfc_mfc_p) = { "dout_shared0_div3", "dout_shared4_div2",
486 "dout_shared2_div3", "dout_shared1_div4" };
487
488 PNAME(mout_clkcmu_mfc_wfd_p) = { "dout_shared0_div3", "dout_shared4_div2",
489 "dout_shared2_div3", "dout_shared1_div4" };
490
491 PNAME(mout_clkcmu_mfd_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
492 "dout_shared4_div2", "dout_shared1_div3",
493 "dout_shared2_div3", "fout_shared5_pll",
494 "fout_shared3_pll", "oscclk" };
495
496 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
497 "fout_shared2_pll", "fout_shared4_pll",
498 "dout_shared0_div2", "dout_shared1_div2",
499 "dout_shared2_div2", "fout_shared5_pll" };
500
501 PNAME(mout_clkcmu_mif_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4",
502 "dout_shared2_div4", "dout_shared4_div4" };
503
504 PNAME(mout_clkcmu_misc_noc_p) = { "dout_shared4_div2", "dout_shared2_div3",
505 "dout_shared1_div4", "dout_shared2_div4" };
506
507 PNAME(mout_clkcmu_nocl0_noc_p) = { "dout_shared0_div2", "dout_shared1_div2",
508 "dout_shared2_div2", "dout_shared0_div3",
509 "dout_shared4_div2", "dout_shared1_div3",
510 "dout_shared2_div3", "fout_shared3_pll" };
511
512 PNAME(mout_clkcmu_nocl1_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
513 "dout_shared4_div2", "dout_shared1_div3",
514 "dout_shared2_div3", "fout_shared5_pll",
515 "fout_shared3_pll", "oscclk" };
516
517 PNAME(mout_clkcmu_nocl2_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
518 "dout_shared4_div2", "dout_shared1_div3",
519 "dout_shared2_div3", "fout_shared5_pll",
520 "fout_shared3_pll", "oscclk" };
521
522 PNAME(mout_clkcmu_peric0_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" };
523
524 PNAME(mout_clkcmu_peric0_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" };
525
526 PNAME(mout_clkcmu_peric1_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" };
527
528 PNAME(mout_clkcmu_peric1_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" };
529
530 PNAME(mout_clkcmu_sdma_noc_p) = { "dout_shared1_div2", "dout_shared2_div2",
531 "dout_shared0_div3", "dout_shared4_div2",
532 "dout_shared1_div3", "dout_shared2_div3",
533 "dout_shared1_div4", "fout_shared3_pll" };
534
535 PNAME(mout_clkcmu_snw_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
536 "dout_shared4_div2", "dout_shared1_div3",
537 "dout_shared2_div3", "fout_shared5_pll",
538 "fout_shared3_pll", "oscclk" };
539
540 PNAME(mout_clkcmu_ssp_noc_p) = { "dout_shared2_div3", "dout_shared1_div4",
541 "dout_shared2_div2", "dout_shared4_div4" };
542
543 PNAME(mout_clkcmu_taa_noc_p) = { "dout_shared2_div2", "dout_shared0_div3",
544 "dout_shared4_div2", "dout_shared1_div3",
545 "dout_shared2_div3", "fout_shared5_pll",
546 "fout_shared3_pll", "oscclk" };
547
548 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
549 /* CMU_TOP_PURECLKCOMP */
550 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
551 PLL_CON0_PLL_SHARED0, 4, 1),
552 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
553 PLL_CON0_PLL_SHARED1, 4, 1),
554 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
555 PLL_CON0_PLL_SHARED2, 4, 1),
556 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
557 PLL_CON0_PLL_SHARED3, 4, 1),
558 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
559 PLL_CON0_PLL_SHARED4, 4, 1),
560 MUX(MOUT_SHARED5_PLL, "mout_shared5_pll", mout_shared5_pll_p,
561 PLL_CON0_PLL_SHARED5, 4, 1),
562 MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
563 PLL_CON0_PLL_MMC, 4, 1),
564
565 /* BOOST */
566 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
567 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
568 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
569 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
570
571 /* ACC */
572 MUX(MOUT_CLKCMU_ACC_NOC, "mout_clkcmu_acc_noc",
573 mout_clkcmu_acc_noc_p, CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 0, 3),
574 MUX(MOUT_CLKCMU_ACC_ORB, "mout_clkcmu_acc_orb",
575 mout_clkcmu_acc_orb_p, CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 0, 3),
576
577 /* APM */
578 MUX(MOUT_CLKCMU_APM_NOC, "mout_clkcmu_apm_noc",
579 mout_clkcmu_apm_noc_p, CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 0, 2),
580
581 /* AUD */
582 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu",
583 mout_clkcmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
584 MUX(MOUT_CLKCMU_AUD_NOC, "mout_clkcmu_aud_noc",
585 mout_clkcmu_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 2),
586
587 /* CPUCL0 */
588 MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch",
589 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
590 0, 2),
591 MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster",
592 mout_clkcmu_cpucl0_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER,
593 0, 3),
594 MUX(MOUT_CLKCMU_CPUCL0_DBG, "mout_clkcmu_cpucl0_dbg",
595 mout_clkcmu_cpucl0_dbg_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
596 0, 2),
597
598 /* CPUCL1 */
599 MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch",
600 mout_clkcmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
601 0, 2),
602 MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster",
603 mout_clkcmu_cpucl1_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER,
604 0, 3),
605
606 /* CPUCL2 */
607 MUX(MOUT_CLKCMU_CPUCL2_SWITCH, "mout_clkcmu_cpucl2_switch",
608 mout_clkcmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
609 0, 2),
610 MUX(MOUT_CLKCMU_CPUCL2_CLUSTER, "mout_clkcmu_cpucl2_cluster",
611 mout_clkcmu_cpucl2_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER,
612 0, 3),
613
614 /* DNC */
615 MUX(MOUT_CLKCMU_DNC_NOC, "mout_clkcmu_dnc_noc",
616 mout_clkcmu_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3),
617
618 /* DPTX */
619 MUX(MOUT_CLKCMU_DPTX_NOC, "mout_clkcmu_dptx_noc",
620 mout_clkcmu_dptx_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 0, 2),
621 MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc",
622 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
623 MUX(MOUT_CLKCMU_DPTX_DPOSC, "mout_clkcmu_dptx_dposc",
624 mout_clkcmu_dptx_dposc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 0, 1),
625
626 /* DPUB */
627 MUX(MOUT_CLKCMU_DPUB_NOC, "mout_clkcmu_dpub_noc",
628 mout_clkcmu_dpub_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 0, 3),
629 MUX(MOUT_CLKCMU_DPUB_DSIM, "mout_clkcmu_dpub_dsim",
630 mout_clkcmu_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 1),
631
632 /* DPUF */
633 MUX(MOUT_CLKCMU_DPUF0_NOC, "mout_clkcmu_dpuf0_noc",
634 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 0, 3),
635 MUX(MOUT_CLKCMU_DPUF1_NOC, "mout_clkcmu_dpuf1_noc",
636 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 0, 3),
637 MUX(MOUT_CLKCMU_DPUF2_NOC, "mout_clkcmu_dpuf2_noc",
638 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 0, 3),
639
640 /* DSP */
641 MUX(MOUT_CLKCMU_DSP_NOC, "mout_clkcmu_dsp_noc",
642 mout_clkcmu_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3),
643
644 /* G3D */
645 MUX(MOUT_CLKCMU_G3D_SWITCH, "mout_clkcmu_g3d_switch",
646 mout_clkcmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2),
647 MUX(MOUT_CLKCMU_G3D_NOCP, "mout_clkcmu_g3d_nocp",
648 mout_clkcmu_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2),
649
650 /* GNPU */
651 MUX(MOUT_CLKCMU_GNPU_NOC, "mout_clkcmu_gnpu_noc",
652 mout_clkcmu_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3),
653
654 /* HSI0 */
655 MUX(MOUT_CLKCMU_HSI0_NOC, "mout_clkcmu_hsi0_noc",
656 mout_clkcmu_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2),
657
658 /* HSI1 */
659 MUX(MOUT_CLKCMU_HSI1_NOC, "mout_clkcmu_hsi1_noc",
660 mout_clkcmu_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC,
661 0, 2),
662 MUX(MOUT_CLKCMU_HSI1_USBDRD, "mout_clkcmu_hsi1_usbdrd",
663 mout_clkcmu_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD,
664 0, 2),
665 MUX(MOUT_CLKCMU_HSI1_MMC_CARD, "mout_clkcmu_hsi1_mmc_card",
666 mout_clkcmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
667 0, 2),
668
669 /* HSI2 */
670 MUX(MOUT_CLKCMU_HSI2_NOC, "mout_clkcmu_hsi2_noc",
671 mout_clkcmu_hsi2_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC,
672 0, 2),
673 MUX(MOUT_CLKCMU_HSI2_NOC_UFS, "mout_clkcmu_hsi2_noc_ufs",
674 mout_clkcmu_hsi2_noc_ufs_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS,
675 0, 2),
676 MUX(MOUT_CLKCMU_HSI2_UFS_EMBD, "mout_clkcmu_hsi2_ufs_embd",
677 mout_clkcmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
678 0, 2),
679 MUX(MOUT_CLKCMU_HSI2_ETHERNET, "mout_clkcmu_hsi2_ethernet",
680 mout_clkcmu_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET,
681 0, 2),
682
683 /* ISP */
684 MUX(MOUT_CLKCMU_ISP_NOC, "mout_clkcmu_isp_noc",
685 mout_clkcmu_isp_noc_p, CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 0, 3),
686
687 /* M2M */
688 MUX(MOUT_CLKCMU_M2M_NOC, "mout_clkcmu_m2m_noc",
689 mout_clkcmu_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 2),
690 MUX(MOUT_CLKCMU_M2M_JPEG, "mout_clkcmu_m2m_jpeg",
691 mout_clkcmu_m2m_jpeg_p, CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 0, 2),
692
693 /* MFC */
694 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc",
695 mout_clkcmu_mfc_mfc_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
696 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd",
697 mout_clkcmu_mfc_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
698
699 /* MFD */
700 MUX(MOUT_CLKCMU_MFD_NOC, "mout_clkcmu_mfd_noc",
701 mout_clkcmu_mfd_noc_p, CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 0, 3),
702
703 /* MIF */
704 MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch",
705 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
706 MUX(MOUT_CLKCMU_MIF_NOCP, "mout_clkcmu_mif_nocp",
707 mout_clkcmu_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2),
708
709 /* MISC */
710 MUX(MOUT_CLKCMU_MISC_NOC, "mout_clkcmu_misc_noc",
711 mout_clkcmu_misc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0, 2),
712
713 /* NOCL0 */
714 MUX(MOUT_CLKCMU_NOCL0_NOC, "mout_clkcmu_nocl0_noc",
715 mout_clkcmu_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3),
716
717 /* NOCL1 */
718 MUX(MOUT_CLKCMU_NOCL1_NOC, "mout_clkcmu_nocl1_noc",
719 mout_clkcmu_nocl1_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 0, 3),
720
721 /* NOCL2 */
722 MUX(MOUT_CLKCMU_NOCL2_NOC, "mout_clkcmu_nocl2_noc",
723 mout_clkcmu_nocl2_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 0, 3),
724
725 /* PERIC0 */
726 MUX(MOUT_CLKCMU_PERIC0_NOC, "mout_clkcmu_peric0_noc",
727 mout_clkcmu_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0, 1),
728 MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip",
729 mout_clkcmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
730
731 /* PERIC1 */
732 MUX(MOUT_CLKCMU_PERIC1_NOC, "mout_clkcmu_peric1_noc",
733 mout_clkcmu_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0, 1),
734 MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip",
735 mout_clkcmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
736
737 /* SDMA */
738 MUX(MOUT_CLKCMU_SDMA_NOC, "mout_clkcmu_sdma_noc",
739 mout_clkcmu_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3),
740
741 /* SNW */
742 MUX(MOUT_CLKCMU_SNW_NOC, "mout_clkcmu_snw_noc",
743 mout_clkcmu_snw_noc_p, CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 0, 3),
744
745 /* SSP */
746 MUX(MOUT_CLKCMU_SSP_NOC, "mout_clkcmu_ssp_noc",
747 mout_clkcmu_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2),
748
749 /* TAA */
750 MUX(MOUT_CLKCMU_TAA_NOC, "mout_clkcmu_taa_noc",
751 mout_clkcmu_taa_noc_p, CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 0, 3),
752 };
753
754 static const struct samsung_div_clock top_div_clks[] __initconst = {
755 /* CMU_TOP_PURECLKCOMP */
756
757 /* BOOST */
758 DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost",
759 "mout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
760
761 /* ACC */
762 DIV(DOUT_CLKCMU_ACC_NOC, "dout_clkcmu_acc_noc",
763 "mout_clkcmu_acc_noc", CLK_CON_DIV_CLKCMU_ACC_NOC, 0, 4),
764 DIV(DOUT_CLKCMU_ACC_ORB, "dout_clkcmu_acc_orb",
765 "mout_clkcmu_acc_orb", CLK_CON_DIV_CLKCMU_ACC_ORB, 0, 4),
766
767 /* APM */
768 DIV(DOUT_CLKCMU_APM_NOC, "dout_clkcmu_apm_noc",
769 "mout_clkcmu_apm_noc", CLK_CON_DIV_CLKCMU_APM_NOC, 0, 3),
770
771 /* AUD */
772 DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu",
773 "mout_clkcmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
774 DIV(DOUT_CLKCMU_AUD_NOC, "dout_clkcmu_aud_noc",
775 "mout_clkcmu_aud_noc", CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4),
776
777 /* CPUCL0 */
778 DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch",
779 "mout_clkcmu_cpucl0_switch",
780 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
781 DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster",
782 "mout_clkcmu_cpucl0_cluster",
783 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 0, 3),
784 DIV(DOUT_CLKCMU_CPUCL0_DBG, "dout_clkcmu_cpucl0_dbg",
785 "mout_clkcmu_cpucl0_dbg",
786 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
787
788 /* CPUCL1 */
789 DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch",
790 "mout_clkcmu_cpucl1_switch",
791 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
792 DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster",
793 "mout_clkcmu_cpucl1_cluster",
794 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 0, 3),
795
796 /* CPUCL2 */
797 DIV(DOUT_CLKCMU_CPUCL2_SWITCH, "dout_clkcmu_cpucl2_switch",
798 "mout_clkcmu_cpucl2_switch",
799 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
800 DIV(DOUT_CLKCMU_CPUCL2_CLUSTER, "dout_clkcmu_cpucl2_cluster",
801 "mout_clkcmu_cpucl2_cluster",
802 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 0, 3),
803
804 /* DNC */
805 DIV(DOUT_CLKCMU_DNC_NOC, "dout_clkcmu_dnc_noc",
806 "mout_clkcmu_dnc_noc", CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4),
807
808 /* DPTX */
809 DIV(DOUT_CLKCMU_DPTX_NOC, "dout_clkcmu_dptx_noc",
810 "mout_clkcmu_dptx_noc", CLK_CON_DIV_CLKCMU_DPTX_NOC, 0, 4),
811 DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc",
812 "mout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
813 DIV(DOUT_CLKCMU_DPTX_DPOSC, "dout_clkcmu_dptx_dposc",
814 "mout_clkcmu_dptx_dposc", CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 0, 5),
815
816 /* DPUB */
817 DIV(DOUT_CLKCMU_DPUB_NOC, "dout_clkcmu_dpub_noc",
818 "mout_clkcmu_dpub_noc", CLK_CON_DIV_CLKCMU_DPUB_NOC, 0, 4),
819 DIV(DOUT_CLKCMU_DPUB_DSIM, "dout_clkcmu_dpub_dsim",
820 "mout_clkcmu_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4),
821
822 /* DPUF */
823 DIV(DOUT_CLKCMU_DPUF0_NOC, "dout_clkcmu_dpuf0_noc",
824 "mout_clkcmu_dpuf0_noc", CLK_CON_DIV_CLKCMU_DPUF0_NOC, 0, 4),
825 DIV(DOUT_CLKCMU_DPUF1_NOC, "dout_clkcmu_dpuf1_noc",
826 "mout_clkcmu_dpuf1_noc", CLK_CON_DIV_CLKCMU_DPUF1_NOC, 0, 4),
827 DIV(DOUT_CLKCMU_DPUF2_NOC, "dout_clkcmu_dpuf2_noc",
828 "mout_clkcmu_dpuf2_noc", CLK_CON_DIV_CLKCMU_DPUF2_NOC, 0, 4),
829
830 /* DSP */
831 DIV(DOUT_CLKCMU_DSP_NOC, "dout_clkcmu_dsp_noc",
832 "mout_clkcmu_dsp_noc", CLK_CON_DIV_CLKCMU_DSP_NOC, 0, 4),
833
834 /* G3D */
835 DIV(DOUT_CLKCMU_G3D_SWITCH, "dout_clkcmu_g3d_switch",
836 "mout_clkcmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
837 DIV(DOUT_CLKCMU_G3D_NOCP, "dout_clkcmu_g3d_nocp",
838 "mout_clkcmu_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3),
839
840 /* GNPU */
841 DIV(DOUT_CLKCMU_GNPU_NOC, "dout_clkcmu_gnpu_noc",
842 "mout_clkcmu_gnpu_noc", CLK_CON_DIV_CLKCMU_GNPU_NOC, 0, 4),
843
844 /* HSI0 */
845 DIV(DOUT_CLKCMU_HSI0_NOC, "dout_clkcmu_hsi0_noc",
846 "mout_clkcmu_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4),
847
848 /* HSI1 */
849 DIV(DOUT_CLKCMU_HSI1_NOC, "dout_clkcmu_hsi1_noc",
850 "mout_clkcmu_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4),
851 DIV(DOUT_CLKCMU_HSI1_USBDRD, "dout_clkcmu_hsi1_usbdrd",
852 "mout_clkcmu_hsi1_usbdrd", CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 0, 4),
853 DIV(DOUT_CLKCMU_HSI1_MMC_CARD, "dout_clkcmu_hsi1_mmc_card",
854 "mout_clkcmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9),
855
856 /* HSI2 */
857 DIV(DOUT_CLKCMU_HSI2_NOC, "dout_clkcmu_hsi2_noc",
858 "mout_clkcmu_hsi2_noc", CLK_CON_DIV_CLKCMU_HSI2_NOC, 0, 4),
859 DIV(DOUT_CLKCMU_HSI2_NOC_UFS, "dout_clkcmu_hsi2_noc_ufs",
860 "mout_clkcmu_hsi2_noc_ufs", CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 0, 4),
861 DIV(DOUT_CLKCMU_HSI2_UFS_EMBD, "dout_clkcmu_hsi2_ufs_embd",
862 "mout_clkcmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 3),
863 DIV(DOUT_CLKCMU_HSI2_ETHERNET, "dout_clkcmu_hsi2_ethernet",
864 "mout_clkcmu_hsi2_ethernet", CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 0, 3),
865
866 /* ISP */
867 DIV(DOUT_CLKCMU_ISP_NOC, "dout_clkcmu_isp_noc",
868 "mout_clkcmu_isp_noc", CLK_CON_DIV_CLKCMU_ISP_NOC, 0, 4),
869
870 /* M2M */
871 DIV(DOUT_CLKCMU_M2M_NOC, "dout_clkcmu_m2m_noc",
872 "mout_clkcmu_m2m_noc", CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4),
873 DIV(DOUT_CLKCMU_M2M_JPEG, "dout_clkcmu_m2m_jpeg",
874 "mout_clkcmu_m2m_jpeg", CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4),
875
876 /* MFC */
877 DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc",
878 "mout_clkcmu_mfc_mfc", CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
879 DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd",
880 "mout_clkcmu_mfc_wfd", CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
881
882 /* MFD */
883 DIV(DOUT_CLKCMU_MFD_NOC, "dout_clkcmu_mfd_noc",
884 "mout_clkcmu_mfd_noc", CLK_CON_DIV_CLKCMU_MFD_NOC, 0, 4),
885
886 /* MIF */
887 DIV(DOUT_CLKCMU_MIF_NOCP, "dout_clkcmu_mif_nocp",
888 "mout_clkcmu_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4),
889
890 /* MISC */
891 DIV(DOUT_CLKCMU_MISC_NOC, "dout_clkcmu_misc_noc",
892 "mout_clkcmu_misc_noc", CLK_CON_DIV_CLKCMU_MISC_NOC, 0, 4),
893
894 /* NOCL0 */
895 DIV(DOUT_CLKCMU_NOCL0_NOC, "dout_clkcmu_nocl0_noc",
896 "mout_clkcmu_nocl0_noc", CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4),
897
898 /* NOCL1 */
899 DIV(DOUT_CLKCMU_NOCL1_NOC, "dout_clkcmu_nocl1_noc",
900 "mout_clkcmu_nocl1_noc", CLK_CON_DIV_CLKCMU_NOCL1_NOC, 0, 4),
901
902 /* NOCL2 */
903 DIV(DOUT_CLKCMU_NOCL2_NOC, "dout_clkcmu_nocl2_noc",
904 "mout_clkcmu_nocl2_noc", CLK_CON_DIV_CLKCMU_NOCL2_NOC, 0, 4),
905
906 /* PERIC0 */
907 DIV(DOUT_CLKCMU_PERIC0_NOC, "dout_clkcmu_peric0_noc",
908 "mout_clkcmu_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4),
909 DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip",
910 "mout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
911
912 /* PERIC1 */
913 DIV(DOUT_CLKCMU_PERIC1_NOC, "dout_clkcmu_peric1_noc",
914 "mout_clkcmu_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4),
915 DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip",
916 "mout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
917
918 /* SDMA */
919 DIV(DOUT_CLKCMU_SDMA_NOC, "dout_clkcmu_sdma_noc",
920 "mout_clkcmu_sdma_noc", CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4),
921
922 /* SNW */
923 DIV(DOUT_CLKCMU_SNW_NOC, "dout_clkcmu_snw_noc",
924 "mout_clkcmu_snw_noc", CLK_CON_DIV_CLKCMU_SNW_NOC, 0, 4),
925
926 /* SSP */
927 DIV(DOUT_CLKCMU_SSP_NOC, "dout_clkcmu_ssp_noc",
928 "mout_clkcmu_ssp_noc", CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4),
929
930 /* TAA */
931 DIV(DOUT_CLKCMU_TAA_NOC, "dout_clkcmu_taa_noc",
932 "mout_clkcmu_taa_noc", CLK_CON_DIV_CLKCMU_TAA_NOC, 0, 4),
933 };
934
935 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
936 FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1",
937 "mout_shared0_pll", 1, 1, 0),
938 FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2",
939 "mout_shared0_pll", 1, 2, 0),
940 FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3",
941 "mout_shared0_pll", 1, 3, 0),
942 FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4",
943 "mout_shared0_pll", 1, 4, 0),
944 FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1",
945 "mout_shared1_pll", 1, 1, 0),
946 FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2",
947 "mout_shared1_pll", 1, 2, 0),
948 FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3",
949 "mout_shared1_pll", 1, 3, 0),
950 FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4",
951 "mout_shared1_pll", 1, 4, 0),
952 FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1",
953 "mout_shared2_pll", 1, 1, 0),
954 FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2",
955 "mout_shared2_pll", 1, 2, 0),
956 FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3",
957 "mout_shared2_pll", 1, 3, 0),
958 FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4",
959 "mout_shared2_pll", 1, 4, 0),
960 FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1",
961 "mout_shared3_pll", 1, 1, 0),
962 FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2",
963 "mout_shared3_pll", 1, 2, 0),
964 FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3",
965 "mout_shared3_pll", 1, 3, 0),
966 FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4",
967 "mout_shared3_pll", 1, 4, 0),
968 FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1",
969 "mout_shared4_pll", 1, 1, 0),
970 FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2",
971 "mout_shared4_pll", 1, 2, 0),
972 FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3",
973 "mout_shared4_pll", 1, 3, 0),
974 FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4",
975 "mout_shared4_pll", 1, 4, 0),
976 FFACTOR(DOUT_SHARED5_DIV1, "dout_shared5_div1",
977 "mout_shared5_pll", 1, 1, 0),
978 FFACTOR(DOUT_SHARED5_DIV2, "dout_shared5_div2",
979 "mout_shared5_pll", 1, 2, 0),
980 FFACTOR(DOUT_SHARED5_DIV3, "dout_shared5_div3",
981 "mout_shared5_pll", 1, 3, 0),
982 FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",
983 "mout_shared5_pll", 1, 4, 0),
984 FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",
985 "oscclk", 1, 2, 0),
986 };
987
988 static const struct samsung_cmu_info top_cmu_info __initconst = {
989 .pll_clks = top_pll_clks,
990 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
991 .mux_clks = top_mux_clks,
992 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
993 .div_clks = top_div_clks,
994 .nr_div_clks = ARRAY_SIZE(top_div_clks),
995 .fixed_factor_clks = top_fixed_factor_clks,
996 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
997 .nr_clk_ids = CLKS_NR_TOP,
998 .clk_regs = top_clk_regs,
999 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1000 };
1001
exynosautov920_cmu_top_init(struct device_node * np)1002 static void __init exynosautov920_cmu_top_init(struct device_node *np)
1003 {
1004 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1005 }
1006
1007 /* Register CMU_TOP early, as it's a dependency for other early domains */
1008 CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top",
1009 exynosautov920_cmu_top_init);
1010
1011 /* ---- CMU_CPUCL0 --------------------------------------------------------- */
1012
1013 /* Register Offset definitions for CMU_CPUCL0 (0x1EC00000) */
1014 #define PLL_LOCKTIME_PLL_CPUCL0 0x0000
1015 #define PLL_CON0_PLL_CPUCL0 0x0100
1016 #define PLL_CON1_PLL_CPUCL0 0x0104
1017 #define PLL_CON3_PLL_CPUCL0 0x010c
1018 #define PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER 0x0600
1019 #define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0610
1020 #define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0620
1021
1022 #define CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER 0x1000
1023 #define CLK_CON_MUX_MUX_CLK_CPUCL0_CORE 0x1004
1024
1025 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
1026 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1804
1027 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK 0x1808
1028 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK 0x180c
1029 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
1030 #define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC 0x181c
1031 #define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG 0x1820
1032 #define CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP 0x1824
1033
1034 static const unsigned long cpucl0_clk_regs[] __initconst = {
1035 PLL_LOCKTIME_PLL_CPUCL0,
1036 PLL_CON0_PLL_CPUCL0,
1037 PLL_CON1_PLL_CPUCL0,
1038 PLL_CON3_PLL_CPUCL0,
1039 PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER,
1040 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
1041 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
1042 CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER,
1043 CLK_CON_MUX_MUX_CLK_CPUCL0_CORE,
1044 CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
1045 CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
1046 CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK,
1047 CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK,
1048 CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
1049 CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC,
1050 CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG,
1051 CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP,
1052 };
1053
1054 /* List of parent clocks for Muxes in CMU_CPUCL0 */
1055 PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
1056 PNAME(mout_cpucl0_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl0_cluster" };
1057 PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_clkcmu_cpucl0_dbg" };
1058 PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl0_switch" };
1059 PNAME(mout_cpucl0_cluster_p) = { "oscclk", "mout_cpucl0_cluster_user",
1060 "mout_cpucl0_switch_user"};
1061 PNAME(mout_cpucl0_core_p) = { "oscclk", "mout_pll_cpucl0",
1062 "mout_cpucl0_switch_user"};
1063
1064 static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
1065 PLL_35XX_RATE(38400000U, 2400000000U, 250, 4, 0),
1066 PLL_35XX_RATE(38400000U, 2304000000U, 240, 4, 0),
1067 PLL_35XX_RATE(38400000U, 2208000000U, 230, 4, 0),
1068 PLL_35XX_RATE(38400000U, 2112000000U, 220, 4, 0),
1069 PLL_35XX_RATE(38400000U, 2016000000U, 210, 4, 0),
1070 PLL_35XX_RATE(38400000U, 1824000000U, 190, 4, 0),
1071 PLL_35XX_RATE(38400000U, 1680000000U, 175, 4, 0),
1072 PLL_35XX_RATE(38400000U, 1344000000U, 140, 4, 0),
1073 PLL_35XX_RATE(38400000U, 1152000000U, 120, 4, 0),
1074 PLL_35XX_RATE(38400000U, 576000000U, 120, 4, 1),
1075 PLL_35XX_RATE(38400000U, 288000000U, 120, 4, 2),
1076 };
1077
1078 static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
1079 /* CMU_CPUCL0_PURECLKCOMP */
1080 PLL(pll_531x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
1081 PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
1082 };
1083
1084 static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
1085 MUX(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
1086 PLL_CON0_PLL_CPUCL0, 4, 1),
1087 MUX(CLK_MOUT_CPUCL0_CLUSTER_USER, "mout_cpucl0_cluster_user", mout_cpucl0_cluster_user_p,
1088 PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER, 4, 1),
1089 MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user", mout_cpucl0_dbg_user_p,
1090 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
1091 MUX(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user", mout_cpucl0_switch_user_p,
1092 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1),
1093 MUX(CLK_MOUT_CPUCL0_CLUSTER, "mout_cpucl0_cluster", mout_cpucl0_cluster_p,
1094 CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER, 0, 2),
1095 MUX(CLK_MOUT_CPUCL0_CORE, "mout_cpucl0_core", mout_cpucl0_core_p,
1096 CLK_CON_MUX_MUX_CLK_CPUCL0_CORE, 0, 2),
1097 };
1098
1099 static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
1100 DIV(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk",
1101 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4),
1102 DIV(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
1103 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4),
1104 DIV(CLK_DOUT_CLUSTER0_MPCLK, "dout_cluster0_mpclk",
1105 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK, 0, 4),
1106 DIV(CLK_DOUT_CLUSTER0_PCLK, "dout_cluster0_pclk",
1107 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, 0, 4),
1108 DIV(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
1109 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4),
1110 DIV(CLK_DOUT_CPUCL0_DBG_NOC, "dout_cpucl0_dbg_noc",
1111 "mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 0, 3),
1112 DIV(CLK_DOUT_CPUCL0_DBG_PCLKDBG, "dout_cpucl0_dbg_pclkdbg",
1113 "mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0, 3),
1114 DIV(CLK_DOUT_CPUCL0_NOCP, "dout_cpucl0_nocp",
1115 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP, 0, 4),
1116 };
1117
1118 static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
1119 .pll_clks = cpucl0_pll_clks,
1120 .nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
1121 .mux_clks = cpucl0_mux_clks,
1122 .nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
1123 .div_clks = cpucl0_div_clks,
1124 .nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
1125 .nr_clk_ids = CLKS_NR_CPUCL0,
1126 .clk_regs = cpucl0_clk_regs,
1127 .nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
1128 .clk_name = "cpucl0",
1129 };
1130
exynosautov920_cmu_cpucl0_init(struct device_node * np)1131 static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np)
1132 {
1133 exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
1134 }
1135
1136 /* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
1137 CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0",
1138 exynosautov920_cmu_cpucl0_init);
1139
1140 /* ---- CMU_CPUCL1 --------------------------------------------------------- */
1141
1142 /* Register Offset definitions for CMU_CPUCL1 (0x1ED00000) */
1143 #define PLL_LOCKTIME_PLL_CPUCL1 0x0000
1144 #define PLL_CON0_PLL_CPUCL1 0x0100
1145 #define PLL_CON1_PLL_CPUCL1 0x0104
1146 #define PLL_CON3_PLL_CPUCL1 0x010c
1147 #define PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER 0x0600
1148 #define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
1149
1150 #define CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER 0x1000
1151 #define CLK_CON_MUX_MUX_CLK_CPUCL1_CORE 0x1004
1152
1153 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
1154 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1804
1155 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK 0x1808
1156 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK 0x180c
1157 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
1158 #define CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP 0x181c
1159
1160 static const unsigned long cpucl1_clk_regs[] __initconst = {
1161 PLL_LOCKTIME_PLL_CPUCL1,
1162 PLL_CON0_PLL_CPUCL1,
1163 PLL_CON1_PLL_CPUCL1,
1164 PLL_CON3_PLL_CPUCL1,
1165 PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER,
1166 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
1167 CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER,
1168 CLK_CON_MUX_MUX_CLK_CPUCL1_CORE,
1169 CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
1170 CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
1171 CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK,
1172 CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK,
1173 CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
1174 CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP,
1175 };
1176
1177 /* List of parent clocks for Muxes in CMU_CPUCL1 */
1178 PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
1179 PNAME(mout_cpucl1_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl1_cluster" };
1180 PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl1_switch" };
1181 PNAME(mout_cpucl1_cluster_p) = { "oscclk", "mout_cpucl1_cluster_user",
1182 "mout_cpucl1_switch_user"};
1183 PNAME(mout_cpucl1_core_p) = { "oscclk", "mout_pll_cpucl1",
1184 "mout_cpucl1_switch_user"};
1185
1186 static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
1187 /* CMU_CPUCL1_PURECLKCOMP */
1188 PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
1189 PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
1190 };
1191
1192 static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
1193 MUX(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
1194 PLL_CON0_PLL_CPUCL1, 4, 1),
1195 MUX(CLK_MOUT_CPUCL1_CLUSTER_USER, "mout_cpucl1_cluster_user", mout_cpucl1_cluster_user_p,
1196 PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 4, 1),
1197 MUX(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user", mout_cpucl1_switch_user_p,
1198 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1),
1199 MUX(CLK_MOUT_CPUCL1_CLUSTER, "mout_cpucl1_cluster", mout_cpucl1_cluster_p,
1200 CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 0, 2),
1201 MUX(CLK_MOUT_CPUCL1_CORE, "mout_cpucl1_core", mout_cpucl1_core_p,
1202 CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0, 2),
1203 };
1204
1205 static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
1206 DIV(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk",
1207 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4),
1208 DIV(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
1209 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4),
1210 DIV(CLK_DOUT_CLUSTER1_MPCLK, "dout_cluster1_mpclk",
1211 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 0, 4),
1212 DIV(CLK_DOUT_CLUSTER1_PCLK, "dout_cluster1_pclk",
1213 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 0, 4),
1214 DIV(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
1215 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4),
1216 DIV(CLK_DOUT_CPUCL1_NOCP, "dout_cpucl1_nocp",
1217 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 0, 4),
1218 };
1219
1220 static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
1221 .pll_clks = cpucl1_pll_clks,
1222 .nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
1223 .mux_clks = cpucl1_mux_clks,
1224 .nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
1225 .div_clks = cpucl1_div_clks,
1226 .nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
1227 .nr_clk_ids = CLKS_NR_CPUCL1,
1228 .clk_regs = cpucl1_clk_regs,
1229 .nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
1230 .clk_name = "cpucl1",
1231 };
1232
exynosautov920_cmu_cpucl1_init(struct device_node * np)1233 static void __init exynosautov920_cmu_cpucl1_init(struct device_node *np)
1234 {
1235 exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
1236 }
1237
1238 /* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
1239 CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1",
1240 exynosautov920_cmu_cpucl1_init);
1241
1242 /* ---- CMU_CPUCL2 --------------------------------------------------------- */
1243
1244 /* Register Offset definitions for CMU_CPUCL2 (0x1EE00000) */
1245 #define PLL_LOCKTIME_PLL_CPUCL2 0x0000
1246 #define PLL_CON0_PLL_CPUCL2 0x0100
1247 #define PLL_CON1_PLL_CPUCL2 0x0104
1248 #define PLL_CON3_PLL_CPUCL2 0x010c
1249 #define PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER 0x0600
1250 #define PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER 0x0610
1251
1252 #define CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER 0x1000
1253 #define CLK_CON_MUX_MUX_CLK_CPUCL2_CORE 0x1004
1254
1255 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK 0x1800
1256 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK 0x1804
1257 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK 0x1808
1258 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK 0x180c
1259 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK 0x1810
1260 #define CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP 0x181c
1261
1262 static const unsigned long cpucl2_clk_regs[] __initconst = {
1263 PLL_LOCKTIME_PLL_CPUCL2,
1264 PLL_CON0_PLL_CPUCL2,
1265 PLL_CON1_PLL_CPUCL2,
1266 PLL_CON3_PLL_CPUCL2,
1267 PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER,
1268 PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER,
1269 CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER,
1270 CLK_CON_MUX_MUX_CLK_CPUCL2_CORE,
1271 CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK,
1272 CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK,
1273 CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK,
1274 CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK,
1275 CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK,
1276 CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP,
1277 };
1278
1279 /* List of parent clocks for Muxes in CMU_CPUCL2 */
1280 PNAME(mout_pll_cpucl2_p) = { "oscclk", "fout_cpucl2_pll" };
1281 PNAME(mout_cpucl2_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl2_cluster" };
1282 PNAME(mout_cpucl2_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl2_switch" };
1283 PNAME(mout_cpucl2_cluster_p) = { "oscclk", "mout_cpucl2_cluster_user",
1284 "mout_cpucl2_switch_user"};
1285 PNAME(mout_cpucl2_core_p) = { "oscclk", "mout_pll_cpucl2",
1286 "mout_cpucl2_switch_user"};
1287
1288 static const struct samsung_pll_clock cpucl2_pll_clks[] __initconst = {
1289 /* CMU_CPUCL2_PURECLKCOMP */
1290 PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk",
1291 PLL_LOCKTIME_PLL_CPUCL2, PLL_CON3_PLL_CPUCL2, cpu_pll_rates),
1292 };
1293
1294 static const struct samsung_mux_clock cpucl2_mux_clks[] __initconst = {
1295 MUX(CLK_MOUT_PLL_CPUCL2, "mout_pll_cpucl2", mout_pll_cpucl2_p,
1296 PLL_CON0_PLL_CPUCL2, 4, 1),
1297 MUX(CLK_MOUT_CPUCL2_CLUSTER_USER, "mout_cpucl2_cluster_user", mout_cpucl2_cluster_user_p,
1298 PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 4, 1),
1299 MUX(CLK_MOUT_CPUCL2_SWITCH_USER, "mout_cpucl2_switch_user", mout_cpucl2_switch_user_p,
1300 PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 4, 1),
1301 MUX(CLK_MOUT_CPUCL2_CLUSTER, "mout_cpucl2_cluster", mout_cpucl2_cluster_p,
1302 CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 0, 2),
1303 MUX(CLK_MOUT_CPUCL2_CORE, "mout_cpucl2_core", mout_cpucl2_core_p,
1304 CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0, 2),
1305 };
1306
1307 static const struct samsung_div_clock cpucl2_div_clks[] __initconst = {
1308 DIV(CLK_DOUT_CLUSTER2_ACLK, "dout_cluster2_aclk",
1309 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 0, 4),
1310 DIV(CLK_DOUT_CLUSTER2_ATCLK, "dout_cluster2_atclk",
1311 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 0, 4),
1312 DIV(CLK_DOUT_CLUSTER2_MPCLK, "dout_cluster2_mpclk",
1313 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 0, 4),
1314 DIV(CLK_DOUT_CLUSTER2_PCLK, "dout_cluster2_pclk",
1315 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 0, 4),
1316 DIV(CLK_DOUT_CLUSTER2_PERIPHCLK, "dout_cluster2_periphclk",
1317 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 0, 4),
1318 DIV(CLK_DOUT_CPUCL2_NOCP, "dout_cpucl2_nocp",
1319 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 0, 4),
1320 };
1321
1322 static const struct samsung_cmu_info cpucl2_cmu_info __initconst = {
1323 .pll_clks = cpucl2_pll_clks,
1324 .nr_pll_clks = ARRAY_SIZE(cpucl2_pll_clks),
1325 .mux_clks = cpucl2_mux_clks,
1326 .nr_mux_clks = ARRAY_SIZE(cpucl2_mux_clks),
1327 .div_clks = cpucl2_div_clks,
1328 .nr_div_clks = ARRAY_SIZE(cpucl2_div_clks),
1329 .nr_clk_ids = CLKS_NR_CPUCL2,
1330 .clk_regs = cpucl2_clk_regs,
1331 .nr_clk_regs = ARRAY_SIZE(cpucl2_clk_regs),
1332 .clk_name = "cpucl2",
1333 };
1334
exynosautov920_cmu_cpucl2_init(struct device_node * np)1335 static void __init exynosautov920_cmu_cpucl2_init(struct device_node *np)
1336 {
1337 exynos_arm64_register_cmu(NULL, np, &cpucl2_cmu_info);
1338 }
1339
1340 /* Register CMU_CPUCL2 early, as CPU clocks should be available ASAP */
1341 CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2",
1342 exynosautov920_cmu_cpucl2_init);
1343
1344 /* ---- CMU_PERIC0 --------------------------------------------------------- */
1345
1346 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
1347 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0600
1348 #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x0610
1349 #define CLK_CON_MUX_MUX_CLK_PERIC0_I3C 0x1000
1350 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1004
1351 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1008
1352 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x100c
1353 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x1010
1354 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1014
1355 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1018
1356 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI 0x101c
1357 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI 0x1020
1358 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI 0x1024
1359 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1028
1360 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
1361 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804
1362 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808
1363 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c
1364 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810
1365 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814
1366 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818
1367 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI 0x181c
1368 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI 0x1820
1369 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI 0x1824
1370 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828
1371
1372 static const unsigned long peric0_clk_regs[] __initconst = {
1373 PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
1374 PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER,
1375 CLK_CON_MUX_MUX_CLK_PERIC0_I3C,
1376 CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
1377 CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
1378 CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
1379 CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
1380 CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
1381 CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
1382 CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI,
1383 CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI,
1384 CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI,
1385 CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
1386 CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
1387 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1388 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1389 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1390 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1391 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1392 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1393 CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI,
1394 CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI,
1395 CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI,
1396 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
1397 };
1398
1399 /* List of parent clocks for Muxes in CMU_PERIC0 */
1400 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
1401 PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_clkcmu_peric0_noc" };
1402 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
1403
1404 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
1405 MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
1406 mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
1407 MUX(CLK_MOUT_PERIC0_NOC_USER, "mout_peric0_noc_user",
1408 mout_peric0_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 4, 1),
1409 /* USI00 ~ USI08 */
1410 MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
1411 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1412 MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
1413 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1414 MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
1415 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1416 MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
1417 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1418 MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
1419 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1420 MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
1421 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1422 MUX(CLK_MOUT_PERIC0_USI06_USI, "mout_peric0_usi06_usi",
1423 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 0, 1),
1424 MUX(CLK_MOUT_PERIC0_USI07_USI, "mout_peric0_usi07_usi",
1425 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 0, 1),
1426 MUX(CLK_MOUT_PERIC0_USI08_USI, "mout_peric0_usi08_usi",
1427 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 0, 1),
1428 /* USI_I2C */
1429 MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
1430 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1431 /* USI_I3C */
1432 MUX(CLK_MOUT_PERIC0_I3C, "mout_peric0_i3c",
1433 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 0, 1),
1434 };
1435
1436 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
1437 /* USI00 ~ USI08 */
1438 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
1439 "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
1440 0, 4),
1441 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
1442 "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
1443 0, 4),
1444 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
1445 "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
1446 0, 4),
1447 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
1448 "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
1449 0, 4),
1450 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
1451 "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
1452 0, 4),
1453 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
1454 "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
1455 0, 4),
1456 DIV(CLK_DOUT_PERIC0_USI06_USI, "dout_peric0_usi06_usi",
1457 "mout_peric0_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI,
1458 0, 4),
1459 DIV(CLK_DOUT_PERIC0_USI07_USI, "dout_peric0_usi07_usi",
1460 "mout_peric0_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI,
1461 0, 4),
1462 DIV(CLK_DOUT_PERIC0_USI08_USI, "dout_peric0_usi08_usi",
1463 "mout_peric0_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI,
1464 0, 4),
1465 /* USI_I2C */
1466 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
1467 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1468 /* USI_I3C */
1469 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c",
1470 "mout_peric0_i3c", CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
1471 };
1472
1473 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
1474 .mux_clks = peric0_mux_clks,
1475 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
1476 .div_clks = peric0_div_clks,
1477 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
1478 .nr_clk_ids = CLKS_NR_PERIC0,
1479 .clk_regs = peric0_clk_regs,
1480 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
1481 .clk_name = "noc",
1482 };
1483
1484 /* ---- CMU_PERIC1 --------------------------------------------------------- */
1485
1486 /* Register Offset definitions for CMU_PERIC1 (0x10C00000) */
1487 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600
1488 #define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610
1489 #define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000
1490 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004
1491 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008
1492 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c
1493 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010
1494 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014
1495 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018
1496 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c
1497 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020
1498 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024
1499 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028
1500 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
1501 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804
1502 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
1503 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
1504 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
1505 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
1506 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818
1507 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c
1508 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820
1509 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824
1510 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828
1511
1512 static const unsigned long peric1_clk_regs[] __initconst = {
1513 PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,
1514 PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,
1515 CLK_CON_MUX_MUX_CLK_PERIC1_I3C,
1516 CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,
1517 CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,
1518 CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,
1519 CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,
1520 CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,
1521 CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,
1522 CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,
1523 CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,
1524 CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,
1525 CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,
1526 CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
1527 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1528 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1529 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1530 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1531 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
1532 CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
1533 CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
1534 CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1535 CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1536 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,
1537 };
1538
1539 /* List of parent clocks for Muxes in CMU_PERIC1 */
1540 PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };
1541 PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };
1542 PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };
1543
1544 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
1545 MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",
1546 mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),
1547 MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",
1548 mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),
1549 /* USI09 ~ USI17 */
1550 MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",
1551 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1552 MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",
1553 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1554 MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",
1555 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1556 MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",
1557 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),
1558 MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",
1559 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),
1560 MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",
1561 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),
1562 MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",
1563 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),
1564 MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",
1565 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),
1566 MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",
1567 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),
1568 /* USI_I2C */
1569 MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",
1570 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1571 /* USI_I3C */
1572 MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",
1573 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),
1574 };
1575
1576 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
1577 /* USI09 ~ USI17 */
1578 DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",
1579 "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,
1580 0, 4),
1581 DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",
1582 "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
1583 0, 4),
1584 DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",
1585 "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
1586 0, 4),
1587 DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",
1588 "mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
1589 0, 4),
1590 DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",
1591 "mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
1592 0, 4),
1593 DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",
1594 "mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,
1595 0, 4),
1596 DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",
1597 "mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,
1598 0, 4),
1599 DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",
1600 "mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,
1601 0, 4),
1602 DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",
1603 "mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,
1604 0, 4),
1605 /* USI_I2C */
1606 DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",
1607 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1608 /* USI_I3C */
1609 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",
1610 "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
1611 };
1612
1613 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
1614 .mux_clks = peric1_mux_clks,
1615 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
1616 .div_clks = peric1_div_clks,
1617 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
1618 .nr_clk_ids = CLKS_NR_PERIC1,
1619 .clk_regs = peric1_clk_regs,
1620 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
1621 .clk_name = "noc",
1622 };
1623
1624 /* ---- CMU_MISC --------------------------------------------------------- */
1625
1626 /* Register Offset definitions for CMU_MISC (0x10020000) */
1627 #define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600
1628 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
1629 #define CLK_CON_DIV_CLKCMU_OTP 0x1800
1630 #define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804
1631 #define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808
1632
1633 static const unsigned long misc_clk_regs[] __initconst = {
1634 PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,
1635 CLK_CON_MUX_MUX_CLK_MISC_GIC,
1636 CLK_CON_DIV_CLKCMU_OTP,
1637 CLK_CON_DIV_DIV_CLK_MISC_NOCP,
1638 CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,
1639 };
1640
1641 /* List of parent clocks for Muxes in CMU_MISC */
1642 PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };
1643 PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };
1644
1645 static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
1646 MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",
1647 mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),
1648 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",
1649 mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),
1650 };
1651
1652 static const struct samsung_div_clock misc_div_clks[] __initconst = {
1653 DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",
1654 "mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,
1655 0, 3),
1656 };
1657
1658 static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {
1659 FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",
1660 "oscclk", 1, 10, 0),
1661 FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",
1662 "oscclk", 1, 2, 0),
1663 };
1664
1665 static const struct samsung_cmu_info misc_cmu_info __initconst = {
1666 .mux_clks = misc_mux_clks,
1667 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
1668 .div_clks = misc_div_clks,
1669 .nr_div_clks = ARRAY_SIZE(misc_div_clks),
1670 .fixed_factor_clks = misc_fixed_factor_clks,
1671 .nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks),
1672 .nr_clk_ids = CLKS_NR_MISC,
1673 .clk_regs = misc_clk_regs,
1674 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
1675 .clk_name = "noc",
1676 };
1677
1678 /* ---- CMU_HSI0 --------------------------------------------------------- */
1679
1680 /* Register Offset definitions for CMU_HSI0 (0x16000000) */
1681 #define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600
1682 #define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800
1683
1684 static const unsigned long hsi0_clk_regs[] __initconst = {
1685 PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,
1686 CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
1687 };
1688
1689 /* List of parent clocks for Muxes in CMU_HSI0 */
1690 PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };
1691
1692 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
1693 MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",
1694 mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),
1695 };
1696
1697 static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
1698 DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",
1699 "mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,
1700 0, 4),
1701 };
1702
1703 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
1704 .mux_clks = hsi0_mux_clks,
1705 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
1706 .div_clks = hsi0_div_clks,
1707 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
1708 .nr_clk_ids = CLKS_NR_HSI0,
1709 .clk_regs = hsi0_clk_regs,
1710 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
1711 .clk_name = "noc",
1712 };
1713
1714 /* ---- CMU_HSI1 --------------------------------------------------------- */
1715
1716 /* Register Offset definitions for CMU_HSI1 (0x16400000) */
1717 #define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600
1718 #define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610
1719 #define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620
1720 #define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000
1721
1722 static const unsigned long hsi1_clk_regs[] __initconst = {
1723 PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,
1724 PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,
1725 PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,
1726 CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,
1727 };
1728
1729 /* List of parent clocks for Muxes in CMU_HSI1 */
1730 PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
1731 PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
1732 PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_hsi1_usbdrd" };
1733 PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
1734
1735 static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
1736 MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",
1737 mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),
1738 MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",
1739 mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),
1740 MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",
1741 mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),
1742 MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",
1743 mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),
1744 };
1745
1746 static const struct samsung_cmu_info hsi1_cmu_info __initconst = {
1747 .mux_clks = hsi1_mux_clks,
1748 .nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks),
1749 .nr_clk_ids = CLKS_NR_HSI1,
1750 .clk_regs = hsi1_clk_regs,
1751 .nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs),
1752 .clk_name = "noc",
1753 };
1754
exynosautov920_cmu_probe(struct platform_device * pdev)1755 static int __init exynosautov920_cmu_probe(struct platform_device *pdev)
1756 {
1757 const struct samsung_cmu_info *info;
1758 struct device *dev = &pdev->dev;
1759
1760 info = of_device_get_match_data(dev);
1761 exynos_arm64_register_cmu(dev, dev->of_node, info);
1762
1763 return 0;
1764 }
1765
1766 static const struct of_device_id exynosautov920_cmu_of_match[] = {
1767 {
1768 .compatible = "samsung,exynosautov920-cmu-peric0",
1769 .data = &peric0_cmu_info,
1770 }, {
1771 .compatible = "samsung,exynosautov920-cmu-peric1",
1772 .data = &peric1_cmu_info,
1773 }, {
1774 .compatible = "samsung,exynosautov920-cmu-misc",
1775 .data = &misc_cmu_info,
1776 }, {
1777 .compatible = "samsung,exynosautov920-cmu-hsi0",
1778 .data = &hsi0_cmu_info,
1779 }, {
1780 .compatible = "samsung,exynosautov920-cmu-hsi1",
1781 .data = &hsi1_cmu_info,
1782 },
1783 { }
1784 };
1785
1786 static struct platform_driver exynosautov920_cmu_driver __refdata = {
1787 .driver = {
1788 .name = "exynosautov920-cmu",
1789 .of_match_table = exynosautov920_cmu_of_match,
1790 .suppress_bind_attrs = true,
1791 },
1792 .probe = exynosautov920_cmu_probe,
1793 };
1794
exynosautov920_cmu_init(void)1795 static int __init exynosautov920_cmu_init(void)
1796 {
1797 return platform_driver_register(&exynosautov920_cmu_driver);
1798 }
1799 core_initcall(exynosautov920_cmu_init);
1800