1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Renesas RZ/V2H(P) Clock Pulse Generator 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #ifndef __RENESAS_RZV2H_CPG_H__ 9 #define __RENESAS_RZV2H_CPG_H__ 10 11 #include <linux/bitfield.h> 12 #include <linux/types.h> 13 14 /** 15 * struct pll - Structure for PLL configuration 16 * 17 * @offset: STBY register offset 18 * @has_clkn: Flag to indicate if CLK1/2 are accessible or not 19 * @instance: PLL instance number 20 */ 21 struct pll { 22 unsigned int offset:9; 23 unsigned int has_clkn:1; 24 unsigned int instance:2; 25 const struct rzv2h_pll_limits *limits; 26 }; 27 28 #define PLL_PACK_LIMITS(_offset, _has_clkn, _instance, _limits) \ 29 ((struct pll){ \ 30 .offset = _offset, \ 31 .has_clkn = _has_clkn, \ 32 .instance = _instance, \ 33 .limits = _limits \ 34 }) 35 36 #define PLL_PACK(_offset, _has_clkn, _instance) \ 37 PLL_PACK_LIMITS(_offset, _has_clkn, _instance, NULL) 38 39 #define PLLCA55 PLL_PACK(0x60, 1, 0) 40 #define PLLGPU PLL_PACK(0x120, 1, 0) 41 42 /** 43 * struct ddiv - Structure for dynamic switching divider 44 * 45 * @offset: register offset 46 * @shift: position of the divider bit 47 * @width: width of the divider 48 * @monbit: monitor bit in CPG_CLKSTATUS0 register 49 * @no_rmw: flag to indicate if the register is read-modify-write 50 * (1: no RMW, 0: RMW) 51 */ 52 struct ddiv { 53 unsigned int offset:11; 54 unsigned int shift:4; 55 unsigned int width:4; 56 unsigned int monbit:5; 57 unsigned int no_rmw:1; 58 }; 59 60 /* 61 * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits, 62 * while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value 63 * `0x1f` to indicate that monitor bits are not supported for static divider 64 * clocks. 65 */ 66 #define CSDIV_NO_MON (0x1f) 67 68 #define DDIV_PACK(_offset, _shift, _width, _monbit) \ 69 ((struct ddiv){ \ 70 .offset = _offset, \ 71 .shift = _shift, \ 72 .width = _width, \ 73 .monbit = _monbit \ 74 }) 75 76 #define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \ 77 ((struct ddiv){ \ 78 .offset = (_offset), \ 79 .shift = (_shift), \ 80 .width = (_width), \ 81 .monbit = (_monbit), \ 82 .no_rmw = 1 \ 83 }) 84 85 /** 86 * struct smuxed - Structure for static muxed clocks 87 * 88 * @offset: register offset 89 * @shift: position of the divider field 90 * @width: width of the divider field 91 */ 92 struct smuxed { 93 unsigned int offset:11; 94 unsigned int shift:4; 95 unsigned int width:4; 96 }; 97 98 #define SMUX_PACK(_offset, _shift, _width) \ 99 ((struct smuxed){ \ 100 .offset = (_offset), \ 101 .shift = (_shift), \ 102 .width = (_width), \ 103 }) 104 105 /** 106 * struct fixed_mod_conf - Structure for fixed module configuration 107 * 108 * @mon_index: monitor index 109 * @mon_bit: monitor bit 110 */ 111 struct fixed_mod_conf { 112 u8 mon_index; 113 u8 mon_bit; 114 }; 115 116 #define FIXED_MOD_CONF_PACK(_index, _bit) \ 117 ((struct fixed_mod_conf){ \ 118 .mon_index = (_index), \ 119 .mon_bit = (_bit), \ 120 }) 121 122 #define CPG_SSEL0 (0x300) 123 #define CPG_SSEL1 (0x304) 124 #define CPG_SSEL3 (0x30C) 125 #define CPG_CDDIV0 (0x400) 126 #define CPG_CDDIV1 (0x404) 127 #define CPG_CDDIV2 (0x408) 128 #define CPG_CDDIV3 (0x40C) 129 #define CPG_CDDIV4 (0x410) 130 #define CPG_CSDIV0 (0x500) 131 #define CPG_CSDIV1 (0x504) 132 133 #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) 134 #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) 135 #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) 136 #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5) 137 #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6) 138 #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7) 139 #define CDDIV2_DIVCTL3 DDIV_PACK(CPG_CDDIV2, 12, 3, 11) 140 #define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13) 141 #define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14) 142 #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15) 143 #define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16) 144 #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) 145 #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) 146 147 #define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) 148 #define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) 149 #define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON) 150 #define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON) 151 #define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON) 152 #define CSDIV1_DIVCTL3 DDIV_PACK(CPG_CSDIV1, 12, 4, CSDIV_NO_MON) 153 154 #define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) 155 #define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) 156 #define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1) 157 #define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1) 158 #define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1) 159 #define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1) 160 #define SSEL3_SELCTL0 SMUX_PACK(CPG_SSEL3, 0, 1) 161 #define SSEL3_SELCTL1 SMUX_PACK(CPG_SSEL3, 4, 1) 162 163 #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) 164 #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) 165 #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) | \ 166 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask))) 167 #define BUS_MSTOP_NONE GENMASK(31, 0) 168 169 #define FIXED_MOD_CONF_XSPI FIXED_MOD_CONF_PACK(5, 1) 170 171 /** 172 * Definitions of CPG Core Clocks 173 * 174 * These include: 175 * - Clock outputs exported to DT 176 * - External input clocks 177 * - Internal CPG clocks 178 */ 179 struct cpg_core_clk { 180 const char *name; 181 unsigned int id; 182 unsigned int parent; 183 unsigned int div; 184 unsigned int mult; 185 unsigned int type; 186 union { 187 unsigned int conf; 188 struct ddiv ddiv; 189 struct pll pll; 190 struct smuxed smux; 191 struct fixed_mod_conf fixed_mod; 192 } cfg; 193 const struct clk_div_table *dtable; 194 const char * const *parent_names; 195 unsigned int num_parents; 196 u8 mux_flags; 197 u32 flag; 198 }; 199 200 enum clk_types { 201 /* Generic */ 202 CLK_TYPE_IN, /* External Clock Input */ 203 CLK_TYPE_FF, /* Fixed Factor Clock */ 204 CLK_TYPE_FF_MOD_STATUS, /* Fixed Factor Clock which can report the status of module clock */ 205 CLK_TYPE_PLL, 206 CLK_TYPE_DDIV, /* Dynamic Switching Divider */ 207 CLK_TYPE_SMUX, /* Static Mux */ 208 CLK_TYPE_PLLDSI, /* PLLDSI */ 209 CLK_TYPE_PLLDSI_DIV, /* PLLDSI divider */ 210 CLK_TYPE_PLLDSI_SMUX, /* PLLDSI Static Mux */ 211 }; 212 213 #define DEF_TYPE(_name, _id, _type...) \ 214 { .name = _name, .id = _id, .type = _type } 215 #define DEF_BASE(_name, _id, _type, _parent...) \ 216 DEF_TYPE(_name, _id, _type, .parent = _parent) 217 #define DEF_PLL(_name, _id, _parent, _pll_packed) \ 218 DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed) 219 #define DEF_INPUT(_name, _id) \ 220 DEF_TYPE(_name, _id, CLK_TYPE_IN) 221 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 222 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 223 #define DEF_FIXED_MOD_STATUS(_name, _id, _parent, _mult, _div, _gate) \ 224 DEF_BASE(_name, _id, CLK_TYPE_FF_MOD_STATUS, _parent, .div = _div, \ 225 .mult = _mult, .cfg.fixed_mod = _gate) 226 #define DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ 227 DEF_TYPE(_name, _id, CLK_TYPE_DDIV, \ 228 .cfg.ddiv = _ddiv_packed, \ 229 .parent = _parent, \ 230 .dtable = _dtable, \ 231 .flag = CLK_DIVIDER_HIWORD_MASK) 232 #define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ 233 DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) 234 #define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \ 235 DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \ 236 .cfg.smux = _smux_packed, \ 237 .parent_names = _parent_names, \ 238 .num_parents = ARRAY_SIZE(_parent_names), \ 239 .flag = CLK_SET_RATE_PARENT, \ 240 .mux_flags = CLK_MUX_HIWORD_MASK) 241 #define DEF_PLLDSI(_name, _id, _parent, _pll_packed) \ 242 DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI, .parent = _parent, .cfg.pll = _pll_packed) 243 #define DEF_PLLDSI_DIV(_name, _id, _parent, _ddiv_packed, _dtable) \ 244 DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_DIV, \ 245 .cfg.ddiv = _ddiv_packed, \ 246 .dtable = _dtable, \ 247 .parent = _parent, \ 248 .flag = CLK_SET_RATE_PARENT) 249 #define DEF_PLLDSI_SMUX(_name, _id, _smux_packed, _parent_names) \ 250 DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_SMUX, \ 251 .cfg.smux = _smux_packed, \ 252 .parent_names = _parent_names, \ 253 .num_parents = ARRAY_SIZE(_parent_names), \ 254 .flag = CLK_SET_RATE_PARENT, \ 255 .mux_flags = CLK_MUX_HIWORD_MASK) 256 257 /** 258 * struct rzv2h_mod_clk - Module Clocks definitions 259 * 260 * @name: handle between common and hardware-specific interfaces 261 * @mstop_data: packed data mstop register offset and mask 262 * @parent: id of parent clock 263 * @critical: flag to indicate the clock is critical 264 * @no_pm: flag to indicate PM is not supported 265 * @on_index: control register index 266 * @on_bit: ON bit 267 * @mon_index: monitor register index 268 * @mon_bit: monitor bit 269 * @ext_clk_mux_index: mux index for external clock source, or -1 if internal 270 */ 271 struct rzv2h_mod_clk { 272 const char *name; 273 u32 mstop_data; 274 u16 parent; 275 bool critical; 276 bool no_pm; 277 u8 on_index; 278 u8 on_bit; 279 s8 mon_index; 280 u8 mon_bit; 281 s8 ext_clk_mux_index; 282 }; 283 284 #define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \ 285 _onbit, _monindex, _monbit, _ext_clk_mux_index) \ 286 { \ 287 .name = (_name), \ 288 .mstop_data = (_mstop), \ 289 .parent = (_parent), \ 290 .critical = (_critical), \ 291 .no_pm = (_no_pm), \ 292 .on_index = (_onindex), \ 293 .on_bit = (_onbit), \ 294 .mon_index = (_monindex), \ 295 .mon_bit = (_monbit), \ 296 .ext_clk_mux_index = (_ext_clk_mux_index), \ 297 } 298 299 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 300 DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, -1) 301 302 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 303 DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit, -1) 304 305 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ 306 DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit, -1) 307 308 #define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop, \ 309 _ext_clk_mux_index) \ 310 DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit, \ 311 _ext_clk_mux_index) 312 313 /** 314 * struct rzv2h_reset - Reset definitions 315 * 316 * @reset_index: reset register index 317 * @reset_bit: reset bit 318 * @mon_index: monitor register index 319 * @mon_bit: monitor bit 320 */ 321 struct rzv2h_reset { 322 u8 reset_index; 323 u8 reset_bit; 324 u8 mon_index; 325 u8 mon_bit; 326 }; 327 328 #define DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) \ 329 { \ 330 .reset_index = (_resindex), \ 331 .reset_bit = (_resbit), \ 332 .mon_index = (_monindex), \ 333 .mon_bit = (_monbit), \ 334 } 335 336 #define DEF_RST(_resindex, _resbit, _monindex, _monbit) \ 337 DEF_RST_BASE(_resindex, _resbit, _monindex, _monbit) 338 339 /** 340 * struct rzv2h_cpg_info - SoC-specific CPG Description 341 * 342 * @core_clks: Array of Core Clock definitions 343 * @num_core_clks: Number of entries in core_clks[] 344 * @last_dt_core_clk: ID of the last Core Clock exported to DT 345 * @num_total_core_clks: Total number of Core Clocks (exported + internal) 346 * 347 * @mod_clks: Array of Module Clock definitions 348 * @num_mod_clks: Number of entries in mod_clks[] 349 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware 350 * 351 * @resets: Array of Module Reset definitions 352 * @num_resets: Number of entries in resets[] 353 * 354 * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the 355 * number of CPG_BUS_m_MSTOP registers multiplied by 16. 356 */ 357 struct rzv2h_cpg_info { 358 /* Core Clocks */ 359 const struct cpg_core_clk *core_clks; 360 unsigned int num_core_clks; 361 unsigned int last_dt_core_clk; 362 unsigned int num_total_core_clks; 363 364 /* Module Clocks */ 365 const struct rzv2h_mod_clk *mod_clks; 366 unsigned int num_mod_clks; 367 unsigned int num_hw_mod_clks; 368 369 /* Resets */ 370 const struct rzv2h_reset *resets; 371 unsigned int num_resets; 372 373 unsigned int num_mstop_bits; 374 }; 375 376 extern const struct rzv2h_cpg_info r9a09g047_cpg_info; 377 extern const struct rzv2h_cpg_info r9a09g056_cpg_info; 378 extern const struct rzv2h_cpg_info r9a09g057_cpg_info; 379 380 #endif /* __RENESAS_RZV2H_CPG_H__ */ 381