1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2021 Intel Corporation
4 */
5
6 #include "xe_pci.h"
7
8 #include <kunit/static_stub.h>
9 #include <linux/device/driver.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/pm_runtime.h>
13
14 #include <drm/drm_color_mgmt.h>
15 #include <drm/drm_drv.h>
16 #include <drm/intel/pciids.h>
17
18 #include "display/xe_display.h"
19 #include "regs/xe_gt_regs.h"
20 #include "regs/xe_regs.h"
21 #include "xe_configfs.h"
22 #include "xe_device.h"
23 #include "xe_drv.h"
24 #include "xe_gt.h"
25 #include "xe_gt_sriov_vf.h"
26 #include "xe_guc.h"
27 #include "xe_mmio.h"
28 #include "xe_module.h"
29 #include "xe_pci_rebar.h"
30 #include "xe_pci_sriov.h"
31 #include "xe_pci_types.h"
32 #include "xe_pm.h"
33 #include "xe_printk.h"
34 #include "xe_sriov.h"
35 #include "xe_step.h"
36 #include "xe_survivability_mode.h"
37 #include "xe_tile.h"
38
39 enum toggle_d3cold {
40 D3COLD_DISABLE,
41 D3COLD_ENABLE,
42 };
43
44 __diag_push();
45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
46
47 #define PLATFORM(x) \
48 .platform = XE_##x, \
49 .platform_name = #x
50
51 #define NOP(x) x
52
53 static const struct xe_graphics_desc graphics_xelp = {
54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
55 .num_geometry_xecore_fuse_regs = 1,
56 };
57
58 #define XE_HP_FEATURES \
59 .has_range_tlb_inval = true
60
61 static const struct xe_graphics_desc graphics_xehpg = {
62 .hw_engine_mask =
63 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
64 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
65 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
66 .num_geometry_xecore_fuse_regs = 1,
67 .num_compute_xecore_fuse_regs = 1,
68
69 XE_HP_FEATURES,
70 };
71
72 static const struct xe_graphics_desc graphics_xehpc = {
73 .hw_engine_mask =
74 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) |
75 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) |
76 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) |
77 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) |
78 BIT(XE_HW_ENGINE_BCS8) |
79 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
80 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
81
82 XE_HP_FEATURES,
83
84 .has_access_counter = 1,
85 .has_asid = 1,
86 .has_atomic_enable_pte_bit = 1,
87 .has_usm = 1,
88 .num_compute_xecore_fuse_regs = 2,
89 };
90
91 static const struct xe_graphics_desc graphics_xelpg = {
92 .hw_engine_mask =
93 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
94 BIT(XE_HW_ENGINE_CCS0),
95 .num_geometry_xecore_fuse_regs = 1,
96 .num_compute_xecore_fuse_regs = 1,
97
98 XE_HP_FEATURES,
99 };
100
101 #define XE2_GFX_FEATURES \
102 .has_access_counter = 1, \
103 .has_asid = 1, \
104 .has_atomic_enable_pte_bit = 1, \
105 .has_range_tlb_inval = 1, \
106 .has_usm = 1, \
107 .has_64bit_timestamp = 1, \
108 .hw_engine_mask = \
109 BIT(XE_HW_ENGINE_RCS0) | \
110 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
111 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
112
113 static const struct xe_graphics_desc graphics_xe2 = {
114 XE2_GFX_FEATURES,
115 .num_geometry_xecore_fuse_regs = 3,
116 .num_compute_xecore_fuse_regs = 3,
117 };
118
119 static const struct xe_graphics_desc graphics_xe3p_lpg = {
120 XE2_GFX_FEATURES,
121 .has_indirect_ring_state = 1,
122 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE),
123 .num_geometry_xecore_fuse_regs = 3,
124 .num_compute_xecore_fuse_regs = 3,
125 };
126
127 static const struct xe_graphics_desc graphics_xe3p_xpc = {
128 XE2_GFX_FEATURES,
129 .has_access_counter = 0,
130 .has_indirect_ring_state = 1,
131 .hw_engine_mask =
132 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
133 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
134 .multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) |
135 BIT(XE_ENGINE_CLASS_COMPUTE),
136 .num_geometry_xecore_fuse_regs = 4,
137 .num_compute_xecore_fuse_regs = 4,
138 };
139
140 static const struct xe_media_desc media_xem = {
141 .hw_engine_mask =
142 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
143 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0),
144 };
145
146 static const struct xe_media_desc media_xelpmp = {
147 .hw_engine_mask =
148 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
149 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
150 BIT(XE_HW_ENGINE_GSCCS0)
151 };
152
153 /* Pre-GMDID Graphics IPs */
154 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp };
155 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp };
156 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg };
157 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc };
158
159 /* GMDID-based Graphics IPs */
160 static const struct xe_ip graphics_ips[] = {
161 { 1270, "Xe_LPG", &graphics_xelpg },
162 { 1271, "Xe_LPG", &graphics_xelpg },
163 { 1274, "Xe_LPG+", &graphics_xelpg },
164 { 2001, "Xe2_HPG", &graphics_xe2 },
165 { 2002, "Xe2_HPG", &graphics_xe2 },
166 { 2004, "Xe2_LPG", &graphics_xe2 },
167 { 3000, "Xe3_LPG", &graphics_xe2 },
168 { 3001, "Xe3_LPG", &graphics_xe2 },
169 { 3003, "Xe3_LPG", &graphics_xe2 },
170 { 3004, "Xe3_LPG", &graphics_xe2 },
171 { 3005, "Xe3_LPG", &graphics_xe2 },
172 { 3510, "Xe3p_LPG", &graphics_xe3p_lpg },
173 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
174 };
175
176 /* Pre-GMDID Media IPs */
177 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem };
178 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem };
179
180 /* GMDID-based Media IPs */
181 static const struct xe_ip media_ips[] = {
182 { 1300, "Xe_LPM+", &media_xelpmp },
183 { 1301, "Xe2_HPM", &media_xelpmp },
184 { 2000, "Xe2_LPM", &media_xelpmp },
185 { 3000, "Xe3_LPM", &media_xelpmp },
186 { 3002, "Xe3_LPM", &media_xelpmp },
187 { 3500, "Xe3p_LPM", &media_xelpmp },
188 { 3503, "Xe3p_HPM", &media_xelpmp },
189 };
190
191 #define MULTI_LRC_MASK \
192 .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \
193 BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE)
194
195 static const struct xe_device_desc tgl_desc = {
196 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
197 .pre_gmdid_media_ip = &media_ip_xem,
198 PLATFORM(TIGERLAKE),
199 .dma_mask_size = 39,
200 .has_cached_pt = true,
201 .has_display = true,
202 .has_llc = true,
203 .has_sriov = true,
204 .max_gt_per_tile = 1,
205 MULTI_LRC_MASK,
206 .require_force_probe = true,
207 .va_bits = 48,
208 .vm_max_level = 3,
209 };
210
211 static const struct xe_device_desc rkl_desc = {
212 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
213 .pre_gmdid_media_ip = &media_ip_xem,
214 PLATFORM(ROCKETLAKE),
215 .dma_mask_size = 39,
216 .has_cached_pt = true,
217 .has_display = true,
218 .has_llc = true,
219 .max_gt_per_tile = 1,
220 MULTI_LRC_MASK,
221 .require_force_probe = true,
222 .va_bits = 48,
223 .vm_max_level = 3,
224 };
225
226 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
227
228 static const struct xe_device_desc adl_s_desc = {
229 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
230 .pre_gmdid_media_ip = &media_ip_xem,
231 PLATFORM(ALDERLAKE_S),
232 .dma_mask_size = 39,
233 .has_cached_pt = true,
234 .has_display = true,
235 .has_llc = true,
236 .has_sriov = true,
237 .max_gt_per_tile = 1,
238 MULTI_LRC_MASK,
239 .require_force_probe = true,
240 .subplatforms = (const struct xe_subplatform_desc[]) {
241 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
242 {},
243 },
244 .va_bits = 48,
245 .vm_max_level = 3,
246 };
247
248 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
249
250 static const struct xe_device_desc adl_p_desc = {
251 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
252 .pre_gmdid_media_ip = &media_ip_xem,
253 PLATFORM(ALDERLAKE_P),
254 .dma_mask_size = 39,
255 .has_cached_pt = true,
256 .has_display = true,
257 .has_llc = true,
258 .has_sriov = true,
259 .max_gt_per_tile = 1,
260 MULTI_LRC_MASK,
261 .require_force_probe = true,
262 .subplatforms = (const struct xe_subplatform_desc[]) {
263 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
264 {},
265 },
266 .va_bits = 48,
267 .vm_max_level = 3,
268 };
269
270 static const struct xe_device_desc adl_n_desc = {
271 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
272 .pre_gmdid_media_ip = &media_ip_xem,
273 PLATFORM(ALDERLAKE_N),
274 .dma_mask_size = 39,
275 .has_cached_pt = true,
276 .has_display = true,
277 .has_llc = true,
278 .has_sriov = true,
279 .max_gt_per_tile = 1,
280 MULTI_LRC_MASK,
281 .require_force_probe = true,
282 .va_bits = 48,
283 .vm_max_level = 3,
284 };
285
286 #define DGFX_FEATURES \
287 .is_dgfx = 1
288
289 static const struct xe_device_desc dg1_desc = {
290 .pre_gmdid_graphics_ip = &graphics_ip_xelpp,
291 .pre_gmdid_media_ip = &media_ip_xem,
292 DGFX_FEATURES,
293 PLATFORM(DG1),
294 .dma_mask_size = 39,
295 .has_display = true,
296 .has_gsc_nvm = 1,
297 .has_heci_gscfi = 1,
298 .max_gt_per_tile = 1,
299 MULTI_LRC_MASK,
300 .require_force_probe = true,
301 .va_bits = 48,
302 .vm_max_level = 3,
303 };
304
305 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
306 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 };
307 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
308
309 #define DG2_FEATURES \
310 DGFX_FEATURES, \
311 PLATFORM(DG2), \
312 .has_flat_ccs = 1, \
313 .has_gsc_nvm = 1, \
314 .has_heci_gscfi = 1, \
315 .subplatforms = (const struct xe_subplatform_desc[]) { \
316 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \
317 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
318 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
319 { } \
320 }, \
321 .va_bits = 48, \
322 .vm_max_level = 3, \
323 .vram_flags = XE_VRAM_FLAGS_NEED64K
324
325 static const struct xe_device_desc ats_m_desc = {
326 .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
327 .pre_gmdid_media_ip = &media_ip_xehpm,
328 .dma_mask_size = 46,
329 .max_gt_per_tile = 1,
330 MULTI_LRC_MASK,
331 .require_force_probe = true,
332
333 DG2_FEATURES,
334 .has_display = false,
335 .has_sriov = true,
336 };
337
338 static const struct xe_device_desc dg2_desc = {
339 .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
340 .pre_gmdid_media_ip = &media_ip_xehpm,
341 .dma_mask_size = 46,
342 .max_gt_per_tile = 1,
343 MULTI_LRC_MASK,
344 .require_force_probe = true,
345
346 DG2_FEATURES,
347 .has_display = true,
348 .has_fan_control = true,
349 .has_mbx_power_limits = false,
350 };
351
352 static const __maybe_unused struct xe_device_desc pvc_desc = {
353 .pre_gmdid_graphics_ip = &graphics_ip_xehpc,
354 DGFX_FEATURES,
355 PLATFORM(PVC),
356 .dma_mask_size = 52,
357 .has_display = false,
358 .has_gsc_nvm = 1,
359 .has_heci_gscfi = 1,
360 .max_gt_per_tile = 1,
361 .max_remote_tiles = 1,
362 MULTI_LRC_MASK,
363 .require_force_probe = true,
364 .va_bits = 57,
365 .vm_max_level = 4,
366 .vram_flags = XE_VRAM_FLAGS_NEED64K,
367 .has_mbx_power_limits = false,
368 };
369
370 static const struct xe_device_desc mtl_desc = {
371 /* .graphics and .media determined via GMD_ID */
372 .require_force_probe = true,
373 PLATFORM(METEORLAKE),
374 .dma_mask_size = 46,
375 .has_display = true,
376 .has_pxp = true,
377 .max_gt_per_tile = 2,
378 MULTI_LRC_MASK,
379 .va_bits = 48,
380 .vm_max_level = 3,
381 };
382
383 static const struct xe_device_desc lnl_desc = {
384 PLATFORM(LUNARLAKE),
385 .dma_mask_size = 46,
386 .has_display = true,
387 .has_flat_ccs = 1,
388 .has_pxp = true,
389 .max_gt_per_tile = 2,
390 MULTI_LRC_MASK,
391 .needs_scratch = true,
392 .va_bits = 48,
393 .vm_max_level = 4,
394 };
395
396 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 };
397
398 static const struct xe_device_desc bmg_desc = {
399 DGFX_FEATURES,
400 PLATFORM(BATTLEMAGE),
401 .dma_mask_size = 46,
402 .has_display = true,
403 .has_fan_control = true,
404 .has_flat_ccs = 1,
405 .has_mbx_power_limits = true,
406 .has_mbx_thermal_info = true,
407 .has_gsc_nvm = 1,
408 .has_heci_cscfi = 1,
409 .has_i2c = true,
410 .has_late_bind = true,
411 .has_pre_prod_wa = 1,
412 .has_soc_remapper_telem = true,
413 .has_sriov = true,
414 .max_gt_per_tile = 2,
415 MULTI_LRC_MASK,
416 .needs_scratch = true,
417 .subplatforms = (const struct xe_subplatform_desc[]) {
418 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
419 { }
420 },
421 .va_bits = 48,
422 .vm_max_level = 4,
423 };
424
425 static const struct xe_device_desc ptl_desc = {
426 PLATFORM(PANTHERLAKE),
427 .dma_mask_size = 46,
428 .has_display = true,
429 .has_flat_ccs = 1,
430 .has_sriov = true,
431 .has_pre_prod_wa = 1,
432 .has_pxp = true,
433 .max_gt_per_tile = 2,
434 MULTI_LRC_MASK,
435 .needs_scratch = true,
436 .needs_shared_vf_gt_wq = true,
437 .va_bits = 48,
438 .vm_max_level = 4,
439 };
440
441 static const struct xe_device_desc nvls_desc = {
442 PLATFORM(NOVALAKE_S),
443 .dma_mask_size = 46,
444 .has_display = true,
445 .has_flat_ccs = 1,
446 .has_pre_prod_wa = 1,
447 .max_gt_per_tile = 2,
448 MULTI_LRC_MASK,
449 .require_force_probe = true,
450 .va_bits = 48,
451 .vm_max_level = 4,
452 };
453
454 static const struct xe_device_desc cri_desc = {
455 DGFX_FEATURES,
456 PLATFORM(CRESCENTISLAND),
457 .dma_mask_size = 52,
458 .has_display = false,
459 .has_flat_ccs = false,
460 .has_gsc_nvm = 1,
461 .has_i2c = true,
462 .has_mbx_power_limits = true,
463 .has_mbx_thermal_info = true,
464 .has_mert = true,
465 .has_pre_prod_wa = 1,
466 .has_soc_remapper_sysctrl = true,
467 .has_soc_remapper_telem = true,
468 .has_sriov = true,
469 .max_gt_per_tile = 2,
470 MULTI_LRC_MASK,
471 .require_force_probe = true,
472 .va_bits = 57,
473 .vm_max_level = 4,
474 };
475
476 static const struct xe_device_desc nvlp_desc = {
477 PLATFORM(NOVALAKE_P),
478 .dma_mask_size = 46,
479 .has_cached_pt = true,
480 .has_display = true,
481 .has_flat_ccs = 1,
482 .has_page_reclaim_hw_assist = true,
483 .has_pre_prod_wa = true,
484 .max_gt_per_tile = 2,
485 MULTI_LRC_MASK,
486 .require_force_probe = true,
487 .va_bits = 48,
488 .vm_max_level = 4,
489 };
490
491 #undef PLATFORM
492 __diag_pop();
493
494 /*
495 * Make sure any device matches here are from most specific to most
496 * general. For example, since the Quanta match is based on the subsystem
497 * and subvendor IDs, we need it to come before the more general IVB
498 * PCI ID matches, otherwise we'll use the wrong info struct above.
499 */
500 static const struct pci_device_id pciidlist[] = {
501 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
502 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
503 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
504 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
505 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
506 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
507 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
508 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
509 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
510 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
511 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
512 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
513 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
514 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
515 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
516 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
517 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
518 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
519 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
520 INTEL_NVLP_IDS(INTEL_VGA_DEVICE, &nvlp_desc),
521 { }
522 };
523 MODULE_DEVICE_TABLE(pci, pciidlist);
524
525 /* is device_id present in comma separated list of ids */
device_id_in_list(u16 device_id,const char * devices,bool negative)526 static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
527 {
528 char *s, *p, *tok;
529 bool ret;
530
531 if (!devices || !*devices)
532 return false;
533
534 /* match everything */
535 if (negative && strcmp(devices, "!*") == 0)
536 return true;
537 if (!negative && strcmp(devices, "*") == 0)
538 return true;
539
540 s = kstrdup(devices, GFP_KERNEL);
541 if (!s)
542 return false;
543
544 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
545 u16 val;
546
547 if (negative && tok[0] == '!')
548 tok++;
549 else if ((negative && tok[0] != '!') ||
550 (!negative && tok[0] == '!'))
551 continue;
552
553 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
554 ret = true;
555 break;
556 }
557 }
558
559 kfree(s);
560
561 return ret;
562 }
563
id_forced(u16 device_id)564 static bool id_forced(u16 device_id)
565 {
566 return device_id_in_list(device_id, xe_modparam.force_probe, false);
567 }
568
id_blocked(u16 device_id)569 static bool id_blocked(u16 device_id)
570 {
571 return device_id_in_list(device_id, xe_modparam.force_probe, true);
572 }
573
574 static const struct xe_subplatform_desc *
find_subplatform(const struct xe_device * xe,const struct xe_device_desc * desc)575 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
576 {
577 const struct xe_subplatform_desc *sp;
578 const u16 *id;
579
580 for (sp = desc->subplatforms; sp && sp->subplatform; sp++)
581 for (id = sp->pciidlist; *id; id++)
582 if (*id == xe->info.devid)
583 return sp;
584
585 return NULL;
586 }
587
588 enum xe_gmdid_type {
589 GMDID_GRAPHICS,
590 GMDID_MEDIA
591 };
592
read_gmdid(struct xe_device * xe,enum xe_gmdid_type type,u32 * ver,u32 * revid)593 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
594 {
595 struct xe_mmio *mmio = xe_root_tile_mmio(xe);
596 struct xe_reg gmdid_reg = GMD_ID;
597 u32 val;
598
599 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
600
601 if (IS_SRIOV_VF(xe)) {
602 /*
603 * To get the value of the GMDID register, VFs must obtain it
604 * from the GuC using MMIO communication.
605 *
606 * Note that at this point the GTs are not initialized and only
607 * tile-level access to MMIO registers is possible. To use our
608 * existing GuC communication functions we must create a dummy
609 * GT structure and perform at least basic xe_gt and xe_guc
610 * initialization.
611 */
612 struct xe_gt *gt __free(kfree) = NULL;
613 int err;
614
615 /* Don't try to read media ver if media GT is not allowed */
616 if (type == GMDID_MEDIA && !xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) {
617 *ver = *revid = 0;
618 return 0;
619 }
620
621 gt = kzalloc(sizeof(*gt), GFP_KERNEL);
622 if (!gt)
623 return -ENOMEM;
624
625 gt->tile = &xe->tiles[0];
626 if (type == GMDID_MEDIA) {
627 gt->info.id = 1;
628 gt->info.type = XE_GT_TYPE_MEDIA;
629 } else {
630 gt->info.id = 0;
631 gt->info.type = XE_GT_TYPE_MAIN;
632 }
633
634 xe_gt_mmio_init(gt);
635 xe_guc_comm_init_early(>->uc.guc);
636
637 err = xe_gt_sriov_vf_bootstrap(gt);
638 if (err)
639 return err;
640
641 val = xe_gt_sriov_vf_gmdid(gt);
642 } else {
643 /*
644 * GMD_ID is a GT register, but at this point in the driver
645 * init we haven't fully initialized the GT yet so we need to
646 * read the register with the tile's MMIO accessor. That means
647 * we need to apply the GSI offset manually since it won't get
648 * automatically added as it would if we were using a GT mmio
649 * accessor.
650 */
651 if (type == GMDID_MEDIA)
652 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;
653
654 val = xe_mmio_read32(mmio, gmdid_reg);
655 }
656
657 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
658 *revid = REG_FIELD_GET(GMD_ID_REVID, val);
659
660 return 0;
661 }
662
find_graphics_ip(unsigned int verx100)663 static const struct xe_ip *find_graphics_ip(unsigned int verx100)
664 {
665 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100);
666
667 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++)
668 if (graphics_ips[i].verx100 == verx100)
669 return &graphics_ips[i];
670 return NULL;
671 }
672
find_media_ip(unsigned int verx100)673 static const struct xe_ip *find_media_ip(unsigned int verx100)
674 {
675 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100);
676
677 for (int i = 0; i < ARRAY_SIZE(media_ips); i++)
678 if (media_ips[i].verx100 == verx100)
679 return &media_ips[i];
680 return NULL;
681 }
682
683 /*
684 * Read IP version from hardware and select graphics/media IP descriptors
685 * based on the result.
686 */
handle_gmdid(struct xe_device * xe,const struct xe_ip ** graphics_ip,const struct xe_ip ** media_ip,u32 * graphics_revid,u32 * media_revid)687 static int handle_gmdid(struct xe_device *xe,
688 const struct xe_ip **graphics_ip,
689 const struct xe_ip **media_ip,
690 u32 *graphics_revid,
691 u32 *media_revid)
692 {
693 u32 ver;
694 int ret;
695
696 *graphics_ip = NULL;
697 *media_ip = NULL;
698
699 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
700 if (ret)
701 return ret;
702
703 *graphics_ip = find_graphics_ip(ver);
704 if (!*graphics_ip) {
705 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n",
706 ver / 100, ver % 100);
707 }
708
709 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
710 if (ret)
711 return ret;
712
713 /* Media may legitimately be fused off / not present */
714 if (ver == 0)
715 return 0;
716
717 *media_ip = find_media_ip(ver);
718 if (!*media_ip) {
719 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n",
720 ver / 100, ver % 100);
721 }
722
723 return 0;
724 }
725
726 /*
727 * Initialize device info content that only depends on static driver_data
728 * passed to the driver at probe time from PCI ID table.
729 */
xe_info_init_early(struct xe_device * xe,const struct xe_device_desc * desc,const struct xe_subplatform_desc * subplatform_desc)730 static int xe_info_init_early(struct xe_device *xe,
731 const struct xe_device_desc *desc,
732 const struct xe_subplatform_desc *subplatform_desc)
733 {
734 int err;
735
736 xe->info.platform_name = desc->platform_name;
737 xe->info.platform = desc->platform;
738 xe->info.subplatform = subplatform_desc ?
739 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
740
741 xe->info.dma_mask_size = desc->dma_mask_size;
742 xe->info.va_bits = desc->va_bits;
743 xe->info.vm_max_level = desc->vm_max_level;
744 xe->info.vram_flags = desc->vram_flags;
745
746 xe->info.is_dgfx = desc->is_dgfx;
747 xe->info.has_cached_pt = desc->has_cached_pt;
748 xe->info.has_fan_control = desc->has_fan_control;
749 /* runtime fusing may force flat_ccs to disabled later */
750 xe->info.has_flat_ccs = desc->has_flat_ccs;
751 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
752 xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
753 xe->info.has_gsc_nvm = desc->has_gsc_nvm;
754 xe->info.has_heci_gscfi = desc->has_heci_gscfi;
755 xe->info.has_heci_cscfi = desc->has_heci_cscfi;
756 xe->info.has_i2c = desc->has_i2c;
757 xe->info.has_late_bind = desc->has_late_bind;
758 xe->info.has_llc = desc->has_llc;
759 xe->info.has_mert = desc->has_mert;
760 xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
761 xe->info.has_pre_prod_wa = desc->has_pre_prod_wa;
762 xe->info.has_pxp = desc->has_pxp;
763 xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl;
764 xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
765 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
766 desc->has_sriov;
767 xe->info.skip_guc_pc = desc->skip_guc_pc;
768 xe->info.skip_mtcfg = desc->skip_mtcfg;
769 xe->info.skip_pcode = desc->skip_pcode;
770 xe->info.needs_scratch = desc->needs_scratch;
771 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
772 xe->info.multi_lrc_mask = desc->multi_lrc_mask;
773
774 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
775 xe_modparam.probe_display &&
776 desc->has_display;
777
778 xe_assert(xe, desc->max_gt_per_tile > 0);
779 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE);
780 xe->info.max_gt_per_tile = desc->max_gt_per_tile;
781 xe->info.tile_count = 1 + desc->max_remote_tiles;
782
783 xe_step_platform_get(xe);
784
785 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);
786 if (err)
787 return err;
788
789 return 0;
790 }
791
792 /*
793 * Possibly override number of tile based on configuration register.
794 */
xe_info_probe_tile_count(struct xe_device * xe)795 static void xe_info_probe_tile_count(struct xe_device *xe)
796 {
797 struct xe_mmio *mmio;
798 u8 tile_count;
799 u32 mtcfg;
800
801 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe);
802
803 /*
804 * Probe for tile count only for platforms that support multiple
805 * tiles.
806 */
807 if (xe->info.tile_count == 1)
808 return;
809
810 if (xe->info.skip_mtcfg)
811 return;
812
813 mmio = xe_root_tile_mmio(xe);
814
815 /*
816 * Although the per-tile mmio regs are not yet initialized, this
817 * is fine as it's going to the root tile's mmio, that's
818 * guaranteed to be initialized earlier in xe_mmio_probe_early()
819 */
820 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR);
821 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
822
823 if (tile_count < xe->info.tile_count) {
824 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n",
825 xe->info.tile_count, tile_count);
826 xe->info.tile_count = tile_count;
827 }
828 }
829
alloc_primary_gt(struct xe_tile * tile,const struct xe_graphics_desc * graphics_desc,const struct xe_media_desc * media_desc)830 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
831 const struct xe_graphics_desc *graphics_desc,
832 const struct xe_media_desc *media_desc)
833 {
834 struct xe_device *xe = tile_to_xe(tile);
835 struct xe_gt *gt;
836
837 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) {
838 xe_info(xe, "Primary GT disabled via configfs\n");
839 return NULL;
840 }
841
842 gt = xe_gt_alloc(tile);
843 if (IS_ERR(gt))
844 return gt;
845
846 gt->info.type = XE_GT_TYPE_MAIN;
847 gt->info.id = tile->id * xe->info.max_gt_per_tile;
848 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
849 gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask;
850 gt->info.engine_mask = graphics_desc->hw_engine_mask;
851 gt->info.num_geometry_xecore_fuse_regs = graphics_desc->num_geometry_xecore_fuse_regs;
852 gt->info.num_compute_xecore_fuse_regs = graphics_desc->num_compute_xecore_fuse_regs;
853
854 /*
855 * Before media version 13, the media IP was part of the primary GT
856 * so we need to add the media engines to the primary GT's engine list.
857 */
858 if (MEDIA_VER(xe) < 13 && media_desc)
859 gt->info.engine_mask |= media_desc->hw_engine_mask;
860
861 return gt;
862 }
863
alloc_media_gt(struct xe_tile * tile,const struct xe_media_desc * media_desc)864 static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
865 const struct xe_media_desc *media_desc)
866 {
867 struct xe_device *xe = tile_to_xe(tile);
868 struct xe_gt *gt;
869
870 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) {
871 xe_info(xe, "Media GT disabled via configfs\n");
872 return NULL;
873 }
874
875 if (MEDIA_VER(xe) < 13 || !media_desc)
876 return NULL;
877
878 gt = xe_gt_alloc(tile);
879 if (IS_ERR(gt))
880 return gt;
881
882 gt->info.type = XE_GT_TYPE_MEDIA;
883 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
884 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
885 gt->info.engine_mask = media_desc->hw_engine_mask;
886
887 return gt;
888 }
889
890 /*
891 * Initialize device info content that does require knowledge about
892 * graphics / media IP version.
893 * Make sure that GT / tile structures allocated by the driver match the data
894 * present in device info.
895 */
xe_info_init(struct xe_device * xe,const struct xe_device_desc * desc)896 static int xe_info_init(struct xe_device *xe,
897 const struct xe_device_desc *desc)
898 {
899 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0;
900 const struct xe_ip *graphics_ip;
901 const struct xe_ip *media_ip;
902 const struct xe_graphics_desc *graphics_desc;
903 const struct xe_media_desc *media_desc;
904 struct xe_tile *tile;
905 struct xe_gt *gt;
906 int ret;
907 u8 id;
908
909 /*
910 * If this platform supports GMD_ID, we'll detect the proper IP
911 * descriptor to use from hardware registers.
912 * desc->pre_gmdid_graphics_ip will only ever be set at this point for
913 * platforms before GMD_ID. In that case the IP descriptions and
914 * versions are simply derived from that.
915 */
916 if (desc->pre_gmdid_graphics_ip) {
917 graphics_ip = desc->pre_gmdid_graphics_ip;
918 media_ip = desc->pre_gmdid_media_ip;
919 xe_step_pre_gmdid_get(xe);
920 } else {
921 xe_assert(xe, !desc->pre_gmdid_media_ip);
922 ret = handle_gmdid(xe, &graphics_ip, &media_ip,
923 &graphics_gmdid_revid, &media_gmdid_revid);
924 if (ret)
925 return ret;
926
927 xe_step_gmdid_get(xe, graphics_gmdid_revid, media_gmdid_revid);
928 }
929
930 /*
931 * If we couldn't detect the graphics IP, that's considered a fatal
932 * error and we should abort driver load. Failing to detect media
933 * IP is non-fatal; we'll just proceed without enabling media support.
934 */
935 if (!graphics_ip)
936 return -ENODEV;
937
938 xe->info.graphics_verx100 = graphics_ip->verx100;
939 xe->info.graphics_name = graphics_ip->name;
940 graphics_desc = graphics_ip->desc;
941
942 if (media_ip) {
943 xe->info.media_verx100 = media_ip->verx100;
944 xe->info.media_name = media_ip->name;
945 media_desc = media_ip->desc;
946 } else {
947 xe->info.media_name = "none";
948 media_desc = NULL;
949 }
950
951 xe->info.has_access_counter = graphics_desc->has_access_counter;
952 xe->info.has_asid = graphics_desc->has_asid;
953 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
954 if (xe->info.platform != XE_PVC)
955 xe->info.has_device_atomics_on_smem = 1;
956
957 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval;
958 xe->info.has_ctx_tlb_inval = graphics_desc->has_ctx_tlb_inval;
959 xe->info.has_usm = graphics_desc->has_usm;
960 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
961 xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20;
962
963 xe_info_probe_tile_count(xe);
964
965 for_each_remote_tile(tile, xe, id) {
966 int err;
967
968 err = xe_tile_init_early(tile, xe, id);
969 if (err)
970 return err;
971 }
972
973 /* Allocate any GT and VRAM structures necessary for the platform. */
974 for_each_tile(tile, xe, id) {
975 int err;
976
977 err = xe_tile_alloc_vram(tile);
978 if (err)
979 return err;
980
981 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc);
982 if (IS_ERR(tile->primary_gt))
983 return PTR_ERR(tile->primary_gt);
984
985 /*
986 * It's not currently possible to probe a device with the
987 * primary GT disabled. With some work, this may be future in
988 * the possible for igpu platforms (although probably not for
989 * dgpu's since access to the primary GT's BCS engines is
990 * required for VRAM management).
991 */
992 if (!tile->primary_gt) {
993 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
994 return -ENODEV;
995 }
996
997 tile->media_gt = alloc_media_gt(tile, media_desc);
998 if (IS_ERR(tile->media_gt))
999 return PTR_ERR(tile->media_gt);
1000 }
1001
1002 /*
1003 * Now that we have tiles and GTs defined, let's loop over valid GTs
1004 * in order to define gt_count.
1005 */
1006 for_each_gt(gt, xe, id)
1007 xe->info.gt_count++;
1008
1009 return 0;
1010 }
1011
xe_pci_remove(struct pci_dev * pdev)1012 static void xe_pci_remove(struct pci_dev *pdev)
1013 {
1014 struct xe_device *xe = pdev_to_xe_device(pdev);
1015
1016 if (IS_SRIOV_PF(xe))
1017 xe_pci_sriov_configure(pdev, 0);
1018
1019 if (xe_survivability_mode_is_boot_enabled(xe))
1020 return;
1021
1022 xe_device_remove(xe);
1023 xe_pm_fini(xe);
1024 }
1025
1026 /*
1027 * Probe the PCI device, initialize various parts of the driver.
1028 *
1029 * Fault injection is used to test the error paths of some initialization
1030 * functions called either directly from xe_pci_probe() or indirectly for
1031 * example through xe_device_probe(). Those functions use the kernel fault
1032 * injection capabilities infrastructure, see
1033 * Documentation/fault-injection/fault-injection.rst for details. The macro
1034 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution
1035 * at runtime and use a provided return value. The first requirement for
1036 * error injectable functions is proper handling of the error code by the
1037 * caller for recovery, which is always the case here. The second
1038 * requirement is that no state is changed before the first error return.
1039 * It is not strictly fulfilled for all initialization functions using the
1040 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those
1041 * error cases at probe time, the error code is simply propagated up by the
1042 * caller. Therefore there is no consequence on those specific callers when
1043 * function error injection skips the whole function.
1044 */
xe_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1045 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1046 {
1047 const struct xe_device_desc *desc = (const void *)ent->driver_data;
1048 const struct xe_subplatform_desc *subplatform_desc;
1049 struct xe_device *xe;
1050 int err;
1051
1052 xe_configfs_check_device(pdev);
1053
1054 if (desc->require_force_probe && !id_forced(pdev->device)) {
1055 dev_info(&pdev->dev,
1056 "Your graphics device %04x is not officially supported\n"
1057 "by xe driver in this kernel version. To force Xe probe,\n"
1058 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"
1059 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"
1060 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",
1061 pdev->device, pdev->device, pdev->device,
1062 pdev->device, pdev->device);
1063 return -ENODEV;
1064 }
1065
1066 if (id_blocked(pdev->device)) {
1067 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n",
1068 pdev->vendor, pdev->device);
1069 return -ENODEV;
1070 }
1071
1072 if (xe_display_driver_probe_defer(pdev))
1073 return -EPROBE_DEFER;
1074
1075 err = pcim_enable_device(pdev);
1076 if (err)
1077 return err;
1078
1079 xe = xe_device_create(pdev, ent);
1080 if (IS_ERR(xe))
1081 return PTR_ERR(xe);
1082
1083 pci_set_drvdata(pdev, &xe->drm);
1084
1085 xe_pm_assert_unbounded_bridge(xe);
1086 subplatform_desc = find_subplatform(xe, desc);
1087
1088 pci_set_master(pdev);
1089
1090 err = xe_info_init_early(xe, desc, subplatform_desc);
1091 if (err)
1092 return err;
1093
1094 xe_pci_rebar_resize(xe);
1095
1096 err = xe_device_probe_early(xe);
1097 /*
1098 * In Boot Survivability mode, no drm card is exposed and driver
1099 * is loaded with bare minimum to allow for firmware to be
1100 * flashed through mei. Return success, if survivability mode
1101 * is enabled due to pcode failure or configfs being set
1102 */
1103 if (xe_survivability_mode_is_boot_enabled(xe))
1104 return 0;
1105
1106 if (err)
1107 return err;
1108
1109 err = xe_info_init(xe, desc);
1110 if (err)
1111 return err;
1112
1113 err = xe_display_probe(xe);
1114 if (err)
1115 return err;
1116
1117 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d",
1118 desc->platform_name,
1119 subplatform_desc ? subplatform_desc->name : "",
1120 xe->info.devid, xe->info.revid,
1121 xe->info.is_dgfx,
1122 xe->info.graphics_name,
1123 xe->info.graphics_verx100 / 100,
1124 xe->info.graphics_verx100 % 100,
1125 xe->info.media_name,
1126 xe->info.media_verx100 / 100,
1127 xe->info.media_verx100 % 100,
1128 str_yes_no(xe->info.probe_display),
1129 xe->info.dma_mask_size, xe->info.tile_count,
1130 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi);
1131
1132 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n",
1133 xe_step_name(xe->info.step.graphics),
1134 xe_step_name(xe->info.step.media),
1135 xe_step_name(xe->info.step.basedie));
1136
1137 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",
1138 str_yes_no(xe_device_has_sriov(xe)),
1139 xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));
1140
1141 err = xe_pm_init_early(xe);
1142 if (err)
1143 return err;
1144
1145 err = xe_device_probe(xe);
1146 if (err)
1147 return err;
1148
1149 err = xe_pm_init(xe);
1150 if (err)
1151 goto err_driver_cleanup;
1152
1153 drm_dbg(&xe->drm, "d3cold: capable=%s\n",
1154 str_yes_no(xe->d3cold.capable));
1155
1156 return 0;
1157
1158 err_driver_cleanup:
1159 xe_pci_remove(pdev);
1160 return err;
1161 }
1162
xe_pci_shutdown(struct pci_dev * pdev)1163 static void xe_pci_shutdown(struct pci_dev *pdev)
1164 {
1165 xe_device_shutdown(pdev_to_xe_device(pdev));
1166 }
1167
1168 #ifdef CONFIG_PM_SLEEP
d3cold_toggle(struct pci_dev * pdev,enum toggle_d3cold toggle)1169 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle)
1170 {
1171 struct xe_device *xe = pdev_to_xe_device(pdev);
1172 struct pci_dev *root_pdev;
1173
1174 if (!xe->d3cold.capable)
1175 return;
1176
1177 root_pdev = pcie_find_root_port(pdev);
1178 if (!root_pdev)
1179 return;
1180
1181 switch (toggle) {
1182 case D3COLD_DISABLE:
1183 pci_d3cold_disable(root_pdev);
1184 break;
1185 case D3COLD_ENABLE:
1186 pci_d3cold_enable(root_pdev);
1187 break;
1188 }
1189 }
1190
xe_pci_suspend(struct device * dev)1191 static int xe_pci_suspend(struct device *dev)
1192 {
1193 struct pci_dev *pdev = to_pci_dev(dev);
1194 struct xe_device *xe = pdev_to_xe_device(pdev);
1195 int err;
1196
1197 if (xe_survivability_mode_is_boot_enabled(xe))
1198 return -EBUSY;
1199
1200 err = xe_pm_suspend(xe);
1201 if (err)
1202 return err;
1203
1204 /*
1205 * Enabling D3Cold is needed for S2Idle/S0ix.
1206 * It is save to allow here since xe_pm_suspend has evicted
1207 * the local memory and the direct complete optimization is disabled.
1208 */
1209 d3cold_toggle(pdev, D3COLD_ENABLE);
1210
1211 pci_save_state(pdev);
1212 pci_disable_device(pdev);
1213 pci_set_power_state(pdev, PCI_D3cold);
1214
1215 return 0;
1216 }
1217
xe_pci_resume(struct device * dev)1218 static int xe_pci_resume(struct device *dev)
1219 {
1220 struct pci_dev *pdev = to_pci_dev(dev);
1221 int err;
1222
1223 /* Give back the D3Cold decision to the runtime P M*/
1224 d3cold_toggle(pdev, D3COLD_DISABLE);
1225
1226 err = pci_set_power_state(pdev, PCI_D0);
1227 if (err)
1228 return err;
1229
1230 pci_restore_state(pdev);
1231
1232 err = pci_enable_device(pdev);
1233 if (err)
1234 return err;
1235
1236 pci_set_master(pdev);
1237
1238 err = xe_pm_resume(pdev_to_xe_device(pdev));
1239 if (err)
1240 return err;
1241
1242 return 0;
1243 }
1244
xe_pci_runtime_suspend(struct device * dev)1245 static int xe_pci_runtime_suspend(struct device *dev)
1246 {
1247 struct pci_dev *pdev = to_pci_dev(dev);
1248 struct xe_device *xe = pdev_to_xe_device(pdev);
1249 int err;
1250
1251 /*
1252 * We hold an additional reference to the runtime PM to keep PF in D0
1253 * during VFs lifetime, as our VFs do not implement the PM capability.
1254 * This means we should never be runtime suspending as long as VFs are
1255 * enabled.
1256 */
1257 xe_assert(xe, !IS_SRIOV_VF(xe));
1258 xe_assert(xe, !pci_num_vf(pdev));
1259
1260 err = xe_pm_runtime_suspend(xe);
1261 if (err)
1262 return err;
1263
1264 pci_save_state(pdev);
1265
1266 if (xe->d3cold.allowed) {
1267 d3cold_toggle(pdev, D3COLD_ENABLE);
1268 pci_disable_device(pdev);
1269 pci_ignore_hotplug(pdev);
1270 pci_set_power_state(pdev, PCI_D3cold);
1271 } else {
1272 d3cold_toggle(pdev, D3COLD_DISABLE);
1273 pci_set_power_state(pdev, PCI_D3hot);
1274 }
1275
1276 return 0;
1277 }
1278
xe_pci_runtime_resume(struct device * dev)1279 static int xe_pci_runtime_resume(struct device *dev)
1280 {
1281 struct pci_dev *pdev = to_pci_dev(dev);
1282 struct xe_device *xe = pdev_to_xe_device(pdev);
1283 int err;
1284
1285 err = pci_set_power_state(pdev, PCI_D0);
1286 if (err)
1287 return err;
1288
1289 pci_restore_state(pdev);
1290
1291 if (xe->d3cold.allowed) {
1292 err = pci_enable_device(pdev);
1293 if (err)
1294 return err;
1295
1296 pci_set_master(pdev);
1297 }
1298
1299 return xe_pm_runtime_resume(xe);
1300 }
1301
xe_pci_runtime_idle(struct device * dev)1302 static int xe_pci_runtime_idle(struct device *dev)
1303 {
1304 struct pci_dev *pdev = to_pci_dev(dev);
1305 struct xe_device *xe = pdev_to_xe_device(pdev);
1306
1307 xe_pm_d3cold_allowed_toggle(xe);
1308
1309 return 0;
1310 }
1311
1312 static const struct dev_pm_ops xe_pm_ops = {
1313 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume)
1314 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle)
1315 };
1316 #endif
1317
1318 static struct pci_driver xe_pci_driver = {
1319 .name = DRIVER_NAME,
1320 .id_table = pciidlist,
1321 .probe = xe_pci_probe,
1322 .remove = xe_pci_remove,
1323 .shutdown = xe_pci_shutdown,
1324 .sriov_configure = xe_pci_sriov_configure,
1325 #ifdef CONFIG_PM_SLEEP
1326 .driver.pm = &xe_pm_ops,
1327 #endif
1328 };
1329
1330 /**
1331 * xe_pci_to_pf_device() - Get PF &xe_device.
1332 * @pdev: the VF &pci_dev device
1333 *
1334 * Return: pointer to PF &xe_device, NULL otherwise.
1335 */
xe_pci_to_pf_device(struct pci_dev * pdev)1336 struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev)
1337 {
1338 struct drm_device *drm;
1339
1340 drm = pci_iov_get_pf_drvdata(pdev, &xe_pci_driver);
1341 if (IS_ERR(drm))
1342 return NULL;
1343
1344 return to_xe_device(drm);
1345 }
1346
xe_register_pci_driver(void)1347 int xe_register_pci_driver(void)
1348 {
1349 return pci_register_driver(&xe_pci_driver);
1350 }
1351
xe_unregister_pci_driver(void)1352 void xe_unregister_pci_driver(void)
1353 {
1354 pci_unregister_driver(&xe_pci_driver);
1355 }
1356
1357 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
1358 #include "tests/xe_pci.c"
1359 #endif
1360