1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 NVIDIA Corporation
4 */
5
6 #include <linux/clk.h>
7 #include <linux/debugfs.h>
8 #include <linux/delay.h>
9 #include <linux/host1x.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_platform.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset.h>
17
18 #include <video/mipi_display.h>
19
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_debugfs.h>
22 #include <drm/drm_file.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_panel.h>
25 #include <drm/drm_print.h>
26 #include <drm/drm_simple_kms_helper.h>
27
28 #include "dc.h"
29 #include "drm.h"
30 #include "dsi.h"
31 #include "mipi-phy.h"
32 #include "trace.h"
33
34 struct tegra_dsi_state {
35 struct drm_connector_state base;
36
37 struct mipi_dphy_timing timing;
38 unsigned long period;
39
40 unsigned int vrefresh;
41 unsigned int lanes;
42 unsigned long pclk;
43 unsigned long bclk;
44
45 enum tegra_dsi_format format;
46 unsigned int mul;
47 unsigned int div;
48 };
49
50 static inline struct tegra_dsi_state *
to_dsi_state(struct drm_connector_state * state)51 to_dsi_state(struct drm_connector_state *state)
52 {
53 return container_of(state, struct tegra_dsi_state, base);
54 }
55
56 struct tegra_dsi {
57 struct host1x_client client;
58 struct tegra_output output;
59 struct device *dev;
60
61 void __iomem *regs;
62
63 struct reset_control *rst;
64 struct clk *clk_parent;
65 struct clk *clk_lp;
66 struct clk *clk;
67
68 struct drm_info_list *debugfs_files;
69
70 unsigned long flags;
71 enum mipi_dsi_pixel_format format;
72 unsigned int lanes;
73
74 struct tegra_mipi_device *mipi;
75 struct mipi_dsi_host host;
76
77 struct regulator *vdd;
78
79 unsigned int video_fifo_depth;
80 unsigned int host_fifo_depth;
81
82 /* for ganged-mode support */
83 struct tegra_dsi *master;
84 struct tegra_dsi *slave;
85 };
86
87 static inline struct tegra_dsi *
host1x_client_to_dsi(struct host1x_client * client)88 host1x_client_to_dsi(struct host1x_client *client)
89 {
90 return container_of(client, struct tegra_dsi, client);
91 }
92
host_to_tegra(struct mipi_dsi_host * host)93 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
94 {
95 return container_of(host, struct tegra_dsi, host);
96 }
97
to_dsi(struct tegra_output * output)98 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
99 {
100 return container_of(output, struct tegra_dsi, output);
101 }
102
tegra_dsi_get_state(struct tegra_dsi * dsi)103 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
104 {
105 return to_dsi_state(dsi->output.connector.state);
106 }
107
tegra_dsi_readl(struct tegra_dsi * dsi,unsigned int offset)108 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
109 {
110 u32 value = readl(dsi->regs + (offset << 2));
111
112 trace_dsi_readl(dsi->dev, offset, value);
113
114 return value;
115 }
116
tegra_dsi_writel(struct tegra_dsi * dsi,u32 value,unsigned int offset)117 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
118 unsigned int offset)
119 {
120 trace_dsi_writel(dsi->dev, offset, value);
121 writel(value, dsi->regs + (offset << 2));
122 }
123
124 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
125
126 static const struct debugfs_reg32 tegra_dsi_regs[] = {
127 DEBUGFS_REG32(DSI_INCR_SYNCPT),
128 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
129 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
130 DEBUGFS_REG32(DSI_CTXSW),
131 DEBUGFS_REG32(DSI_RD_DATA),
132 DEBUGFS_REG32(DSI_WR_DATA),
133 DEBUGFS_REG32(DSI_POWER_CONTROL),
134 DEBUGFS_REG32(DSI_INT_ENABLE),
135 DEBUGFS_REG32(DSI_INT_STATUS),
136 DEBUGFS_REG32(DSI_INT_MASK),
137 DEBUGFS_REG32(DSI_HOST_CONTROL),
138 DEBUGFS_REG32(DSI_CONTROL),
139 DEBUGFS_REG32(DSI_SOL_DELAY),
140 DEBUGFS_REG32(DSI_MAX_THRESHOLD),
141 DEBUGFS_REG32(DSI_TRIGGER),
142 DEBUGFS_REG32(DSI_TX_CRC),
143 DEBUGFS_REG32(DSI_STATUS),
144 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
152 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
153 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
154 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
155 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
156 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
157 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
158 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
159 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
160 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
161 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
162 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
163 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
164 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
165 DEBUGFS_REG32(DSI_DCS_CMDS),
166 DEBUGFS_REG32(DSI_PKT_LEN_0_1),
167 DEBUGFS_REG32(DSI_PKT_LEN_2_3),
168 DEBUGFS_REG32(DSI_PKT_LEN_4_5),
169 DEBUGFS_REG32(DSI_PKT_LEN_6_7),
170 DEBUGFS_REG32(DSI_PHY_TIMING_0),
171 DEBUGFS_REG32(DSI_PHY_TIMING_1),
172 DEBUGFS_REG32(DSI_PHY_TIMING_2),
173 DEBUGFS_REG32(DSI_BTA_TIMING),
174 DEBUGFS_REG32(DSI_TIMEOUT_0),
175 DEBUGFS_REG32(DSI_TIMEOUT_1),
176 DEBUGFS_REG32(DSI_TO_TALLY),
177 DEBUGFS_REG32(DSI_PAD_CONTROL_0),
178 DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
179 DEBUGFS_REG32(DSI_PAD_CD_STATUS),
180 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
181 DEBUGFS_REG32(DSI_PAD_CONTROL_1),
182 DEBUGFS_REG32(DSI_PAD_CONTROL_2),
183 DEBUGFS_REG32(DSI_PAD_CONTROL_3),
184 DEBUGFS_REG32(DSI_PAD_CONTROL_4),
185 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
186 DEBUGFS_REG32(DSI_GANGED_MODE_START),
187 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
188 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
189 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
197 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
198 };
199
tegra_dsi_show_regs(struct seq_file * s,void * data)200 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
201 {
202 struct drm_info_node *node = s->private;
203 struct tegra_dsi *dsi = node->info_ent->data;
204 struct drm_crtc *crtc = dsi->output.encoder.crtc;
205 struct drm_device *drm = node->minor->dev;
206 unsigned int i;
207 int err = 0;
208
209 drm_modeset_lock_all(drm);
210
211 if (!crtc || !crtc->state->active) {
212 err = -EBUSY;
213 goto unlock;
214 }
215
216 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
217 unsigned int offset = tegra_dsi_regs[i].offset;
218
219 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
220 offset, tegra_dsi_readl(dsi, offset));
221 }
222
223 unlock:
224 drm_modeset_unlock_all(drm);
225 return err;
226 }
227
228 static struct drm_info_list debugfs_files[] = {
229 { "regs", tegra_dsi_show_regs, 0, NULL },
230 };
231
tegra_dsi_late_register(struct drm_connector * connector)232 static int tegra_dsi_late_register(struct drm_connector *connector)
233 {
234 struct tegra_output *output = connector_to_output(connector);
235 unsigned int i, count = ARRAY_SIZE(debugfs_files);
236 struct drm_minor *minor = connector->dev->primary;
237 struct dentry *root = connector->debugfs_entry;
238 struct tegra_dsi *dsi = to_dsi(output);
239
240 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
241 GFP_KERNEL);
242 if (!dsi->debugfs_files)
243 return -ENOMEM;
244
245 for (i = 0; i < count; i++)
246 dsi->debugfs_files[i].data = dsi;
247
248 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
249
250 return 0;
251 }
252
tegra_dsi_early_unregister(struct drm_connector * connector)253 static void tegra_dsi_early_unregister(struct drm_connector *connector)
254 {
255 struct tegra_output *output = connector_to_output(connector);
256 unsigned int count = ARRAY_SIZE(debugfs_files);
257 struct tegra_dsi *dsi = to_dsi(output);
258
259 drm_debugfs_remove_files(dsi->debugfs_files, count,
260 connector->debugfs_entry,
261 connector->dev->primary);
262 kfree(dsi->debugfs_files);
263 dsi->debugfs_files = NULL;
264 }
265
266 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
267 #define PKT_LEN0(len) (((len) & 0x07) << 0)
268 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
269 #define PKT_LEN1(len) (((len) & 0x07) << 10)
270 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
271 #define PKT_LEN2(len) (((len) & 0x07) << 20)
272
273 #define PKT_LP (1 << 30)
274 #define NUM_PKT_SEQ 12
275
276 /*
277 * non-burst mode with sync pulses
278 */
279 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
280 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
281 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
282 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
283 PKT_LP,
284 [ 1] = 0,
285 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
286 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
287 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
288 PKT_LP,
289 [ 3] = 0,
290 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
291 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
292 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
293 PKT_LP,
294 [ 5] = 0,
295 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
296 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
297 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
298 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
299 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
300 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
301 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
302 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
303 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
304 PKT_LP,
305 [ 9] = 0,
306 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
307 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
308 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
309 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
310 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
311 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
312 };
313
314 /*
315 * non-burst mode with sync events
316 */
317 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
318 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
319 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
320 PKT_LP,
321 [ 1] = 0,
322 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
323 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
324 PKT_LP,
325 [ 3] = 0,
326 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
327 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
328 PKT_LP,
329 [ 5] = 0,
330 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
331 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
332 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
333 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
334 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
335 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
336 PKT_LP,
337 [ 9] = 0,
338 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
339 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
340 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
341 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
342 };
343
344 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
345 [ 0] = 0,
346 [ 1] = 0,
347 [ 2] = 0,
348 [ 3] = 0,
349 [ 4] = 0,
350 [ 5] = 0,
351 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
352 [ 7] = 0,
353 [ 8] = 0,
354 [ 9] = 0,
355 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
356 [11] = 0,
357 };
358
tegra_dsi_set_phy_timing(struct tegra_dsi * dsi,unsigned long period,const struct mipi_dphy_timing * timing)359 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
360 unsigned long period,
361 const struct mipi_dphy_timing *timing)
362 {
363 u32 value;
364
365 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
366 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
367 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
368 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
369 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
370
371 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
372 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
373 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
374 DSI_TIMING_FIELD(timing->lpx, period, 1);
375 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
376
377 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
378 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
379 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
380 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
381
382 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
383 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
384 DSI_TIMING_FIELD(timing->tago, period, 1);
385 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
386
387 if (dsi->slave)
388 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
389 }
390
tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,unsigned int * mulp,unsigned int * divp)391 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
392 unsigned int *mulp, unsigned int *divp)
393 {
394 switch (format) {
395 case MIPI_DSI_FMT_RGB666_PACKED:
396 case MIPI_DSI_FMT_RGB888:
397 *mulp = 3;
398 *divp = 1;
399 break;
400
401 case MIPI_DSI_FMT_RGB565:
402 *mulp = 2;
403 *divp = 1;
404 break;
405
406 case MIPI_DSI_FMT_RGB666:
407 *mulp = 9;
408 *divp = 4;
409 break;
410
411 default:
412 return -EINVAL;
413 }
414
415 return 0;
416 }
417
tegra_dsi_get_format(enum mipi_dsi_pixel_format format,enum tegra_dsi_format * fmt)418 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
419 enum tegra_dsi_format *fmt)
420 {
421 switch (format) {
422 case MIPI_DSI_FMT_RGB888:
423 *fmt = TEGRA_DSI_FORMAT_24P;
424 break;
425
426 case MIPI_DSI_FMT_RGB666:
427 *fmt = TEGRA_DSI_FORMAT_18NP;
428 break;
429
430 case MIPI_DSI_FMT_RGB666_PACKED:
431 *fmt = TEGRA_DSI_FORMAT_18P;
432 break;
433
434 case MIPI_DSI_FMT_RGB565:
435 *fmt = TEGRA_DSI_FORMAT_16P;
436 break;
437
438 default:
439 return -EINVAL;
440 }
441
442 return 0;
443 }
444
tegra_dsi_ganged_enable(struct tegra_dsi * dsi,unsigned int start,unsigned int size)445 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
446 unsigned int size)
447 {
448 u32 value;
449
450 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
451 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
452
453 value = DSI_GANGED_MODE_CONTROL_ENABLE;
454 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
455 }
456
tegra_dsi_enable(struct tegra_dsi * dsi)457 static void tegra_dsi_enable(struct tegra_dsi *dsi)
458 {
459 u32 value;
460
461 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
462 value |= DSI_POWER_CONTROL_ENABLE;
463 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
464
465 if (dsi->slave)
466 tegra_dsi_enable(dsi->slave);
467 }
468
tegra_dsi_get_lanes(struct tegra_dsi * dsi)469 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
470 {
471 if (dsi->master)
472 return dsi->master->lanes + dsi->lanes;
473
474 if (dsi->slave)
475 return dsi->lanes + dsi->slave->lanes;
476
477 return dsi->lanes;
478 }
479
tegra_dsi_configure(struct tegra_dsi * dsi,unsigned int pipe,const struct drm_display_mode * mode)480 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
481 const struct drm_display_mode *mode)
482 {
483 unsigned int hact, hsw, hbp, hfp, i, mul, div;
484 struct tegra_dsi_state *state;
485 const u32 *pkt_seq;
486 u32 value;
487
488 /* XXX: pass in state into this function? */
489 if (dsi->master)
490 state = tegra_dsi_get_state(dsi->master);
491 else
492 state = tegra_dsi_get_state(dsi);
493
494 mul = state->mul;
495 div = state->div;
496
497 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
498 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
499 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
500 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
501 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
502 pkt_seq = pkt_seq_video_non_burst_sync_events;
503 } else {
504 DRM_DEBUG_KMS("Command mode\n");
505 pkt_seq = pkt_seq_command_mode;
506 }
507
508 value = DSI_CONTROL_CHANNEL(0) |
509 DSI_CONTROL_FORMAT(state->format) |
510 DSI_CONTROL_LANES(dsi->lanes - 1) |
511 DSI_CONTROL_SOURCE(pipe);
512 tegra_dsi_writel(dsi, value, DSI_CONTROL);
513
514 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
515
516 value = DSI_HOST_CONTROL_HS;
517 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
518
519 value = tegra_dsi_readl(dsi, DSI_CONTROL);
520
521 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
522 value |= DSI_CONTROL_HS_CLK_CTRL;
523
524 value &= ~DSI_CONTROL_TX_TRIG(3);
525
526 /* enable DCS commands for command mode */
527 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
528 value &= ~DSI_CONTROL_DCS_ENABLE;
529 else
530 value |= DSI_CONTROL_DCS_ENABLE;
531
532 value |= DSI_CONTROL_VIDEO_ENABLE;
533 value &= ~DSI_CONTROL_HOST_ENABLE;
534 tegra_dsi_writel(dsi, value, DSI_CONTROL);
535
536 for (i = 0; i < NUM_PKT_SEQ; i++)
537 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
538
539 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
540 /* horizontal active pixels */
541 hact = mode->hdisplay * mul / div;
542
543 /* horizontal sync width */
544 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
545
546 /* horizontal back porch */
547 hbp = (mode->htotal - mode->hsync_end) * mul / div;
548
549 /* horizontal front porch */
550 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
551
552 if (dsi->master || dsi->slave) {
553 hact /= 2;
554 hsw /= 2;
555 hbp /= 2;
556 hfp /= 2;
557 }
558
559 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
560 hbp += hsw;
561
562 /* subtract packet overhead */
563 hsw -= 10;
564 hbp -= 14;
565 hfp -= 8;
566
567 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
568 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
569 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
570 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
571 } else {
572 u16 bytes;
573
574 if (dsi->master || dsi->slave) {
575 /*
576 * For ganged mode, assume symmetric left-right mode.
577 */
578 bytes = 1 + (mode->hdisplay / 2) * mul / div;
579 } else {
580 /* 1 byte (DCS command) + pixel data */
581 bytes = 1 + mode->hdisplay * mul / div;
582 }
583
584 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
585 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
586 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
587 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
588
589 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
590 MIPI_DCS_WRITE_MEMORY_CONTINUE;
591 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
592 }
593
594 /* set SOL delay */
595 if (dsi->master || dsi->slave) {
596 unsigned long delay, bclk, bclk_ganged;
597 unsigned int lanes = state->lanes;
598
599 /* SOL to valid, valid to FIFO and FIFO write delay */
600 delay = 4 + 4 + 2;
601 delay = DIV_ROUND_UP(delay * mul, div * lanes);
602 /* FIFO read delay */
603 delay = delay + 6;
604
605 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
606 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
607 value = bclk - bclk_ganged + delay + 20;
608 } else {
609 value = 8 * mul / div;
610 }
611
612 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
613
614 if (dsi->slave) {
615 tegra_dsi_configure(dsi->slave, pipe, mode);
616
617 /*
618 * TODO: Support modes other than symmetrical left-right
619 * split.
620 */
621 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
622 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
623 mode->hdisplay / 2);
624 }
625 }
626
tegra_dsi_wait_idle(struct tegra_dsi * dsi,unsigned long timeout)627 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
628 {
629 u32 value;
630
631 timeout = jiffies + msecs_to_jiffies(timeout);
632
633 while (time_before(jiffies, timeout)) {
634 value = tegra_dsi_readl(dsi, DSI_STATUS);
635 if (value & DSI_STATUS_IDLE)
636 return 0;
637
638 usleep_range(1000, 2000);
639 }
640
641 return -ETIMEDOUT;
642 }
643
tegra_dsi_video_disable(struct tegra_dsi * dsi)644 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
645 {
646 u32 value;
647
648 value = tegra_dsi_readl(dsi, DSI_CONTROL);
649 value &= ~DSI_CONTROL_VIDEO_ENABLE;
650 tegra_dsi_writel(dsi, value, DSI_CONTROL);
651
652 if (dsi->slave)
653 tegra_dsi_video_disable(dsi->slave);
654 }
655
tegra_dsi_ganged_disable(struct tegra_dsi * dsi)656 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
657 {
658 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
659 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
660 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
661 }
662
tegra_dsi_pad_enable(struct tegra_dsi * dsi)663 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
664 {
665 u32 value;
666
667 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
668 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
669
670 return 0;
671 }
672
tegra_dsi_pad_calibrate(struct tegra_dsi * dsi)673 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
674 {
675 u32 value;
676 int err;
677
678 /*
679 * XXX Is this still needed? The module reset is deasserted right
680 * before this function is called.
681 */
682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
684 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
685 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
686 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
687
688 /* start calibration */
689 tegra_dsi_pad_enable(dsi);
690
691 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
692 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
693 DSI_PAD_OUT_CLK(0x0);
694 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
695
696 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
697 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
698 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
699
700 err = tegra_mipi_start_calibration(dsi->mipi);
701 if (err < 0)
702 return err;
703
704 return tegra_mipi_finish_calibration(dsi->mipi);
705 }
706
tegra_dsi_set_timeout(struct tegra_dsi * dsi,unsigned long bclk,unsigned int vrefresh)707 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
708 unsigned int vrefresh)
709 {
710 unsigned int timeout;
711 u32 value;
712
713 /* one frame high-speed transmission timeout */
714 timeout = (bclk / vrefresh) / 512;
715 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
716 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
717
718 /* 2 ms peripheral timeout for panel */
719 timeout = 2 * bclk / 512 * 1000;
720 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
721 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
722
723 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
724 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
725
726 if (dsi->slave)
727 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
728 }
729
tegra_dsi_disable(struct tegra_dsi * dsi)730 static void tegra_dsi_disable(struct tegra_dsi *dsi)
731 {
732 u32 value;
733
734 if (dsi->slave) {
735 tegra_dsi_ganged_disable(dsi->slave);
736 tegra_dsi_ganged_disable(dsi);
737 }
738
739 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
740 value &= ~DSI_POWER_CONTROL_ENABLE;
741 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
742
743 if (dsi->slave)
744 tegra_dsi_disable(dsi->slave);
745
746 usleep_range(5000, 10000);
747 }
748
tegra_dsi_soft_reset(struct tegra_dsi * dsi)749 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
750 {
751 u32 value;
752
753 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
754 value &= ~DSI_POWER_CONTROL_ENABLE;
755 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
756
757 usleep_range(300, 1000);
758
759 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
760 value |= DSI_POWER_CONTROL_ENABLE;
761 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
762
763 usleep_range(300, 1000);
764
765 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
766 if (value)
767 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
768
769 if (dsi->slave)
770 tegra_dsi_soft_reset(dsi->slave);
771 }
772
tegra_dsi_connector_reset(struct drm_connector * connector)773 static void tegra_dsi_connector_reset(struct drm_connector *connector)
774 {
775 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
776
777 if (!state)
778 return;
779
780 if (connector->state) {
781 __drm_atomic_helper_connector_destroy_state(connector->state);
782 kfree(connector->state);
783 }
784
785 __drm_atomic_helper_connector_reset(connector, &state->base);
786 }
787
788 static struct drm_connector_state *
tegra_dsi_connector_duplicate_state(struct drm_connector * connector)789 tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
790 {
791 struct tegra_dsi_state *state = to_dsi_state(connector->state);
792 struct tegra_dsi_state *copy;
793
794 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
795 if (!copy)
796 return NULL;
797
798 __drm_atomic_helper_connector_duplicate_state(connector,
799 ©->base);
800
801 return ©->base;
802 }
803
804 static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
805 .reset = tegra_dsi_connector_reset,
806 .detect = tegra_output_connector_detect,
807 .fill_modes = drm_helper_probe_single_connector_modes,
808 .destroy = tegra_output_connector_destroy,
809 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
810 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
811 .late_register = tegra_dsi_late_register,
812 .early_unregister = tegra_dsi_early_unregister,
813 };
814
815 static enum drm_mode_status
tegra_dsi_connector_mode_valid(struct drm_connector * connector,const struct drm_display_mode * mode)816 tegra_dsi_connector_mode_valid(struct drm_connector *connector,
817 const struct drm_display_mode *mode)
818 {
819 return MODE_OK;
820 }
821
822 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
823 .get_modes = tegra_output_connector_get_modes,
824 .mode_valid = tegra_dsi_connector_mode_valid,
825 };
826
tegra_dsi_unprepare(struct tegra_dsi * dsi)827 static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
828 {
829 int err;
830
831 if (dsi->slave)
832 tegra_dsi_unprepare(dsi->slave);
833
834 err = tegra_mipi_disable(dsi->mipi);
835 if (err < 0)
836 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
837 err);
838
839 err = host1x_client_suspend(&dsi->client);
840 if (err < 0)
841 dev_err(dsi->dev, "failed to suspend: %d\n", err);
842 }
843
tegra_dsi_encoder_disable(struct drm_encoder * encoder)844 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
845 {
846 struct tegra_output *output = encoder_to_output(encoder);
847 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
848 struct tegra_dsi *dsi = to_dsi(output);
849 u32 value;
850 int err;
851
852 if (output->panel)
853 drm_panel_disable(output->panel);
854
855 tegra_dsi_video_disable(dsi);
856
857 /*
858 * The following accesses registers of the display controller, so make
859 * sure it's only executed when the output is attached to one.
860 */
861 if (dc) {
862 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
863 value &= ~DSI_ENABLE;
864 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
865
866 tegra_dc_commit(dc);
867 }
868
869 err = tegra_dsi_wait_idle(dsi, 100);
870 if (err < 0)
871 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
872
873 tegra_dsi_soft_reset(dsi);
874
875 if (output->panel)
876 drm_panel_unprepare(output->panel);
877
878 tegra_dsi_disable(dsi);
879
880 tegra_dsi_unprepare(dsi);
881 }
882
tegra_dsi_prepare(struct tegra_dsi * dsi)883 static int tegra_dsi_prepare(struct tegra_dsi *dsi)
884 {
885 int err;
886
887 err = host1x_client_resume(&dsi->client);
888 if (err < 0) {
889 dev_err(dsi->dev, "failed to resume: %d\n", err);
890 return err;
891 }
892
893 err = tegra_mipi_enable(dsi->mipi);
894 if (err < 0)
895 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
896 err);
897
898 err = tegra_dsi_pad_calibrate(dsi);
899 if (err < 0)
900 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
901
902 if (dsi->slave)
903 tegra_dsi_prepare(dsi->slave);
904
905 return 0;
906 }
907
tegra_dsi_encoder_enable(struct drm_encoder * encoder)908 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
909 {
910 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
911 struct tegra_output *output = encoder_to_output(encoder);
912 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
913 struct tegra_dsi *dsi = to_dsi(output);
914 struct tegra_dsi_state *state;
915 u32 value;
916 int err;
917
918 err = tegra_dsi_prepare(dsi);
919 if (err < 0) {
920 dev_err(dsi->dev, "failed to prepare: %d\n", err);
921 return;
922 }
923
924 state = tegra_dsi_get_state(dsi);
925
926 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
927
928 /*
929 * The D-PHY timing fields are expressed in byte-clock cycles, so
930 * multiply the period by 8.
931 */
932 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
933
934 if (output->panel)
935 drm_panel_prepare(output->panel);
936
937 tegra_dsi_configure(dsi, dc->pipe, mode);
938
939 /* enable display controller */
940 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
941 value |= DSI_ENABLE;
942 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
943
944 tegra_dc_commit(dc);
945
946 /* enable DSI controller */
947 tegra_dsi_enable(dsi);
948
949 if (output->panel)
950 drm_panel_enable(output->panel);
951 }
952
953 static int
tegra_dsi_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)954 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
955 struct drm_crtc_state *crtc_state,
956 struct drm_connector_state *conn_state)
957 {
958 struct tegra_output *output = encoder_to_output(encoder);
959 struct tegra_dsi_state *state = to_dsi_state(conn_state);
960 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
961 struct tegra_dsi *dsi = to_dsi(output);
962 unsigned int scdiv;
963 unsigned long plld;
964 int err;
965
966 state->pclk = crtc_state->mode.clock * 1000;
967
968 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
969 if (err < 0)
970 return err;
971
972 state->lanes = tegra_dsi_get_lanes(dsi);
973
974 err = tegra_dsi_get_format(dsi->format, &state->format);
975 if (err < 0)
976 return err;
977
978 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
979
980 /* compute byte clock */
981 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
982
983 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
984 state->lanes);
985 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
986 state->vrefresh);
987 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
988
989 /*
990 * Compute bit clock and round up to the next MHz.
991 */
992 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
993 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
994
995 err = mipi_dphy_timing_get_default(&state->timing, state->period);
996 if (err < 0)
997 return err;
998
999 err = mipi_dphy_timing_validate(&state->timing, state->period);
1000 if (err < 0) {
1001 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
1002 return err;
1003 }
1004
1005 /*
1006 * We divide the frequency by two here, but we make up for that by
1007 * setting the shift clock divider (further below) to half of the
1008 * correct value.
1009 */
1010 plld /= 2;
1011
1012 /*
1013 * Derive pixel clock from bit clock using the shift clock divider.
1014 * Note that this is only half of what we would expect, but we need
1015 * that to make up for the fact that we divided the bit clock by a
1016 * factor of two above.
1017 *
1018 * It's not clear exactly why this is necessary, but the display is
1019 * not working properly otherwise. Perhaps the PLLs cannot generate
1020 * frequencies sufficiently high.
1021 */
1022 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1023
1024 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1025 plld, scdiv);
1026 if (err < 0) {
1027 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1028 return err;
1029 }
1030
1031 return err;
1032 }
1033
1034 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1035 .disable = tegra_dsi_encoder_disable,
1036 .enable = tegra_dsi_encoder_enable,
1037 .atomic_check = tegra_dsi_encoder_atomic_check,
1038 };
1039
tegra_dsi_init(struct host1x_client * client)1040 static int tegra_dsi_init(struct host1x_client *client)
1041 {
1042 struct drm_device *drm = dev_get_drvdata(client->host);
1043 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1044 int err;
1045
1046 /* Gangsters must not register their own outputs. */
1047 if (!dsi->master) {
1048 dsi->output.dev = client->dev;
1049
1050 drm_connector_init(drm, &dsi->output.connector,
1051 &tegra_dsi_connector_funcs,
1052 DRM_MODE_CONNECTOR_DSI);
1053 drm_connector_helper_add(&dsi->output.connector,
1054 &tegra_dsi_connector_helper_funcs);
1055 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1056
1057 drm_simple_encoder_init(drm, &dsi->output.encoder,
1058 DRM_MODE_ENCODER_DSI);
1059 drm_encoder_helper_add(&dsi->output.encoder,
1060 &tegra_dsi_encoder_helper_funcs);
1061
1062 drm_connector_attach_encoder(&dsi->output.connector,
1063 &dsi->output.encoder);
1064 drm_connector_register(&dsi->output.connector);
1065
1066 err = tegra_output_init(drm, &dsi->output);
1067 if (err < 0)
1068 dev_err(dsi->dev, "failed to initialize output: %d\n",
1069 err);
1070
1071 dsi->output.encoder.possible_crtcs = 0x3;
1072 }
1073
1074 return 0;
1075 }
1076
tegra_dsi_exit(struct host1x_client * client)1077 static int tegra_dsi_exit(struct host1x_client *client)
1078 {
1079 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1080
1081 tegra_output_exit(&dsi->output);
1082
1083 return 0;
1084 }
1085
tegra_dsi_runtime_suspend(struct host1x_client * client)1086 static int tegra_dsi_runtime_suspend(struct host1x_client *client)
1087 {
1088 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1089 struct device *dev = client->dev;
1090 int err;
1091
1092 if (dsi->rst) {
1093 err = reset_control_assert(dsi->rst);
1094 if (err < 0) {
1095 dev_err(dev, "failed to assert reset: %d\n", err);
1096 return err;
1097 }
1098 }
1099
1100 usleep_range(1000, 2000);
1101
1102 clk_disable_unprepare(dsi->clk_lp);
1103 clk_disable_unprepare(dsi->clk);
1104
1105 regulator_disable(dsi->vdd);
1106 pm_runtime_put_sync(dev);
1107
1108 return 0;
1109 }
1110
tegra_dsi_runtime_resume(struct host1x_client * client)1111 static int tegra_dsi_runtime_resume(struct host1x_client *client)
1112 {
1113 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1114 struct device *dev = client->dev;
1115 int err;
1116
1117 err = pm_runtime_resume_and_get(dev);
1118 if (err < 0) {
1119 dev_err(dev, "failed to get runtime PM: %d\n", err);
1120 return err;
1121 }
1122
1123 err = regulator_enable(dsi->vdd);
1124 if (err < 0) {
1125 dev_err(dev, "failed to enable VDD supply: %d\n", err);
1126 goto put_rpm;
1127 }
1128
1129 err = clk_prepare_enable(dsi->clk);
1130 if (err < 0) {
1131 dev_err(dev, "cannot enable DSI clock: %d\n", err);
1132 goto disable_vdd;
1133 }
1134
1135 err = clk_prepare_enable(dsi->clk_lp);
1136 if (err < 0) {
1137 dev_err(dev, "cannot enable low-power clock: %d\n", err);
1138 goto disable_clk;
1139 }
1140
1141 usleep_range(1000, 2000);
1142
1143 if (dsi->rst) {
1144 err = reset_control_deassert(dsi->rst);
1145 if (err < 0) {
1146 dev_err(dev, "cannot assert reset: %d\n", err);
1147 goto disable_clk_lp;
1148 }
1149 }
1150
1151 return 0;
1152
1153 disable_clk_lp:
1154 clk_disable_unprepare(dsi->clk_lp);
1155 disable_clk:
1156 clk_disable_unprepare(dsi->clk);
1157 disable_vdd:
1158 regulator_disable(dsi->vdd);
1159 put_rpm:
1160 pm_runtime_put_sync(dev);
1161 return err;
1162 }
1163
1164 static const struct host1x_client_ops dsi_client_ops = {
1165 .init = tegra_dsi_init,
1166 .exit = tegra_dsi_exit,
1167 .suspend = tegra_dsi_runtime_suspend,
1168 .resume = tegra_dsi_runtime_resume,
1169 };
1170
tegra_dsi_setup_clocks(struct tegra_dsi * dsi)1171 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1172 {
1173 struct clk *parent;
1174 int err;
1175
1176 parent = clk_get_parent(dsi->clk);
1177 if (!parent)
1178 return -EINVAL;
1179
1180 err = clk_set_parent(parent, dsi->clk_parent);
1181 if (err < 0)
1182 return err;
1183
1184 return 0;
1185 }
1186
1187 static const char * const error_report[16] = {
1188 "SoT Error",
1189 "SoT Sync Error",
1190 "EoT Sync Error",
1191 "Escape Mode Entry Command Error",
1192 "Low-Power Transmit Sync Error",
1193 "Peripheral Timeout Error",
1194 "False Control Error",
1195 "Contention Detected",
1196 "ECC Error, single-bit",
1197 "ECC Error, multi-bit",
1198 "Checksum Error",
1199 "DSI Data Type Not Recognized",
1200 "DSI VC ID Invalid",
1201 "Invalid Transmission Length",
1202 "Reserved",
1203 "DSI Protocol Violation",
1204 };
1205
tegra_dsi_read_response(struct tegra_dsi * dsi,const struct mipi_dsi_msg * msg,size_t count)1206 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1207 const struct mipi_dsi_msg *msg,
1208 size_t count)
1209 {
1210 u8 *rx = msg->rx_buf;
1211 unsigned int i, j, k;
1212 size_t size = 0;
1213 u16 errors;
1214 u32 value;
1215
1216 /* read and parse packet header */
1217 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1218
1219 switch (value & 0x3f) {
1220 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1221 errors = (value >> 8) & 0xffff;
1222 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1223 errors);
1224 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1225 if (errors & BIT(i))
1226 dev_dbg(dsi->dev, " %2u: %s\n", i,
1227 error_report[i]);
1228 break;
1229
1230 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1231 rx[0] = (value >> 8) & 0xff;
1232 size = 1;
1233 break;
1234
1235 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1236 rx[0] = (value >> 8) & 0xff;
1237 rx[1] = (value >> 16) & 0xff;
1238 size = 2;
1239 break;
1240
1241 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1242 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1243 break;
1244
1245 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1246 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1247 break;
1248
1249 default:
1250 dev_err(dsi->dev, "unhandled response type: %02x\n",
1251 value & 0x3f);
1252 return -EPROTO;
1253 }
1254
1255 size = min(size, msg->rx_len);
1256
1257 if (msg->rx_buf && size > 0) {
1258 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1259 u8 *rx = msg->rx_buf + j;
1260
1261 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1262
1263 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1264 rx[j + k] = (value >> (k << 3)) & 0xff;
1265 }
1266 }
1267
1268 return size;
1269 }
1270
tegra_dsi_transmit(struct tegra_dsi * dsi,unsigned long timeout)1271 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1272 {
1273 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1274
1275 timeout = jiffies + msecs_to_jiffies(timeout);
1276
1277 while (time_before(jiffies, timeout)) {
1278 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1279 if ((value & DSI_TRIGGER_HOST) == 0)
1280 return 0;
1281
1282 usleep_range(1000, 2000);
1283 }
1284
1285 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1286 return -ETIMEDOUT;
1287 }
1288
tegra_dsi_wait_for_response(struct tegra_dsi * dsi,unsigned long timeout)1289 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1290 unsigned long timeout)
1291 {
1292 timeout = jiffies + msecs_to_jiffies(250);
1293
1294 while (time_before(jiffies, timeout)) {
1295 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1296 u8 count = value & 0x1f;
1297
1298 if (count > 0)
1299 return count;
1300
1301 usleep_range(1000, 2000);
1302 }
1303
1304 DRM_DEBUG_KMS("peripheral returned no data\n");
1305 return -ETIMEDOUT;
1306 }
1307
tegra_dsi_writesl(struct tegra_dsi * dsi,unsigned long offset,const void * buffer,size_t size)1308 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1309 const void *buffer, size_t size)
1310 {
1311 const u8 *buf = buffer;
1312 size_t i, j;
1313 u32 value;
1314
1315 for (j = 0; j < size; j += 4) {
1316 value = 0;
1317
1318 for (i = 0; i < 4 && j + i < size; i++)
1319 value |= buf[j + i] << (i << 3);
1320
1321 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1322 }
1323 }
1324
tegra_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1325 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1326 const struct mipi_dsi_msg *msg)
1327 {
1328 struct tegra_dsi *dsi = host_to_tegra(host);
1329 struct mipi_dsi_packet packet;
1330 const u8 *header;
1331 size_t count;
1332 ssize_t err;
1333 u32 value;
1334
1335 err = mipi_dsi_create_packet(&packet, msg);
1336 if (err < 0)
1337 return err;
1338
1339 header = packet.header;
1340
1341 /* maximum FIFO depth is 1920 words */
1342 if (packet.size > dsi->video_fifo_depth * 4)
1343 return -ENOSPC;
1344
1345 /* reset underflow/overflow flags */
1346 value = tegra_dsi_readl(dsi, DSI_STATUS);
1347 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1348 value = DSI_HOST_CONTROL_FIFO_RESET;
1349 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1350 usleep_range(10, 20);
1351 }
1352
1353 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1354 value |= DSI_POWER_CONTROL_ENABLE;
1355 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1356
1357 usleep_range(5000, 10000);
1358
1359 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1360 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1361
1362 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1363 value |= DSI_HOST_CONTROL_HS;
1364
1365 /*
1366 * The host FIFO has a maximum of 64 words, so larger transmissions
1367 * need to use the video FIFO.
1368 */
1369 if (packet.size > dsi->host_fifo_depth * 4)
1370 value |= DSI_HOST_CONTROL_FIFO_SEL;
1371
1372 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1373
1374 /*
1375 * For reads and messages with explicitly requested ACK, generate a
1376 * BTA sequence after the transmission of the packet.
1377 */
1378 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1379 (msg->rx_buf && msg->rx_len > 0)) {
1380 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1381 value |= DSI_HOST_CONTROL_PKT_BTA;
1382 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1383 }
1384
1385 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1386 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1387
1388 /* write packet header, ECC is generated by hardware */
1389 value = header[2] << 16 | header[1] << 8 | header[0];
1390 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1391
1392 /* write payload (if any) */
1393 if (packet.payload_length > 0)
1394 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1395 packet.payload_length);
1396
1397 err = tegra_dsi_transmit(dsi, 250);
1398 if (err < 0)
1399 return err;
1400
1401 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1402 (msg->rx_buf && msg->rx_len > 0)) {
1403 err = tegra_dsi_wait_for_response(dsi, 250);
1404 if (err < 0)
1405 return err;
1406
1407 count = err;
1408
1409 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1410 switch (value) {
1411 case 0x84:
1412 /*
1413 dev_dbg(dsi->dev, "ACK\n");
1414 */
1415 break;
1416
1417 case 0x87:
1418 /*
1419 dev_dbg(dsi->dev, "ESCAPE\n");
1420 */
1421 break;
1422
1423 default:
1424 dev_err(dsi->dev, "unknown status: %08x\n", value);
1425 break;
1426 }
1427
1428 if (count > 1) {
1429 err = tegra_dsi_read_response(dsi, msg, count);
1430 if (err < 0)
1431 dev_err(dsi->dev,
1432 "failed to parse response: %zd\n",
1433 err);
1434 else {
1435 /*
1436 * For read commands, return the number of
1437 * bytes returned by the peripheral.
1438 */
1439 count = err;
1440 }
1441 }
1442 } else {
1443 /*
1444 * For write commands, we have transmitted the 4-byte header
1445 * plus the variable-length payload.
1446 */
1447 count = 4 + packet.payload_length;
1448 }
1449
1450 return count;
1451 }
1452
tegra_dsi_ganged_setup(struct tegra_dsi * dsi)1453 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1454 {
1455 struct clk *parent;
1456 int err;
1457
1458 /* make sure both DSI controllers share the same PLL */
1459 parent = clk_get_parent(dsi->slave->clk);
1460 if (!parent)
1461 return -EINVAL;
1462
1463 err = clk_set_parent(parent, dsi->clk_parent);
1464 if (err < 0)
1465 return err;
1466
1467 return 0;
1468 }
1469
tegra_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1470 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1471 struct mipi_dsi_device *device)
1472 {
1473 struct tegra_dsi *dsi = host_to_tegra(host);
1474
1475 dsi->flags = device->mode_flags;
1476 dsi->format = device->format;
1477 dsi->lanes = device->lanes;
1478
1479 if (dsi->slave) {
1480 int err;
1481
1482 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1483 dev_name(&device->dev));
1484
1485 err = tegra_dsi_ganged_setup(dsi);
1486 if (err < 0) {
1487 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1488 err);
1489 return err;
1490 }
1491 }
1492
1493 /*
1494 * Slaves don't have a panel associated with them, so they provide
1495 * merely the second channel.
1496 */
1497 if (!dsi->master) {
1498 struct tegra_output *output = &dsi->output;
1499
1500 output->panel = of_drm_find_panel(device->dev.of_node);
1501 if (IS_ERR(output->panel))
1502 output->panel = NULL;
1503
1504 if (output->panel && output->connector.dev)
1505 drm_helper_hpd_irq_event(output->connector.dev);
1506 }
1507
1508 return 0;
1509 }
1510
tegra_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1511 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1512 struct mipi_dsi_device *device)
1513 {
1514 struct tegra_dsi *dsi = host_to_tegra(host);
1515 struct tegra_output *output = &dsi->output;
1516
1517 if (output->panel && &device->dev == output->panel->dev) {
1518 output->panel = NULL;
1519
1520 if (output->connector.dev)
1521 drm_helper_hpd_irq_event(output->connector.dev);
1522 }
1523
1524 return 0;
1525 }
1526
1527 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1528 .attach = tegra_dsi_host_attach,
1529 .detach = tegra_dsi_host_detach,
1530 .transfer = tegra_dsi_host_transfer,
1531 };
1532
tegra_dsi_ganged_probe(struct tegra_dsi * dsi)1533 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1534 {
1535 struct device_node *np;
1536
1537 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1538 if (np) {
1539 struct platform_device *gangster = of_find_device_by_node(np);
1540 of_node_put(np);
1541 if (!gangster)
1542 return -EPROBE_DEFER;
1543
1544 dsi->slave = platform_get_drvdata(gangster);
1545
1546 if (!dsi->slave) {
1547 put_device(&gangster->dev);
1548 return -EPROBE_DEFER;
1549 }
1550
1551 dsi->slave->master = dsi;
1552 }
1553
1554 return 0;
1555 }
1556
tegra_dsi_probe(struct platform_device * pdev)1557 static int tegra_dsi_probe(struct platform_device *pdev)
1558 {
1559 struct tegra_dsi *dsi;
1560 int err;
1561
1562 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1563 if (!dsi)
1564 return -ENOMEM;
1565
1566 dsi->output.dev = dsi->dev = &pdev->dev;
1567 dsi->video_fifo_depth = 1920;
1568 dsi->host_fifo_depth = 64;
1569
1570 err = tegra_dsi_ganged_probe(dsi);
1571 if (err < 0)
1572 return err;
1573
1574 err = tegra_output_probe(&dsi->output);
1575 if (err < 0)
1576 return err;
1577
1578 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1579
1580 /*
1581 * Assume these values by default. When a DSI peripheral driver
1582 * attaches to the DSI host, the parameters will be taken from
1583 * the attached device.
1584 */
1585 dsi->flags = MIPI_DSI_MODE_VIDEO;
1586 dsi->format = MIPI_DSI_FMT_RGB888;
1587 dsi->lanes = 4;
1588
1589 if (!pdev->dev.pm_domain) {
1590 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1591 if (IS_ERR(dsi->rst)) {
1592 err = PTR_ERR(dsi->rst);
1593 goto remove;
1594 }
1595 }
1596
1597 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1598 if (IS_ERR(dsi->clk)) {
1599 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk),
1600 "cannot get DSI clock\n");
1601 goto remove;
1602 }
1603
1604 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1605 if (IS_ERR(dsi->clk_lp)) {
1606 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_lp),
1607 "cannot get low-power clock\n");
1608 goto remove;
1609 }
1610
1611 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1612 if (IS_ERR(dsi->clk_parent)) {
1613 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->clk_parent),
1614 "cannot get parent clock\n");
1615 goto remove;
1616 }
1617
1618 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1619 if (IS_ERR(dsi->vdd)) {
1620 err = dev_err_probe(&pdev->dev, PTR_ERR(dsi->vdd),
1621 "cannot get VDD supply\n");
1622 goto remove;
1623 }
1624
1625 err = tegra_dsi_setup_clocks(dsi);
1626 if (err < 0) {
1627 dev_err(&pdev->dev, "cannot setup clocks\n");
1628 goto remove;
1629 }
1630
1631 dsi->regs = devm_platform_ioremap_resource(pdev, 0);
1632 if (IS_ERR(dsi->regs)) {
1633 err = PTR_ERR(dsi->regs);
1634 goto remove;
1635 }
1636
1637 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node);
1638 if (IS_ERR(dsi->mipi)) {
1639 err = PTR_ERR(dsi->mipi);
1640 goto remove;
1641 }
1642
1643 dsi->host.ops = &tegra_dsi_host_ops;
1644 dsi->host.dev = &pdev->dev;
1645
1646 err = mipi_dsi_host_register(&dsi->host);
1647 if (err < 0) {
1648 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1649 goto mipi_free;
1650 }
1651
1652 platform_set_drvdata(pdev, dsi);
1653 pm_runtime_enable(&pdev->dev);
1654
1655 INIT_LIST_HEAD(&dsi->client.list);
1656 dsi->client.ops = &dsi_client_ops;
1657 dsi->client.dev = &pdev->dev;
1658
1659 err = host1x_client_register(&dsi->client);
1660 if (err < 0) {
1661 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1662 err);
1663 goto unregister;
1664 }
1665
1666 return 0;
1667
1668 unregister:
1669 pm_runtime_disable(&pdev->dev);
1670 mipi_dsi_host_unregister(&dsi->host);
1671 mipi_free:
1672 tegra_mipi_free(dsi->mipi);
1673 remove:
1674 tegra_output_remove(&dsi->output);
1675 return err;
1676 }
1677
tegra_dsi_remove(struct platform_device * pdev)1678 static void tegra_dsi_remove(struct platform_device *pdev)
1679 {
1680 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1681
1682 pm_runtime_disable(&pdev->dev);
1683
1684 host1x_client_unregister(&dsi->client);
1685
1686 tegra_output_remove(&dsi->output);
1687
1688 mipi_dsi_host_unregister(&dsi->host);
1689 tegra_mipi_free(dsi->mipi);
1690 }
1691
1692 static const struct of_device_id tegra_dsi_of_match[] = {
1693 { .compatible = "nvidia,tegra210-dsi", },
1694 { .compatible = "nvidia,tegra132-dsi", },
1695 { .compatible = "nvidia,tegra124-dsi", },
1696 { .compatible = "nvidia,tegra114-dsi", },
1697 { },
1698 };
1699 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1700
1701 struct platform_driver tegra_dsi_driver = {
1702 .driver = {
1703 .name = "tegra-dsi",
1704 .of_match_table = tegra_dsi_of_match,
1705 },
1706 .probe = tegra_dsi_probe,
1707 .remove = tegra_dsi_remove,
1708 };
1709