1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dma-resv.h> 28 #include <linux/i2c.h> 29 #include <linux/input.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_dp_helper.h> 36 #include <drm/display/drm_dp_tunnel.h> 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_atomic_uapi.h> 40 #include <drm/drm_damage_helper.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_fixed.h> 43 #include <drm/drm_fourcc.h> 44 #include <drm/drm_print.h> 45 #include <drm/drm_probe_helper.h> 46 #include <drm/drm_rect.h> 47 #include <drm/drm_vblank.h> 48 49 #include "g4x_dp.h" 50 #include "g4x_hdmi.h" 51 #include "hsw_ips.h" 52 #include "i915_config.h" 53 #include "i915_reg.h" 54 #include "i9xx_plane.h" 55 #include "i9xx_plane_regs.h" 56 #include "i9xx_wm.h" 57 #include "intel_alpm.h" 58 #include "intel_atomic.h" 59 #include "intel_audio.h" 60 #include "intel_bo.h" 61 #include "intel_bw.h" 62 #include "intel_casf.h" 63 #include "intel_cdclk.h" 64 #include "intel_clock_gating.h" 65 #include "intel_color.h" 66 #include "intel_crt.h" 67 #include "intel_crtc.h" 68 #include "intel_crtc_state_dump.h" 69 #include "intel_cursor.h" 70 #include "intel_cursor_regs.h" 71 #include "intel_cx0_phy.h" 72 #include "intel_ddi.h" 73 #include "intel_de.h" 74 #include "intel_display_driver.h" 75 #include "intel_display_power.h" 76 #include "intel_display_regs.h" 77 #include "intel_display_rpm.h" 78 #include "intel_display_types.h" 79 #include "intel_display_utils.h" 80 #include "intel_display_wa.h" 81 #include "intel_dmc.h" 82 #include "intel_dp.h" 83 #include "intel_dp_link_training.h" 84 #include "intel_dp_mst.h" 85 #include "intel_dp_tunnel.h" 86 #include "intel_dpll.h" 87 #include "intel_dpll_mgr.h" 88 #include "intel_dpt.h" 89 #include "intel_dpt_common.h" 90 #include "intel_drrs.h" 91 #include "intel_dsb.h" 92 #include "intel_dsi.h" 93 #include "intel_dvo.h" 94 #include "intel_fb.h" 95 #include "intel_fbc.h" 96 #include "intel_fdi.h" 97 #include "intel_fifo_underrun.h" 98 #include "intel_flipq.h" 99 #include "intel_frontbuffer.h" 100 #include "intel_hdmi.h" 101 #include "intel_hotplug.h" 102 #include "intel_initial_plane.h" 103 #include "intel_link_bw.h" 104 #include "intel_lt_phy.h" 105 #include "intel_lvds.h" 106 #include "intel_lvds_regs.h" 107 #include "intel_modeset_setup.h" 108 #include "intel_modeset_verify.h" 109 #include "intel_overlay.h" 110 #include "intel_panel.h" 111 #include "intel_pch_display.h" 112 #include "intel_pch_refclk.h" 113 #include "intel_pfit.h" 114 #include "intel_pipe_crc.h" 115 #include "intel_plane.h" 116 #include "intel_pmdemand.h" 117 #include "intel_pps.h" 118 #include "intel_psr.h" 119 #include "intel_psr_regs.h" 120 #include "intel_sdvo.h" 121 #include "intel_snps_phy.h" 122 #include "intel_tc.h" 123 #include "intel_tdf.h" 124 #include "intel_tv.h" 125 #include "intel_vblank.h" 126 #include "intel_vdsc.h" 127 #include "intel_vdsc_regs.h" 128 #include "intel_vga.h" 129 #include "intel_vrr.h" 130 #include "intel_wm.h" 131 #include "skl_scaler.h" 132 #include "skl_universal_plane.h" 133 #include "skl_watermark.h" 134 #include "vlv_dsi.h" 135 #include "vlv_dsi_pll.h" 136 #include "vlv_dsi_regs.h" 137 138 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state); 139 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); 140 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state); 141 static void bdw_set_pipe_misc(struct intel_dsb *dsb, 142 const struct intel_crtc_state *crtc_state); 143 144 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) 145 { 146 return (crtc_state->active_planes & 147 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0; 148 } 149 150 /* WA Display #0827: Gen9:all */ 151 static void 152 skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) 153 { 154 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 155 DUPS1_GATING_DIS | DUPS2_GATING_DIS, 156 enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0); 157 } 158 159 /* Wa_2006604312:icl,ehl */ 160 static void 161 icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, 162 bool enable) 163 { 164 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 165 DPFR_GATING_DIS, 166 enable ? DPFR_GATING_DIS : 0); 167 } 168 169 /* Wa_1604331009:icl,jsl,ehl */ 170 static void 171 icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, 172 bool enable) 173 { 174 intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), 175 CURSOR_GATING_DIS, 176 enable ? CURSOR_GATING_DIS : 0); 177 } 178 179 static bool 180 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) 181 { 182 return crtc_state->master_transcoder != INVALID_TRANSCODER; 183 } 184 185 bool 186 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) 187 { 188 return crtc_state->sync_mode_slaves_mask != 0; 189 } 190 191 bool 192 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) 193 { 194 return is_trans_port_sync_master(crtc_state) || 195 is_trans_port_sync_slave(crtc_state); 196 } 197 198 static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state) 199 { 200 return ffs(crtc_state->joiner_pipes) - 1; 201 } 202 203 /* 204 * The following helper functions, despite being named for bigjoiner, 205 * are applicable to both bigjoiner and uncompressed joiner configurations. 206 */ 207 static bool is_bigjoiner(const struct intel_crtc_state *crtc_state) 208 { 209 return hweight8(crtc_state->joiner_pipes) >= 2; 210 } 211 212 static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state) 213 { 214 if (!is_bigjoiner(crtc_state)) 215 return 0; 216 217 return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state)); 218 } 219 220 static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 221 { 222 if (!is_bigjoiner(crtc_state)) 223 return 0; 224 225 return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state)); 226 } 227 228 bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state) 229 { 230 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 231 232 if (!is_bigjoiner(crtc_state)) 233 return false; 234 235 return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state); 236 } 237 238 bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state) 239 { 240 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 241 242 if (!is_bigjoiner(crtc_state)) 243 return false; 244 245 return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state); 246 } 247 248 u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state) 249 { 250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 251 252 if (!is_bigjoiner(crtc_state)) 253 return BIT(crtc->pipe); 254 255 return bigjoiner_primary_pipes(crtc_state); 256 } 257 258 u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state) 259 { 260 return bigjoiner_secondary_pipes(crtc_state); 261 } 262 263 bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state) 264 { 265 return intel_crtc_num_joined_pipes(crtc_state) >= 4; 266 } 267 268 static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state) 269 { 270 if (!intel_crtc_is_ultrajoiner(crtc_state)) 271 return 0; 272 273 return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state)); 274 } 275 276 bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state) 277 { 278 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 279 280 return intel_crtc_is_ultrajoiner(crtc_state) && 281 BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state); 282 } 283 284 /* 285 * The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or 286 * any other logic, so lets just add helper function to 287 * at least hide this hassle.. 288 */ 289 static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state) 290 { 291 if (!intel_crtc_is_ultrajoiner(crtc_state)) 292 return 0; 293 294 return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state)); 295 } 296 297 bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state) 298 { 299 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 300 301 return intel_crtc_is_ultrajoiner(crtc_state) && 302 BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state); 303 } 304 305 u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) 306 { 307 if (crtc_state->joiner_pipes) 308 return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state)); 309 else 310 return 0; 311 } 312 313 bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) 314 { 315 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 316 317 return crtc_state->joiner_pipes && 318 crtc->pipe != joiner_primary_pipe(crtc_state); 319 } 320 321 bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state) 322 { 323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 324 325 return crtc_state->joiner_pipes && 326 crtc->pipe == joiner_primary_pipe(crtc_state); 327 } 328 329 int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state) 330 { 331 return hweight8(intel_crtc_joined_pipe_mask(crtc_state)); 332 } 333 334 u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) 335 { 336 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 337 338 return BIT(crtc->pipe) | crtc_state->joiner_pipes; 339 } 340 341 struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) 342 { 343 struct intel_display *display = to_intel_display(crtc_state); 344 345 if (intel_crtc_is_joiner_secondary(crtc_state)) 346 return intel_crtc_for_pipe(display, joiner_primary_pipe(crtc_state)); 347 else 348 return to_intel_crtc(crtc_state->uapi.crtc); 349 } 350 351 static void 352 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) 353 { 354 struct intel_display *display = to_intel_display(old_crtc_state); 355 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 356 357 if (DISPLAY_VER(display) >= 4) { 358 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 359 360 /* Wait for the Pipe State to go off */ 361 if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder), 362 TRANSCONF_STATE_ENABLE, 100)) 363 drm_WARN(display->drm, 1, "pipe_off wait timed out\n"); 364 } else { 365 intel_wait_for_pipe_scanline_stopped(crtc); 366 } 367 } 368 369 void assert_transcoder(struct intel_display *display, 370 enum transcoder cpu_transcoder, bool state) 371 { 372 bool cur_state; 373 enum intel_display_power_domain power_domain; 374 struct ref_tracker *wakeref; 375 376 /* we keep both pipes enabled on 830 */ 377 if (display->platform.i830) 378 state = true; 379 380 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 381 wakeref = intel_display_power_get_if_enabled(display, power_domain); 382 if (wakeref) { 383 u32 val = intel_de_read(display, 384 TRANSCONF(display, cpu_transcoder)); 385 cur_state = !!(val & TRANSCONF_ENABLE); 386 387 intel_display_power_put(display, power_domain, wakeref); 388 } else { 389 cur_state = false; 390 } 391 392 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 393 "transcoder %s assertion failure (expected %s, current %s)\n", 394 transcoder_name(cpu_transcoder), str_on_off(state), 395 str_on_off(cur_state)); 396 } 397 398 static void assert_plane(struct intel_plane *plane, bool state) 399 { 400 struct intel_display *display = to_intel_display(plane->base.dev); 401 enum pipe pipe; 402 bool cur_state; 403 404 cur_state = plane->get_hw_state(plane, &pipe); 405 406 INTEL_DISPLAY_STATE_WARN(display, cur_state != state, 407 "%s assertion failure (expected %s, current %s)\n", 408 plane->base.name, str_on_off(state), 409 str_on_off(cur_state)); 410 } 411 412 #define assert_plane_enabled(p) assert_plane(p, true) 413 #define assert_plane_disabled(p) assert_plane(p, false) 414 415 static void assert_planes_disabled(struct intel_crtc *crtc) 416 { 417 struct intel_display *display = to_intel_display(crtc); 418 struct intel_plane *plane; 419 420 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 421 assert_plane_disabled(plane); 422 } 423 424 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 425 { 426 struct intel_display *display = to_intel_display(new_crtc_state); 427 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 428 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 429 enum pipe pipe = crtc->pipe; 430 u32 val; 431 432 drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe)); 433 434 assert_planes_disabled(crtc); 435 436 /* 437 * A pipe without a PLL won't actually be able to drive bits from 438 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 439 * need the check. 440 */ 441 if (HAS_GMCH(display)) { 442 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) 443 assert_dsi_pll_enabled(display); 444 else 445 assert_pll_enabled(display, pipe); 446 } else { 447 if (new_crtc_state->has_pch_encoder) { 448 /* if driving the PCH, we need FDI enabled */ 449 assert_fdi_rx_pll_enabled(display, 450 intel_crtc_pch_transcoder(crtc)); 451 assert_fdi_tx_pll_enabled(display, 452 (enum pipe) cpu_transcoder); 453 } 454 /* FIXME: assert CPU port conditions for SNB+ */ 455 } 456 457 /* Wa_22012358565:adl-p */ 458 if (DISPLAY_VER(display) == 13) 459 intel_de_rmw(display, PIPE_ARB_CTL(display, pipe), 460 0, PIPE_ARB_USE_PROG_SLOTS); 461 462 if (DISPLAY_VER(display) >= 14) { 463 u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; 464 u32 set = 0; 465 466 if (DISPLAY_VER(display) == 14) 467 set |= DP_FEC_BS_JITTER_WA; 468 469 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 470 clear, set); 471 } 472 473 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 474 if (val & TRANSCONF_ENABLE) { 475 /* we keep both pipes enabled on 830 */ 476 drm_WARN_ON(display->drm, !display->platform.i830); 477 return; 478 } 479 480 /* Wa_1409098942:adlp+ */ 481 if (DISPLAY_VER(display) >= 13 && 482 new_crtc_state->dsc.compression_enable) { 483 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 484 val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK, 485 TRANSCONF_PIXEL_COUNT_SCALING_X4); 486 } 487 488 intel_de_write(display, TRANSCONF(display, cpu_transcoder), 489 val | TRANSCONF_ENABLE); 490 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 491 492 /* 493 * Until the pipe starts PIPEDSL reads will return a stale value, 494 * which causes an apparent vblank timestamp jump when PIPEDSL 495 * resets to its proper value. That also messes up the frame count 496 * when it's derived from the timestamps. So let's wait for the 497 * pipe to start properly before we call drm_crtc_vblank_on() 498 */ 499 if (intel_crtc_max_vblank_count(new_crtc_state) == 0) 500 intel_wait_for_pipe_scanline_moving(crtc); 501 } 502 503 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 504 { 505 struct intel_display *display = to_intel_display(old_crtc_state); 506 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 507 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 508 enum pipe pipe = crtc->pipe; 509 u32 val; 510 511 drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe)); 512 513 /* 514 * Make sure planes won't keep trying to pump pixels to us, 515 * or we might hang the display. 516 */ 517 assert_planes_disabled(crtc); 518 519 val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 520 if ((val & TRANSCONF_ENABLE) == 0) 521 return; 522 523 /* 524 * Double wide has implications for planes 525 * so best keep it disabled when not needed. 526 */ 527 if (old_crtc_state->double_wide) 528 val &= ~TRANSCONF_DOUBLE_WIDE; 529 530 /* Don't disable pipe or pipe PLLs if needed */ 531 if (!display->platform.i830) 532 val &= ~TRANSCONF_ENABLE; 533 534 /* Wa_1409098942:adlp+ */ 535 if (DISPLAY_VER(display) >= 13 && 536 old_crtc_state->dsc.compression_enable) 537 val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; 538 539 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 540 541 if (DISPLAY_VER(display) >= 12) 542 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 543 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 544 545 if ((val & TRANSCONF_ENABLE) == 0) 546 intel_wait_for_pipe_off(old_crtc_state); 547 } 548 549 u32 intel_plane_fb_max_stride(struct intel_display *display, 550 const struct drm_format_info *info, 551 u64 modifier) 552 { 553 struct intel_crtc *crtc; 554 struct intel_plane *plane; 555 556 /* 557 * We assume the primary plane for pipe A has 558 * the highest stride limits of them all, 559 * if in case pipe A is disabled, use the first pipe from pipe_mask. 560 */ 561 crtc = intel_first_crtc(display); 562 if (!crtc) 563 return 0; 564 565 plane = to_intel_plane(crtc->base.primary); 566 567 return plane->max_stride(plane, info, modifier, 568 DRM_MODE_ROTATE_0); 569 } 570 571 u32 intel_dumb_fb_max_stride(struct drm_device *drm, 572 u32 pixel_format, u64 modifier) 573 { 574 struct intel_display *display = to_intel_display(drm); 575 576 if (!HAS_DISPLAY(display)) 577 return 0; 578 579 return intel_plane_fb_max_stride(display, 580 drm_get_format_info(drm, pixel_format, modifier), 581 modifier); 582 } 583 584 void intel_set_plane_visible(struct intel_crtc_state *crtc_state, 585 struct intel_plane_state *plane_state, 586 bool visible) 587 { 588 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 589 590 plane_state->uapi.visible = visible; 591 592 if (visible) 593 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); 594 else 595 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); 596 } 597 598 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) 599 { 600 struct intel_display *display = to_intel_display(crtc_state); 601 struct drm_plane *plane; 602 603 /* 604 * Active_planes aliases if multiple "primary" or cursor planes 605 * have been used on the same (or wrong) pipe. plane_mask uses 606 * unique ids, hence we can use that to reconstruct active_planes. 607 */ 608 crtc_state->enabled_planes = 0; 609 crtc_state->active_planes = 0; 610 611 drm_for_each_plane_mask(plane, display->drm, 612 crtc_state->uapi.plane_mask) { 613 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); 614 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); 615 } 616 } 617 618 void intel_plane_disable_noatomic(struct intel_crtc *crtc, 619 struct intel_plane *plane) 620 { 621 struct intel_display *display = to_intel_display(crtc); 622 struct intel_crtc_state *crtc_state = 623 to_intel_crtc_state(crtc->base.state); 624 struct intel_plane_state *plane_state = 625 to_intel_plane_state(plane->base.state); 626 627 drm_dbg_kms(display->drm, 628 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", 629 plane->base.base.id, plane->base.name, 630 crtc->base.base.id, crtc->base.name); 631 632 intel_plane_set_invisible(crtc_state, plane_state); 633 intel_set_plane_visible(crtc_state, plane_state, false); 634 intel_plane_fixup_bitmasks(crtc_state); 635 636 skl_wm_plane_disable_noatomic(crtc, plane); 637 638 if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && 639 hsw_ips_disable(crtc_state)) { 640 crtc_state->ips_enabled = false; 641 intel_initial_plane_vblank_wait(crtc); 642 } 643 644 /* 645 * Vblank time updates from the shadow to live plane control register 646 * are blocked if the memory self-refresh mode is active at that 647 * moment. So to make sure the plane gets truly disabled, disable 648 * first the self-refresh mode. The self-refresh enable bit in turn 649 * will be checked/applied by the HW only at the next frame start 650 * event which is after the vblank start event, so we need to have a 651 * wait-for-vblank between disabling the plane and the pipe. 652 */ 653 if (HAS_GMCH(display) && 654 intel_set_memory_cxsr(display, false)) 655 intel_initial_plane_vblank_wait(crtc); 656 657 /* 658 * Gen2 reports pipe underruns whenever all planes are disabled. 659 * So disable underrun reporting before all the planes get disabled. 660 */ 661 if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes) 662 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false); 663 664 intel_plane_disable_arm(NULL, plane, crtc_state); 665 intel_initial_plane_vblank_wait(crtc); 666 } 667 668 unsigned int 669 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) 670 { 671 int x = 0, y = 0; 672 673 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, 674 plane_state->view.color_plane[0].offset, 0); 675 676 return y; 677 } 678 679 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) 680 { 681 struct intel_display *display = to_intel_display(crtc_state); 682 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 683 enum pipe pipe = crtc->pipe; 684 u32 tmp; 685 686 tmp = intel_de_read(display, PIPE_CHICKEN(pipe)); 687 688 /* 689 * Display WA #1153: icl 690 * enable hardware to bypass the alpha math 691 * and rounding for per-pixel values 00 and 0xff 692 */ 693 tmp |= PER_PIXEL_ALPHA_BYPASS_EN; 694 /* 695 * Display WA # 1605353570: icl 696 * Set the pixel rounding bit to 1 for allowing 697 * passthrough of Frame buffer pixels unmodified 698 * across pipe 699 */ 700 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; 701 702 /* 703 * Underrun recovery must always be disabled on display 13+. 704 * DG2 chicken bit meaning is inverted compared to other platforms. 705 */ 706 if (display->platform.dg2) 707 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; 708 else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30)) 709 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; 710 711 /* Wa_14010547955:dg2 */ 712 if (display->platform.dg2) 713 tmp |= DG2_RENDER_CCSTAG_4_3_EN; 714 715 intel_de_write(display, PIPE_CHICKEN(pipe), tmp); 716 } 717 718 bool intel_has_pending_fb_unpin(struct intel_display *display) 719 { 720 struct drm_crtc *crtc; 721 bool cleanup_done; 722 723 drm_for_each_crtc(crtc, display->drm) { 724 struct drm_crtc_commit *commit; 725 spin_lock(&crtc->commit_lock); 726 commit = list_first_entry_or_null(&crtc->commit_list, 727 struct drm_crtc_commit, commit_entry); 728 cleanup_done = commit ? 729 try_wait_for_completion(&commit->cleanup_done) : true; 730 spin_unlock(&crtc->commit_lock); 731 732 if (cleanup_done) 733 continue; 734 735 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc)); 736 737 return true; 738 } 739 740 return false; 741 } 742 743 /* 744 * Finds the encoder associated with the given CRTC. This can only be 745 * used when we know that the CRTC isn't feeding multiple encoders! 746 */ 747 struct intel_encoder * 748 intel_get_crtc_new_encoder(const struct intel_atomic_state *state, 749 const struct intel_crtc_state *crtc_state) 750 { 751 const struct drm_connector_state *connector_state; 752 const struct drm_connector *connector; 753 struct intel_encoder *encoder = NULL; 754 struct intel_crtc *primary_crtc; 755 int num_encoders = 0; 756 int i; 757 758 primary_crtc = intel_primary_crtc(crtc_state); 759 760 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 761 if (connector_state->crtc != &primary_crtc->base) 762 continue; 763 764 encoder = to_intel_encoder(connector_state->best_encoder); 765 num_encoders++; 766 } 767 768 drm_WARN(state->base.dev, num_encoders != 1, 769 "%d encoders for pipe %c\n", 770 num_encoders, pipe_name(primary_crtc->pipe)); 771 772 return encoder; 773 } 774 775 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) 776 { 777 if (crtc->overlay) 778 (void) intel_overlay_switch_off(crtc->overlay); 779 780 /* Let userspace switch the overlay on again. In most cases userspace 781 * has to recompute where to put it anyway. 782 */ 783 } 784 785 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) 786 { 787 struct intel_display *display = to_intel_display(crtc_state); 788 789 if (!crtc_state->nv12_planes) 790 return false; 791 792 /* WA Display #0827: Gen9:all */ 793 if (DISPLAY_VER(display) == 9) 794 return true; 795 796 return false; 797 } 798 799 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) 800 { 801 struct intel_display *display = to_intel_display(crtc_state); 802 803 /* Wa_2006604312:icl,ehl */ 804 if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11) 805 return true; 806 807 return false; 808 } 809 810 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) 811 { 812 struct intel_display *display = to_intel_display(crtc_state); 813 814 /* Wa_1604331009:icl,jsl,ehl */ 815 if (is_hdr_mode(crtc_state) && 816 crtc_state->active_planes & BIT(PLANE_CURSOR) && 817 DISPLAY_VER(display) == 11) 818 return true; 819 820 return false; 821 } 822 823 static void intel_async_flip_vtd_wa(struct intel_display *display, 824 enum pipe pipe, bool enable) 825 { 826 if (DISPLAY_VER(display) == 9) { 827 /* 828 * "Plane N stretch max must be programmed to 11b (x1) 829 * when Async flips are enabled on that plane." 830 */ 831 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 832 SKL_PLANE1_STRETCH_MAX_MASK, 833 enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); 834 } else { 835 /* Also needed on HSW/BDW albeit undocumented */ 836 intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 837 HSW_PRI_STRETCH_MAX_MASK, 838 enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); 839 } 840 } 841 842 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) 843 { 844 struct intel_display *display = to_intel_display(crtc_state); 845 846 return crtc_state->uapi.async_flip && intel_display_vtd_active(display) && 847 (DISPLAY_VER(display) == 9 || display->platform.broadwell || 848 display->platform.haswell); 849 } 850 851 static void intel_encoders_audio_enable(struct intel_atomic_state *state, 852 struct intel_crtc *crtc) 853 { 854 const struct intel_crtc_state *crtc_state = 855 intel_atomic_get_new_crtc_state(state, crtc); 856 const struct drm_connector_state *conn_state; 857 struct drm_connector *conn; 858 int i; 859 860 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 861 struct intel_encoder *encoder = 862 to_intel_encoder(conn_state->best_encoder); 863 864 if (conn_state->crtc != &crtc->base) 865 continue; 866 867 if (encoder->audio_enable) 868 encoder->audio_enable(encoder, crtc_state, conn_state); 869 } 870 } 871 872 static void intel_encoders_audio_disable(struct intel_atomic_state *state, 873 struct intel_crtc *crtc) 874 { 875 const struct intel_crtc_state *old_crtc_state = 876 intel_atomic_get_old_crtc_state(state, crtc); 877 const struct drm_connector_state *old_conn_state; 878 struct drm_connector *conn; 879 int i; 880 881 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 882 struct intel_encoder *encoder = 883 to_intel_encoder(old_conn_state->best_encoder); 884 885 if (old_conn_state->crtc != &crtc->base) 886 continue; 887 888 if (encoder->audio_disable) 889 encoder->audio_disable(encoder, old_crtc_state, old_conn_state); 890 } 891 } 892 893 #define is_enabling(feature, old_crtc_state, new_crtc_state) \ 894 ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \ 895 (new_crtc_state)->feature) 896 #define is_disabling(feature, old_crtc_state, new_crtc_state) \ 897 ((old_crtc_state)->feature && \ 898 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state))) 899 900 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state, 901 const struct intel_crtc_state *new_crtc_state) 902 { 903 if (!new_crtc_state->hw.active) 904 return false; 905 906 return is_enabling(active_planes, old_crtc_state, new_crtc_state); 907 } 908 909 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state, 910 const struct intel_crtc_state *new_crtc_state) 911 { 912 if (!old_crtc_state->hw.active) 913 return false; 914 915 return is_disabling(active_planes, old_crtc_state, new_crtc_state); 916 } 917 918 static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, 919 const struct intel_crtc_state *new_crtc_state) 920 { 921 return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline || 922 old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin || 923 old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax || 924 old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband || 925 old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full || 926 old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start || 927 old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end; 928 } 929 930 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, 931 const struct intel_crtc_state *new_crtc_state) 932 { 933 return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || 934 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; 935 } 936 937 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state, 938 struct intel_crtc *crtc) 939 { 940 const struct intel_crtc_state *old_crtc_state = 941 intel_atomic_get_old_crtc_state(state, crtc); 942 const struct intel_crtc_state *new_crtc_state = 943 intel_atomic_get_new_crtc_state(state, crtc); 944 945 if (!new_crtc_state->hw.active) 946 return false; 947 948 return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) || 949 (new_crtc_state->vrr.enable && 950 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 951 vrr_params_changed(old_crtc_state, new_crtc_state))); 952 } 953 954 bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 955 struct intel_crtc *crtc) 956 { 957 const struct intel_crtc_state *old_crtc_state = 958 intel_atomic_get_old_crtc_state(state, crtc); 959 const struct intel_crtc_state *new_crtc_state = 960 intel_atomic_get_new_crtc_state(state, crtc); 961 962 if (!old_crtc_state->hw.active) 963 return false; 964 965 return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) || 966 (old_crtc_state->vrr.enable && 967 (new_crtc_state->update_m_n || new_crtc_state->update_lrr || 968 vrr_params_changed(old_crtc_state, new_crtc_state))); 969 } 970 971 static bool audio_enabling(const struct intel_crtc_state *old_crtc_state, 972 const struct intel_crtc_state *new_crtc_state) 973 { 974 if (!new_crtc_state->hw.active) 975 return false; 976 977 return is_enabling(has_audio, old_crtc_state, new_crtc_state) || 978 (new_crtc_state->has_audio && 979 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 980 } 981 982 static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, 983 const struct intel_crtc_state *new_crtc_state) 984 { 985 if (!old_crtc_state->hw.active) 986 return false; 987 988 return is_disabling(has_audio, old_crtc_state, new_crtc_state) || 989 (old_crtc_state->has_audio && 990 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); 991 } 992 993 static bool intel_casf_enabling(const struct intel_crtc_state *new_crtc_state, 994 const struct intel_crtc_state *old_crtc_state) 995 { 996 if (!new_crtc_state->hw.active) 997 return false; 998 999 return is_enabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state); 1000 } 1001 1002 static bool intel_casf_disabling(const struct intel_crtc_state *old_crtc_state, 1003 const struct intel_crtc_state *new_crtc_state) 1004 { 1005 if (!new_crtc_state->hw.active) 1006 return false; 1007 1008 return is_disabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state); 1009 } 1010 1011 #undef is_disabling 1012 #undef is_enabling 1013 1014 static void intel_post_plane_update(struct intel_atomic_state *state, 1015 struct intel_crtc *crtc) 1016 { 1017 struct intel_display *display = to_intel_display(state); 1018 const struct intel_crtc_state *old_crtc_state = 1019 intel_atomic_get_old_crtc_state(state, crtc); 1020 const struct intel_crtc_state *new_crtc_state = 1021 intel_atomic_get_new_crtc_state(state, crtc); 1022 enum pipe pipe = crtc->pipe; 1023 1024 intel_frontbuffer_flip(display, new_crtc_state->fb_bits); 1025 1026 if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) 1027 intel_update_watermarks(display); 1028 1029 intel_fbc_post_update(state, crtc); 1030 1031 if (needs_async_flip_vtd_wa(old_crtc_state) && 1032 !needs_async_flip_vtd_wa(new_crtc_state)) 1033 intel_async_flip_vtd_wa(display, pipe, false); 1034 1035 if (needs_nv12_wa(old_crtc_state) && 1036 !needs_nv12_wa(new_crtc_state)) 1037 skl_wa_827(display, pipe, false); 1038 1039 if (needs_scalerclk_wa(old_crtc_state) && 1040 !needs_scalerclk_wa(new_crtc_state)) 1041 icl_wa_scalerclkgating(display, pipe, false); 1042 1043 if (needs_cursorclk_wa(old_crtc_state) && 1044 !needs_cursorclk_wa(new_crtc_state)) 1045 icl_wa_cursorclkgating(display, pipe, false); 1046 1047 if (intel_crtc_needs_color_update(new_crtc_state)) 1048 intel_color_post_update(new_crtc_state); 1049 1050 if (audio_enabling(old_crtc_state, new_crtc_state)) 1051 intel_encoders_audio_enable(state, crtc); 1052 1053 if (intel_display_wa(display, 14011503117)) { 1054 if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled) 1055 adl_scaler_ecc_unmask(new_crtc_state); 1056 } 1057 1058 intel_alpm_post_plane_update(state, crtc); 1059 1060 intel_psr_post_plane_update(state, crtc); 1061 } 1062 1063 static void intel_post_plane_update_after_readout(struct intel_atomic_state *state, 1064 struct intel_crtc *crtc) 1065 { 1066 const struct intel_crtc_state *new_crtc_state = 1067 intel_atomic_get_new_crtc_state(state, crtc); 1068 1069 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */ 1070 hsw_ips_post_update(state, crtc); 1071 1072 /* 1073 * Activate DRRS after state readout to avoid 1074 * dp_m_n vs. dp_m2_n2 confusion on BDW+. 1075 */ 1076 intel_drrs_activate(new_crtc_state); 1077 } 1078 1079 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state, 1080 struct intel_crtc *crtc) 1081 { 1082 const struct intel_crtc_state *crtc_state = 1083 intel_atomic_get_new_crtc_state(state, crtc); 1084 u8 update_planes = crtc_state->update_planes; 1085 const struct intel_plane_state __maybe_unused *plane_state; 1086 struct intel_plane *plane; 1087 int i; 1088 1089 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1090 if (plane->pipe == crtc->pipe && 1091 update_planes & BIT(plane->id)) 1092 plane->enable_flip_done(plane); 1093 } 1094 } 1095 1096 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state, 1097 struct intel_crtc *crtc) 1098 { 1099 const struct intel_crtc_state *crtc_state = 1100 intel_atomic_get_new_crtc_state(state, crtc); 1101 u8 update_planes = crtc_state->update_planes; 1102 const struct intel_plane_state __maybe_unused *plane_state; 1103 struct intel_plane *plane; 1104 int i; 1105 1106 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1107 if (plane->pipe == crtc->pipe && 1108 update_planes & BIT(plane->id)) 1109 plane->disable_flip_done(plane); 1110 } 1111 } 1112 1113 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, 1114 struct intel_crtc *crtc) 1115 { 1116 const struct intel_crtc_state *old_crtc_state = 1117 intel_atomic_get_old_crtc_state(state, crtc); 1118 const struct intel_crtc_state *new_crtc_state = 1119 intel_atomic_get_new_crtc_state(state, crtc); 1120 u8 disable_async_flip_planes = old_crtc_state->async_flip_planes & 1121 ~new_crtc_state->async_flip_planes; 1122 const struct intel_plane_state *old_plane_state; 1123 struct intel_plane *plane; 1124 bool need_vbl_wait = false; 1125 int i; 1126 1127 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1128 if (plane->need_async_flip_toggle_wa && 1129 plane->pipe == crtc->pipe && 1130 disable_async_flip_planes & BIT(plane->id)) { 1131 /* 1132 * Apart from the async flip bit we want to 1133 * preserve the old state for the plane. 1134 */ 1135 intel_plane_async_flip(NULL, plane, 1136 old_crtc_state, old_plane_state, false); 1137 need_vbl_wait = true; 1138 } 1139 } 1140 1141 if (need_vbl_wait) 1142 intel_crtc_wait_for_next_vblank(crtc); 1143 } 1144 1145 static void intel_pre_plane_update(struct intel_atomic_state *state, 1146 struct intel_crtc *crtc) 1147 { 1148 struct intel_display *display = to_intel_display(state); 1149 const struct intel_crtc_state *old_crtc_state = 1150 intel_atomic_get_old_crtc_state(state, crtc); 1151 const struct intel_crtc_state *new_crtc_state = 1152 intel_atomic_get_new_crtc_state(state, crtc); 1153 enum pipe pipe = crtc->pipe; 1154 1155 intel_alpm_pre_plane_update(state, crtc); 1156 intel_psr_pre_plane_update(state, crtc); 1157 1158 if (intel_crtc_vrr_disabling(state, crtc)) { 1159 intel_vrr_disable(old_crtc_state); 1160 intel_vrr_dcb_reset(old_crtc_state, crtc); 1161 intel_crtc_update_active_timings(old_crtc_state, false); 1162 } 1163 1164 if (audio_disabling(old_crtc_state, new_crtc_state)) 1165 intel_encoders_audio_disable(state, crtc); 1166 1167 if (intel_casf_disabling(old_crtc_state, new_crtc_state)) 1168 intel_casf_disable(new_crtc_state); 1169 1170 intel_drrs_deactivate(old_crtc_state); 1171 1172 if (hsw_ips_pre_update(state, crtc)) 1173 intel_crtc_wait_for_next_vblank(crtc); 1174 1175 if (intel_fbc_pre_update(state, crtc)) 1176 intel_crtc_wait_for_next_vblank(crtc); 1177 1178 if (!needs_async_flip_vtd_wa(old_crtc_state) && 1179 needs_async_flip_vtd_wa(new_crtc_state)) 1180 intel_async_flip_vtd_wa(display, pipe, true); 1181 1182 /* Display WA 827 */ 1183 if (!needs_nv12_wa(old_crtc_state) && 1184 needs_nv12_wa(new_crtc_state)) 1185 skl_wa_827(display, pipe, true); 1186 1187 /* Wa_2006604312:icl,ehl */ 1188 if (!needs_scalerclk_wa(old_crtc_state) && 1189 needs_scalerclk_wa(new_crtc_state)) 1190 icl_wa_scalerclkgating(display, pipe, true); 1191 1192 /* Wa_1604331009:icl,jsl,ehl */ 1193 if (!needs_cursorclk_wa(old_crtc_state) && 1194 needs_cursorclk_wa(new_crtc_state)) 1195 icl_wa_cursorclkgating(display, pipe, true); 1196 1197 /* 1198 * Vblank time updates from the shadow to live plane control register 1199 * are blocked if the memory self-refresh mode is active at that 1200 * moment. So to make sure the plane gets truly disabled, disable 1201 * first the self-refresh mode. The self-refresh enable bit in turn 1202 * will be checked/applied by the HW only at the next frame start 1203 * event which is after the vblank start event, so we need to have a 1204 * wait-for-vblank between disabling the plane and the pipe. 1205 */ 1206 if (HAS_GMCH(display) && old_crtc_state->hw.active && 1207 new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, false)) 1208 intel_crtc_wait_for_next_vblank(crtc); 1209 1210 /* 1211 * IVB workaround: must disable low power watermarks for at least 1212 * one frame before enabling scaling. LP watermarks can be re-enabled 1213 * when scaling is disabled. 1214 * 1215 * WaCxSRDisabledForSpriteScaling:ivb 1216 */ 1217 if (!HAS_GMCH(display) && old_crtc_state->hw.active && 1218 new_crtc_state->disable_cxsr && ilk_disable_cxsr(display)) 1219 intel_crtc_wait_for_next_vblank(crtc); 1220 1221 /* 1222 * If we're doing a modeset we don't need to do any 1223 * pre-vblank watermark programming here. 1224 */ 1225 if (!intel_crtc_needs_modeset(new_crtc_state)) { 1226 /* 1227 * For platforms that support atomic watermarks, program the 1228 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these 1229 * will be the intermediate values that are safe for both pre- and 1230 * post- vblank; when vblank happens, the 'active' values will be set 1231 * to the final 'target' values and we'll do this again to get the 1232 * optimal watermarks. For gen9+ platforms, the values we program here 1233 * will be the final target values which will get automatically latched 1234 * at vblank time; no further programming will be necessary. 1235 * 1236 * If a platform hasn't been transitioned to atomic watermarks yet, 1237 * we'll continue to update watermarks the old way, if flags tell 1238 * us to. 1239 */ 1240 if (!intel_initial_watermarks(state, crtc)) 1241 if (new_crtc_state->update_wm_pre) 1242 intel_update_watermarks(display); 1243 } 1244 1245 /* 1246 * Gen2 reports pipe underruns whenever all planes are disabled. 1247 * So disable underrun reporting before all the planes get disabled. 1248 * 1249 * We do this after .initial_watermarks() so that we have a 1250 * chance of catching underruns with the intermediate watermarks 1251 * vs. the old plane configuration. 1252 */ 1253 if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) 1254 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1255 1256 /* 1257 * WA for platforms where async address update enable bit 1258 * is double buffered and only latched at start of vblank. 1259 */ 1260 if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes) 1261 intel_crtc_async_flip_disable_wa(state, crtc); 1262 } 1263 1264 static void intel_crtc_disable_planes(struct intel_atomic_state *state, 1265 struct intel_crtc *crtc) 1266 { 1267 struct intel_display *display = to_intel_display(state); 1268 const struct intel_crtc_state *new_crtc_state = 1269 intel_atomic_get_new_crtc_state(state, crtc); 1270 unsigned int update_mask = new_crtc_state->update_planes; 1271 const struct intel_plane_state *old_plane_state; 1272 struct intel_plane *plane; 1273 unsigned fb_bits = 0; 1274 int i; 1275 1276 intel_crtc_dpms_overlay_disable(crtc); 1277 1278 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 1279 if (crtc->pipe != plane->pipe || 1280 !(update_mask & BIT(plane->id))) 1281 continue; 1282 1283 intel_plane_disable_arm(NULL, plane, new_crtc_state); 1284 1285 if (old_plane_state->uapi.visible) 1286 fb_bits |= plane->frontbuffer_bit; 1287 } 1288 1289 intel_frontbuffer_flip(display, fb_bits); 1290 } 1291 1292 static void intel_encoders_update_prepare(struct intel_atomic_state *state) 1293 { 1294 struct intel_display *display = to_intel_display(state); 1295 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 1296 struct intel_crtc *crtc; 1297 int i; 1298 1299 /* 1300 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. 1301 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. 1302 */ 1303 if (display->dpll.mgr) { 1304 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 1305 if (intel_crtc_needs_modeset(new_crtc_state)) 1306 continue; 1307 1308 new_crtc_state->intel_dpll = old_crtc_state->intel_dpll; 1309 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; 1310 } 1311 } 1312 } 1313 1314 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, 1315 struct intel_crtc *crtc) 1316 { 1317 const struct intel_crtc_state *crtc_state = 1318 intel_atomic_get_new_crtc_state(state, crtc); 1319 const struct drm_connector_state *conn_state; 1320 struct drm_connector *conn; 1321 int i; 1322 1323 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1324 struct intel_encoder *encoder = 1325 to_intel_encoder(conn_state->best_encoder); 1326 1327 if (conn_state->crtc != &crtc->base) 1328 continue; 1329 1330 if (encoder->pre_pll_enable) 1331 encoder->pre_pll_enable(state, encoder, 1332 crtc_state, conn_state); 1333 } 1334 } 1335 1336 static void intel_encoders_pre_enable(struct intel_atomic_state *state, 1337 struct intel_crtc *crtc) 1338 { 1339 const struct intel_crtc_state *crtc_state = 1340 intel_atomic_get_new_crtc_state(state, crtc); 1341 const struct drm_connector_state *conn_state; 1342 struct drm_connector *conn; 1343 int i; 1344 1345 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1346 struct intel_encoder *encoder = 1347 to_intel_encoder(conn_state->best_encoder); 1348 1349 if (conn_state->crtc != &crtc->base) 1350 continue; 1351 1352 if (encoder->pre_enable) 1353 encoder->pre_enable(state, encoder, 1354 crtc_state, conn_state); 1355 } 1356 } 1357 1358 static void intel_encoders_enable(struct intel_atomic_state *state, 1359 struct intel_crtc *crtc) 1360 { 1361 const struct intel_crtc_state *crtc_state = 1362 intel_atomic_get_new_crtc_state(state, crtc); 1363 const struct drm_connector_state *conn_state; 1364 struct drm_connector *conn; 1365 int i; 1366 1367 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1368 struct intel_encoder *encoder = 1369 to_intel_encoder(conn_state->best_encoder); 1370 1371 if (conn_state->crtc != &crtc->base) 1372 continue; 1373 1374 if (encoder->enable) 1375 encoder->enable(state, encoder, 1376 crtc_state, conn_state); 1377 intel_opregion_notify_encoder(encoder, true); 1378 } 1379 } 1380 1381 static void intel_encoders_disable(struct intel_atomic_state *state, 1382 struct intel_crtc *crtc) 1383 { 1384 const struct intel_crtc_state *old_crtc_state = 1385 intel_atomic_get_old_crtc_state(state, crtc); 1386 const struct drm_connector_state *old_conn_state; 1387 struct drm_connector *conn; 1388 int i; 1389 1390 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1391 struct intel_encoder *encoder = 1392 to_intel_encoder(old_conn_state->best_encoder); 1393 1394 if (old_conn_state->crtc != &crtc->base) 1395 continue; 1396 1397 intel_opregion_notify_encoder(encoder, false); 1398 if (encoder->disable) 1399 encoder->disable(state, encoder, 1400 old_crtc_state, old_conn_state); 1401 } 1402 } 1403 1404 static void intel_encoders_post_disable(struct intel_atomic_state *state, 1405 struct intel_crtc *crtc) 1406 { 1407 const struct intel_crtc_state *old_crtc_state = 1408 intel_atomic_get_old_crtc_state(state, crtc); 1409 const struct drm_connector_state *old_conn_state; 1410 struct drm_connector *conn; 1411 int i; 1412 1413 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1414 struct intel_encoder *encoder = 1415 to_intel_encoder(old_conn_state->best_encoder); 1416 1417 if (old_conn_state->crtc != &crtc->base) 1418 continue; 1419 1420 if (encoder->post_disable) 1421 encoder->post_disable(state, encoder, 1422 old_crtc_state, old_conn_state); 1423 } 1424 } 1425 1426 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, 1427 struct intel_crtc *crtc) 1428 { 1429 const struct intel_crtc_state *old_crtc_state = 1430 intel_atomic_get_old_crtc_state(state, crtc); 1431 const struct drm_connector_state *old_conn_state; 1432 struct drm_connector *conn; 1433 int i; 1434 1435 for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) { 1436 struct intel_encoder *encoder = 1437 to_intel_encoder(old_conn_state->best_encoder); 1438 1439 if (old_conn_state->crtc != &crtc->base) 1440 continue; 1441 1442 if (encoder->post_pll_disable) 1443 encoder->post_pll_disable(state, encoder, 1444 old_crtc_state, old_conn_state); 1445 } 1446 } 1447 1448 static void intel_encoders_update_pipe(struct intel_atomic_state *state, 1449 struct intel_crtc *crtc) 1450 { 1451 const struct intel_crtc_state *crtc_state = 1452 intel_atomic_get_new_crtc_state(state, crtc); 1453 const struct drm_connector_state *conn_state; 1454 struct drm_connector *conn; 1455 int i; 1456 1457 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { 1458 struct intel_encoder *encoder = 1459 to_intel_encoder(conn_state->best_encoder); 1460 1461 if (conn_state->crtc != &crtc->base) 1462 continue; 1463 1464 if (encoder->update_pipe) 1465 encoder->update_pipe(state, encoder, 1466 crtc_state, conn_state); 1467 } 1468 } 1469 1470 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1471 { 1472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1473 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1474 1475 if (crtc_state->has_pch_encoder) { 1476 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1477 &crtc_state->fdi_m_n); 1478 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1479 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1480 &crtc_state->dp_m_n); 1481 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1482 &crtc_state->dp_m2_n2); 1483 } 1484 1485 intel_set_transcoder_timings(crtc_state); 1486 1487 ilk_set_pipeconf(crtc_state); 1488 } 1489 1490 static void ilk_crtc_enable(struct intel_atomic_state *state, 1491 struct intel_crtc *crtc) 1492 { 1493 struct intel_display *display = to_intel_display(crtc); 1494 const struct intel_crtc_state *new_crtc_state = 1495 intel_atomic_get_new_crtc_state(state, crtc); 1496 enum pipe pipe = crtc->pipe; 1497 1498 if (drm_WARN_ON(display->drm, crtc->active)) 1499 return; 1500 1501 /* 1502 * Sometimes spurious CPU pipe underruns happen during FDI 1503 * training, at least with VGA+HDMI cloning. Suppress them. 1504 * 1505 * On ILK we get an occasional spurious CPU pipe underruns 1506 * between eDP port A enable and vdd enable. Also PCH port 1507 * enable seems to result in the occasional CPU pipe underrun. 1508 * 1509 * Spurious PCH underruns also occur during PCH enabling. 1510 */ 1511 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1512 intel_set_pch_fifo_underrun_reporting(display, pipe, false); 1513 1514 ilk_configure_cpu_transcoder(new_crtc_state); 1515 1516 intel_set_pipe_src_size(new_crtc_state); 1517 1518 crtc->active = true; 1519 1520 intel_encoders_pre_enable(state, crtc); 1521 1522 if (new_crtc_state->has_pch_encoder) { 1523 ilk_pch_pre_enable(state, crtc); 1524 } else { 1525 assert_fdi_tx_disabled(display, pipe); 1526 assert_fdi_rx_disabled(display, pipe); 1527 } 1528 1529 ilk_pfit_enable(new_crtc_state); 1530 1531 /* 1532 * On ILK+ LUT must be loaded before the pipe is running but with 1533 * clocks enabled 1534 */ 1535 intel_color_modeset(new_crtc_state); 1536 1537 intel_initial_watermarks(state, crtc); 1538 intel_enable_transcoder(new_crtc_state); 1539 1540 if (new_crtc_state->has_pch_encoder) 1541 ilk_pch_enable(state, crtc); 1542 1543 intel_crtc_vblank_on(new_crtc_state); 1544 1545 intel_encoders_enable(state, crtc); 1546 1547 if (HAS_PCH_CPT(display)) 1548 intel_wait_for_pipe_scanline_moving(crtc); 1549 1550 /* 1551 * Must wait for vblank to avoid spurious PCH FIFO underruns. 1552 * And a second vblank wait is needed at least on ILK with 1553 * some interlaced HDMI modes. Let's do the double wait always 1554 * in case there are more corner cases we don't know about. 1555 */ 1556 if (new_crtc_state->has_pch_encoder) { 1557 intel_crtc_wait_for_next_vblank(crtc); 1558 intel_crtc_wait_for_next_vblank(crtc); 1559 } 1560 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 1561 intel_set_pch_fifo_underrun_reporting(display, pipe, true); 1562 } 1563 1564 /* Display WA #1180: WaDisableScalarClockGating: glk */ 1565 static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state) 1566 { 1567 struct intel_display *display = to_intel_display(crtc_state); 1568 1569 return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled; 1570 } 1571 1572 static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable) 1573 { 1574 struct intel_display *display = to_intel_display(crtc); 1575 u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; 1576 1577 intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe), 1578 mask, enable ? mask : 0); 1579 } 1580 1581 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) 1582 { 1583 struct intel_display *display = to_intel_display(crtc_state); 1584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1585 1586 intel_de_write(display, WM_LINETIME(crtc->pipe), 1587 HSW_LINETIME(crtc_state->linetime) | 1588 HSW_IPS_LINETIME(crtc_state->ips_linetime)); 1589 } 1590 1591 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1592 { 1593 struct intel_display *display = to_intel_display(crtc_state); 1594 1595 intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder), 1596 HSW_FRAME_START_DELAY_MASK, 1597 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1598 } 1599 1600 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 1601 { 1602 struct intel_display *display = to_intel_display(crtc_state); 1603 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1604 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1605 1606 if (crtc_state->has_pch_encoder) { 1607 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1608 &crtc_state->fdi_m_n); 1609 } else if (intel_crtc_has_dp_encoder(crtc_state)) { 1610 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 1611 &crtc_state->dp_m_n); 1612 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 1613 &crtc_state->dp_m2_n2); 1614 } 1615 1616 intel_set_transcoder_timings(crtc_state); 1617 1618 if (cpu_transcoder != TRANSCODER_EDP) 1619 intel_de_write(display, TRANS_MULT(display, cpu_transcoder), 1620 crtc_state->pixel_multiplier - 1); 1621 1622 hsw_set_frame_start_delay(crtc_state); 1623 1624 hsw_set_transconf(crtc_state); 1625 } 1626 1627 static void hsw_crtc_enable(struct intel_atomic_state *state, 1628 struct intel_crtc *crtc) 1629 { 1630 struct intel_display *display = to_intel_display(state); 1631 const struct intel_crtc_state *new_crtc_state = 1632 intel_atomic_get_new_crtc_state(state, crtc); 1633 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; 1634 struct intel_crtc *pipe_crtc; 1635 int i; 1636 1637 if (drm_WARN_ON(display->drm, crtc->active)) 1638 return; 1639 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { 1640 const struct intel_crtc_state *new_pipe_crtc_state = 1641 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1642 1643 intel_dmc_enable_pipe(new_pipe_crtc_state); 1644 } 1645 1646 intel_encoders_pre_pll_enable(state, crtc); 1647 1648 if (new_crtc_state->intel_dpll) 1649 intel_dpll_enable(new_crtc_state); 1650 1651 intel_encoders_pre_enable(state, crtc); 1652 1653 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { 1654 const struct intel_crtc_state *pipe_crtc_state = 1655 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1656 1657 intel_dsc_enable(pipe_crtc_state); 1658 1659 if (HAS_UNCOMPRESSED_JOINER(display)) 1660 intel_uncompressed_joiner_enable(pipe_crtc_state); 1661 1662 intel_set_pipe_src_size(pipe_crtc_state); 1663 1664 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) 1665 bdw_set_pipe_misc(NULL, pipe_crtc_state); 1666 } 1667 1668 if (!transcoder_is_dsi(cpu_transcoder)) 1669 hsw_configure_cpu_transcoder(new_crtc_state); 1670 1671 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { 1672 const struct intel_crtc_state *pipe_crtc_state = 1673 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1674 1675 pipe_crtc->active = true; 1676 1677 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) 1678 glk_pipe_scaler_clock_gating_wa(pipe_crtc, true); 1679 1680 if (DISPLAY_VER(display) >= 9) 1681 skl_pfit_enable(pipe_crtc_state); 1682 else 1683 ilk_pfit_enable(pipe_crtc_state); 1684 1685 /* 1686 * On ILK+ LUT must be loaded before the pipe is running but with 1687 * clocks enabled 1688 */ 1689 intel_color_modeset(pipe_crtc_state); 1690 1691 hsw_set_linetime_wm(pipe_crtc_state); 1692 1693 if (DISPLAY_VER(display) >= 11) 1694 icl_set_pipe_chicken(pipe_crtc_state); 1695 1696 intel_initial_watermarks(state, pipe_crtc); 1697 } 1698 1699 intel_encoders_enable(state, crtc); 1700 1701 for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) { 1702 const struct intel_crtc_state *pipe_crtc_state = 1703 intel_atomic_get_new_crtc_state(state, pipe_crtc); 1704 enum pipe hsw_workaround_pipe; 1705 1706 if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) { 1707 intel_crtc_wait_for_next_vblank(pipe_crtc); 1708 glk_pipe_scaler_clock_gating_wa(pipe_crtc, false); 1709 } 1710 1711 /* 1712 * If we change the relative order between pipe/planes 1713 * enabling, we need to change the workaround. 1714 */ 1715 hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe; 1716 if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) { 1717 struct intel_crtc *wa_crtc = 1718 intel_crtc_for_pipe(display, hsw_workaround_pipe); 1719 1720 intel_crtc_wait_for_next_vblank(wa_crtc); 1721 intel_crtc_wait_for_next_vblank(wa_crtc); 1722 } 1723 } 1724 } 1725 1726 static void ilk_crtc_disable(struct intel_atomic_state *state, 1727 struct intel_crtc *crtc) 1728 { 1729 struct intel_display *display = to_intel_display(crtc); 1730 const struct intel_crtc_state *old_crtc_state = 1731 intel_atomic_get_old_crtc_state(state, crtc); 1732 enum pipe pipe = crtc->pipe; 1733 1734 /* 1735 * Sometimes spurious CPU pipe underruns happen when the 1736 * pipe is already disabled, but FDI RX/TX is still enabled. 1737 * Happens at least with VGA+HDMI cloning. Suppress them. 1738 */ 1739 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 1740 intel_set_pch_fifo_underrun_reporting(display, pipe, false); 1741 1742 intel_encoders_disable(state, crtc); 1743 1744 intel_crtc_vblank_off(old_crtc_state); 1745 1746 intel_disable_transcoder(old_crtc_state); 1747 1748 ilk_pfit_disable(old_crtc_state); 1749 1750 if (old_crtc_state->has_pch_encoder) 1751 ilk_pch_disable(state, crtc); 1752 1753 intel_encoders_post_disable(state, crtc); 1754 1755 if (old_crtc_state->has_pch_encoder) 1756 ilk_pch_post_disable(state, crtc); 1757 1758 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 1759 intel_set_pch_fifo_underrun_reporting(display, pipe, true); 1760 } 1761 1762 static void hsw_crtc_disable(struct intel_atomic_state *state, 1763 struct intel_crtc *crtc) 1764 { 1765 struct intel_display *display = to_intel_display(state); 1766 const struct intel_crtc_state *old_crtc_state = 1767 intel_atomic_get_old_crtc_state(state, crtc); 1768 struct intel_crtc *pipe_crtc; 1769 int i; 1770 1771 /* 1772 * FIXME collapse everything to one hook. 1773 * Need care with mst->ddi interactions. 1774 */ 1775 intel_encoders_disable(state, crtc); 1776 intel_encoders_post_disable(state, crtc); 1777 1778 intel_dpll_disable(old_crtc_state); 1779 1780 intel_encoders_post_pll_disable(state, crtc); 1781 1782 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { 1783 const struct intel_crtc_state *old_pipe_crtc_state = 1784 intel_atomic_get_old_crtc_state(state, pipe_crtc); 1785 1786 intel_dmc_disable_pipe(old_pipe_crtc_state); 1787 } 1788 } 1789 1790 /* Prefer intel_encoder_is_combo() */ 1791 bool intel_phy_is_combo(struct intel_display *display, enum phy phy) 1792 { 1793 if (phy == PHY_NONE) 1794 return false; 1795 else if (display->platform.alderlake_s) 1796 return phy <= PHY_E; 1797 else if (display->platform.dg1 || display->platform.rocketlake) 1798 return phy <= PHY_D; 1799 else if (display->platform.jasperlake || display->platform.elkhartlake) 1800 return phy <= PHY_C; 1801 else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12)) 1802 return phy <= PHY_B; 1803 else 1804 /* 1805 * DG2 outputs labelled as "combo PHY" in the bspec use 1806 * SNPS PHYs with completely different programming, 1807 * hence we always return false here. 1808 */ 1809 return false; 1810 } 1811 1812 /* 1813 * This function returns true if the DDI port respective to the PHY enumeration 1814 * is a Type-C capable port. 1815 * 1816 * Depending on the VBT, the port might be configured 1817 * as a "dedicated external" port, meaning that actual physical PHY is outside 1818 * of the Type-C subsystem and, as such, not really a "Type-C PHY". 1819 * 1820 * Prefer intel_encoder_is_tc(), especially if you really need to know if we 1821 * are dealing with Type-C connections. 1822 */ 1823 bool intel_phy_is_tc(struct intel_display *display, enum phy phy) 1824 { 1825 /* 1826 * Discrete GPU phy's are not attached to FIA's to support TC 1827 * subsystem Legacy or non-legacy, and only support native DP/HDMI 1828 */ 1829 if (display->platform.dgfx) 1830 return false; 1831 1832 if (DISPLAY_VER(display) >= 13) 1833 return phy >= PHY_F && phy <= PHY_I; 1834 else if (display->platform.tigerlake) 1835 return phy >= PHY_D && phy <= PHY_I; 1836 else if (display->platform.icelake) 1837 return phy >= PHY_C && phy <= PHY_F; 1838 1839 return false; 1840 } 1841 1842 /* Prefer intel_encoder_is_snps() */ 1843 bool intel_phy_is_snps(struct intel_display *display, enum phy phy) 1844 { 1845 /* 1846 * For DG2, and for DG2 only, all four "combo" ports and the TC1 port 1847 * (PHY E) use Synopsis PHYs. See intel_phy_is_tc(). 1848 */ 1849 return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E; 1850 } 1851 1852 /* Prefer intel_encoder_to_phy() */ 1853 enum phy intel_port_to_phy(struct intel_display *display, enum port port) 1854 { 1855 if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) 1856 return PHY_D + port - PORT_D_XELPD; 1857 else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1) 1858 return PHY_F + port - PORT_TC1; 1859 else if (display->platform.alderlake_s && port >= PORT_TC1) 1860 return PHY_B + port - PORT_TC1; 1861 else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1) 1862 return PHY_C + port - PORT_TC1; 1863 else if ((display->platform.jasperlake || display->platform.elkhartlake) && 1864 port == PORT_D) 1865 return PHY_A; 1866 1867 return PHY_A + port - PORT_A; 1868 } 1869 1870 /* Prefer intel_encoder_to_tc() */ 1871 /* 1872 * Return TC_PORT_1..I915_MAX_TC_PORTS for any TypeC DDI port. The function 1873 * can be also called for TypeC DDI ports not connected to a TypeC PHY such as 1874 * the PORT_TC1..4 ports on RKL/ADLS/BMG. 1875 */ 1876 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) 1877 { 1878 if (DISPLAY_VER(display) >= 12) 1879 return TC_PORT_1 + port - PORT_TC1; 1880 else 1881 return TC_PORT_1 + port - PORT_C; 1882 } 1883 1884 /* 1885 * Return TC_PORT_1..I915_MAX_TC_PORTS for TypeC DDI ports connected to a TypeC PHY. 1886 * Note that on RKL, ADLS, BMG the PORT_TC1..4 ports are connected to a non-TypeC 1887 * PHY, so on those platforms the function returns TC_PORT_NONE. 1888 */ 1889 enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port) 1890 { 1891 if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) 1892 return TC_PORT_NONE; 1893 1894 return intel_port_to_tc(display, port); 1895 } 1896 1897 enum phy intel_encoder_to_phy(struct intel_encoder *encoder) 1898 { 1899 struct intel_display *display = to_intel_display(encoder); 1900 1901 return intel_port_to_phy(display, encoder->port); 1902 } 1903 1904 bool intel_encoder_is_combo(struct intel_encoder *encoder) 1905 { 1906 struct intel_display *display = to_intel_display(encoder); 1907 1908 return intel_phy_is_combo(display, intel_encoder_to_phy(encoder)); 1909 } 1910 1911 bool intel_encoder_is_snps(struct intel_encoder *encoder) 1912 { 1913 struct intel_display *display = to_intel_display(encoder); 1914 1915 return intel_phy_is_snps(display, intel_encoder_to_phy(encoder)); 1916 } 1917 1918 bool intel_encoder_is_tc(struct intel_encoder *encoder) 1919 { 1920 struct intel_display *display = to_intel_display(encoder); 1921 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1922 1923 if (dig_port && dig_port->dedicated_external) 1924 return false; 1925 1926 return intel_phy_is_tc(display, intel_encoder_to_phy(encoder)); 1927 } 1928 1929 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) 1930 { 1931 struct intel_display *display = to_intel_display(encoder); 1932 1933 return intel_tc_phy_port_to_tc(display, encoder->port); 1934 } 1935 1936 enum intel_display_power_domain 1937 intel_aux_power_domain(struct intel_digital_port *dig_port) 1938 { 1939 struct intel_display *display = to_intel_display(dig_port); 1940 1941 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 1942 return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch); 1943 1944 return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); 1945 } 1946 1947 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1948 struct intel_power_domain_mask *mask) 1949 { 1950 struct intel_display *display = to_intel_display(crtc_state); 1951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1952 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1953 struct drm_encoder *encoder; 1954 enum pipe pipe = crtc->pipe; 1955 1956 bitmap_zero(mask->bits, POWER_DOMAIN_NUM); 1957 1958 if (!crtc_state->hw.active) 1959 return; 1960 1961 set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits); 1962 set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits); 1963 if (crtc_state->pch_pfit.enabled || 1964 crtc_state->pch_pfit.force_thru) 1965 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); 1966 1967 drm_for_each_encoder_mask(encoder, display->drm, 1968 crtc_state->uapi.encoder_mask) { 1969 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 1970 1971 set_bit(intel_encoder->power_domain, mask->bits); 1972 } 1973 1974 if (HAS_DDI(display) && crtc_state->has_audio) 1975 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); 1976 1977 if (crtc_state->intel_dpll) 1978 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits); 1979 1980 if (crtc_state->dsc.compression_enable) 1981 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits); 1982 } 1983 1984 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, 1985 struct intel_power_domain_mask *old_domains) 1986 { 1987 struct intel_display *display = to_intel_display(crtc_state); 1988 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1989 enum intel_display_power_domain domain; 1990 struct intel_power_domain_mask domains, new_domains; 1991 1992 get_crtc_power_domains(crtc_state, &domains); 1993 1994 bitmap_andnot(new_domains.bits, 1995 domains.bits, 1996 crtc->enabled_power_domains.mask.bits, 1997 POWER_DOMAIN_NUM); 1998 bitmap_andnot(old_domains->bits, 1999 crtc->enabled_power_domains.mask.bits, 2000 domains.bits, 2001 POWER_DOMAIN_NUM); 2002 2003 for_each_power_domain(domain, &new_domains) 2004 intel_display_power_get_in_set(display, 2005 &crtc->enabled_power_domains, 2006 domain); 2007 } 2008 2009 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, 2010 struct intel_power_domain_mask *domains) 2011 { 2012 struct intel_display *display = to_intel_display(crtc); 2013 2014 intel_display_power_put_mask_in_set(display, 2015 &crtc->enabled_power_domains, 2016 domains); 2017 } 2018 2019 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) 2020 { 2021 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2022 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2023 2024 if (intel_crtc_has_dp_encoder(crtc_state)) { 2025 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder, 2026 &crtc_state->dp_m_n); 2027 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder, 2028 &crtc_state->dp_m2_n2); 2029 } 2030 2031 intel_set_transcoder_timings(crtc_state); 2032 2033 i9xx_set_pipeconf(crtc_state); 2034 } 2035 2036 static void valleyview_crtc_enable(struct intel_atomic_state *state, 2037 struct intel_crtc *crtc) 2038 { 2039 struct intel_display *display = to_intel_display(crtc); 2040 const struct intel_crtc_state *new_crtc_state = 2041 intel_atomic_get_new_crtc_state(state, crtc); 2042 enum pipe pipe = crtc->pipe; 2043 2044 if (drm_WARN_ON(display->drm, crtc->active)) 2045 return; 2046 2047 i9xx_configure_cpu_transcoder(new_crtc_state); 2048 2049 intel_set_pipe_src_size(new_crtc_state); 2050 2051 intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0); 2052 2053 if (display->platform.cherryview && pipe == PIPE_B) { 2054 intel_de_write(display, CHV_BLEND(display, pipe), 2055 CHV_BLEND_LEGACY); 2056 intel_de_write(display, CHV_CANVAS(display, pipe), 0); 2057 } 2058 2059 crtc->active = true; 2060 2061 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 2062 2063 intel_encoders_pre_pll_enable(state, crtc); 2064 2065 if (display->platform.cherryview) 2066 chv_enable_pll(new_crtc_state); 2067 else 2068 vlv_enable_pll(new_crtc_state); 2069 2070 intel_encoders_pre_enable(state, crtc); 2071 2072 i9xx_pfit_enable(new_crtc_state); 2073 2074 intel_color_modeset(new_crtc_state); 2075 2076 intel_initial_watermarks(state, crtc); 2077 intel_enable_transcoder(new_crtc_state); 2078 2079 intel_crtc_vblank_on(new_crtc_state); 2080 2081 intel_encoders_enable(state, crtc); 2082 } 2083 2084 static void i9xx_crtc_enable(struct intel_atomic_state *state, 2085 struct intel_crtc *crtc) 2086 { 2087 struct intel_display *display = to_intel_display(crtc); 2088 const struct intel_crtc_state *new_crtc_state = 2089 intel_atomic_get_new_crtc_state(state, crtc); 2090 enum pipe pipe = crtc->pipe; 2091 2092 if (drm_WARN_ON(display->drm, crtc->active)) 2093 return; 2094 2095 i9xx_configure_cpu_transcoder(new_crtc_state); 2096 2097 intel_set_pipe_src_size(new_crtc_state); 2098 2099 crtc->active = true; 2100 2101 if (DISPLAY_VER(display) != 2) 2102 intel_set_cpu_fifo_underrun_reporting(display, pipe, true); 2103 2104 intel_encoders_pre_enable(state, crtc); 2105 2106 i9xx_enable_pll(new_crtc_state); 2107 2108 i9xx_pfit_enable(new_crtc_state); 2109 2110 intel_color_modeset(new_crtc_state); 2111 2112 if (!intel_initial_watermarks(state, crtc)) 2113 intel_update_watermarks(display); 2114 intel_enable_transcoder(new_crtc_state); 2115 2116 intel_crtc_vblank_on(new_crtc_state); 2117 2118 intel_encoders_enable(state, crtc); 2119 2120 /* prevents spurious underruns */ 2121 if (DISPLAY_VER(display) == 2) 2122 intel_crtc_wait_for_next_vblank(crtc); 2123 } 2124 2125 static void i9xx_crtc_disable(struct intel_atomic_state *state, 2126 struct intel_crtc *crtc) 2127 { 2128 struct intel_display *display = to_intel_display(state); 2129 struct intel_crtc_state *old_crtc_state = 2130 intel_atomic_get_old_crtc_state(state, crtc); 2131 enum pipe pipe = crtc->pipe; 2132 2133 /* 2134 * On gen2 planes are double buffered but the pipe isn't, so we must 2135 * wait for planes to fully turn off before disabling the pipe. 2136 */ 2137 if (DISPLAY_VER(display) == 2) 2138 intel_crtc_wait_for_next_vblank(crtc); 2139 2140 intel_encoders_disable(state, crtc); 2141 2142 intel_crtc_vblank_off(old_crtc_state); 2143 2144 intel_disable_transcoder(old_crtc_state); 2145 2146 i9xx_pfit_disable(old_crtc_state); 2147 2148 intel_encoders_post_disable(state, crtc); 2149 2150 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { 2151 if (display->platform.cherryview) 2152 chv_disable_pll(display, pipe); 2153 else if (display->platform.valleyview) 2154 vlv_disable_pll(display, pipe); 2155 else 2156 i9xx_disable_pll(old_crtc_state); 2157 } 2158 2159 intel_encoders_post_pll_disable(state, crtc); 2160 2161 if (DISPLAY_VER(display) != 2) 2162 intel_set_cpu_fifo_underrun_reporting(display, pipe, false); 2163 2164 if (!display->funcs.wm->initial_watermarks) 2165 intel_update_watermarks(display); 2166 2167 /* clock the pipe down to 640x480@60 to potentially save power */ 2168 if (display->platform.i830) 2169 i830_enable_pipe(display, pipe); 2170 } 2171 2172 void intel_encoder_destroy(struct drm_encoder *encoder) 2173 { 2174 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2175 2176 drm_encoder_cleanup(encoder); 2177 kfree(intel_encoder); 2178 } 2179 2180 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) 2181 { 2182 struct intel_display *display = to_intel_display(crtc); 2183 2184 /* GDG double wide on either pipe, otherwise pipe A only */ 2185 return HAS_DOUBLE_WIDE(display) && 2186 (crtc->pipe == PIPE_A || display->platform.i915g); 2187 } 2188 2189 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) 2190 { 2191 u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; 2192 struct drm_rect src; 2193 2194 /* 2195 * We only use IF-ID interlacing. If we ever use 2196 * PF-ID we'll need to adjust the pixel_rate here. 2197 */ 2198 2199 if (!crtc_state->pch_pfit.enabled) 2200 return pixel_rate; 2201 2202 drm_rect_init(&src, 0, 0, 2203 drm_rect_width(&crtc_state->pipe_src) << 16, 2204 drm_rect_height(&crtc_state->pipe_src) << 16); 2205 2206 return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst, 2207 pixel_rate); 2208 } 2209 2210 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, 2211 const struct drm_display_mode *timings) 2212 { 2213 mode->hdisplay = timings->crtc_hdisplay; 2214 mode->htotal = timings->crtc_htotal; 2215 mode->hsync_start = timings->crtc_hsync_start; 2216 mode->hsync_end = timings->crtc_hsync_end; 2217 2218 mode->vdisplay = timings->crtc_vdisplay; 2219 mode->vtotal = timings->crtc_vtotal; 2220 mode->vsync_start = timings->crtc_vsync_start; 2221 mode->vsync_end = timings->crtc_vsync_end; 2222 2223 mode->flags = timings->flags; 2224 mode->type = DRM_MODE_TYPE_DRIVER; 2225 2226 mode->clock = timings->crtc_clock; 2227 2228 drm_mode_set_name(mode); 2229 } 2230 2231 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) 2232 { 2233 struct intel_display *display = to_intel_display(crtc_state); 2234 2235 if (HAS_GMCH(display)) 2236 /* FIXME calculate proper pipe pixel rate for GMCH pfit */ 2237 crtc_state->pixel_rate = 2238 crtc_state->hw.pipe_mode.crtc_clock; 2239 else 2240 crtc_state->pixel_rate = 2241 ilk_pipe_pixel_rate(crtc_state); 2242 } 2243 2244 static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state, 2245 struct drm_display_mode *mode) 2246 { 2247 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2248 2249 if (num_pipes == 1) 2250 return; 2251 2252 mode->crtc_clock /= num_pipes; 2253 mode->crtc_hdisplay /= num_pipes; 2254 mode->crtc_hblank_start /= num_pipes; 2255 mode->crtc_hblank_end /= num_pipes; 2256 mode->crtc_hsync_start /= num_pipes; 2257 mode->crtc_hsync_end /= num_pipes; 2258 mode->crtc_htotal /= num_pipes; 2259 } 2260 2261 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state, 2262 struct drm_display_mode *mode) 2263 { 2264 int overlap = crtc_state->splitter.pixel_overlap; 2265 int n = crtc_state->splitter.link_count; 2266 2267 if (!crtc_state->splitter.enable) 2268 return; 2269 2270 /* 2271 * eDP MSO uses segment timings from EDID for transcoder 2272 * timings, but full mode for everything else. 2273 * 2274 * h_full = (h_segment - pixel_overlap) * link_count 2275 */ 2276 mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n; 2277 mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n; 2278 mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n; 2279 mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n; 2280 mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n; 2281 mode->crtc_htotal = (mode->crtc_htotal - overlap) * n; 2282 mode->crtc_clock *= n; 2283 } 2284 2285 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state) 2286 { 2287 struct drm_display_mode *mode = &crtc_state->hw.mode; 2288 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2289 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2290 2291 /* 2292 * Start with the adjusted_mode crtc timings, which 2293 * have been filled with the transcoder timings. 2294 */ 2295 drm_mode_copy(pipe_mode, adjusted_mode); 2296 2297 /* Expand MSO per-segment transcoder timings to full */ 2298 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2299 2300 /* 2301 * We want the full numbers in adjusted_mode normal timings, 2302 * adjusted_mode crtc timings are left with the raw transcoder 2303 * timings. 2304 */ 2305 intel_mode_from_crtc_timings(adjusted_mode, pipe_mode); 2306 2307 /* Populate the "user" mode with full numbers */ 2308 drm_mode_copy(mode, pipe_mode); 2309 intel_mode_from_crtc_timings(mode, mode); 2310 mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * 2311 intel_crtc_num_joined_pipes(crtc_state); 2312 mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); 2313 2314 /* Derive per-pipe timings in case joiner is used */ 2315 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2316 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2317 2318 intel_crtc_compute_pixel_rate(crtc_state); 2319 } 2320 2321 void intel_encoder_get_config(struct intel_encoder *encoder, 2322 struct intel_crtc_state *crtc_state) 2323 { 2324 encoder->get_config(encoder, crtc_state); 2325 2326 intel_crtc_readout_derived_state(crtc_state); 2327 } 2328 2329 static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) 2330 { 2331 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2332 int width, height; 2333 2334 if (num_pipes == 1) 2335 return; 2336 2337 width = drm_rect_width(&crtc_state->pipe_src); 2338 height = drm_rect_height(&crtc_state->pipe_src); 2339 2340 drm_rect_init(&crtc_state->pipe_src, 0, 0, 2341 width / num_pipes, height); 2342 } 2343 2344 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) 2345 { 2346 struct intel_display *display = to_intel_display(crtc_state); 2347 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2348 2349 intel_joiner_compute_pipe_src(crtc_state); 2350 2351 /* 2352 * Pipe horizontal size must be even in: 2353 * - DVO ganged mode 2354 * - LVDS dual channel mode 2355 * - Double wide pipe 2356 */ 2357 if (drm_rect_width(&crtc_state->pipe_src) & 1) { 2358 if (crtc_state->double_wide) { 2359 drm_dbg_kms(display->drm, 2360 "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", 2361 crtc->base.base.id, crtc->base.name); 2362 return -EINVAL; 2363 } 2364 2365 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 2366 intel_is_dual_link_lvds(display)) { 2367 drm_dbg_kms(display->drm, 2368 "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", 2369 crtc->base.base.id, crtc->base.name); 2370 return -EINVAL; 2371 } 2372 } 2373 2374 return 0; 2375 } 2376 2377 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) 2378 { 2379 struct intel_display *display = to_intel_display(crtc_state); 2380 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2381 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2382 struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; 2383 int clock_limit = display->cdclk.max_dotclk_freq; 2384 2385 /* 2386 * Start with the adjusted_mode crtc timings, which 2387 * have been filled with the transcoder timings. 2388 */ 2389 drm_mode_copy(pipe_mode, adjusted_mode); 2390 2391 /* Expand MSO per-segment transcoder timings to full */ 2392 intel_splitter_adjust_timings(crtc_state, pipe_mode); 2393 2394 /* Derive per-pipe timings in case joiner is used */ 2395 intel_joiner_adjust_timings(crtc_state, pipe_mode); 2396 intel_mode_from_crtc_timings(pipe_mode, pipe_mode); 2397 2398 if (DISPLAY_VER(display) < 4) { 2399 clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; 2400 2401 /* 2402 * Enable double wide mode when the dot clock 2403 * is > 90% of the (display) core speed. 2404 */ 2405 if (intel_crtc_supports_double_wide(crtc) && 2406 pipe_mode->crtc_clock > clock_limit) { 2407 clock_limit = display->cdclk.max_dotclk_freq; 2408 crtc_state->double_wide = true; 2409 } 2410 } 2411 2412 if (pipe_mode->crtc_clock > clock_limit) { 2413 drm_dbg_kms(display->drm, 2414 "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", 2415 crtc->base.base.id, crtc->base.name, 2416 pipe_mode->crtc_clock, clock_limit, 2417 str_yes_no(crtc_state->double_wide)); 2418 return -EINVAL; 2419 } 2420 2421 return 0; 2422 } 2423 2424 static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state) 2425 { 2426 struct intel_display *display = to_intel_display(crtc_state); 2427 int set_context_latency = 0; 2428 2429 if (!HAS_DSB(display)) 2430 return 0; 2431 2432 set_context_latency = max(set_context_latency, 2433 intel_psr_min_set_context_latency(crtc_state)); 2434 2435 return set_context_latency; 2436 } 2437 2438 static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *state, 2439 struct intel_crtc *crtc) 2440 { 2441 struct intel_display *display = to_intel_display(state); 2442 struct intel_crtc_state *crtc_state = 2443 intel_atomic_get_new_crtc_state(state, crtc); 2444 struct drm_display_mode *adjusted_mode = 2445 &crtc_state->hw.adjusted_mode; 2446 int set_context_latency, max_vblank_delay; 2447 2448 set_context_latency = intel_crtc_set_context_latency(crtc_state); 2449 2450 max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1; 2451 2452 if (set_context_latency > max_vblank_delay) { 2453 drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n", 2454 crtc->base.base.id, crtc->base.name, 2455 set_context_latency, 2456 max_vblank_delay); 2457 return -EINVAL; 2458 } 2459 2460 crtc_state->set_context_latency = set_context_latency; 2461 adjusted_mode->crtc_vblank_start += set_context_latency; 2462 2463 return 0; 2464 } 2465 2466 static int intel_crtc_compute_config(struct intel_atomic_state *state, 2467 struct intel_crtc *crtc) 2468 { 2469 struct intel_crtc_state *crtc_state = 2470 intel_atomic_get_new_crtc_state(state, crtc); 2471 int ret; 2472 2473 ret = intel_dpll_crtc_compute_clock(state, crtc); 2474 if (ret) 2475 return ret; 2476 2477 ret = intel_crtc_compute_set_context_latency(state, crtc); 2478 if (ret) 2479 return ret; 2480 2481 ret = intel_crtc_compute_pipe_src(crtc_state); 2482 if (ret) 2483 return ret; 2484 2485 ret = intel_crtc_compute_pipe_mode(crtc_state); 2486 if (ret) 2487 return ret; 2488 2489 intel_crtc_compute_pixel_rate(crtc_state); 2490 2491 if (crtc_state->has_pch_encoder) 2492 return ilk_fdi_compute_config(crtc, crtc_state); 2493 2494 intel_vrr_compute_guardband(crtc_state); 2495 2496 return 0; 2497 } 2498 2499 static void 2500 intel_reduce_m_n_ratio(u32 *num, u32 *den) 2501 { 2502 while (*num > DATA_LINK_M_N_MASK || 2503 *den > DATA_LINK_M_N_MASK) { 2504 *num >>= 1; 2505 *den >>= 1; 2506 } 2507 } 2508 2509 static void compute_m_n(u32 *ret_m, u32 *ret_n, 2510 u32 m, u32 n, u32 constant_n) 2511 { 2512 if (constant_n) 2513 *ret_n = constant_n; 2514 else 2515 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); 2516 2517 *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); 2518 intel_reduce_m_n_ratio(ret_m, ret_n); 2519 } 2520 2521 void 2522 intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, 2523 int pixel_clock, int link_clock, 2524 int bw_overhead, 2525 struct intel_link_m_n *m_n) 2526 { 2527 u32 link_symbol_clock = intel_dp_link_symbol_clock(link_clock); 2528 u32 data_m = intel_dp_effective_data_rate(pixel_clock, bits_per_pixel_x16, 2529 bw_overhead); 2530 u32 data_n = drm_dp_max_dprx_data_rate(link_clock, nlanes); 2531 2532 /* 2533 * Windows/BIOS uses fixed M/N values always. Follow suit. 2534 * 2535 * Also several DP dongles in particular seem to be fussy 2536 * about too large link M/N values. Presumably the 20bit 2537 * value used by Windows/BIOS is acceptable to everyone. 2538 */ 2539 m_n->tu = 64; 2540 compute_m_n(&m_n->data_m, &m_n->data_n, 2541 data_m, data_n, 2542 0x8000000); 2543 2544 compute_m_n(&m_n->link_m, &m_n->link_n, 2545 pixel_clock, link_symbol_clock, 2546 0x80000); 2547 } 2548 2549 void intel_panel_sanitize_ssc(struct intel_display *display) 2550 { 2551 /* 2552 * There may be no VBT; and if the BIOS enabled SSC we can 2553 * just keep using it to avoid unnecessary flicker. Whereas if the 2554 * BIOS isn't using it, don't assume it will work even if the VBT 2555 * indicates as much. 2556 */ 2557 if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) { 2558 bool bios_lvds_use_ssc = intel_de_read(display, 2559 PCH_DREF_CONTROL) & 2560 DREF_SSC1_ENABLE; 2561 2562 if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) { 2563 drm_dbg_kms(display->drm, 2564 "SSC %s by BIOS, overriding VBT which says %s\n", 2565 str_enabled_disabled(bios_lvds_use_ssc), 2566 str_enabled_disabled(display->vbt.lvds_use_ssc)); 2567 display->vbt.lvds_use_ssc = bios_lvds_use_ssc; 2568 } 2569 } 2570 } 2571 2572 void intel_zero_m_n(struct intel_link_m_n *m_n) 2573 { 2574 /* corresponds to 0 register value */ 2575 memset(m_n, 0, sizeof(*m_n)); 2576 m_n->tu = 1; 2577 } 2578 2579 void intel_set_m_n(struct intel_display *display, 2580 const struct intel_link_m_n *m_n, 2581 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 2582 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 2583 { 2584 intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); 2585 intel_de_write(display, data_n_reg, m_n->data_n); 2586 intel_de_write(display, link_m_reg, m_n->link_m); 2587 /* 2588 * On BDW+ writing LINK_N arms the double buffered update 2589 * of all the M/N registers, so it must be written last. 2590 */ 2591 intel_de_write(display, link_n_reg, m_n->link_n); 2592 } 2593 2594 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, 2595 enum transcoder transcoder) 2596 { 2597 if (display->platform.haswell) 2598 return transcoder == TRANSCODER_EDP; 2599 2600 return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview; 2601 } 2602 2603 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, 2604 enum transcoder transcoder, 2605 const struct intel_link_m_n *m_n) 2606 { 2607 struct intel_display *display = to_intel_display(crtc); 2608 enum pipe pipe = crtc->pipe; 2609 2610 if (DISPLAY_VER(display) >= 5) 2611 intel_set_m_n(display, m_n, 2612 PIPE_DATA_M1(display, transcoder), 2613 PIPE_DATA_N1(display, transcoder), 2614 PIPE_LINK_M1(display, transcoder), 2615 PIPE_LINK_N1(display, transcoder)); 2616 else 2617 intel_set_m_n(display, m_n, 2618 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 2619 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 2620 } 2621 2622 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, 2623 enum transcoder transcoder, 2624 const struct intel_link_m_n *m_n) 2625 { 2626 struct intel_display *display = to_intel_display(crtc); 2627 2628 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 2629 return; 2630 2631 intel_set_m_n(display, m_n, 2632 PIPE_DATA_M2(display, transcoder), 2633 PIPE_DATA_N2(display, transcoder), 2634 PIPE_LINK_M2(display, transcoder), 2635 PIPE_LINK_N2(display, transcoder)); 2636 } 2637 2638 static bool 2639 transcoder_has_vrr(const struct intel_crtc_state *crtc_state) 2640 { 2641 struct intel_display *display = to_intel_display(crtc_state); 2642 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2643 2644 return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder); 2645 } 2646 2647 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 2648 { 2649 struct intel_display *display = to_intel_display(crtc_state); 2650 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2651 enum pipe pipe = crtc->pipe; 2652 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2653 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2654 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2655 int vsyncshift = 0; 2656 2657 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 2658 2659 /* We need to be careful not to changed the adjusted mode, for otherwise 2660 * the hw state checker will get angry at the mismatch. */ 2661 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2662 crtc_vtotal = adjusted_mode->crtc_vtotal; 2663 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2664 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2665 2666 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2667 /* the chip adds 2 halflines automatically */ 2668 crtc_vtotal -= 1; 2669 crtc_vblank_end -= 1; 2670 2671 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2672 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; 2673 else 2674 vsyncshift = adjusted_mode->crtc_hsync_start - 2675 adjusted_mode->crtc_htotal / 2; 2676 if (vsyncshift < 0) 2677 vsyncshift += adjusted_mode->crtc_htotal; 2678 } 2679 2680 /* 2681 * VBLANK_START no longer works on ADL+, instead we must use 2682 * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. 2683 */ 2684 if (DISPLAY_VER(display) >= 13) { 2685 intel_de_write(display, 2686 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), 2687 crtc_state->set_context_latency); 2688 2689 /* 2690 * VBLANK_START not used by hw, just clear it 2691 * to make it stand out in register dumps. 2692 */ 2693 crtc_vblank_start = 1; 2694 } else if (DISPLAY_VER(display) == 12) { 2695 /* VBLANK_START - VACTIVE defines SCL on TGL */ 2696 crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency; 2697 } 2698 2699 if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35) 2700 intel_de_write(display, 2701 TRANS_VSYNCSHIFT(display, cpu_transcoder), 2702 vsyncshift); 2703 2704 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), 2705 HACTIVE(adjusted_mode->crtc_hdisplay - 1) | 2706 HTOTAL(adjusted_mode->crtc_htotal - 1)); 2707 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), 2708 HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | 2709 HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); 2710 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), 2711 HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | 2712 HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); 2713 2714 /* 2715 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal 2716 * bits are not required. Since the support for these bits is going to 2717 * be deprecated in upcoming platforms, avoid writing these bits for the 2718 * platforms that do not use legacy Timing Generator. 2719 */ 2720 if (intel_vrr_always_use_vrr_tg(display)) 2721 crtc_vtotal = 1; 2722 2723 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 2724 VACTIVE(crtc_vdisplay - 1) | 2725 VTOTAL(crtc_vtotal - 1)); 2726 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 2727 VBLANK_START(crtc_vblank_start - 1) | 2728 VBLANK_END(crtc_vblank_end - 1)); 2729 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), 2730 VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | 2731 VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); 2732 2733 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 2734 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 2735 * documented on the DDI_FUNC_CTL register description, EDP Input Select 2736 * bits. */ 2737 if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP && 2738 (pipe == PIPE_B || pipe == PIPE_C)) 2739 intel_de_write(display, TRANS_VTOTAL(display, pipe), 2740 VACTIVE(crtc_vdisplay - 1) | 2741 VTOTAL(crtc_vtotal - 1)); 2742 2743 if (DISPLAY_VER(display) >= 30) { 2744 /* 2745 * Address issues for resolutions with high refresh rate that 2746 * have small Hblank, specifically where Hblank is smaller than 2747 * one MTP. Simulations indicate this will address the 2748 * jitter issues that currently causes BS to be immediately 2749 * followed by BE which DPRX devices are unable to handle. 2750 * https://groups.vesa.org/wg/DP/document/20494 2751 */ 2752 intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder), 2753 crtc_state->min_hblank); 2754 } 2755 } 2756 2757 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) 2758 { 2759 struct intel_display *display = to_intel_display(crtc_state); 2760 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2761 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2762 u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; 2763 2764 drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); 2765 2766 crtc_vdisplay = adjusted_mode->crtc_vdisplay; 2767 crtc_vtotal = adjusted_mode->crtc_vtotal; 2768 crtc_vblank_start = adjusted_mode->crtc_vblank_start; 2769 crtc_vblank_end = adjusted_mode->crtc_vblank_end; 2770 2771 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 2772 /* the chip adds 2 halflines automatically */ 2773 crtc_vtotal -= 1; 2774 crtc_vblank_end -= 1; 2775 } 2776 2777 if (DISPLAY_VER(display) >= 13) { 2778 intel_de_write(display, 2779 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), 2780 crtc_state->set_context_latency); 2781 2782 /* 2783 * VBLANK_START not used by hw, just clear it 2784 * to make it stand out in register dumps. 2785 */ 2786 crtc_vblank_start = 1; 2787 } else if (DISPLAY_VER(display) == 12) { 2788 /* VBLANK_START - VACTIVE defines SCL on TGL */ 2789 crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency; 2790 } 2791 2792 /* 2793 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. 2794 * But let's write it anyway to keep the state checker happy. 2795 */ 2796 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 2797 VBLANK_START(crtc_vblank_start - 1) | 2798 VBLANK_END(crtc_vblank_end - 1)); 2799 /* 2800 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal 2801 * bits are not required. Since the support for these bits is going to 2802 * be deprecated in upcoming platforms, avoid writing these bits for the 2803 * platforms that do not use legacy Timing Generator. 2804 */ 2805 if (intel_vrr_always_use_vrr_tg(display)) 2806 crtc_vtotal = 1; 2807 2808 /* 2809 * The double buffer latch point for TRANS_VTOTAL 2810 * is the transcoder's undelayed vblank. 2811 */ 2812 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 2813 VACTIVE(crtc_vdisplay - 1) | 2814 VTOTAL(crtc_vtotal - 1)); 2815 2816 intel_vrr_set_fixed_rr_timings(crtc_state); 2817 intel_vrr_transcoder_enable(crtc_state); 2818 } 2819 2820 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) 2821 { 2822 struct intel_display *display = to_intel_display(crtc_state); 2823 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2824 int width = drm_rect_width(&crtc_state->pipe_src); 2825 int height = drm_rect_height(&crtc_state->pipe_src); 2826 enum pipe pipe = crtc->pipe; 2827 2828 /* pipesrc controls the size that is scaled from, which should 2829 * always be the user's requested size. 2830 */ 2831 intel_de_write(display, PIPESRC(display, pipe), 2832 PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); 2833 } 2834 2835 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) 2836 { 2837 struct intel_display *display = to_intel_display(crtc_state); 2838 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2839 2840 if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35) 2841 return false; 2842 2843 if (DISPLAY_VER(display) >= 9 || 2844 display->platform.broadwell || display->platform.haswell) 2845 return intel_de_read(display, 2846 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; 2847 else 2848 return intel_de_read(display, 2849 TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; 2850 } 2851 2852 static void intel_get_transcoder_timings(struct intel_crtc *crtc, 2853 struct intel_crtc_state *pipe_config) 2854 { 2855 struct intel_display *display = to_intel_display(crtc); 2856 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 2857 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2858 u32 tmp; 2859 2860 tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)); 2861 adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; 2862 adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; 2863 2864 if (!transcoder_is_dsi(cpu_transcoder)) { 2865 tmp = intel_de_read(display, 2866 TRANS_HBLANK(display, cpu_transcoder)); 2867 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; 2868 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; 2869 } 2870 2871 tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)); 2872 adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; 2873 adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; 2874 2875 tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); 2876 adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; 2877 adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; 2878 2879 /* FIXME TGL+ DSI transcoders have this! */ 2880 if (!transcoder_is_dsi(cpu_transcoder)) { 2881 tmp = intel_de_read(display, 2882 TRANS_VBLANK(display, cpu_transcoder)); 2883 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; 2884 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; 2885 } 2886 tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)); 2887 adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; 2888 adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; 2889 2890 if (intel_pipe_is_interlaced(pipe_config)) { 2891 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2892 adjusted_mode->crtc_vtotal += 1; 2893 adjusted_mode->crtc_vblank_end += 1; 2894 } 2895 2896 if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) { 2897 pipe_config->set_context_latency = 2898 intel_de_read(display, 2899 TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)); 2900 adjusted_mode->crtc_vblank_start = 2901 adjusted_mode->crtc_vdisplay + 2902 pipe_config->set_context_latency; 2903 } else if (DISPLAY_VER(display) == 12) { 2904 /* 2905 * TGL doesn't have a dedicated register for SCL. 2906 * Instead, the hardware derives SCL from the difference between 2907 * TRANS_VBLANK.vblank_start and TRANS_VTOTAL.vactive. 2908 * To reflect the HW behaviour, readout the value for SCL as 2909 * Vblank start - Vactive. 2910 */ 2911 pipe_config->set_context_latency = 2912 adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; 2913 } 2914 2915 if (DISPLAY_VER(display) >= 30) 2916 pipe_config->min_hblank = intel_de_read(display, 2917 DP_MIN_HBLANK_CTL(cpu_transcoder)); 2918 } 2919 2920 static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) 2921 { 2922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2923 int num_pipes = intel_crtc_num_joined_pipes(crtc_state); 2924 enum pipe primary_pipe, pipe = crtc->pipe; 2925 int width; 2926 2927 if (num_pipes == 1) 2928 return; 2929 2930 primary_pipe = joiner_primary_pipe(crtc_state); 2931 width = drm_rect_width(&crtc_state->pipe_src); 2932 2933 drm_rect_translate_to(&crtc_state->pipe_src, 2934 (pipe - primary_pipe) * width, 0); 2935 } 2936 2937 static void intel_get_pipe_src_size(struct intel_crtc *crtc, 2938 struct intel_crtc_state *pipe_config) 2939 { 2940 struct intel_display *display = to_intel_display(crtc); 2941 u32 tmp; 2942 2943 tmp = intel_de_read(display, PIPESRC(display, crtc->pipe)); 2944 2945 drm_rect_init(&pipe_config->pipe_src, 0, 0, 2946 REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, 2947 REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); 2948 2949 intel_joiner_adjust_pipe_src(pipe_config); 2950 } 2951 2952 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) 2953 { 2954 struct intel_display *display = to_intel_display(crtc_state); 2955 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 2956 u32 val = 0; 2957 2958 /* 2959 * - We keep both pipes enabled on 830 2960 * - During modeset the pipe is still disabled and must remain so 2961 * - During fastset the pipe is already enabled and must remain so 2962 */ 2963 if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state)) 2964 val |= TRANSCONF_ENABLE; 2965 2966 if (crtc_state->double_wide) 2967 val |= TRANSCONF_DOUBLE_WIDE; 2968 2969 /* only g4x and later have fancy bpc/dither controls */ 2970 if (display->platform.g4x || display->platform.valleyview || 2971 display->platform.cherryview) { 2972 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 2973 if (crtc_state->dither && crtc_state->pipe_bpp != 30) 2974 val |= TRANSCONF_DITHER_EN | 2975 TRANSCONF_DITHER_TYPE_SP; 2976 2977 switch (crtc_state->pipe_bpp) { 2978 default: 2979 /* Case prevented by intel_choose_pipe_bpp_dither. */ 2980 MISSING_CASE(crtc_state->pipe_bpp); 2981 fallthrough; 2982 case 18: 2983 val |= TRANSCONF_BPC_6; 2984 break; 2985 case 24: 2986 val |= TRANSCONF_BPC_8; 2987 break; 2988 case 30: 2989 val |= TRANSCONF_BPC_10; 2990 break; 2991 } 2992 } 2993 2994 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 2995 if (DISPLAY_VER(display) < 4 || 2996 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 2997 val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; 2998 else 2999 val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT; 3000 } else { 3001 val |= TRANSCONF_INTERLACE_PROGRESSIVE; 3002 } 3003 3004 if ((display->platform.valleyview || display->platform.cherryview) && 3005 crtc_state->limited_color_range) 3006 val |= TRANSCONF_COLOR_RANGE_SELECT; 3007 3008 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3009 3010 if (crtc_state->wgc_enable) 3011 val |= TRANSCONF_WGC_ENABLE; 3012 3013 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3014 3015 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3016 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3017 } 3018 3019 static enum intel_output_format 3020 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) 3021 { 3022 struct intel_display *display = to_intel_display(crtc); 3023 u32 tmp; 3024 3025 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); 3026 3027 if (tmp & PIPE_MISC_YUV420_ENABLE) { 3028 /* 3029 * We support 4:2:0 in full blend mode only. 3030 * For xe3_lpd+ this is implied in YUV420 Enable bit. 3031 * Ensure the same for prior platforms in YUV420 Mode bit. 3032 */ 3033 if (DISPLAY_VER(display) < 30) 3034 drm_WARN_ON(display->drm, 3035 (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 3036 3037 return INTEL_OUTPUT_FORMAT_YCBCR420; 3038 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { 3039 return INTEL_OUTPUT_FORMAT_YCBCR444; 3040 } else { 3041 return INTEL_OUTPUT_FORMAT_RGB; 3042 } 3043 } 3044 3045 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 3046 struct intel_crtc_state *pipe_config) 3047 { 3048 struct intel_display *display = to_intel_display(crtc); 3049 enum intel_display_power_domain power_domain; 3050 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3051 struct ref_tracker *wakeref; 3052 bool ret = false; 3053 u32 tmp; 3054 3055 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3056 wakeref = intel_display_power_get_if_enabled(display, power_domain); 3057 if (!wakeref) 3058 return false; 3059 3060 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 3061 if (!(tmp & TRANSCONF_ENABLE)) 3062 goto out; 3063 3064 pipe_config->cpu_transcoder = cpu_transcoder; 3065 3066 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3067 pipe_config->sink_format = pipe_config->output_format; 3068 3069 if (display->platform.g4x || display->platform.valleyview || 3070 display->platform.cherryview) { 3071 switch (tmp & TRANSCONF_BPC_MASK) { 3072 case TRANSCONF_BPC_6: 3073 pipe_config->pipe_bpp = 18; 3074 break; 3075 case TRANSCONF_BPC_8: 3076 pipe_config->pipe_bpp = 24; 3077 break; 3078 case TRANSCONF_BPC_10: 3079 pipe_config->pipe_bpp = 30; 3080 break; 3081 default: 3082 MISSING_CASE(tmp); 3083 break; 3084 } 3085 } 3086 3087 if ((display->platform.valleyview || display->platform.cherryview) && 3088 (tmp & TRANSCONF_COLOR_RANGE_SELECT)) 3089 pipe_config->limited_color_range = true; 3090 3091 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp); 3092 3093 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3094 3095 if ((display->platform.valleyview || display->platform.cherryview) && 3096 (tmp & TRANSCONF_WGC_ENABLE)) 3097 pipe_config->wgc_enable = true; 3098 3099 intel_color_get_config(pipe_config); 3100 3101 if (HAS_DOUBLE_WIDE(display)) 3102 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3103 3104 intel_get_transcoder_timings(crtc, pipe_config); 3105 intel_get_pipe_src_size(crtc, pipe_config); 3106 3107 i9xx_pfit_get_config(pipe_config); 3108 3109 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); 3110 3111 if (DISPLAY_VER(display) >= 4) { 3112 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; 3113 pipe_config->pixel_multiplier = 3114 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) 3115 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; 3116 } else if (display->platform.i945g || display->platform.i945gm || 3117 display->platform.g33 || display->platform.pineview) { 3118 tmp = pipe_config->dpll_hw_state.i9xx.dpll; 3119 pipe_config->pixel_multiplier = 3120 ((tmp & SDVO_MULTIPLIER_MASK) 3121 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; 3122 } else { 3123 /* Note that on i915G/GM the pixel multiplier is in the sdvo 3124 * port and will be fixed up in the encoder->get_config 3125 * function. */ 3126 pipe_config->pixel_multiplier = 1; 3127 } 3128 3129 if (display->platform.cherryview) 3130 chv_crtc_clock_get(pipe_config); 3131 else if (display->platform.valleyview) 3132 vlv_crtc_clock_get(pipe_config); 3133 else 3134 i9xx_crtc_clock_get(pipe_config); 3135 3136 /* 3137 * Normally the dotclock is filled in by the encoder .get_config() 3138 * but in case the pipe is enabled w/o any ports we need a sane 3139 * default. 3140 */ 3141 pipe_config->hw.adjusted_mode.crtc_clock = 3142 pipe_config->port_clock / pipe_config->pixel_multiplier; 3143 3144 ret = true; 3145 3146 out: 3147 intel_display_power_put(display, power_domain, wakeref); 3148 3149 return ret; 3150 } 3151 3152 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) 3153 { 3154 struct intel_display *display = to_intel_display(crtc_state); 3155 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3156 u32 val = 0; 3157 3158 /* 3159 * - During modeset the pipe is still disabled and must remain so 3160 * - During fastset the pipe is already enabled and must remain so 3161 */ 3162 if (!intel_crtc_needs_modeset(crtc_state)) 3163 val |= TRANSCONF_ENABLE; 3164 3165 switch (crtc_state->pipe_bpp) { 3166 default: 3167 /* Case prevented by intel_choose_pipe_bpp_dither. */ 3168 MISSING_CASE(crtc_state->pipe_bpp); 3169 fallthrough; 3170 case 18: 3171 val |= TRANSCONF_BPC_6; 3172 break; 3173 case 24: 3174 val |= TRANSCONF_BPC_8; 3175 break; 3176 case 30: 3177 val |= TRANSCONF_BPC_10; 3178 break; 3179 case 36: 3180 val |= TRANSCONF_BPC_12; 3181 break; 3182 } 3183 3184 if (crtc_state->dither) 3185 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3186 3187 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3188 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3189 else 3190 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3191 3192 /* 3193 * This would end up with an odd purple hue over 3194 * the entire display. Make sure we don't do it. 3195 */ 3196 drm_WARN_ON(display->drm, crtc_state->limited_color_range && 3197 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 3198 3199 if (crtc_state->limited_color_range && 3200 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) 3201 val |= TRANSCONF_COLOR_RANGE_SELECT; 3202 3203 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3204 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709; 3205 3206 val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); 3207 3208 val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); 3209 val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); 3210 3211 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3212 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3213 } 3214 3215 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) 3216 { 3217 struct intel_display *display = to_intel_display(crtc_state); 3218 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3219 u32 val = 0; 3220 3221 /* 3222 * - During modeset the pipe is still disabled and must remain so 3223 * - During fastset the pipe is already enabled and must remain so 3224 */ 3225 if (!intel_crtc_needs_modeset(crtc_state)) 3226 val |= TRANSCONF_ENABLE; 3227 3228 if (display->platform.haswell && crtc_state->dither) 3229 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; 3230 3231 if (DISPLAY_VER(display) < 35) { 3232 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 3233 val |= TRANSCONF_INTERLACE_IF_ID_ILK; 3234 else 3235 val |= TRANSCONF_INTERLACE_PF_PD_ILK; 3236 } 3237 3238 if (display->platform.haswell && 3239 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 3240 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; 3241 3242 intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); 3243 intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); 3244 } 3245 3246 static void bdw_set_pipe_misc(struct intel_dsb *dsb, 3247 const struct intel_crtc_state *crtc_state) 3248 { 3249 struct intel_display *display = to_intel_display(crtc_state); 3250 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3251 u32 val = 0; 3252 3253 switch (crtc_state->pipe_bpp) { 3254 case 18: 3255 val |= PIPE_MISC_BPC_6; 3256 break; 3257 case 24: 3258 val |= PIPE_MISC_BPC_8; 3259 break; 3260 case 30: 3261 val |= PIPE_MISC_BPC_10; 3262 break; 3263 case 36: 3264 /* Port output 12BPC defined for ADLP+ */ 3265 if (DISPLAY_VER(display) >= 13) 3266 val |= PIPE_MISC_BPC_12_ADLP; 3267 break; 3268 default: 3269 MISSING_CASE(crtc_state->pipe_bpp); 3270 break; 3271 } 3272 3273 if (crtc_state->dither) 3274 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP; 3275 3276 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 3277 crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 3278 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3279 3280 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3281 val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE : 3282 PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND; 3283 3284 if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state)) 3285 val |= PIPE_MISC_HDR_MODE_PRECISION; 3286 3287 if (DISPLAY_VER(display) >= 12) 3288 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; 3289 3290 /* allow PSR with sprite enabled */ 3291 if (display->platform.broadwell) 3292 val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; 3293 3294 intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val); 3295 } 3296 3297 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) 3298 { 3299 struct intel_display *display = to_intel_display(crtc); 3300 u32 tmp; 3301 3302 tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); 3303 3304 switch (tmp & PIPE_MISC_BPC_MASK) { 3305 case PIPE_MISC_BPC_6: 3306 return 18; 3307 case PIPE_MISC_BPC_8: 3308 return 24; 3309 case PIPE_MISC_BPC_10: 3310 return 30; 3311 /* 3312 * PORT OUTPUT 12 BPC defined for ADLP+. 3313 * 3314 * TODO: 3315 * For previous platforms with DSI interface, bits 5:7 3316 * are used for storing pipe_bpp irrespective of dithering. 3317 * Since the value of 12 BPC is not defined for these bits 3318 * on older platforms, need to find a workaround for 12 BPC 3319 * MIPI DSI HW readout. 3320 */ 3321 case PIPE_MISC_BPC_12_ADLP: 3322 if (DISPLAY_VER(display) >= 13) 3323 return 36; 3324 fallthrough; 3325 default: 3326 MISSING_CASE(tmp); 3327 return 0; 3328 } 3329 } 3330 3331 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) 3332 { 3333 /* 3334 * Account for spread spectrum to avoid 3335 * oversubscribing the link. Max center spread 3336 * is 2.5%; use 5% for safety's sake. 3337 */ 3338 u32 bps = target_clock * bpp * 21 / 20; 3339 return DIV_ROUND_UP(bps, link_bw * 8); 3340 } 3341 3342 void intel_get_m_n(struct intel_display *display, 3343 struct intel_link_m_n *m_n, 3344 i915_reg_t data_m_reg, i915_reg_t data_n_reg, 3345 i915_reg_t link_m_reg, i915_reg_t link_n_reg) 3346 { 3347 m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; 3348 m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; 3349 m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK; 3350 m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK; 3351 m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1; 3352 } 3353 3354 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, 3355 enum transcoder transcoder, 3356 struct intel_link_m_n *m_n) 3357 { 3358 struct intel_display *display = to_intel_display(crtc); 3359 enum pipe pipe = crtc->pipe; 3360 3361 if (DISPLAY_VER(display) >= 5) 3362 intel_get_m_n(display, m_n, 3363 PIPE_DATA_M1(display, transcoder), 3364 PIPE_DATA_N1(display, transcoder), 3365 PIPE_LINK_M1(display, transcoder), 3366 PIPE_LINK_N1(display, transcoder)); 3367 else 3368 intel_get_m_n(display, m_n, 3369 PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), 3370 PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); 3371 } 3372 3373 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, 3374 enum transcoder transcoder, 3375 struct intel_link_m_n *m_n) 3376 { 3377 struct intel_display *display = to_intel_display(crtc); 3378 3379 if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) 3380 return; 3381 3382 intel_get_m_n(display, m_n, 3383 PIPE_DATA_M2(display, transcoder), 3384 PIPE_DATA_N2(display, transcoder), 3385 PIPE_LINK_M2(display, transcoder), 3386 PIPE_LINK_N2(display, transcoder)); 3387 } 3388 3389 static bool ilk_get_pipe_config(struct intel_crtc *crtc, 3390 struct intel_crtc_state *pipe_config) 3391 { 3392 struct intel_display *display = to_intel_display(crtc); 3393 enum intel_display_power_domain power_domain; 3394 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3395 struct ref_tracker *wakeref; 3396 bool ret = false; 3397 u32 tmp; 3398 3399 power_domain = POWER_DOMAIN_PIPE(crtc->pipe); 3400 wakeref = intel_display_power_get_if_enabled(display, power_domain); 3401 if (!wakeref) 3402 return false; 3403 3404 tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); 3405 if (!(tmp & TRANSCONF_ENABLE)) 3406 goto out; 3407 3408 pipe_config->cpu_transcoder = cpu_transcoder; 3409 3410 switch (tmp & TRANSCONF_BPC_MASK) { 3411 case TRANSCONF_BPC_6: 3412 pipe_config->pipe_bpp = 18; 3413 break; 3414 case TRANSCONF_BPC_8: 3415 pipe_config->pipe_bpp = 24; 3416 break; 3417 case TRANSCONF_BPC_10: 3418 pipe_config->pipe_bpp = 30; 3419 break; 3420 case TRANSCONF_BPC_12: 3421 pipe_config->pipe_bpp = 36; 3422 break; 3423 default: 3424 break; 3425 } 3426 3427 if (tmp & TRANSCONF_COLOR_RANGE_SELECT) 3428 pipe_config->limited_color_range = true; 3429 3430 switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) { 3431 case TRANSCONF_OUTPUT_COLORSPACE_YUV601: 3432 case TRANSCONF_OUTPUT_COLORSPACE_YUV709: 3433 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 3434 break; 3435 default: 3436 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 3437 break; 3438 } 3439 3440 pipe_config->sink_format = pipe_config->output_format; 3441 3442 pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); 3443 3444 pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; 3445 3446 pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp); 3447 3448 intel_color_get_config(pipe_config); 3449 3450 pipe_config->pixel_multiplier = 1; 3451 3452 ilk_pch_get_config(pipe_config); 3453 3454 intel_get_transcoder_timings(crtc, pipe_config); 3455 intel_get_pipe_src_size(crtc, pipe_config); 3456 3457 ilk_pfit_get_config(pipe_config); 3458 3459 ret = true; 3460 3461 out: 3462 intel_display_power_put(display, power_domain, wakeref); 3463 3464 return ret; 3465 } 3466 3467 static u8 joiner_pipes(struct intel_display *display) 3468 { 3469 u8 pipes; 3470 3471 if (DISPLAY_VER(display) >= 12) 3472 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); 3473 else if (DISPLAY_VER(display) >= 11) 3474 pipes = BIT(PIPE_B) | BIT(PIPE_C); 3475 else 3476 pipes = 0; 3477 3478 return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask; 3479 } 3480 3481 static bool transcoder_ddi_func_is_enabled(struct intel_display *display, 3482 enum transcoder cpu_transcoder) 3483 { 3484 enum intel_display_power_domain power_domain; 3485 u32 tmp = 0; 3486 3487 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3488 3489 with_intel_display_power_if_enabled(display, power_domain) 3490 tmp = intel_de_read(display, 3491 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3492 3493 return tmp & TRANS_DDI_FUNC_ENABLE; 3494 } 3495 3496 static void enabled_uncompressed_joiner_pipes(struct intel_display *display, 3497 u8 *primary_pipes, u8 *secondary_pipes) 3498 { 3499 struct intel_crtc *crtc; 3500 3501 *primary_pipes = 0; 3502 *secondary_pipes = 0; 3503 3504 if (!HAS_UNCOMPRESSED_JOINER(display)) 3505 return; 3506 3507 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, 3508 joiner_pipes(display)) { 3509 enum intel_display_power_domain power_domain; 3510 enum pipe pipe = crtc->pipe; 3511 3512 power_domain = POWER_DOMAIN_PIPE(pipe); 3513 with_intel_display_power_if_enabled(display, power_domain) { 3514 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3515 3516 if (tmp & UNCOMPRESSED_JOINER_PRIMARY) 3517 *primary_pipes |= BIT(pipe); 3518 if (tmp & UNCOMPRESSED_JOINER_SECONDARY) 3519 *secondary_pipes |= BIT(pipe); 3520 } 3521 } 3522 } 3523 3524 static void enabled_bigjoiner_pipes(struct intel_display *display, 3525 u8 *primary_pipes, u8 *secondary_pipes) 3526 { 3527 struct intel_crtc *crtc; 3528 3529 *primary_pipes = 0; 3530 *secondary_pipes = 0; 3531 3532 if (!HAS_BIGJOINER(display)) 3533 return; 3534 3535 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, 3536 joiner_pipes(display)) { 3537 enum intel_display_power_domain power_domain; 3538 enum pipe pipe = crtc->pipe; 3539 3540 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3541 with_intel_display_power_if_enabled(display, power_domain) { 3542 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3543 3544 if (!(tmp & BIG_JOINER_ENABLE)) 3545 continue; 3546 3547 if (tmp & PRIMARY_BIG_JOINER_ENABLE) 3548 *primary_pipes |= BIT(pipe); 3549 else 3550 *secondary_pipes |= BIT(pipe); 3551 } 3552 } 3553 } 3554 3555 static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes) 3556 { 3557 u8 secondary_pipes = 0; 3558 3559 for (int i = 1; i < num_pipes; i++) 3560 secondary_pipes |= primary_pipes << i; 3561 3562 return secondary_pipes; 3563 } 3564 3565 static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes) 3566 { 3567 return expected_secondary_pipes(uncompjoiner_primary_pipes, 2); 3568 } 3569 3570 static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes) 3571 { 3572 return expected_secondary_pipes(bigjoiner_primary_pipes, 2); 3573 } 3574 3575 static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes) 3576 { 3577 primary_pipes &= GENMASK(pipe, 0); 3578 3579 return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0; 3580 } 3581 3582 static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes) 3583 { 3584 return expected_secondary_pipes(ultrajoiner_primary_pipes, 4); 3585 } 3586 3587 static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes, 3588 u8 ultrajoiner_secondary_pipes) 3589 { 3590 return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3; 3591 } 3592 3593 static void enabled_ultrajoiner_pipes(struct intel_display *display, 3594 u8 *primary_pipes, u8 *secondary_pipes) 3595 { 3596 struct intel_crtc *crtc; 3597 3598 *primary_pipes = 0; 3599 *secondary_pipes = 0; 3600 3601 if (!HAS_ULTRAJOINER(display)) 3602 return; 3603 3604 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, 3605 joiner_pipes(display)) { 3606 enum intel_display_power_domain power_domain; 3607 enum pipe pipe = crtc->pipe; 3608 3609 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3610 with_intel_display_power_if_enabled(display, power_domain) { 3611 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3612 3613 if (!(tmp & ULTRA_JOINER_ENABLE)) 3614 continue; 3615 3616 if (tmp & PRIMARY_ULTRA_JOINER_ENABLE) 3617 *primary_pipes |= BIT(pipe); 3618 else 3619 *secondary_pipes |= BIT(pipe); 3620 } 3621 } 3622 } 3623 3624 static void enabled_joiner_pipes(struct intel_display *display, 3625 enum pipe pipe, 3626 u8 *primary_pipe, u8 *secondary_pipes) 3627 { 3628 u8 primary_ultrajoiner_pipes; 3629 u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes; 3630 u8 secondary_ultrajoiner_pipes; 3631 u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes; 3632 u8 ultrajoiner_pipes; 3633 u8 uncompressed_joiner_pipes, bigjoiner_pipes; 3634 3635 enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes, 3636 &secondary_ultrajoiner_pipes); 3637 /* 3638 * For some strange reason the last pipe in the set of four 3639 * shouldn't have ultrajoiner enable bit set in hardware. 3640 * Set the bit anyway to make life easier. 3641 */ 3642 drm_WARN_ON(display->drm, 3643 expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != 3644 secondary_ultrajoiner_pipes); 3645 secondary_ultrajoiner_pipes = 3646 fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes, 3647 secondary_ultrajoiner_pipes); 3648 3649 drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0); 3650 3651 enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes, 3652 &secondary_uncompressed_joiner_pipes); 3653 3654 drm_WARN_ON(display->drm, 3655 (primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0); 3656 3657 enabled_bigjoiner_pipes(display, &primary_bigjoiner_pipes, 3658 &secondary_bigjoiner_pipes); 3659 3660 drm_WARN_ON(display->drm, 3661 (primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0); 3662 3663 ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes; 3664 uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes | 3665 secondary_uncompressed_joiner_pipes; 3666 bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes; 3667 3668 drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes, 3669 "Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n", 3670 ultrajoiner_pipes, bigjoiner_pipes); 3671 3672 drm_WARN(display->drm, secondary_ultrajoiner_pipes != 3673 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), 3674 "Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n", 3675 expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes), 3676 secondary_ultrajoiner_pipes); 3677 3678 drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0, 3679 "Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n", 3680 uncompressed_joiner_pipes, bigjoiner_pipes); 3681 3682 drm_WARN(display->drm, secondary_bigjoiner_pipes != 3683 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), 3684 "Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n", 3685 expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes), 3686 secondary_bigjoiner_pipes); 3687 3688 drm_WARN(display->drm, secondary_uncompressed_joiner_pipes != 3689 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes), 3690 "Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n", 3691 expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes), 3692 secondary_uncompressed_joiner_pipes); 3693 3694 *primary_pipe = 0; 3695 *secondary_pipes = 0; 3696 3697 if (ultrajoiner_pipes & BIT(pipe)) { 3698 *primary_pipe = get_joiner_primary_pipe(pipe, primary_ultrajoiner_pipes); 3699 *secondary_pipes = secondary_ultrajoiner_pipes & 3700 expected_ultrajoiner_secondary_pipes(*primary_pipe); 3701 3702 drm_WARN(display->drm, 3703 expected_ultrajoiner_secondary_pipes(*primary_pipe) != 3704 *secondary_pipes, 3705 "Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3706 *primary_pipe, 3707 expected_ultrajoiner_secondary_pipes(*primary_pipe), 3708 *secondary_pipes); 3709 return; 3710 } 3711 3712 if (uncompressed_joiner_pipes & BIT(pipe)) { 3713 *primary_pipe = get_joiner_primary_pipe(pipe, primary_uncompressed_joiner_pipes); 3714 *secondary_pipes = secondary_uncompressed_joiner_pipes & 3715 expected_uncompressed_joiner_secondary_pipes(*primary_pipe); 3716 3717 drm_WARN(display->drm, 3718 expected_uncompressed_joiner_secondary_pipes(*primary_pipe) != 3719 *secondary_pipes, 3720 "Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3721 *primary_pipe, 3722 expected_uncompressed_joiner_secondary_pipes(*primary_pipe), 3723 *secondary_pipes); 3724 return; 3725 } 3726 3727 if (bigjoiner_pipes & BIT(pipe)) { 3728 *primary_pipe = get_joiner_primary_pipe(pipe, primary_bigjoiner_pipes); 3729 *secondary_pipes = secondary_bigjoiner_pipes & 3730 expected_bigjoiner_secondary_pipes(*primary_pipe); 3731 3732 drm_WARN(display->drm, 3733 expected_bigjoiner_secondary_pipes(*primary_pipe) != 3734 *secondary_pipes, 3735 "Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n", 3736 *primary_pipe, 3737 expected_bigjoiner_secondary_pipes(*primary_pipe), 3738 *secondary_pipes); 3739 return; 3740 } 3741 } 3742 3743 static u8 hsw_panel_transcoders(struct intel_display *display) 3744 { 3745 u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); 3746 3747 if (DISPLAY_VER(display) >= 11) 3748 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); 3749 3750 return panel_transcoder_mask; 3751 } 3752 3753 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) 3754 { 3755 struct intel_display *display = to_intel_display(crtc); 3756 u8 panel_transcoder_mask = hsw_panel_transcoders(display); 3757 enum transcoder cpu_transcoder; 3758 u8 primary_pipe, secondary_pipes; 3759 u8 enabled_transcoders = 0; 3760 3761 /* 3762 * XXX: Do intel_display_power_get_if_enabled before reading this (for 3763 * consistency and less surprising code; it's in always on power). 3764 */ 3765 for_each_cpu_transcoder_masked(display, cpu_transcoder, 3766 panel_transcoder_mask) { 3767 enum intel_display_power_domain power_domain; 3768 enum pipe trans_pipe; 3769 u32 tmp = 0; 3770 3771 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3772 with_intel_display_power_if_enabled(display, power_domain) 3773 tmp = intel_de_read(display, 3774 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3775 3776 if (!(tmp & TRANS_DDI_FUNC_ENABLE)) 3777 continue; 3778 3779 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 3780 default: 3781 drm_WARN(display->drm, 1, 3782 "unknown pipe linked to transcoder %s\n", 3783 transcoder_name(cpu_transcoder)); 3784 fallthrough; 3785 case TRANS_DDI_EDP_INPUT_A_ONOFF: 3786 case TRANS_DDI_EDP_INPUT_A_ON: 3787 trans_pipe = PIPE_A; 3788 break; 3789 case TRANS_DDI_EDP_INPUT_B_ONOFF: 3790 trans_pipe = PIPE_B; 3791 break; 3792 case TRANS_DDI_EDP_INPUT_C_ONOFF: 3793 trans_pipe = PIPE_C; 3794 break; 3795 case TRANS_DDI_EDP_INPUT_D_ONOFF: 3796 trans_pipe = PIPE_D; 3797 break; 3798 } 3799 3800 if (trans_pipe == crtc->pipe) 3801 enabled_transcoders |= BIT(cpu_transcoder); 3802 } 3803 3804 /* single pipe or joiner primary */ 3805 cpu_transcoder = (enum transcoder) crtc->pipe; 3806 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) 3807 enabled_transcoders |= BIT(cpu_transcoder); 3808 3809 /* joiner secondary -> consider the primary pipe's transcoder as well */ 3810 enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes); 3811 if (secondary_pipes & BIT(crtc->pipe)) { 3812 cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1; 3813 if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) 3814 enabled_transcoders |= BIT(cpu_transcoder); 3815 } 3816 3817 return enabled_transcoders; 3818 } 3819 3820 static bool has_edp_transcoders(u8 enabled_transcoders) 3821 { 3822 return enabled_transcoders & BIT(TRANSCODER_EDP); 3823 } 3824 3825 static bool has_dsi_transcoders(u8 enabled_transcoders) 3826 { 3827 return enabled_transcoders & (BIT(TRANSCODER_DSI_0) | 3828 BIT(TRANSCODER_DSI_1)); 3829 } 3830 3831 static bool has_pipe_transcoders(u8 enabled_transcoders) 3832 { 3833 return enabled_transcoders & ~(BIT(TRANSCODER_EDP) | 3834 BIT(TRANSCODER_DSI_0) | 3835 BIT(TRANSCODER_DSI_1)); 3836 } 3837 3838 static void assert_enabled_transcoders(struct intel_display *display, 3839 u8 enabled_transcoders) 3840 { 3841 /* Only one type of transcoder please */ 3842 drm_WARN_ON(display->drm, 3843 has_edp_transcoders(enabled_transcoders) + 3844 has_dsi_transcoders(enabled_transcoders) + 3845 has_pipe_transcoders(enabled_transcoders) > 1); 3846 3847 /* Only DSI transcoders can be ganged */ 3848 drm_WARN_ON(display->drm, 3849 !has_dsi_transcoders(enabled_transcoders) && 3850 !is_power_of_2(enabled_transcoders)); 3851 } 3852 3853 static bool hsw_get_transcoder_state(struct intel_crtc *crtc, 3854 struct intel_crtc_state *pipe_config, 3855 struct intel_display_power_domain_set *power_domain_set) 3856 { 3857 struct intel_display *display = to_intel_display(crtc); 3858 unsigned long enabled_transcoders; 3859 u32 tmp; 3860 3861 enabled_transcoders = hsw_enabled_transcoders(crtc); 3862 if (!enabled_transcoders) 3863 return false; 3864 3865 assert_enabled_transcoders(display, enabled_transcoders); 3866 3867 /* 3868 * With the exception of DSI we should only ever have 3869 * a single enabled transcoder. With DSI let's just 3870 * pick the first one. 3871 */ 3872 pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; 3873 3874 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, 3875 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) 3876 return false; 3877 3878 if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) { 3879 tmp = intel_de_read(display, 3880 TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder)); 3881 3882 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) 3883 pipe_config->pch_pfit.force_thru = true; 3884 } 3885 3886 tmp = intel_de_read(display, 3887 TRANSCONF(display, pipe_config->cpu_transcoder)); 3888 3889 return tmp & TRANSCONF_ENABLE; 3890 } 3891 3892 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 3893 struct intel_crtc_state *pipe_config, 3894 struct intel_display_power_domain_set *power_domain_set) 3895 { 3896 struct intel_display *display = to_intel_display(crtc); 3897 enum transcoder cpu_transcoder; 3898 enum port port; 3899 u32 tmp; 3900 3901 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { 3902 if (port == PORT_A) 3903 cpu_transcoder = TRANSCODER_DSI_A; 3904 else 3905 cpu_transcoder = TRANSCODER_DSI_C; 3906 3907 if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, 3908 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 3909 continue; 3910 3911 /* 3912 * The PLL needs to be enabled with a valid divider 3913 * configuration, otherwise accessing DSI registers will hang 3914 * the machine. See BSpec North Display Engine 3915 * registers/MIPI[BXT]. We can break out here early, since we 3916 * need the same DSI PLL to be enabled for both DSI ports. 3917 */ 3918 if (!bxt_dsi_pll_is_enabled(display)) 3919 break; 3920 3921 /* XXX: this works for video mode only */ 3922 tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port)); 3923 if (!(tmp & DPI_ENABLE)) 3924 continue; 3925 3926 tmp = intel_de_read(display, MIPI_CTRL(display, port)); 3927 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) 3928 continue; 3929 3930 pipe_config->cpu_transcoder = cpu_transcoder; 3931 break; 3932 } 3933 3934 return transcoder_is_dsi(pipe_config->cpu_transcoder); 3935 } 3936 3937 static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) 3938 { 3939 struct intel_display *display = to_intel_display(crtc_state); 3940 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3941 u8 primary_pipe, secondary_pipes; 3942 enum pipe pipe = crtc->pipe; 3943 3944 enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes); 3945 3946 if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0) 3947 return; 3948 3949 crtc_state->joiner_pipes = primary_pipe | secondary_pipes; 3950 } 3951 3952 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 3953 struct intel_crtc_state *pipe_config) 3954 { 3955 struct intel_display *display = to_intel_display(crtc); 3956 bool active; 3957 u32 tmp; 3958 3959 if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, 3960 POWER_DOMAIN_PIPE(crtc->pipe))) 3961 return false; 3962 3963 active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); 3964 3965 if ((display->platform.geminilake || display->platform.broxton) && 3966 bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { 3967 drm_WARN_ON(display->drm, active); 3968 active = true; 3969 } 3970 3971 if (!active) 3972 goto out; 3973 3974 intel_joiner_get_config(pipe_config); 3975 intel_dsc_get_config(pipe_config); 3976 3977 /* intel_vrr_get_config() depends on .framestart_delay */ 3978 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 3979 tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder)); 3980 3981 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 3982 } else { 3983 /* no idea if this is correct */ 3984 pipe_config->framestart_delay = 1; 3985 } 3986 3987 /* 3988 * intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY 3989 * readout done by intel_get_transcoder_timings(). 3990 */ 3991 if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || 3992 DISPLAY_VER(display) >= 11) 3993 intel_get_transcoder_timings(crtc, pipe_config); 3994 3995 if (transcoder_has_vrr(pipe_config)) 3996 intel_vrr_get_config(pipe_config); 3997 3998 intel_get_pipe_src_size(crtc, pipe_config); 3999 4000 if (display->platform.haswell) { 4001 u32 tmp = intel_de_read(display, 4002 TRANSCONF(display, pipe_config->cpu_transcoder)); 4003 4004 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) 4005 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; 4006 else 4007 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 4008 } else { 4009 pipe_config->output_format = 4010 bdw_get_pipe_misc_output_format(crtc); 4011 } 4012 4013 pipe_config->sink_format = pipe_config->output_format; 4014 4015 intel_color_get_config(pipe_config); 4016 4017 tmp = intel_de_read(display, WM_LINETIME(crtc->pipe)); 4018 pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); 4019 if (display->platform.broadwell || display->platform.haswell) 4020 pipe_config->ips_linetime = 4021 REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); 4022 4023 if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, 4024 POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { 4025 if (DISPLAY_VER(display) >= 9) 4026 skl_scaler_get_config(pipe_config); 4027 else 4028 ilk_pfit_get_config(pipe_config); 4029 } 4030 4031 hsw_ips_get_config(pipe_config); 4032 4033 if (pipe_config->cpu_transcoder != TRANSCODER_EDP && 4034 !transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4035 pipe_config->pixel_multiplier = 4036 intel_de_read(display, 4037 TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1; 4038 } else { 4039 pipe_config->pixel_multiplier = 1; 4040 } 4041 4042 out: 4043 intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains); 4044 4045 return active; 4046 } 4047 4048 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) 4049 { 4050 struct intel_display *display = to_intel_display(crtc_state); 4051 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4052 4053 if (!display->funcs.display->get_pipe_config(crtc, crtc_state)) 4054 return false; 4055 4056 crtc_state->hw.active = true; 4057 4058 intel_crtc_readout_derived_state(crtc_state); 4059 4060 return true; 4061 } 4062 4063 int intel_dotclock_calculate(int link_freq, 4064 const struct intel_link_m_n *m_n) 4065 { 4066 /* 4067 * The calculation for the data clock -> pixel clock is: 4068 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp 4069 * But we want to avoid losing precision if possible, so: 4070 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) 4071 * 4072 * and for link freq (10kbs units) -> pixel clock it is: 4073 * link_symbol_clock = link_freq * 10 / link_symbol_size 4074 * pixel_clock = (m * link_symbol_clock) / n 4075 * or for more precision: 4076 * pixel_clock = (m * link_freq * 10) / (n * link_symbol_size) 4077 */ 4078 4079 if (!m_n->link_n) 4080 return 0; 4081 4082 return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10), 4083 m_n->link_n * intel_dp_link_symbol_size(link_freq)); 4084 } 4085 4086 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config) 4087 { 4088 int dotclock; 4089 4090 if (intel_crtc_has_dp_encoder(pipe_config)) 4091 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 4092 &pipe_config->dp_m_n); 4093 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) 4094 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, 4095 pipe_config->pipe_bpp); 4096 else 4097 dotclock = pipe_config->port_clock; 4098 4099 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 4100 !intel_crtc_has_dp_encoder(pipe_config)) 4101 dotclock *= 2; 4102 4103 if (pipe_config->pixel_multiplier) 4104 dotclock /= pipe_config->pixel_multiplier; 4105 4106 return dotclock; 4107 } 4108 4109 /* Returns the currently programmed mode of the given encoder. */ 4110 struct drm_display_mode * 4111 intel_encoder_current_mode(struct intel_encoder *encoder) 4112 { 4113 struct intel_display *display = to_intel_display(encoder); 4114 struct intel_crtc_state *crtc_state; 4115 struct drm_display_mode *mode; 4116 struct intel_crtc *crtc; 4117 enum pipe pipe; 4118 4119 if (!encoder->get_hw_state(encoder, &pipe)) 4120 return NULL; 4121 4122 crtc = intel_crtc_for_pipe(display, pipe); 4123 4124 mode = kzalloc_obj(*mode); 4125 if (!mode) 4126 return NULL; 4127 4128 crtc_state = intel_crtc_state_alloc(crtc); 4129 if (!crtc_state) { 4130 kfree(mode); 4131 return NULL; 4132 } 4133 4134 if (!intel_crtc_get_pipe_config(crtc_state)) { 4135 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4136 kfree(mode); 4137 return NULL; 4138 } 4139 4140 intel_encoder_get_config(encoder, crtc_state); 4141 4142 intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode); 4143 4144 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi); 4145 4146 return mode; 4147 } 4148 4149 static bool encoders_cloneable(const struct intel_encoder *a, 4150 const struct intel_encoder *b) 4151 { 4152 /* masks could be asymmetric, so check both ways */ 4153 return a == b || (a->cloneable & BIT(b->type) && 4154 b->cloneable & BIT(a->type)); 4155 } 4156 4157 static bool check_single_encoder_cloning(struct intel_atomic_state *state, 4158 struct intel_crtc *crtc, 4159 struct intel_encoder *encoder) 4160 { 4161 struct intel_encoder *source_encoder; 4162 struct drm_connector *connector; 4163 struct drm_connector_state *connector_state; 4164 int i; 4165 4166 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4167 if (connector_state->crtc != &crtc->base) 4168 continue; 4169 4170 source_encoder = 4171 to_intel_encoder(connector_state->best_encoder); 4172 if (!encoders_cloneable(encoder, source_encoder)) 4173 return false; 4174 } 4175 4176 return true; 4177 } 4178 4179 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) 4180 { 4181 const struct drm_display_mode *pipe_mode = 4182 &crtc_state->hw.pipe_mode; 4183 int linetime_wm; 4184 4185 if (!crtc_state->hw.enable) 4186 return 0; 4187 4188 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4189 pipe_mode->crtc_clock); 4190 4191 return min(linetime_wm, 0x1ff); 4192 } 4193 4194 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, 4195 const struct intel_cdclk_state *cdclk_state) 4196 { 4197 const struct drm_display_mode *pipe_mode = 4198 &crtc_state->hw.pipe_mode; 4199 int linetime_wm; 4200 4201 if (!crtc_state->hw.enable) 4202 return 0; 4203 4204 linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8, 4205 intel_cdclk_logical(cdclk_state)); 4206 4207 return min(linetime_wm, 0x1ff); 4208 } 4209 4210 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) 4211 { 4212 struct intel_display *display = to_intel_display(crtc_state); 4213 const struct drm_display_mode *pipe_mode = 4214 &crtc_state->hw.pipe_mode; 4215 int linetime_wm; 4216 4217 if (!crtc_state->hw.enable) 4218 return 0; 4219 4220 linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8, 4221 crtc_state->pixel_rate); 4222 4223 /* Display WA #1135: BXT:ALL GLK:ALL */ 4224 if ((display->platform.geminilake || display->platform.broxton) && 4225 skl_watermark_ipc_enabled(display)) 4226 linetime_wm /= 2; 4227 4228 return min(linetime_wm, 0x1ff); 4229 } 4230 4231 static int hsw_compute_linetime_wm(struct intel_atomic_state *state, 4232 struct intel_crtc *crtc) 4233 { 4234 struct intel_display *display = to_intel_display(state); 4235 struct intel_crtc_state *crtc_state = 4236 intel_atomic_get_new_crtc_state(state, crtc); 4237 const struct intel_cdclk_state *cdclk_state; 4238 4239 if (DISPLAY_VER(display) >= 9) 4240 crtc_state->linetime = skl_linetime_wm(crtc_state); 4241 else 4242 crtc_state->linetime = hsw_linetime_wm(crtc_state); 4243 4244 if (!hsw_crtc_supports_ips(crtc)) 4245 return 0; 4246 4247 cdclk_state = intel_atomic_get_cdclk_state(state); 4248 if (IS_ERR(cdclk_state)) 4249 return PTR_ERR(cdclk_state); 4250 4251 crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, 4252 cdclk_state); 4253 4254 return 0; 4255 } 4256 4257 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4258 struct intel_crtc *crtc) 4259 { 4260 struct intel_display *display = to_intel_display(crtc); 4261 struct intel_crtc_state *crtc_state = 4262 intel_atomic_get_new_crtc_state(state, crtc); 4263 int ret; 4264 4265 if (DISPLAY_VER(display) < 5 && !display->platform.g4x && 4266 intel_crtc_needs_modeset(crtc_state) && 4267 !crtc_state->hw.active) 4268 crtc_state->update_wm_post = true; 4269 4270 if (intel_crtc_needs_modeset(crtc_state)) { 4271 ret = intel_dpll_crtc_get_dpll(state, crtc); 4272 if (ret) 4273 return ret; 4274 } 4275 4276 ret = intel_color_check(state, crtc); 4277 if (ret) 4278 return ret; 4279 4280 ret = intel_wm_compute(state, crtc); 4281 if (ret) { 4282 drm_dbg_kms(display->drm, 4283 "[CRTC:%d:%s] watermarks are invalid\n", 4284 crtc->base.base.id, crtc->base.name); 4285 return ret; 4286 } 4287 4288 ret = intel_casf_compute_config(crtc_state); 4289 if (ret) 4290 return ret; 4291 4292 if (DISPLAY_VER(display) >= 9) { 4293 if (intel_crtc_needs_modeset(crtc_state) || 4294 intel_crtc_needs_fastset(crtc_state) || 4295 intel_casf_needs_scaler(crtc_state)) { 4296 ret = skl_update_scaler_crtc(crtc_state); 4297 if (ret) 4298 return ret; 4299 } 4300 4301 ret = intel_atomic_setup_scalers(state, crtc); 4302 if (ret) 4303 return ret; 4304 } 4305 4306 if (HAS_IPS(display)) { 4307 ret = hsw_ips_compute_config(state, crtc); 4308 if (ret) 4309 return ret; 4310 } 4311 4312 if (DISPLAY_VER(display) >= 9 || 4313 display->platform.broadwell || display->platform.haswell) { 4314 ret = hsw_compute_linetime_wm(state, crtc); 4315 if (ret) 4316 return ret; 4317 4318 } 4319 4320 ret = intel_psr2_sel_fetch_update(state, crtc); 4321 if (ret) 4322 return ret; 4323 4324 return 0; 4325 } 4326 4327 static int 4328 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, 4329 struct intel_crtc_state *crtc_state) 4330 { 4331 struct intel_display *display = to_intel_display(crtc_state); 4332 struct drm_connector *connector = conn_state->connector; 4333 const struct drm_display_info *info = &connector->display_info; 4334 int bpp; 4335 4336 switch (conn_state->max_bpc) { 4337 case 6 ... 7: 4338 bpp = 6 * 3; 4339 break; 4340 case 8 ... 9: 4341 bpp = 8 * 3; 4342 break; 4343 case 10 ... 11: 4344 bpp = 10 * 3; 4345 break; 4346 case 12 ... 16: 4347 bpp = 12 * 3; 4348 break; 4349 default: 4350 MISSING_CASE(conn_state->max_bpc); 4351 return -EINVAL; 4352 } 4353 4354 if (bpp < crtc_state->pipe_bpp) { 4355 drm_dbg_kms(display->drm, 4356 "[CONNECTOR:%d:%s] Limiting display bpp to %d " 4357 "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", 4358 connector->base.id, connector->name, 4359 bpp, 3 * info->bpc, 4360 3 * conn_state->max_requested_bpc, 4361 crtc_state->pipe_bpp); 4362 4363 crtc_state->pipe_bpp = bpp; 4364 } 4365 4366 return 0; 4367 } 4368 4369 int intel_display_min_pipe_bpp(void) 4370 { 4371 return 6 * 3; 4372 } 4373 4374 int intel_display_max_pipe_bpp(struct intel_display *display) 4375 { 4376 if (display->platform.g4x || display->platform.valleyview || 4377 display->platform.cherryview) 4378 return 10*3; 4379 else if (DISPLAY_VER(display) >= 5) 4380 return 12*3; 4381 else 4382 return 8*3; 4383 } 4384 4385 static int 4386 compute_baseline_pipe_bpp(struct intel_atomic_state *state, 4387 struct intel_crtc *crtc) 4388 { 4389 struct intel_display *display = to_intel_display(crtc); 4390 struct intel_crtc_state *crtc_state = 4391 intel_atomic_get_new_crtc_state(state, crtc); 4392 struct drm_connector *connector; 4393 struct drm_connector_state *connector_state; 4394 int i; 4395 4396 crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display); 4397 4398 /* Clamp display bpp to connector max bpp */ 4399 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4400 int ret; 4401 4402 if (connector_state->crtc != &crtc->base) 4403 continue; 4404 4405 ret = compute_sink_pipe_bpp(connector_state, crtc_state); 4406 if (ret) 4407 return ret; 4408 } 4409 4410 return 0; 4411 } 4412 4413 static bool check_digital_port_conflicts(struct intel_atomic_state *state) 4414 { 4415 struct intel_display *display = to_intel_display(state); 4416 struct drm_connector *connector; 4417 struct drm_connector_list_iter conn_iter; 4418 unsigned int used_ports = 0; 4419 unsigned int used_mst_ports = 0; 4420 bool ret = true; 4421 4422 /* 4423 * We're going to peek into connector->state, 4424 * hence connection_mutex must be held. 4425 */ 4426 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); 4427 4428 /* 4429 * Walk the connector list instead of the encoder 4430 * list to detect the problem on ddi platforms 4431 * where there's just one encoder per digital port. 4432 */ 4433 drm_connector_list_iter_begin(display->drm, &conn_iter); 4434 drm_for_each_connector_iter(connector, &conn_iter) { 4435 struct drm_connector_state *connector_state; 4436 struct intel_encoder *encoder; 4437 4438 connector_state = 4439 drm_atomic_get_new_connector_state(&state->base, 4440 connector); 4441 if (!connector_state) 4442 connector_state = connector->state; 4443 4444 if (!connector_state->best_encoder) 4445 continue; 4446 4447 encoder = to_intel_encoder(connector_state->best_encoder); 4448 4449 drm_WARN_ON(display->drm, !connector_state->crtc); 4450 4451 switch (encoder->type) { 4452 case INTEL_OUTPUT_DDI: 4453 if (drm_WARN_ON(display->drm, !HAS_DDI(display))) 4454 break; 4455 fallthrough; 4456 case INTEL_OUTPUT_DP: 4457 case INTEL_OUTPUT_HDMI: 4458 case INTEL_OUTPUT_EDP: 4459 /* the same port mustn't appear more than once */ 4460 if (used_ports & BIT(encoder->port)) 4461 ret = false; 4462 4463 used_ports |= BIT(encoder->port); 4464 break; 4465 case INTEL_OUTPUT_DP_MST: 4466 used_mst_ports |= 4467 1 << encoder->port; 4468 break; 4469 default: 4470 break; 4471 } 4472 } 4473 drm_connector_list_iter_end(&conn_iter); 4474 4475 /* can't mix MST and SST/HDMI on the same port */ 4476 if (used_ports & used_mst_ports) 4477 return false; 4478 4479 return ret; 4480 } 4481 4482 static void 4483 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, 4484 struct intel_crtc *crtc) 4485 { 4486 struct intel_crtc_state *crtc_state = 4487 intel_atomic_get_new_crtc_state(state, crtc); 4488 4489 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4490 4491 drm_property_replace_blob(&crtc_state->hw.degamma_lut, 4492 crtc_state->uapi.degamma_lut); 4493 drm_property_replace_blob(&crtc_state->hw.gamma_lut, 4494 crtc_state->uapi.gamma_lut); 4495 drm_property_replace_blob(&crtc_state->hw.ctm, 4496 crtc_state->uapi.ctm); 4497 } 4498 4499 static void 4500 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, 4501 struct intel_crtc *crtc) 4502 { 4503 struct intel_crtc_state *crtc_state = 4504 intel_atomic_get_new_crtc_state(state, crtc); 4505 4506 WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); 4507 4508 crtc_state->hw.enable = crtc_state->uapi.enable; 4509 crtc_state->hw.active = crtc_state->uapi.active; 4510 drm_mode_copy(&crtc_state->hw.mode, 4511 &crtc_state->uapi.mode); 4512 drm_mode_copy(&crtc_state->hw.adjusted_mode, 4513 &crtc_state->uapi.adjusted_mode); 4514 crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter; 4515 4516 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 4517 } 4518 4519 static void 4520 copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state, 4521 struct intel_crtc *secondary_crtc) 4522 { 4523 struct intel_crtc_state *secondary_crtc_state = 4524 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4525 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4526 const struct intel_crtc_state *primary_crtc_state = 4527 intel_atomic_get_new_crtc_state(state, primary_crtc); 4528 4529 drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut, 4530 primary_crtc_state->hw.degamma_lut); 4531 drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut, 4532 primary_crtc_state->hw.gamma_lut); 4533 drm_property_replace_blob(&secondary_crtc_state->hw.ctm, 4534 primary_crtc_state->hw.ctm); 4535 4536 secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed; 4537 } 4538 4539 static int 4540 copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, 4541 struct intel_crtc *secondary_crtc) 4542 { 4543 struct intel_crtc_state *secondary_crtc_state = 4544 intel_atomic_get_new_crtc_state(state, secondary_crtc); 4545 struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); 4546 const struct intel_crtc_state *primary_crtc_state = 4547 intel_atomic_get_new_crtc_state(state, primary_crtc); 4548 struct intel_crtc_state *saved_state; 4549 4550 WARN_ON(primary_crtc_state->joiner_pipes != 4551 secondary_crtc_state->joiner_pipes); 4552 4553 saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL); 4554 if (!saved_state) 4555 return -ENOMEM; 4556 4557 /* preserve some things from the slave's original crtc state */ 4558 saved_state->uapi = secondary_crtc_state->uapi; 4559 saved_state->scaler_state = secondary_crtc_state->scaler_state; 4560 saved_state->intel_dpll = secondary_crtc_state->intel_dpll; 4561 saved_state->crc_enabled = secondary_crtc_state->crc_enabled; 4562 4563 intel_crtc_free_hw_state(secondary_crtc_state); 4564 if (secondary_crtc_state->dp_tunnel_ref.tunnel) 4565 drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref); 4566 memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state)); 4567 kfree(saved_state); 4568 4569 /* Re-init hw state */ 4570 memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw)); 4571 secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable; 4572 secondary_crtc_state->hw.active = primary_crtc_state->hw.active; 4573 drm_mode_copy(&secondary_crtc_state->hw.mode, 4574 &primary_crtc_state->hw.mode); 4575 drm_mode_copy(&secondary_crtc_state->hw.pipe_mode, 4576 &primary_crtc_state->hw.pipe_mode); 4577 drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode, 4578 &primary_crtc_state->hw.adjusted_mode); 4579 secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter; 4580 4581 if (primary_crtc_state->dp_tunnel_ref.tunnel) 4582 drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel, 4583 &secondary_crtc_state->dp_tunnel_ref); 4584 4585 copy_joiner_crtc_state_nomodeset(state, secondary_crtc); 4586 4587 secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed; 4588 secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed; 4589 secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed; 4590 4591 WARN_ON(primary_crtc_state->joiner_pipes != 4592 secondary_crtc_state->joiner_pipes); 4593 4594 return 0; 4595 } 4596 4597 static int 4598 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 4599 struct intel_crtc *crtc) 4600 { 4601 struct intel_display *display = to_intel_display(state); 4602 struct intel_crtc_state *crtc_state = 4603 intel_atomic_get_new_crtc_state(state, crtc); 4604 struct intel_crtc_state *saved_state; 4605 int err; 4606 4607 saved_state = intel_crtc_state_alloc(crtc); 4608 if (!saved_state) 4609 return -ENOMEM; 4610 4611 /* free the old crtc_state->hw members */ 4612 intel_crtc_free_hw_state(crtc_state); 4613 4614 err = intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state); 4615 if (err) { 4616 kfree(saved_state); 4617 4618 return err; 4619 } 4620 4621 /* FIXME: before the switch to atomic started, a new pipe_config was 4622 * kzalloc'd. Code that depends on any field being zero should be 4623 * fixed, so that the crtc_state can be safely duplicated. For now, 4624 * only fields that are know to not cause problems are preserved. */ 4625 4626 saved_state->uapi = crtc_state->uapi; 4627 saved_state->inherited = crtc_state->inherited; 4628 saved_state->scaler_state = crtc_state->scaler_state; 4629 saved_state->intel_dpll = crtc_state->intel_dpll; 4630 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; 4631 memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, 4632 sizeof(saved_state->icl_port_dplls)); 4633 saved_state->crc_enabled = crtc_state->crc_enabled; 4634 if (display->platform.g4x || 4635 display->platform.valleyview || display->platform.cherryview) 4636 saved_state->wm = crtc_state->wm; 4637 4638 memcpy(crtc_state, saved_state, sizeof(*crtc_state)); 4639 kfree(saved_state); 4640 4641 intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc); 4642 4643 return 0; 4644 } 4645 4646 static int 4647 intel_modeset_pipe_config(struct intel_atomic_state *state, 4648 struct intel_crtc *crtc, 4649 const struct intel_link_bw_limits *limits) 4650 { 4651 struct intel_display *display = to_intel_display(crtc); 4652 struct intel_crtc_state *crtc_state = 4653 intel_atomic_get_new_crtc_state(state, crtc); 4654 struct drm_connector *connector; 4655 struct drm_connector_state *connector_state; 4656 int pipe_src_w, pipe_src_h; 4657 int base_bpp, ret, i; 4658 4659 crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe; 4660 4661 crtc_state->framestart_delay = 1; 4662 4663 /* 4664 * Sanitize sync polarity flags based on requested ones. If neither 4665 * positive or negative polarity is requested, treat this as meaning 4666 * negative polarity. 4667 */ 4668 if (!(crtc_state->hw.adjusted_mode.flags & 4669 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 4670 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 4671 4672 if (!(crtc_state->hw.adjusted_mode.flags & 4673 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 4674 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 4675 4676 ret = compute_baseline_pipe_bpp(state, crtc); 4677 if (ret) 4678 return ret; 4679 4680 crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe); 4681 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe]; 4682 4683 if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) { 4684 drm_dbg_kms(display->drm, 4685 "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n", 4686 crtc->base.base.id, crtc->base.name, 4687 FXP_Q4_ARGS(crtc_state->max_link_bpp_x16)); 4688 crtc_state->bw_constrained = true; 4689 } 4690 4691 base_bpp = crtc_state->pipe_bpp; 4692 4693 /* 4694 * Determine the real pipe dimensions. Note that stereo modes can 4695 * increase the actual pipe size due to the frame doubling and 4696 * insertion of additional space for blanks between the frame. This 4697 * is stored in the crtc timings. We use the requested mode to do this 4698 * computation to clearly distinguish it from the adjusted mode, which 4699 * can be changed by the connectors in the below retry loop. 4700 */ 4701 drm_mode_get_hv_timing(&crtc_state->hw.mode, 4702 &pipe_src_w, &pipe_src_h); 4703 drm_rect_init(&crtc_state->pipe_src, 0, 0, 4704 pipe_src_w, pipe_src_h); 4705 4706 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4707 struct intel_encoder *encoder = 4708 to_intel_encoder(connector_state->best_encoder); 4709 4710 if (connector_state->crtc != &crtc->base) 4711 continue; 4712 4713 if (!check_single_encoder_cloning(state, crtc, encoder)) { 4714 drm_dbg_kms(display->drm, 4715 "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", 4716 encoder->base.base.id, encoder->base.name); 4717 return -EINVAL; 4718 } 4719 4720 /* 4721 * Determine output_types before calling the .compute_config() 4722 * hooks so that the hooks can use this information safely. 4723 */ 4724 if (encoder->compute_output_type) 4725 crtc_state->output_types |= 4726 BIT(encoder->compute_output_type(encoder, crtc_state, 4727 connector_state)); 4728 else 4729 crtc_state->output_types |= BIT(encoder->type); 4730 } 4731 4732 /* Ensure the port clock defaults are reset when retrying. */ 4733 crtc_state->port_clock = 0; 4734 crtc_state->pixel_multiplier = 1; 4735 4736 /* Fill in default crtc timings, allow encoders to overwrite them. */ 4737 drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode, 4738 CRTC_STEREO_DOUBLE); 4739 4740 /* Pass our mode to the connectors and the CRTC to give them a chance to 4741 * adjust it according to limitations or connector properties, and also 4742 * a chance to reject the mode entirely. 4743 */ 4744 for_each_new_connector_in_state(&state->base, connector, connector_state, i) { 4745 struct intel_encoder *encoder = 4746 to_intel_encoder(connector_state->best_encoder); 4747 4748 if (connector_state->crtc != &crtc->base) 4749 continue; 4750 4751 ret = encoder->compute_config(encoder, crtc_state, 4752 connector_state); 4753 if (ret == -EDEADLK) 4754 return ret; 4755 if (ret < 0) { 4756 drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n", 4757 encoder->base.base.id, encoder->base.name, ret); 4758 return ret; 4759 } 4760 } 4761 4762 /* Set default port clock if not overwritten by the encoder. Needs to be 4763 * done afterwards in case the encoder adjusts the mode. */ 4764 if (!crtc_state->port_clock) 4765 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock 4766 * crtc_state->pixel_multiplier; 4767 4768 ret = intel_crtc_compute_config(state, crtc); 4769 if (ret == -EDEADLK) 4770 return ret; 4771 if (ret < 0) { 4772 drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n", 4773 crtc->base.base.id, crtc->base.name, ret); 4774 return ret; 4775 } 4776 4777 /* Dithering seems to not pass-through bits correctly when it should, so 4778 * only enable it on 6bpc panels and when its not a compliance 4779 * test requesting 6bpc video pattern. 4780 */ 4781 crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && 4782 !crtc_state->dither_force_disable; 4783 drm_dbg_kms(display->drm, 4784 "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", 4785 crtc->base.base.id, crtc->base.name, 4786 base_bpp, crtc_state->pipe_bpp, crtc_state->dither); 4787 4788 return 0; 4789 } 4790 4791 static int 4792 intel_modeset_pipe_config_late(struct intel_atomic_state *state, 4793 struct intel_crtc *crtc) 4794 { 4795 struct intel_crtc_state *crtc_state = 4796 intel_atomic_get_new_crtc_state(state, crtc); 4797 struct drm_connector_state *conn_state; 4798 struct drm_connector *connector; 4799 int i; 4800 4801 for_each_new_connector_in_state(&state->base, connector, 4802 conn_state, i) { 4803 struct intel_encoder *encoder = 4804 to_intel_encoder(conn_state->best_encoder); 4805 int ret; 4806 4807 if (conn_state->crtc != &crtc->base || 4808 !encoder->compute_config_late) 4809 continue; 4810 4811 ret = encoder->compute_config_late(encoder, crtc_state, 4812 conn_state); 4813 if (ret) 4814 return ret; 4815 } 4816 4817 return 0; 4818 } 4819 4820 bool intel_fuzzy_clock_check(int clock1, int clock2) 4821 { 4822 int diff; 4823 4824 if (clock1 == clock2) 4825 return true; 4826 4827 if (!clock1 || !clock2) 4828 return false; 4829 4830 diff = abs(clock1 - clock2); 4831 4832 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) 4833 return true; 4834 4835 return false; 4836 } 4837 4838 static bool 4839 intel_compare_link_m_n(const struct intel_link_m_n *m_n, 4840 const struct intel_link_m_n *m2_n2) 4841 { 4842 return m_n->tu == m2_n2->tu && 4843 m_n->data_m == m2_n2->data_m && 4844 m_n->data_n == m2_n2->data_n && 4845 m_n->link_m == m2_n2->link_m && 4846 m_n->link_n == m2_n2->link_n; 4847 } 4848 4849 static bool 4850 intel_compare_infoframe(const union hdmi_infoframe *a, 4851 const union hdmi_infoframe *b) 4852 { 4853 return memcmp(a, b, sizeof(*a)) == 0; 4854 } 4855 4856 static bool 4857 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, 4858 const struct drm_dp_vsc_sdp *b) 4859 { 4860 return a->pixelformat == b->pixelformat && 4861 a->colorimetry == b->colorimetry && 4862 a->bpc == b->bpc && 4863 a->dynamic_range == b->dynamic_range && 4864 a->content_type == b->content_type; 4865 } 4866 4867 static bool 4868 intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a, 4869 const struct drm_dp_as_sdp *b) 4870 { 4871 return a->vtotal == b->vtotal && 4872 a->target_rr == b->target_rr && 4873 a->duration_incr_ms == b->duration_incr_ms && 4874 a->duration_decr_ms == b->duration_decr_ms && 4875 a->mode == b->mode; 4876 } 4877 4878 static bool 4879 intel_compare_buffer(const u8 *a, const u8 *b, size_t len) 4880 { 4881 return memcmp(a, b, len) == 0; 4882 } 4883 4884 static void __printf(5, 6) 4885 pipe_config_mismatch(struct drm_printer *p, bool fastset, 4886 const struct intel_crtc *crtc, 4887 const char *name, const char *format, ...) 4888 { 4889 struct va_format vaf; 4890 va_list args; 4891 4892 va_start(args, format); 4893 vaf.fmt = format; 4894 vaf.va = &args; 4895 4896 if (fastset) 4897 drm_printf(p, "[CRTC:%d:%s] fastset requirement not met in %s %pV\n", 4898 crtc->base.base.id, crtc->base.name, name, &vaf); 4899 else 4900 drm_printf(p, "[CRTC:%d:%s] mismatch in %s %pV\n", 4901 crtc->base.base.id, crtc->base.name, name, &vaf); 4902 4903 va_end(args); 4904 } 4905 4906 static void 4907 pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset, 4908 const struct intel_crtc *crtc, 4909 const char *name, 4910 const union hdmi_infoframe *a, 4911 const union hdmi_infoframe *b) 4912 { 4913 struct intel_display *display = to_intel_display(crtc); 4914 const char *loglevel; 4915 4916 if (fastset) { 4917 if (!drm_debug_enabled(DRM_UT_KMS)) 4918 return; 4919 4920 loglevel = KERN_DEBUG; 4921 } else { 4922 loglevel = KERN_ERR; 4923 } 4924 4925 pipe_config_mismatch(p, fastset, crtc, name, "infoframe"); 4926 4927 drm_printf(p, "expected:\n"); 4928 hdmi_infoframe_log(loglevel, display->drm->dev, a); 4929 drm_printf(p, "found:\n"); 4930 hdmi_infoframe_log(loglevel, display->drm->dev, b); 4931 } 4932 4933 static void 4934 pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset, 4935 const struct intel_crtc *crtc, 4936 const char *name, 4937 const struct drm_dp_vsc_sdp *a, 4938 const struct drm_dp_vsc_sdp *b) 4939 { 4940 pipe_config_mismatch(p, fastset, crtc, name, "dp vsc sdp"); 4941 4942 drm_printf(p, "expected:\n"); 4943 drm_dp_vsc_sdp_log(p, a); 4944 drm_printf(p, "found:\n"); 4945 drm_dp_vsc_sdp_log(p, b); 4946 } 4947 4948 static void 4949 pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset, 4950 const struct intel_crtc *crtc, 4951 const char *name, 4952 const struct drm_dp_as_sdp *a, 4953 const struct drm_dp_as_sdp *b) 4954 { 4955 pipe_config_mismatch(p, fastset, crtc, name, "dp as sdp"); 4956 4957 drm_printf(p, "expected:\n"); 4958 drm_dp_as_sdp_log(p, a); 4959 drm_printf(p, "found:\n"); 4960 drm_dp_as_sdp_log(p, b); 4961 } 4962 4963 /* Returns the length up to and including the last differing byte */ 4964 static size_t 4965 memcmp_diff_len(const u8 *a, const u8 *b, size_t len) 4966 { 4967 int i; 4968 4969 for (i = len - 1; i >= 0; i--) { 4970 if (a[i] != b[i]) 4971 return i + 1; 4972 } 4973 4974 return 0; 4975 } 4976 4977 static void 4978 pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset, 4979 const struct intel_crtc *crtc, 4980 const char *name, 4981 const u8 *a, const u8 *b, size_t len) 4982 { 4983 pipe_config_mismatch(p, fastset, crtc, name, "buffer"); 4984 4985 /* only dump up to the last difference */ 4986 len = memcmp_diff_len(a, b, len); 4987 4988 drm_print_hex_dump(p, "expected: ", a, len); 4989 drm_print_hex_dump(p, "found: ", b, len); 4990 } 4991 4992 static void 4993 pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, 4994 const struct intel_crtc *crtc, 4995 const char *name, 4996 const struct intel_dpll_hw_state *a, 4997 const struct intel_dpll_hw_state *b) 4998 { 4999 struct intel_display *display = to_intel_display(crtc); 5000 5001 pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */ 5002 5003 drm_printf(p, "expected:\n"); 5004 intel_dpll_dump_hw_state(display, p, a); 5005 drm_printf(p, "found:\n"); 5006 intel_dpll_dump_hw_state(display, p, b); 5007 } 5008 5009 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state) 5010 { 5011 struct intel_display *display = to_intel_display(old_crtc_state); 5012 5013 /* 5014 * Allow fastboot to fix up vblank delay (handled via LRR 5015 * codepaths), a bit dodgy as the registers aren't 5016 * double buffered but seems to be working more or less... 5017 * 5018 * Also allow this when the VRR timing generator is always on, 5019 * and optimized guardband is used. In such cases, 5020 * vblank delay may vary even without inherited state, but it's 5021 * still safe as VRR guardband is still same. 5022 */ 5023 return HAS_LRR(display) && 5024 (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) && 5025 !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI); 5026 } 5027 5028 static void 5029 pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset, 5030 const struct intel_crtc *crtc, 5031 const char *name, 5032 const struct intel_lt_phy_pll_state *a, 5033 const struct intel_lt_phy_pll_state *b) 5034 { 5035 struct intel_display *display = to_intel_display(crtc); 5036 char *chipname = "LTPHY"; 5037 5038 pipe_config_mismatch(p, fastset, crtc, name, chipname); 5039 5040 drm_printf(p, "expected:\n"); 5041 intel_lt_phy_dump_hw_state(display, a); 5042 drm_printf(p, "found:\n"); 5043 intel_lt_phy_dump_hw_state(display, b); 5044 } 5045 5046 bool 5047 intel_pipe_config_compare(const struct intel_crtc_state *current_config, 5048 const struct intel_crtc_state *pipe_config, 5049 bool fastset) 5050 { 5051 struct intel_display *display = to_intel_display(current_config); 5052 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5053 struct drm_printer p; 5054 u32 exclude_infoframes = 0; 5055 bool ret = true; 5056 5057 if (fastset) 5058 p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); 5059 else 5060 p = drm_err_printer(display->drm, NULL); 5061 5062 #define PIPE_CONF_CHECK_X(name) do { \ 5063 if (current_config->name != pipe_config->name) { \ 5064 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5065 __stringify(name) " is bool"); \ 5066 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5067 "(expected 0x%08x, found 0x%08x)", \ 5068 current_config->name, \ 5069 pipe_config->name); \ 5070 ret = false; \ 5071 } \ 5072 } while (0) 5073 5074 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \ 5075 if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \ 5076 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5077 __stringify(name) " is bool"); \ 5078 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5079 "(expected 0x%08x, found 0x%08x)", \ 5080 current_config->name & (mask), \ 5081 pipe_config->name & (mask)); \ 5082 ret = false; \ 5083 } \ 5084 } while (0) 5085 5086 #define PIPE_CONF_CHECK_I(name) do { \ 5087 if (current_config->name != pipe_config->name) { \ 5088 BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \ 5089 __stringify(name) " is bool"); \ 5090 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5091 "(expected %i, found %i)", \ 5092 current_config->name, \ 5093 pipe_config->name); \ 5094 ret = false; \ 5095 } \ 5096 } while (0) 5097 5098 #define PIPE_CONF_CHECK_LLI(name) do { \ 5099 if (current_config->name != pipe_config->name) { \ 5100 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5101 "(expected %lli, found %lli)", \ 5102 current_config->name, \ 5103 pipe_config->name); \ 5104 ret = false; \ 5105 } \ 5106 } while (0) 5107 5108 #define PIPE_CONF_CHECK_BOOL(name) do { \ 5109 if (current_config->name != pipe_config->name) { \ 5110 BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ 5111 __stringify(name) " is not bool"); \ 5112 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5113 "(expected %s, found %s)", \ 5114 str_yes_no(current_config->name), \ 5115 str_yes_no(pipe_config->name)); \ 5116 ret = false; \ 5117 } \ 5118 } while (0) 5119 5120 #define PIPE_CONF_CHECK_P(name) do { \ 5121 if (current_config->name != pipe_config->name) { \ 5122 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5123 "(expected %p, found %p)", \ 5124 current_config->name, \ 5125 pipe_config->name); \ 5126 ret = false; \ 5127 } \ 5128 } while (0) 5129 5130 #define PIPE_CONF_CHECK_M_N(name) do { \ 5131 if (!intel_compare_link_m_n(¤t_config->name, \ 5132 &pipe_config->name)) { \ 5133 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5134 "(expected tu %i data %i/%i link %i/%i, " \ 5135 "found tu %i, data %i/%i link %i/%i)", \ 5136 current_config->name.tu, \ 5137 current_config->name.data_m, \ 5138 current_config->name.data_n, \ 5139 current_config->name.link_m, \ 5140 current_config->name.link_n, \ 5141 pipe_config->name.tu, \ 5142 pipe_config->name.data_m, \ 5143 pipe_config->name.data_n, \ 5144 pipe_config->name.link_m, \ 5145 pipe_config->name.link_n); \ 5146 ret = false; \ 5147 } \ 5148 } while (0) 5149 5150 #define PIPE_CONF_CHECK_PLL(name) do { \ 5151 if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \ 5152 &pipe_config->name)) { \ 5153 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5154 ¤t_config->name, \ 5155 &pipe_config->name); \ 5156 ret = false; \ 5157 } \ 5158 } while (0) 5159 5160 #define PIPE_CONF_CHECK_PLL_LT(name) do { \ 5161 if (!intel_lt_phy_pll_compare_hw_state(¤t_config->name, \ 5162 &pipe_config->name)) { \ 5163 pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5164 ¤t_config->name, \ 5165 &pipe_config->name); \ 5166 ret = false; \ 5167 } \ 5168 } while (0) 5169 5170 #define PIPE_CONF_CHECK_TIMINGS(name) do { \ 5171 PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ 5172 PIPE_CONF_CHECK_I(name.crtc_htotal); \ 5173 PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ 5174 PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ 5175 PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ 5176 PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ 5177 PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ 5178 if (!fastset || !allow_vblank_delay_fastset(current_config)) \ 5179 PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ 5180 PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ 5181 PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ 5182 if (!fastset || !pipe_config->update_lrr) { \ 5183 PIPE_CONF_CHECK_I(name.crtc_vtotal); \ 5184 PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ 5185 } \ 5186 } while (0) 5187 5188 #define PIPE_CONF_CHECK_RECT(name) do { \ 5189 PIPE_CONF_CHECK_I(name.x1); \ 5190 PIPE_CONF_CHECK_I(name.x2); \ 5191 PIPE_CONF_CHECK_I(name.y1); \ 5192 PIPE_CONF_CHECK_I(name.y2); \ 5193 } while (0) 5194 5195 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ 5196 if ((current_config->name ^ pipe_config->name) & (mask)) { \ 5197 pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ 5198 "(%x) (expected %i, found %i)", \ 5199 (mask), \ 5200 current_config->name & (mask), \ 5201 pipe_config->name & (mask)); \ 5202 ret = false; \ 5203 } \ 5204 } while (0) 5205 5206 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \ 5207 if (!intel_compare_infoframe(¤t_config->infoframes.name, \ 5208 &pipe_config->infoframes.name)) { \ 5209 pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \ 5210 ¤t_config->infoframes.name, \ 5211 &pipe_config->infoframes.name); \ 5212 ret = false; \ 5213 } \ 5214 } while (0) 5215 5216 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \ 5217 if (!intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ 5218 &pipe_config->infoframes.name)) { \ 5219 pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5220 ¤t_config->infoframes.name, \ 5221 &pipe_config->infoframes.name); \ 5222 ret = false; \ 5223 } \ 5224 } while (0) 5225 5226 #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \ 5227 if (!intel_compare_dp_as_sdp(¤t_config->infoframes.name, \ 5228 &pipe_config->infoframes.name)) { \ 5229 pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5230 ¤t_config->infoframes.name, \ 5231 &pipe_config->infoframes.name); \ 5232 ret = false; \ 5233 } \ 5234 } while (0) 5235 5236 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \ 5237 BUILD_BUG_ON(sizeof(current_config->name) != (len)); \ 5238 BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \ 5239 if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \ 5240 pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \ 5241 current_config->name, \ 5242 pipe_config->name, \ 5243 (len)); \ 5244 ret = false; \ 5245 } \ 5246 } while (0) 5247 5248 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \ 5249 if (current_config->gamma_mode == pipe_config->gamma_mode && \ 5250 !intel_color_lut_equal(current_config, \ 5251 current_config->lut, pipe_config->lut, \ 5252 is_pre_csc_lut)) { \ 5253 pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \ 5254 "hw_state doesn't match sw_state"); \ 5255 ret = false; \ 5256 } \ 5257 } while (0) 5258 5259 #define PIPE_CONF_CHECK_CSC(name) do { \ 5260 PIPE_CONF_CHECK_X(name.preoff[0]); \ 5261 PIPE_CONF_CHECK_X(name.preoff[1]); \ 5262 PIPE_CONF_CHECK_X(name.preoff[2]); \ 5263 PIPE_CONF_CHECK_X(name.coeff[0]); \ 5264 PIPE_CONF_CHECK_X(name.coeff[1]); \ 5265 PIPE_CONF_CHECK_X(name.coeff[2]); \ 5266 PIPE_CONF_CHECK_X(name.coeff[3]); \ 5267 PIPE_CONF_CHECK_X(name.coeff[4]); \ 5268 PIPE_CONF_CHECK_X(name.coeff[5]); \ 5269 PIPE_CONF_CHECK_X(name.coeff[6]); \ 5270 PIPE_CONF_CHECK_X(name.coeff[7]); \ 5271 PIPE_CONF_CHECK_X(name.coeff[8]); \ 5272 PIPE_CONF_CHECK_X(name.postoff[0]); \ 5273 PIPE_CONF_CHECK_X(name.postoff[1]); \ 5274 PIPE_CONF_CHECK_X(name.postoff[2]); \ 5275 } while (0) 5276 5277 #define PIPE_CONF_QUIRK(quirk) \ 5278 ((current_config->quirks | pipe_config->quirks) & (quirk)) 5279 5280 PIPE_CONF_CHECK_BOOL(hw.enable); 5281 PIPE_CONF_CHECK_BOOL(hw.active); 5282 5283 PIPE_CONF_CHECK_I(cpu_transcoder); 5284 PIPE_CONF_CHECK_I(mst_master_transcoder); 5285 5286 PIPE_CONF_CHECK_BOOL(has_pch_encoder); 5287 PIPE_CONF_CHECK_I(fdi_lanes); 5288 PIPE_CONF_CHECK_M_N(fdi_m_n); 5289 5290 PIPE_CONF_CHECK_I(lane_count); 5291 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5292 5293 PIPE_CONF_CHECK_I(min_hblank); 5294 5295 if (HAS_DOUBLE_BUFFERED_M_N(display)) { 5296 if (!fastset || !pipe_config->update_m_n) 5297 PIPE_CONF_CHECK_M_N(dp_m_n); 5298 } else { 5299 PIPE_CONF_CHECK_M_N(dp_m_n); 5300 PIPE_CONF_CHECK_M_N(dp_m2_n2); 5301 } 5302 5303 PIPE_CONF_CHECK_X(output_types); 5304 5305 PIPE_CONF_CHECK_I(framestart_delay); 5306 PIPE_CONF_CHECK_I(msa_timing_delay); 5307 5308 PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); 5309 PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); 5310 5311 PIPE_CONF_CHECK_I(pixel_multiplier); 5312 5313 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5314 DRM_MODE_FLAG_INTERLACE); 5315 5316 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 5317 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5318 DRM_MODE_FLAG_PHSYNC); 5319 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5320 DRM_MODE_FLAG_NHSYNC); 5321 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5322 DRM_MODE_FLAG_PVSYNC); 5323 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, 5324 DRM_MODE_FLAG_NVSYNC); 5325 } 5326 5327 PIPE_CONF_CHECK_I(output_format); 5328 PIPE_CONF_CHECK_BOOL(has_hdmi_sink); 5329 if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) || 5330 display->platform.valleyview || display->platform.cherryview) 5331 PIPE_CONF_CHECK_BOOL(limited_color_range); 5332 5333 PIPE_CONF_CHECK_BOOL(hdmi_scrambling); 5334 PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); 5335 PIPE_CONF_CHECK_BOOL(has_infoframe); 5336 PIPE_CONF_CHECK_BOOL(enhanced_framing); 5337 PIPE_CONF_CHECK_BOOL(fec_enable); 5338 5339 if (!fastset) { 5340 PIPE_CONF_CHECK_BOOL(has_audio); 5341 PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES); 5342 } 5343 5344 PIPE_CONF_CHECK_X(gmch_pfit.control); 5345 /* pfit ratios are autocomputed by the hw on gen4+ */ 5346 if (DISPLAY_VER(display) < 4) 5347 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); 5348 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 5349 5350 /* 5351 * Changing the EDP transcoder input mux 5352 * (A_ONOFF vs. A_ON) requires a full modeset. 5353 */ 5354 PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); 5355 5356 if (!fastset) { 5357 PIPE_CONF_CHECK_RECT(pipe_src); 5358 5359 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); 5360 PIPE_CONF_CHECK_RECT(pch_pfit.dst); 5361 5362 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 5363 PIPE_CONF_CHECK_I(pixel_rate); 5364 PIPE_CONF_CHECK_BOOL(hw.casf_params.casf_enable); 5365 PIPE_CONF_CHECK_I(hw.casf_params.win_size); 5366 PIPE_CONF_CHECK_I(hw.casf_params.strength); 5367 5368 PIPE_CONF_CHECK_X(gamma_mode); 5369 if (display->platform.cherryview) 5370 PIPE_CONF_CHECK_X(cgm_mode); 5371 else 5372 PIPE_CONF_CHECK_X(csc_mode); 5373 PIPE_CONF_CHECK_BOOL(gamma_enable); 5374 PIPE_CONF_CHECK_BOOL(csc_enable); 5375 PIPE_CONF_CHECK_BOOL(wgc_enable); 5376 5377 PIPE_CONF_CHECK_I(linetime); 5378 PIPE_CONF_CHECK_I(ips_linetime); 5379 5380 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true); 5381 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false); 5382 5383 PIPE_CONF_CHECK_CSC(csc); 5384 PIPE_CONF_CHECK_CSC(output_csc); 5385 } 5386 5387 PIPE_CONF_CHECK_BOOL(double_wide); 5388 5389 if (display->dpll.mgr) 5390 PIPE_CONF_CHECK_P(intel_dpll); 5391 5392 /* FIXME convert everything over the dpll_mgr */ 5393 if (display->dpll.mgr || HAS_GMCH(display)) 5394 PIPE_CONF_CHECK_PLL(dpll_hw_state); 5395 5396 /* FIXME convert MTL+ platforms over to dpll_mgr */ 5397 if (HAS_LT_PHY(display)) 5398 PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll); 5399 5400 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5401 PIPE_CONF_CHECK_X(dsi_pll.div); 5402 5403 if (display->platform.g4x || DISPLAY_VER(display) >= 5) 5404 PIPE_CONF_CHECK_I(pipe_bpp); 5405 5406 if (!fastset || !pipe_config->update_m_n) { 5407 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock); 5408 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock); 5409 } 5410 PIPE_CONF_CHECK_I(port_clock); 5411 5412 PIPE_CONF_CHECK_I(min_voltage_level); 5413 5414 if (current_config->has_psr || pipe_config->has_psr) 5415 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 5416 5417 if (current_config->vrr.enable || pipe_config->vrr.enable) 5418 exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); 5419 5420 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes); 5421 PIPE_CONF_CHECK_X(infoframes.gcp); 5422 PIPE_CONF_CHECK_INFOFRAME(avi); 5423 PIPE_CONF_CHECK_INFOFRAME(spd); 5424 PIPE_CONF_CHECK_INFOFRAME(hdmi); 5425 if (!fastset) { 5426 PIPE_CONF_CHECK_INFOFRAME(drm); 5427 PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); 5428 } 5429 PIPE_CONF_CHECK_DP_VSC_SDP(vsc); 5430 5431 PIPE_CONF_CHECK_X(sync_mode_slaves_mask); 5432 PIPE_CONF_CHECK_I(master_transcoder); 5433 PIPE_CONF_CHECK_X(joiner_pipes); 5434 5435 PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable); 5436 PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb); 5437 PIPE_CONF_CHECK_BOOL(dsc.config.simple_422); 5438 PIPE_CONF_CHECK_BOOL(dsc.config.native_422); 5439 PIPE_CONF_CHECK_BOOL(dsc.config.native_420); 5440 PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable); 5441 PIPE_CONF_CHECK_I(dsc.config.line_buf_depth); 5442 PIPE_CONF_CHECK_I(dsc.config.bits_per_component); 5443 PIPE_CONF_CHECK_I(dsc.config.pic_width); 5444 PIPE_CONF_CHECK_I(dsc.config.pic_height); 5445 PIPE_CONF_CHECK_I(dsc.config.slice_width); 5446 PIPE_CONF_CHECK_I(dsc.config.slice_height); 5447 PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay); 5448 PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay); 5449 PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval); 5450 PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval); 5451 PIPE_CONF_CHECK_I(dsc.config.initial_scale_value); 5452 PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset); 5453 PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp); 5454 PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp); 5455 PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset); 5456 PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset); 5457 PIPE_CONF_CHECK_I(dsc.config.initial_offset); 5458 PIPE_CONF_CHECK_I(dsc.config.final_offset); 5459 PIPE_CONF_CHECK_I(dsc.config.rc_model_size); 5460 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0); 5461 PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1); 5462 PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size); 5463 PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset); 5464 PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); 5465 5466 PIPE_CONF_CHECK_BOOL(dsc.compression_enable); 5467 PIPE_CONF_CHECK_I(dsc.num_streams); 5468 PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); 5469 5470 PIPE_CONF_CHECK_BOOL(splitter.enable); 5471 PIPE_CONF_CHECK_I(splitter.link_count); 5472 PIPE_CONF_CHECK_I(splitter.pixel_overlap); 5473 5474 if (!fastset) { 5475 PIPE_CONF_CHECK_BOOL(vrr.enable); 5476 PIPE_CONF_CHECK_I(vrr.vmin); 5477 PIPE_CONF_CHECK_I(vrr.vmax); 5478 PIPE_CONF_CHECK_I(vrr.flipline); 5479 PIPE_CONF_CHECK_I(vrr.vsync_start); 5480 PIPE_CONF_CHECK_I(vrr.vsync_end); 5481 PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); 5482 PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); 5483 PIPE_CONF_CHECK_BOOL(cmrr.enable); 5484 PIPE_CONF_CHECK_I(vrr.dc_balance.vmin); 5485 PIPE_CONF_CHECK_I(vrr.dc_balance.vmax); 5486 PIPE_CONF_CHECK_I(vrr.dc_balance.guardband); 5487 PIPE_CONF_CHECK_I(vrr.dc_balance.slope); 5488 PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase); 5489 PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease); 5490 PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target); 5491 } 5492 5493 if (!fastset || intel_vrr_always_use_vrr_tg(display)) { 5494 PIPE_CONF_CHECK_I(vrr.pipeline_full); 5495 PIPE_CONF_CHECK_I(vrr.guardband); 5496 } 5497 5498 PIPE_CONF_CHECK_I(set_context_latency); 5499 5500 #undef PIPE_CONF_CHECK_X 5501 #undef PIPE_CONF_CHECK_I 5502 #undef PIPE_CONF_CHECK_LLI 5503 #undef PIPE_CONF_CHECK_BOOL 5504 #undef PIPE_CONF_CHECK_P 5505 #undef PIPE_CONF_CHECK_FLAGS 5506 #undef PIPE_CONF_CHECK_COLOR_LUT 5507 #undef PIPE_CONF_CHECK_TIMINGS 5508 #undef PIPE_CONF_CHECK_RECT 5509 #undef PIPE_CONF_QUIRK 5510 5511 return ret; 5512 } 5513 5514 static void 5515 intel_verify_planes(struct intel_atomic_state *state) 5516 { 5517 struct intel_plane *plane; 5518 const struct intel_plane_state *plane_state; 5519 int i; 5520 5521 for_each_new_intel_plane_in_state(state, plane, 5522 plane_state, i) 5523 assert_plane(plane, plane_state->is_y_plane || 5524 plane_state->uapi.visible); 5525 } 5526 5527 static int intel_modeset_pipe(struct intel_atomic_state *state, 5528 struct intel_crtc_state *crtc_state, 5529 const char *reason) 5530 { 5531 struct intel_display *display = to_intel_display(state); 5532 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 5533 int ret; 5534 5535 drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n", 5536 crtc->base.base.id, crtc->base.name, reason); 5537 5538 ret = drm_atomic_add_affected_connectors(&state->base, 5539 &crtc->base); 5540 if (ret) 5541 return ret; 5542 5543 ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc); 5544 if (ret) 5545 return ret; 5546 5547 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc); 5548 if (ret) 5549 return ret; 5550 5551 ret = intel_plane_add_affected(state, crtc); 5552 if (ret) 5553 return ret; 5554 5555 crtc_state->uapi.mode_changed = true; 5556 5557 return 0; 5558 } 5559 5560 /** 5561 * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes 5562 * @state: intel atomic state 5563 * @reason: the reason for the full modeset 5564 * @mask: mask of pipes to modeset 5565 * 5566 * Add pipes in @mask to @state and force a full modeset on the enabled ones 5567 * due to the description in @reason. 5568 * This function can be called only before new plane states are computed. 5569 * 5570 * Returns 0 in case of success, negative error code otherwise. 5571 */ 5572 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 5573 const char *reason, u8 mask) 5574 { 5575 struct intel_display *display = to_intel_display(state); 5576 struct intel_crtc *crtc; 5577 5578 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) { 5579 struct intel_crtc_state *crtc_state; 5580 int ret; 5581 5582 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5583 if (IS_ERR(crtc_state)) 5584 return PTR_ERR(crtc_state); 5585 5586 if (!crtc_state->hw.enable || 5587 intel_crtc_needs_modeset(crtc_state)) 5588 continue; 5589 5590 ret = intel_modeset_pipe(state, crtc_state, reason); 5591 if (ret) 5592 return ret; 5593 } 5594 5595 return 0; 5596 } 5597 5598 static void 5599 intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state) 5600 { 5601 crtc_state->uapi.mode_changed = true; 5602 5603 crtc_state->update_pipe = false; 5604 crtc_state->update_m_n = false; 5605 crtc_state->update_lrr = false; 5606 } 5607 5608 /** 5609 * intel_modeset_all_pipes_late - force a full modeset on all pipes 5610 * @state: intel atomic state 5611 * @reason: the reason for the full modeset 5612 * 5613 * Add all pipes to @state and force a full modeset on the active ones due to 5614 * the description in @reason. 5615 * This function can be called only after new plane states are computed already. 5616 * 5617 * Returns 0 in case of success, negative error code otherwise. 5618 */ 5619 int intel_modeset_all_pipes_late(struct intel_atomic_state *state, 5620 const char *reason) 5621 { 5622 struct intel_display *display = to_intel_display(state); 5623 struct intel_crtc *crtc; 5624 5625 for_each_intel_crtc(display->drm, crtc) { 5626 struct intel_crtc_state *crtc_state; 5627 int ret; 5628 5629 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5630 if (IS_ERR(crtc_state)) 5631 return PTR_ERR(crtc_state); 5632 5633 if (!crtc_state->hw.active || 5634 intel_crtc_needs_modeset(crtc_state)) 5635 continue; 5636 5637 ret = intel_modeset_pipe(state, crtc_state, reason); 5638 if (ret) 5639 return ret; 5640 5641 intel_crtc_flag_modeset(crtc_state); 5642 5643 crtc_state->update_planes |= crtc_state->active_planes; 5644 crtc_state->async_flip_planes = 0; 5645 crtc_state->do_async_flip = false; 5646 } 5647 5648 return 0; 5649 } 5650 5651 int intel_modeset_commit_pipes(struct intel_display *display, 5652 u8 pipe_mask, 5653 struct drm_modeset_acquire_ctx *ctx) 5654 { 5655 struct drm_atomic_state *state; 5656 struct intel_crtc *crtc; 5657 int ret; 5658 5659 state = drm_atomic_state_alloc(display->drm); 5660 if (!state) 5661 return -ENOMEM; 5662 5663 state->acquire_ctx = ctx; 5664 to_intel_atomic_state(state)->internal = true; 5665 5666 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) { 5667 struct intel_crtc_state *crtc_state = 5668 intel_atomic_get_crtc_state(state, crtc); 5669 5670 if (IS_ERR(crtc_state)) { 5671 ret = PTR_ERR(crtc_state); 5672 goto out; 5673 } 5674 5675 crtc_state->uapi.connectors_changed = true; 5676 } 5677 5678 ret = drm_atomic_commit(state); 5679 out: 5680 drm_atomic_state_put(state); 5681 5682 return ret; 5683 } 5684 5685 /* 5686 * This implements the workaround described in the "notes" section of the mode 5687 * set sequence documentation. When going from no pipes or single pipe to 5688 * multiple pipes, and planes are enabled after the pipe, we need to wait at 5689 * least 2 vblanks on the first pipe before enabling planes on the second pipe. 5690 */ 5691 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) 5692 { 5693 struct intel_crtc_state *crtc_state; 5694 struct intel_crtc *crtc; 5695 struct intel_crtc_state *first_crtc_state = NULL; 5696 struct intel_crtc_state *other_crtc_state = NULL; 5697 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; 5698 int i; 5699 5700 /* look at all crtc's that are going to be enabled in during modeset */ 5701 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5702 if (!crtc_state->hw.active || 5703 !intel_crtc_needs_modeset(crtc_state)) 5704 continue; 5705 5706 if (first_crtc_state) { 5707 other_crtc_state = crtc_state; 5708 break; 5709 } else { 5710 first_crtc_state = crtc_state; 5711 first_pipe = crtc->pipe; 5712 } 5713 } 5714 5715 /* No workaround needed? */ 5716 if (!first_crtc_state) 5717 return 0; 5718 5719 /* w/a possibly needed, check how many crtc's are already enabled. */ 5720 for_each_intel_crtc(state->base.dev, crtc) { 5721 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 5722 if (IS_ERR(crtc_state)) 5723 return PTR_ERR(crtc_state); 5724 5725 crtc_state->hsw_workaround_pipe = INVALID_PIPE; 5726 5727 if (!crtc_state->hw.active || 5728 intel_crtc_needs_modeset(crtc_state)) 5729 continue; 5730 5731 /* 2 or more enabled crtcs means no need for w/a */ 5732 if (enabled_pipe != INVALID_PIPE) 5733 return 0; 5734 5735 enabled_pipe = crtc->pipe; 5736 } 5737 5738 if (enabled_pipe != INVALID_PIPE) 5739 first_crtc_state->hsw_workaround_pipe = enabled_pipe; 5740 else if (other_crtc_state) 5741 other_crtc_state->hsw_workaround_pipe = first_pipe; 5742 5743 return 0; 5744 } 5745 5746 u8 intel_calc_enabled_pipes(struct intel_atomic_state *state, 5747 u8 enabled_pipes) 5748 { 5749 const struct intel_crtc_state *crtc_state; 5750 struct intel_crtc *crtc; 5751 int i; 5752 5753 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5754 if (crtc_state->hw.enable) 5755 enabled_pipes |= BIT(crtc->pipe); 5756 else 5757 enabled_pipes &= ~BIT(crtc->pipe); 5758 } 5759 5760 return enabled_pipes; 5761 } 5762 5763 u8 intel_calc_active_pipes(struct intel_atomic_state *state, 5764 u8 active_pipes) 5765 { 5766 const struct intel_crtc_state *crtc_state; 5767 struct intel_crtc *crtc; 5768 int i; 5769 5770 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5771 if (crtc_state->hw.active) 5772 active_pipes |= BIT(crtc->pipe); 5773 else 5774 active_pipes &= ~BIT(crtc->pipe); 5775 } 5776 5777 return active_pipes; 5778 } 5779 5780 static int intel_modeset_checks(struct intel_atomic_state *state) 5781 { 5782 struct intel_display *display = to_intel_display(state); 5783 5784 state->modeset = true; 5785 5786 if (display->platform.haswell) 5787 return hsw_mode_set_planes_workaround(state); 5788 5789 return 0; 5790 } 5791 5792 static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state, 5793 const struct intel_crtc_state *new_crtc_state) 5794 { 5795 const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode; 5796 const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode; 5797 5798 return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start || 5799 old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end || 5800 old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal || 5801 old_crtc_state->set_context_latency != new_crtc_state->set_context_latency; 5802 } 5803 5804 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, 5805 struct intel_crtc_state *new_crtc_state) 5806 { 5807 struct intel_display *display = to_intel_display(new_crtc_state); 5808 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 5809 5810 /* only allow LRR when the timings stay within the VRR range */ 5811 if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range) 5812 new_crtc_state->update_lrr = false; 5813 5814 if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { 5815 drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n", 5816 crtc->base.base.id, crtc->base.name); 5817 } else { 5818 if (allow_vblank_delay_fastset(old_crtc_state)) 5819 new_crtc_state->update_lrr = true; 5820 new_crtc_state->uapi.mode_changed = false; 5821 } 5822 5823 if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, 5824 &new_crtc_state->dp_m_n)) 5825 new_crtc_state->update_m_n = false; 5826 5827 if (!lrr_params_changed(old_crtc_state, new_crtc_state)) 5828 new_crtc_state->update_lrr = false; 5829 5830 if (intel_crtc_needs_modeset(new_crtc_state)) 5831 intel_crtc_flag_modeset(new_crtc_state); 5832 else 5833 new_crtc_state->update_pipe = true; 5834 } 5835 5836 static int intel_atomic_check_crtcs(struct intel_atomic_state *state) 5837 { 5838 struct intel_display *display = to_intel_display(state); 5839 struct intel_crtc_state __maybe_unused *crtc_state; 5840 struct intel_crtc *crtc; 5841 int i; 5842 5843 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 5844 int ret; 5845 5846 ret = intel_crtc_atomic_check(state, crtc); 5847 if (ret) { 5848 drm_dbg_atomic(display->drm, 5849 "[CRTC:%d:%s] atomic driver check failed\n", 5850 crtc->base.base.id, crtc->base.name); 5851 return ret; 5852 } 5853 } 5854 5855 return 0; 5856 } 5857 5858 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, 5859 u8 transcoders) 5860 { 5861 const struct intel_crtc_state *new_crtc_state; 5862 struct intel_crtc *crtc; 5863 int i; 5864 5865 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5866 if (new_crtc_state->hw.enable && 5867 transcoders & BIT(new_crtc_state->cpu_transcoder) && 5868 intel_crtc_needs_modeset(new_crtc_state)) 5869 return true; 5870 } 5871 5872 return false; 5873 } 5874 5875 static bool intel_pipes_need_modeset(struct intel_atomic_state *state, 5876 u8 pipes) 5877 { 5878 const struct intel_crtc_state *new_crtc_state; 5879 struct intel_crtc *crtc; 5880 int i; 5881 5882 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 5883 if (new_crtc_state->hw.enable && 5884 pipes & BIT(crtc->pipe) && 5885 intel_crtc_needs_modeset(new_crtc_state)) 5886 return true; 5887 } 5888 5889 return false; 5890 } 5891 5892 static int intel_atomic_check_joiner(struct intel_atomic_state *state, 5893 struct intel_crtc *primary_crtc) 5894 { 5895 struct intel_display *display = to_intel_display(state); 5896 struct intel_crtc_state *primary_crtc_state = 5897 intel_atomic_get_new_crtc_state(state, primary_crtc); 5898 struct intel_crtc *secondary_crtc; 5899 5900 if (!primary_crtc_state->joiner_pipes) 5901 return 0; 5902 5903 /* sanity check */ 5904 if (drm_WARN_ON(display->drm, 5905 primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))) 5906 return -EINVAL; 5907 5908 if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) { 5909 drm_dbg_kms(display->drm, 5910 "[CRTC:%d:%s] Cannot act as joiner primary " 5911 "(need 0x%x as pipes, only 0x%x possible)\n", 5912 primary_crtc->base.base.id, primary_crtc->base.name, 5913 primary_crtc_state->joiner_pipes, joiner_pipes(display)); 5914 return -EINVAL; 5915 } 5916 5917 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, 5918 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 5919 struct intel_crtc_state *secondary_crtc_state; 5920 int ret; 5921 5922 secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc); 5923 if (IS_ERR(secondary_crtc_state)) 5924 return PTR_ERR(secondary_crtc_state); 5925 5926 /* primary being enabled, secondary was already configured? */ 5927 if (secondary_crtc_state->uapi.enable) { 5928 drm_dbg_kms(display->drm, 5929 "[CRTC:%d:%s] secondary is enabled as normal CRTC, but " 5930 "[CRTC:%d:%s] claiming this CRTC for joiner.\n", 5931 secondary_crtc->base.base.id, secondary_crtc->base.name, 5932 primary_crtc->base.base.id, primary_crtc->base.name); 5933 return -EINVAL; 5934 } 5935 5936 /* 5937 * The state copy logic assumes the primary crtc gets processed 5938 * before the secondary crtc during the main compute_config loop. 5939 * This works because the crtcs are created in pipe order, 5940 * and the hardware requires primary pipe < secondary pipe as well. 5941 * Should that change we need to rethink the logic. 5942 */ 5943 if (WARN_ON(drm_crtc_index(&primary_crtc->base) > 5944 drm_crtc_index(&secondary_crtc->base))) 5945 return -EINVAL; 5946 5947 drm_dbg_kms(display->drm, 5948 "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n", 5949 secondary_crtc->base.base.id, secondary_crtc->base.name, 5950 primary_crtc->base.base.id, primary_crtc->base.name); 5951 5952 secondary_crtc_state->joiner_pipes = 5953 primary_crtc_state->joiner_pipes; 5954 5955 ret = copy_joiner_crtc_state_modeset(state, secondary_crtc); 5956 if (ret) 5957 return ret; 5958 } 5959 5960 return 0; 5961 } 5962 5963 static void kill_joiner_secondaries(struct intel_atomic_state *state, 5964 struct intel_crtc *primary_crtc) 5965 { 5966 struct intel_display *display = to_intel_display(state); 5967 struct intel_crtc_state *primary_crtc_state = 5968 intel_atomic_get_new_crtc_state(state, primary_crtc); 5969 struct intel_crtc *secondary_crtc; 5970 5971 for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, 5972 intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { 5973 struct intel_crtc_state *secondary_crtc_state = 5974 intel_atomic_get_new_crtc_state(state, secondary_crtc); 5975 5976 secondary_crtc_state->joiner_pipes = 0; 5977 5978 intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc); 5979 } 5980 5981 primary_crtc_state->joiner_pipes = 0; 5982 } 5983 5984 /** 5985 * DOC: asynchronous flip implementation 5986 * 5987 * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC 5988 * flag. Currently async flip is only supported via the drmModePageFlip IOCTL. 5989 * Correspondingly, support is currently added for primary plane only. 5990 * 5991 * Async flip can only change the plane surface address, so anything else 5992 * changing is rejected from the intel_async_flip_check_hw() function. 5993 * Once this check is cleared, flip done interrupt is enabled using 5994 * the intel_crtc_enable_flip_done() function. 5995 * 5996 * As soon as the surface address register is written, flip done interrupt is 5997 * generated and the requested events are sent to the userspace in the interrupt 5998 * handler itself. The timestamp and sequence sent during the flip done event 5999 * correspond to the last vblank and have no relation to the actual time when 6000 * the flip done event was sent. 6001 */ 6002 static int intel_async_flip_check_uapi(struct intel_atomic_state *state, 6003 struct intel_crtc *crtc) 6004 { 6005 struct intel_display *display = to_intel_display(state); 6006 const struct intel_crtc_state *new_crtc_state = 6007 intel_atomic_get_new_crtc_state(state, crtc); 6008 const struct intel_plane_state *old_plane_state; 6009 struct intel_plane_state *new_plane_state; 6010 struct intel_plane *plane; 6011 int i; 6012 6013 if (!new_crtc_state->uapi.async_flip) 6014 return 0; 6015 6016 if (!new_crtc_state->uapi.active) { 6017 drm_dbg_kms(display->drm, 6018 "[CRTC:%d:%s] not active\n", 6019 crtc->base.base.id, crtc->base.name); 6020 return -EINVAL; 6021 } 6022 6023 if (intel_crtc_needs_modeset(new_crtc_state)) { 6024 drm_dbg_kms(display->drm, 6025 "[CRTC:%d:%s] modeset required\n", 6026 crtc->base.base.id, crtc->base.name); 6027 return -EINVAL; 6028 } 6029 6030 /* 6031 * FIXME: joiner+async flip is busted currently. 6032 * Remove this check once the issues are fixed. 6033 */ 6034 if (new_crtc_state->joiner_pipes) { 6035 drm_dbg_kms(display->drm, 6036 "[CRTC:%d:%s] async flip disallowed with joiner\n", 6037 crtc->base.base.id, crtc->base.name); 6038 return -EINVAL; 6039 } 6040 6041 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6042 new_plane_state, i) { 6043 if (plane->pipe != crtc->pipe) 6044 continue; 6045 6046 /* 6047 * TODO: Async flip is only supported through the page flip IOCTL 6048 * as of now. So support currently added for primary plane only. 6049 * Support for other planes on platforms on which supports 6050 * this(vlv/chv and icl+) should be added when async flip is 6051 * enabled in the atomic IOCTL path. 6052 */ 6053 if (!plane->async_flip) { 6054 drm_dbg_kms(display->drm, 6055 "[PLANE:%d:%s] async flip not supported\n", 6056 plane->base.base.id, plane->base.name); 6057 return -EINVAL; 6058 } 6059 6060 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { 6061 drm_dbg_kms(display->drm, 6062 "[PLANE:%d:%s] no old or new framebuffer\n", 6063 plane->base.base.id, plane->base.name); 6064 return -EINVAL; 6065 } 6066 } 6067 6068 return 0; 6069 } 6070 6071 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) 6072 { 6073 struct intel_display *display = to_intel_display(state); 6074 const struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6075 const struct intel_plane_state *new_plane_state, *old_plane_state; 6076 struct intel_plane *plane; 6077 int i; 6078 6079 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 6080 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6081 6082 if (!new_crtc_state->uapi.async_flip) 6083 return 0; 6084 6085 if (!new_crtc_state->hw.active) { 6086 drm_dbg_kms(display->drm, 6087 "[CRTC:%d:%s] not active\n", 6088 crtc->base.base.id, crtc->base.name); 6089 return -EINVAL; 6090 } 6091 6092 if (intel_crtc_needs_modeset(new_crtc_state)) { 6093 drm_dbg_kms(display->drm, 6094 "[CRTC:%d:%s] modeset required\n", 6095 crtc->base.base.id, crtc->base.name); 6096 return -EINVAL; 6097 } 6098 6099 if (old_crtc_state->active_planes != new_crtc_state->active_planes) { 6100 drm_dbg_kms(display->drm, 6101 "[CRTC:%d:%s] Active planes cannot be in async flip\n", 6102 crtc->base.base.id, crtc->base.name); 6103 return -EINVAL; 6104 } 6105 6106 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6107 new_plane_state, i) { 6108 if (plane->pipe != crtc->pipe) 6109 continue; 6110 6111 /* 6112 * Only async flip capable planes should be in the state 6113 * if we're really about to ask the hardware to perform 6114 * an async flip. We should never get this far otherwise. 6115 */ 6116 if (drm_WARN_ON(display->drm, 6117 new_crtc_state->do_async_flip && !plane->async_flip)) 6118 return -EINVAL; 6119 6120 /* 6121 * Only check async flip capable planes other planes 6122 * may be involved in the initial commit due to 6123 * the wm0/ddb optimization. 6124 * 6125 * TODO maybe should track which planes actually 6126 * were requested to do the async flip... 6127 */ 6128 if (!plane->async_flip) 6129 continue; 6130 6131 if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format, 6132 new_plane_state->hw.fb->modifier)) { 6133 drm_dbg_kms(display->drm, 6134 "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n", 6135 plane->base.base.id, plane->base.name, 6136 &new_plane_state->hw.fb->format->format, 6137 new_plane_state->hw.fb->modifier); 6138 return -EINVAL; 6139 } 6140 6141 /* 6142 * We turn the first async flip request into a sync flip 6143 * so that we can reconfigure the plane (eg. change modifier). 6144 */ 6145 if (!new_crtc_state->do_async_flip) 6146 continue; 6147 6148 if (old_plane_state->view.color_plane[0].mapping_stride != 6149 new_plane_state->view.color_plane[0].mapping_stride) { 6150 drm_dbg_kms(display->drm, 6151 "[PLANE:%d:%s] Stride cannot be changed in async flip\n", 6152 plane->base.base.id, plane->base.name); 6153 return -EINVAL; 6154 } 6155 6156 if (old_plane_state->hw.fb->modifier != 6157 new_plane_state->hw.fb->modifier) { 6158 drm_dbg_kms(display->drm, 6159 "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", 6160 plane->base.base.id, plane->base.name); 6161 return -EINVAL; 6162 } 6163 6164 if (old_plane_state->hw.fb->format != 6165 new_plane_state->hw.fb->format) { 6166 drm_dbg_kms(display->drm, 6167 "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", 6168 plane->base.base.id, plane->base.name); 6169 return -EINVAL; 6170 } 6171 6172 if (old_plane_state->hw.rotation != 6173 new_plane_state->hw.rotation) { 6174 drm_dbg_kms(display->drm, 6175 "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", 6176 plane->base.base.id, plane->base.name); 6177 return -EINVAL; 6178 } 6179 6180 if (skl_plane_aux_dist(old_plane_state, 0) != 6181 skl_plane_aux_dist(new_plane_state, 0)) { 6182 drm_dbg_kms(display->drm, 6183 "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n", 6184 plane->base.base.id, plane->base.name); 6185 return -EINVAL; 6186 } 6187 6188 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || 6189 !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { 6190 drm_dbg_kms(display->drm, 6191 "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", 6192 plane->base.base.id, plane->base.name); 6193 return -EINVAL; 6194 } 6195 6196 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { 6197 drm_dbg_kms(display->drm, 6198 "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", 6199 plane->base.base.id, plane->base.name); 6200 return -EINVAL; 6201 } 6202 6203 if (old_plane_state->hw.pixel_blend_mode != 6204 new_plane_state->hw.pixel_blend_mode) { 6205 drm_dbg_kms(display->drm, 6206 "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", 6207 plane->base.base.id, plane->base.name); 6208 return -EINVAL; 6209 } 6210 6211 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { 6212 drm_dbg_kms(display->drm, 6213 "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", 6214 plane->base.base.id, plane->base.name); 6215 return -EINVAL; 6216 } 6217 6218 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { 6219 drm_dbg_kms(display->drm, 6220 "[PLANE:%d:%s] Color range cannot be changed in async flip\n", 6221 plane->base.base.id, plane->base.name); 6222 return -EINVAL; 6223 } 6224 6225 /* plane decryption is allow to change only in synchronous flips */ 6226 if (old_plane_state->decrypt != new_plane_state->decrypt) { 6227 drm_dbg_kms(display->drm, 6228 "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", 6229 plane->base.base.id, plane->base.name); 6230 return -EINVAL; 6231 } 6232 } 6233 6234 return 0; 6235 } 6236 6237 static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) 6238 { 6239 struct intel_display *display = to_intel_display(state); 6240 const struct intel_plane_state *plane_state; 6241 struct intel_crtc_state *crtc_state; 6242 struct intel_plane *plane; 6243 struct intel_crtc *crtc; 6244 u8 affected_pipes = 0; 6245 u8 modeset_pipes = 0; 6246 int i; 6247 6248 /* 6249 * Any plane which is in use by the joiner needs its crtc. 6250 * Pull those in first as this will not have happened yet 6251 * if the plane remains disabled according to uapi. 6252 */ 6253 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 6254 crtc = to_intel_crtc(plane_state->hw.crtc); 6255 if (!crtc) 6256 continue; 6257 6258 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6259 if (IS_ERR(crtc_state)) 6260 return PTR_ERR(crtc_state); 6261 } 6262 6263 /* Now pull in all joined crtcs */ 6264 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6265 affected_pipes |= crtc_state->joiner_pipes; 6266 if (intel_crtc_needs_modeset(crtc_state)) 6267 modeset_pipes |= crtc_state->joiner_pipes; 6268 } 6269 6270 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) { 6271 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 6272 if (IS_ERR(crtc_state)) 6273 return PTR_ERR(crtc_state); 6274 } 6275 6276 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) { 6277 int ret; 6278 6279 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 6280 6281 crtc_state->uapi.mode_changed = true; 6282 6283 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 6284 if (ret) 6285 return ret; 6286 6287 ret = intel_plane_add_affected(state, crtc); 6288 if (ret) 6289 return ret; 6290 } 6291 6292 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 6293 /* Kill old joiner link, we may re-establish afterwards */ 6294 if (intel_crtc_needs_modeset(crtc_state) && 6295 intel_crtc_is_joiner_primary(crtc_state)) 6296 kill_joiner_secondaries(state, crtc); 6297 } 6298 6299 return 0; 6300 } 6301 6302 static int intel_atomic_check_config(struct intel_atomic_state *state, 6303 struct intel_link_bw_limits *limits, 6304 enum pipe *failed_pipe) 6305 { 6306 struct intel_display *display = to_intel_display(state); 6307 struct intel_crtc_state *new_crtc_state; 6308 struct intel_crtc *crtc; 6309 int ret; 6310 int i; 6311 6312 *failed_pipe = INVALID_PIPE; 6313 6314 ret = intel_joiner_add_affected_crtcs(state); 6315 if (ret) 6316 return ret; 6317 6318 ret = intel_fdi_add_affected_crtcs(state); 6319 if (ret) 6320 return ret; 6321 6322 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6323 if (!intel_crtc_needs_modeset(new_crtc_state)) { 6324 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 6325 copy_joiner_crtc_state_nomodeset(state, crtc); 6326 else 6327 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); 6328 continue; 6329 } 6330 6331 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6332 continue; 6333 6334 ret = intel_crtc_prepare_cleared_state(state, crtc); 6335 if (ret) 6336 goto fail; 6337 6338 if (!new_crtc_state->hw.enable) 6339 continue; 6340 6341 ret = intel_modeset_pipe_config(state, crtc, limits); 6342 if (ret) 6343 goto fail; 6344 } 6345 6346 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6347 if (!intel_crtc_needs_modeset(new_crtc_state)) 6348 continue; 6349 6350 if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) 6351 continue; 6352 6353 if (!new_crtc_state->hw.enable) 6354 continue; 6355 6356 ret = intel_modeset_pipe_config_late(state, crtc); 6357 if (ret) 6358 goto fail; 6359 } 6360 6361 fail: 6362 if (ret) 6363 *failed_pipe = crtc->pipe; 6364 6365 return ret; 6366 } 6367 6368 static int intel_atomic_check_config_and_link(struct intel_atomic_state *state) 6369 { 6370 struct intel_link_bw_limits new_limits; 6371 struct intel_link_bw_limits old_limits; 6372 int ret; 6373 6374 intel_link_bw_init_limits(state, &new_limits); 6375 old_limits = new_limits; 6376 6377 while (true) { 6378 enum pipe failed_pipe; 6379 6380 ret = intel_atomic_check_config(state, &new_limits, 6381 &failed_pipe); 6382 if (ret) { 6383 /* 6384 * The bpp limit for a pipe is below the minimum it supports, set the 6385 * limit to the minimum and recalculate the config. 6386 */ 6387 if (ret == -EINVAL && 6388 intel_link_bw_set_bpp_limit_for_pipe(state, 6389 &old_limits, 6390 &new_limits, 6391 failed_pipe)) 6392 continue; 6393 6394 break; 6395 } 6396 6397 old_limits = new_limits; 6398 6399 ret = intel_link_bw_atomic_check(state, &new_limits); 6400 if (ret != -EAGAIN) 6401 break; 6402 } 6403 6404 return ret; 6405 } 6406 /** 6407 * intel_atomic_check - validate state object 6408 * @dev: drm device 6409 * @_state: state to validate 6410 */ 6411 int intel_atomic_check(struct drm_device *dev, 6412 struct drm_atomic_state *_state) 6413 { 6414 struct intel_display *display = to_intel_display(dev); 6415 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6416 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 6417 struct intel_crtc *crtc; 6418 int ret, i; 6419 6420 if (!intel_display_driver_check_access(display)) 6421 return -ENODEV; 6422 6423 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6424 new_crtc_state, i) { 6425 /* 6426 * crtc's state no longer considered to be inherited 6427 * after the first userspace/client initiated commit. 6428 */ 6429 if (!state->internal) 6430 new_crtc_state->inherited = false; 6431 6432 if (new_crtc_state->inherited != old_crtc_state->inherited) 6433 new_crtc_state->uapi.mode_changed = true; 6434 6435 if (new_crtc_state->uapi.scaling_filter != 6436 old_crtc_state->uapi.scaling_filter) 6437 new_crtc_state->uapi.mode_changed = true; 6438 } 6439 6440 intel_vrr_check_modeset(state); 6441 6442 ret = drm_atomic_helper_check_modeset(dev, &state->base); 6443 if (ret) 6444 goto fail; 6445 6446 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6447 ret = intel_async_flip_check_uapi(state, crtc); 6448 if (ret) 6449 return ret; 6450 } 6451 6452 ret = intel_atomic_check_config_and_link(state); 6453 if (ret) 6454 goto fail; 6455 6456 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6457 if (!intel_crtc_needs_modeset(new_crtc_state)) 6458 continue; 6459 6460 if (intel_crtc_is_joiner_secondary(new_crtc_state)) { 6461 drm_WARN_ON(display->drm, new_crtc_state->uapi.enable); 6462 continue; 6463 } 6464 6465 ret = intel_atomic_check_joiner(state, crtc); 6466 if (ret) 6467 goto fail; 6468 } 6469 6470 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6471 new_crtc_state, i) { 6472 if (!intel_crtc_needs_modeset(new_crtc_state)) 6473 continue; 6474 6475 intel_joiner_adjust_pipe_src(new_crtc_state); 6476 6477 intel_crtc_check_fastset(old_crtc_state, new_crtc_state); 6478 } 6479 6480 /** 6481 * Check if fastset is allowed by external dependencies like other 6482 * pipes and transcoders. 6483 * 6484 * Right now it only forces a fullmodeset when the MST master 6485 * transcoder did not changed but the pipe of the master transcoder 6486 * needs a fullmodeset so all slaves also needs to do a fullmodeset or 6487 * in case of port synced crtcs, if one of the synced crtcs 6488 * needs a full modeset, all other synced crtcs should be 6489 * forced a full modeset. 6490 */ 6491 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6492 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state)) 6493 continue; 6494 6495 if (intel_dp_mst_crtc_needs_modeset(state, crtc)) 6496 intel_crtc_flag_modeset(new_crtc_state); 6497 6498 if (intel_dp_mst_is_slave_trans(new_crtc_state)) { 6499 enum transcoder master = new_crtc_state->mst_master_transcoder; 6500 6501 if (intel_cpu_transcoders_need_modeset(state, BIT(master))) 6502 intel_crtc_flag_modeset(new_crtc_state); 6503 } 6504 6505 if (is_trans_port_sync_mode(new_crtc_state)) { 6506 u8 trans = new_crtc_state->sync_mode_slaves_mask; 6507 6508 if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) 6509 trans |= BIT(new_crtc_state->master_transcoder); 6510 6511 if (intel_cpu_transcoders_need_modeset(state, trans)) 6512 intel_crtc_flag_modeset(new_crtc_state); 6513 } 6514 6515 if (new_crtc_state->joiner_pipes) { 6516 if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes)) 6517 intel_crtc_flag_modeset(new_crtc_state); 6518 } 6519 } 6520 6521 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6522 new_crtc_state, i) { 6523 if (!intel_crtc_needs_modeset(new_crtc_state)) 6524 continue; 6525 6526 intel_dpll_release(state, crtc); 6527 } 6528 6529 if (intel_any_crtc_needs_modeset(state) && !check_digital_port_conflicts(state)) { 6530 drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n"); 6531 ret = -EINVAL; 6532 goto fail; 6533 } 6534 6535 ret = intel_plane_atomic_check(state); 6536 if (ret) 6537 goto fail; 6538 6539 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 6540 new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state); 6541 6542 ret = intel_compute_global_watermarks(state); 6543 if (ret) 6544 goto fail; 6545 6546 ret = intel_bw_atomic_check(state); 6547 if (ret) 6548 goto fail; 6549 6550 ret = intel_cdclk_atomic_check(state); 6551 if (ret) 6552 goto fail; 6553 6554 if (intel_any_crtc_needs_modeset(state)) { 6555 ret = intel_modeset_checks(state); 6556 if (ret) 6557 goto fail; 6558 } 6559 6560 ret = intel_pmdemand_atomic_check(state); 6561 if (ret) 6562 goto fail; 6563 6564 ret = intel_atomic_check_crtcs(state); 6565 if (ret) 6566 goto fail; 6567 6568 ret = intel_fbc_atomic_check(state); 6569 if (ret) 6570 goto fail; 6571 6572 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6573 new_crtc_state, i) { 6574 intel_color_assert_luts(new_crtc_state); 6575 6576 ret = intel_async_flip_check_hw(state, crtc); 6577 if (ret) 6578 goto fail; 6579 6580 /* Either full modeset or fastset (or neither), never both */ 6581 drm_WARN_ON(display->drm, 6582 intel_crtc_needs_modeset(new_crtc_state) && 6583 intel_crtc_needs_fastset(new_crtc_state)); 6584 6585 if (!intel_crtc_needs_modeset(new_crtc_state) && 6586 !intel_crtc_needs_fastset(new_crtc_state)) 6587 continue; 6588 6589 intel_crtc_state_dump(new_crtc_state, state, 6590 intel_crtc_needs_modeset(new_crtc_state) ? 6591 "modeset" : "fastset"); 6592 } 6593 6594 return 0; 6595 6596 fail: 6597 if (ret == -EDEADLK) 6598 return ret; 6599 6600 /* 6601 * FIXME would probably be nice to know which crtc specifically 6602 * caused the failure, in cases where we can pinpoint it. 6603 */ 6604 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6605 new_crtc_state, i) 6606 intel_crtc_state_dump(new_crtc_state, state, "failed"); 6607 6608 return ret; 6609 } 6610 6611 static int intel_atomic_prepare_commit(struct intel_atomic_state *state) 6612 { 6613 int ret; 6614 6615 ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); 6616 if (ret < 0) 6617 return ret; 6618 6619 return 0; 6620 } 6621 6622 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, 6623 struct intel_crtc_state *crtc_state) 6624 { 6625 struct intel_display *display = to_intel_display(crtc); 6626 6627 if (DISPLAY_VER(display) != 2 || crtc_state->active_planes) 6628 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); 6629 6630 if (crtc_state->has_pch_encoder) { 6631 enum pipe pch_transcoder = 6632 intel_crtc_pch_transcoder(crtc); 6633 6634 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true); 6635 } 6636 } 6637 6638 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, 6639 const struct intel_crtc_state *new_crtc_state) 6640 { 6641 struct intel_display *display = to_intel_display(new_crtc_state); 6642 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 6643 6644 /* 6645 * Update pipe size and adjust fitter if needed: the reason for this is 6646 * that in compute_mode_changes we check the native mode (not the pfit 6647 * mode) to see if we can flip rather than do a full mode set. In the 6648 * fastboot case, we'll flip, but if we don't update the pipesrc and 6649 * pfit state, we'll end up with a big fb scanned out into the wrong 6650 * sized surface. 6651 */ 6652 intel_set_pipe_src_size(new_crtc_state); 6653 6654 /* on skylake this is done by detaching scalers */ 6655 if (DISPLAY_VER(display) >= 9) { 6656 if (new_crtc_state->pch_pfit.enabled) 6657 skl_pfit_enable(new_crtc_state); 6658 } else if (HAS_PCH_SPLIT(display)) { 6659 if (new_crtc_state->pch_pfit.enabled) 6660 ilk_pfit_enable(new_crtc_state); 6661 else if (old_crtc_state->pch_pfit.enabled) 6662 ilk_pfit_disable(old_crtc_state); 6663 } 6664 6665 /* 6666 * The register is supposedly single buffered so perhaps 6667 * not 100% correct to do this here. But SKL+ calculate 6668 * this based on the adjust pixel rate so pfit changes do 6669 * affect it and so it must be updated for fastsets. 6670 * HSW/BDW only really need this here for fastboot, after 6671 * that the value should not change without a full modeset. 6672 */ 6673 if (DISPLAY_VER(display) >= 9 || 6674 display->platform.broadwell || display->platform.haswell) 6675 hsw_set_linetime_wm(new_crtc_state); 6676 6677 if (new_crtc_state->update_m_n) 6678 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder, 6679 &new_crtc_state->dp_m_n); 6680 6681 if (new_crtc_state->update_lrr) 6682 intel_set_transcoder_timings_lrr(new_crtc_state); 6683 } 6684 6685 static void commit_pipe_pre_planes(struct intel_atomic_state *state, 6686 struct intel_crtc *crtc) 6687 { 6688 struct intel_display *display = to_intel_display(state); 6689 const struct intel_crtc_state *old_crtc_state = 6690 intel_atomic_get_old_crtc_state(state, crtc); 6691 const struct intel_crtc_state *new_crtc_state = 6692 intel_atomic_get_new_crtc_state(state, crtc); 6693 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6694 6695 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq); 6696 6697 /* 6698 * During modesets pipe configuration was programmed as the 6699 * CRTC was enabled. 6700 */ 6701 if (!modeset) { 6702 if (intel_crtc_needs_color_update(new_crtc_state)) 6703 intel_color_commit_arm(NULL, new_crtc_state); 6704 6705 if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) 6706 bdw_set_pipe_misc(NULL, new_crtc_state); 6707 6708 if (intel_crtc_needs_fastset(new_crtc_state)) 6709 intel_pipe_fastset(old_crtc_state, new_crtc_state); 6710 } 6711 6712 intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state); 6713 6714 intel_atomic_update_watermarks(state, crtc); 6715 } 6716 6717 static void commit_pipe_post_planes(struct intel_atomic_state *state, 6718 struct intel_crtc *crtc) 6719 { 6720 struct intel_display *display = to_intel_display(state); 6721 const struct intel_crtc_state *new_crtc_state = 6722 intel_atomic_get_new_crtc_state(state, crtc); 6723 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6724 6725 drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq); 6726 6727 /* 6728 * Disable the scaler(s) after the plane(s) so that we don't 6729 * get a catastrophic underrun even if the two operations 6730 * end up happening in two different frames. 6731 */ 6732 if (DISPLAY_VER(display) >= 9 && !modeset) 6733 skl_detach_scalers(NULL, new_crtc_state); 6734 6735 if (!modeset && 6736 intel_crtc_needs_color_update(new_crtc_state) && 6737 !intel_color_uses_dsb(new_crtc_state) && 6738 HAS_DOUBLE_BUFFERED_LUT(display)) 6739 intel_color_load_luts(new_crtc_state); 6740 6741 if (intel_crtc_vrr_enabling(state, crtc)) 6742 intel_vrr_enable(new_crtc_state); 6743 } 6744 6745 static void intel_enable_crtc(struct intel_atomic_state *state, 6746 struct intel_crtc *crtc) 6747 { 6748 struct intel_display *display = to_intel_display(state); 6749 const struct intel_crtc_state *new_crtc_state = 6750 intel_atomic_get_new_crtc_state(state, crtc); 6751 struct intel_crtc *pipe_crtc; 6752 6753 if (!intel_crtc_needs_modeset(new_crtc_state)) 6754 return; 6755 6756 for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc, 6757 intel_crtc_joined_pipe_mask(new_crtc_state)) { 6758 const struct intel_crtc_state *pipe_crtc_state = 6759 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6760 6761 /* VRR will be enable later, if required */ 6762 intel_crtc_update_active_timings(pipe_crtc_state, false); 6763 } 6764 6765 intel_psr_notify_pipe_change(state, crtc, true); 6766 6767 display->funcs.display->crtc_enable(state, crtc); 6768 6769 /* vblanks work again, re-enable pipe CRC. */ 6770 intel_crtc_enable_pipe_crc(crtc); 6771 } 6772 6773 static void intel_pre_update_crtc(struct intel_atomic_state *state, 6774 struct intel_crtc *crtc) 6775 { 6776 struct intel_display *display = to_intel_display(state); 6777 const struct intel_crtc_state *old_crtc_state = 6778 intel_atomic_get_old_crtc_state(state, crtc); 6779 struct intel_crtc_state *new_crtc_state = 6780 intel_atomic_get_new_crtc_state(state, crtc); 6781 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 6782 6783 if (old_crtc_state->inherited || 6784 intel_crtc_needs_modeset(new_crtc_state)) { 6785 if (HAS_DPT(display)) 6786 intel_dpt_configure(crtc); 6787 } 6788 6789 if (!modeset) { 6790 if (new_crtc_state->preload_luts && 6791 intel_crtc_needs_color_update(new_crtc_state)) 6792 intel_color_load_luts(new_crtc_state); 6793 6794 intel_pre_plane_update(state, crtc); 6795 6796 if (intel_crtc_needs_fastset(new_crtc_state)) 6797 intel_encoders_update_pipe(state, crtc); 6798 6799 if (DISPLAY_VER(display) >= 11 && 6800 intel_crtc_needs_fastset(new_crtc_state)) 6801 icl_set_pipe_chicken(new_crtc_state); 6802 6803 if (vrr_params_changed(old_crtc_state, new_crtc_state) || 6804 cmrr_params_changed(old_crtc_state, new_crtc_state)) 6805 intel_vrr_set_transcoder_timings(new_crtc_state); 6806 } 6807 6808 if (intel_casf_enabling(new_crtc_state, old_crtc_state)) 6809 intel_casf_enable(new_crtc_state); 6810 else if (new_crtc_state->hw.casf_params.strength != old_crtc_state->hw.casf_params.strength) 6811 intel_casf_update_strength(new_crtc_state); 6812 6813 intel_fbc_update(state, crtc); 6814 6815 drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); 6816 6817 if (!modeset && 6818 intel_crtc_needs_color_update(new_crtc_state) && 6819 !new_crtc_state->use_dsb && !new_crtc_state->use_flipq) 6820 intel_color_commit_noarm(NULL, new_crtc_state); 6821 6822 if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq) 6823 intel_crtc_planes_update_noarm(NULL, state, crtc); 6824 } 6825 6826 static void intel_update_crtc(struct intel_atomic_state *state, 6827 struct intel_crtc *crtc) 6828 { 6829 const struct intel_crtc_state *old_crtc_state = 6830 intel_atomic_get_old_crtc_state(state, crtc); 6831 struct intel_crtc_state *new_crtc_state = 6832 intel_atomic_get_new_crtc_state(state, crtc); 6833 6834 if (new_crtc_state->use_flipq) { 6835 intel_flipq_enable(new_crtc_state); 6836 6837 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->flipq_event); 6838 6839 intel_flipq_add(crtc, INTEL_FLIPQ_PLANE_1, 0, INTEL_DSB_0, 6840 new_crtc_state->dsb_commit); 6841 } else if (new_crtc_state->use_dsb) { 6842 intel_crtc_prepare_vblank_event(new_crtc_state, &crtc->dsb_event); 6843 6844 intel_dsb_commit(new_crtc_state->dsb_commit); 6845 } else { 6846 /* Perform vblank evasion around commit operation */ 6847 intel_pipe_update_start(state, crtc); 6848 6849 if (new_crtc_state->dsb_commit) 6850 intel_dsb_commit(new_crtc_state->dsb_commit); 6851 6852 commit_pipe_pre_planes(state, crtc); 6853 6854 intel_crtc_planes_update_arm(NULL, state, crtc); 6855 6856 commit_pipe_post_planes(state, crtc); 6857 6858 intel_pipe_update_end(state, crtc); 6859 } 6860 6861 /* 6862 * VRR/Seamless M/N update may need to update frame timings. 6863 * 6864 * FIXME Should be synchronized with the start of vblank somehow... 6865 */ 6866 if (intel_crtc_vrr_enabling(state, crtc) || 6867 new_crtc_state->update_m_n || new_crtc_state->update_lrr) 6868 intel_crtc_update_active_timings(new_crtc_state, 6869 new_crtc_state->vrr.enable); 6870 6871 if (new_crtc_state->vrr.dc_balance.enable) 6872 intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc); 6873 6874 /* 6875 * We usually enable FIFO underrun interrupts as part of the 6876 * CRTC enable sequence during modesets. But when we inherit a 6877 * valid pipe configuration from the BIOS we need to take care 6878 * of enabling them on the CRTC's first fastset. 6879 */ 6880 if (intel_crtc_needs_fastset(new_crtc_state) && 6881 old_crtc_state->inherited) 6882 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); 6883 } 6884 6885 static void intel_old_crtc_state_disables(struct intel_atomic_state *state, 6886 struct intel_crtc *crtc) 6887 { 6888 struct intel_display *display = to_intel_display(state); 6889 const struct intel_crtc_state *old_crtc_state = 6890 intel_atomic_get_old_crtc_state(state, crtc); 6891 struct intel_crtc *pipe_crtc; 6892 6893 /* 6894 * We need to disable pipe CRC before disabling the pipe, 6895 * or we race against vblank off. 6896 */ 6897 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 6898 intel_crtc_joined_pipe_mask(old_crtc_state)) 6899 intel_crtc_disable_pipe_crc(pipe_crtc); 6900 6901 intel_psr_notify_pipe_change(state, crtc, false); 6902 6903 display->funcs.display->crtc_disable(state, crtc); 6904 6905 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, 6906 intel_crtc_joined_pipe_mask(old_crtc_state)) { 6907 const struct intel_crtc_state *new_pipe_crtc_state = 6908 intel_atomic_get_new_crtc_state(state, pipe_crtc); 6909 6910 pipe_crtc->active = false; 6911 intel_fbc_disable(pipe_crtc); 6912 6913 if (!new_pipe_crtc_state->hw.active) 6914 intel_initial_watermarks(state, pipe_crtc); 6915 } 6916 } 6917 6918 static void intel_commit_modeset_disables(struct intel_atomic_state *state) 6919 { 6920 struct intel_display *display = to_intel_display(state); 6921 const struct intel_crtc_state *new_crtc_state, *old_crtc_state; 6922 struct intel_crtc *crtc; 6923 u8 disable_pipes = 0; 6924 int i; 6925 6926 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 6927 new_crtc_state, i) { 6928 if (!intel_crtc_needs_modeset(new_crtc_state)) 6929 continue; 6930 6931 /* 6932 * Needs to be done even for pipes 6933 * that weren't enabled previously. 6934 */ 6935 intel_pre_plane_update(state, crtc); 6936 6937 if (!old_crtc_state->hw.active) 6938 continue; 6939 6940 disable_pipes |= BIT(crtc->pipe); 6941 } 6942 6943 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 6944 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6945 continue; 6946 6947 intel_crtc_disable_planes(state, crtc); 6948 6949 drm_vblank_work_flush_all(&crtc->base); 6950 } 6951 6952 /* Only disable port sync and MST slaves */ 6953 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 6954 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6955 continue; 6956 6957 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 6958 continue; 6959 6960 /* In case of Transcoder port Sync master slave CRTCs can be 6961 * assigned in any order and we need to make sure that 6962 * slave CRTCs are disabled first and then master CRTC since 6963 * Slave vblanks are masked till Master Vblanks. 6964 */ 6965 if (!is_trans_port_sync_slave(old_crtc_state) && 6966 !intel_dp_mst_is_slave_trans(old_crtc_state)) 6967 continue; 6968 6969 intel_old_crtc_state_disables(state, crtc); 6970 6971 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 6972 } 6973 6974 /* Disable everything else left on */ 6975 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) { 6976 if ((disable_pipes & BIT(crtc->pipe)) == 0) 6977 continue; 6978 6979 if (intel_crtc_is_joiner_secondary(old_crtc_state)) 6980 continue; 6981 6982 intel_old_crtc_state_disables(state, crtc); 6983 6984 disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); 6985 } 6986 6987 drm_WARN_ON(display->drm, disable_pipes); 6988 } 6989 6990 static void intel_commit_modeset_enables(struct intel_atomic_state *state) 6991 { 6992 struct intel_crtc_state *new_crtc_state; 6993 struct intel_crtc *crtc; 6994 int i; 6995 6996 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 6997 if (!new_crtc_state->hw.active) 6998 continue; 6999 7000 intel_enable_crtc(state, crtc); 7001 intel_pre_update_crtc(state, crtc); 7002 } 7003 7004 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7005 if (!new_crtc_state->hw.active) 7006 continue; 7007 7008 intel_update_crtc(state, crtc); 7009 } 7010 } 7011 7012 static void skl_commit_modeset_enables(struct intel_atomic_state *state) 7013 { 7014 struct intel_display *display = to_intel_display(state); 7015 struct intel_crtc *crtc; 7016 struct intel_crtc_state *old_crtc_state, *new_crtc_state; 7017 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 7018 u8 update_pipes = 0, modeset_pipes = 0; 7019 int i; 7020 7021 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7022 enum pipe pipe = crtc->pipe; 7023 7024 if (!new_crtc_state->hw.active) 7025 continue; 7026 7027 /* ignore allocations for crtc's that have been turned off. */ 7028 if (!intel_crtc_needs_modeset(new_crtc_state)) { 7029 entries[pipe] = old_crtc_state->wm.skl.ddb; 7030 update_pipes |= BIT(pipe); 7031 } else { 7032 modeset_pipes |= BIT(pipe); 7033 } 7034 } 7035 7036 /* 7037 * Whenever the number of active pipes changes, we need to make sure we 7038 * update the pipes in the right order so that their ddb allocations 7039 * never overlap with each other between CRTC updates. Otherwise we'll 7040 * cause pipe underruns and other bad stuff. 7041 * 7042 * So first lets enable all pipes that do not need a fullmodeset as 7043 * those don't have any external dependency. 7044 */ 7045 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7046 enum pipe pipe = crtc->pipe; 7047 7048 if ((update_pipes & BIT(pipe)) == 0) 7049 continue; 7050 7051 intel_pre_update_crtc(state, crtc); 7052 } 7053 7054 intel_dbuf_mbus_pre_ddb_update(state); 7055 7056 while (update_pipes) { 7057 /* 7058 * Commit in reverse order to make joiner primary 7059 * send the uapi events after secondaries are done. 7060 */ 7061 for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, 7062 new_crtc_state, i) { 7063 enum pipe pipe = crtc->pipe; 7064 7065 if ((update_pipes & BIT(pipe)) == 0) 7066 continue; 7067 7068 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7069 entries, I915_MAX_PIPES, pipe)) 7070 continue; 7071 7072 entries[pipe] = new_crtc_state->wm.skl.ddb; 7073 update_pipes &= ~BIT(pipe); 7074 7075 intel_update_crtc(state, crtc); 7076 7077 /* 7078 * If this is an already active pipe, it's DDB changed, 7079 * and this isn't the last pipe that needs updating 7080 * then we need to wait for a vblank to pass for the 7081 * new ddb allocation to take effect. 7082 */ 7083 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, 7084 &old_crtc_state->wm.skl.ddb) && 7085 (update_pipes | modeset_pipes)) 7086 intel_crtc_wait_for_next_vblank(crtc); 7087 } 7088 } 7089 7090 intel_dbuf_mbus_post_ddb_update(state); 7091 7092 update_pipes = modeset_pipes; 7093 7094 /* 7095 * Enable all pipes that needs a modeset and do not depends on other 7096 * pipes 7097 */ 7098 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7099 enum pipe pipe = crtc->pipe; 7100 7101 if ((modeset_pipes & BIT(pipe)) == 0) 7102 continue; 7103 7104 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7105 continue; 7106 7107 if (intel_dp_mst_is_slave_trans(new_crtc_state) || 7108 is_trans_port_sync_master(new_crtc_state)) 7109 continue; 7110 7111 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7112 7113 intel_enable_crtc(state, crtc); 7114 } 7115 7116 /* 7117 * Then we enable all remaining pipes that depend on other 7118 * pipes: MST slaves and port sync masters 7119 */ 7120 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7121 enum pipe pipe = crtc->pipe; 7122 7123 if ((modeset_pipes & BIT(pipe)) == 0) 7124 continue; 7125 7126 if (intel_crtc_is_joiner_secondary(new_crtc_state)) 7127 continue; 7128 7129 modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); 7130 7131 intel_enable_crtc(state, crtc); 7132 } 7133 7134 /* 7135 * Finally we do the plane updates/etc. for all pipes that got enabled. 7136 */ 7137 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7138 enum pipe pipe = crtc->pipe; 7139 7140 if ((update_pipes & BIT(pipe)) == 0) 7141 continue; 7142 7143 intel_pre_update_crtc(state, crtc); 7144 } 7145 7146 /* 7147 * Commit in reverse order to make joiner primary 7148 * send the uapi events after secondaries are done. 7149 */ 7150 for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) { 7151 enum pipe pipe = crtc->pipe; 7152 7153 if ((update_pipes & BIT(pipe)) == 0) 7154 continue; 7155 7156 drm_WARN_ON(display->drm, 7157 skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, 7158 entries, I915_MAX_PIPES, pipe)); 7159 7160 entries[pipe] = new_crtc_state->wm.skl.ddb; 7161 update_pipes &= ~BIT(pipe); 7162 7163 intel_update_crtc(state, crtc); 7164 } 7165 7166 drm_WARN_ON(display->drm, modeset_pipes); 7167 drm_WARN_ON(display->drm, update_pipes); 7168 } 7169 7170 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) 7171 { 7172 struct drm_plane *plane; 7173 struct drm_plane_state *new_plane_state; 7174 long ret; 7175 int i; 7176 7177 for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) { 7178 if (new_plane_state->fence) { 7179 ret = dma_fence_wait_timeout(new_plane_state->fence, false, 7180 i915_fence_timeout()); 7181 if (ret <= 0) 7182 break; 7183 7184 dma_fence_put(new_plane_state->fence); 7185 new_plane_state->fence = NULL; 7186 } 7187 } 7188 } 7189 7190 static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state) 7191 { 7192 if (crtc_state->dsb_commit) 7193 intel_dsb_wait(crtc_state->dsb_commit); 7194 7195 intel_color_wait_commit(crtc_state); 7196 } 7197 7198 static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state) 7199 { 7200 if (crtc_state->dsb_commit) { 7201 intel_dsb_cleanup(crtc_state->dsb_commit); 7202 crtc_state->dsb_commit = NULL; 7203 } 7204 7205 intel_color_cleanup_commit(crtc_state); 7206 } 7207 7208 static void intel_atomic_cleanup_work(struct work_struct *work) 7209 { 7210 struct intel_atomic_state *state = 7211 container_of(work, struct intel_atomic_state, cleanup_work); 7212 struct intel_display *display = to_intel_display(state); 7213 struct intel_crtc_state *old_crtc_state; 7214 struct intel_crtc *crtc; 7215 int i; 7216 7217 for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) 7218 intel_atomic_dsb_cleanup(old_crtc_state); 7219 7220 drm_atomic_helper_cleanup_planes(display->drm, &state->base); 7221 drm_atomic_helper_commit_cleanup_done(&state->base); 7222 drm_atomic_state_put(&state->base); 7223 } 7224 7225 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) 7226 { 7227 struct intel_display *display = to_intel_display(state); 7228 struct intel_plane *plane; 7229 struct intel_plane_state *plane_state; 7230 int i; 7231 7232 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 7233 struct drm_framebuffer *fb = plane_state->hw.fb; 7234 int cc_plane; 7235 int ret; 7236 7237 if (!fb) 7238 continue; 7239 7240 cc_plane = intel_fb_rc_ccs_cc_plane(fb); 7241 if (cc_plane < 0) 7242 continue; 7243 7244 /* 7245 * The layout of the fast clear color value expected by HW 7246 * (the DRM ABI requiring this value to be located in fb at 7247 * offset 0 of cc plane, plane #2 previous generations or 7248 * plane #1 for flat ccs): 7249 * - 4 x 4 bytes per-channel value 7250 * (in surface type specific float/int format provided by the fb user) 7251 * - 8 bytes native color value used by the display 7252 * (converted/written by GPU during a fast clear operation using the 7253 * above per-channel values) 7254 * 7255 * The commit's FB prepare hook already ensured that FB obj is pinned and the 7256 * caller made sure that the object is synced wrt. the related color clear value 7257 * GPU write on it. 7258 */ 7259 ret = intel_bo_read_from_page(intel_fb_bo(fb), 7260 fb->offsets[cc_plane] + 16, 7261 &plane_state->ccval, 7262 sizeof(plane_state->ccval)); 7263 /* The above could only fail if the FB obj has an unexpected backing store type. */ 7264 drm_WARN_ON(display->drm, ret); 7265 } 7266 } 7267 7268 static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, 7269 struct intel_crtc *crtc) 7270 { 7271 struct intel_display *display = to_intel_display(state); 7272 struct intel_crtc_state *new_crtc_state = 7273 intel_atomic_get_new_crtc_state(state, crtc); 7274 7275 if (!new_crtc_state->hw.active) 7276 return; 7277 7278 if (state->base.legacy_cursor_update) 7279 return; 7280 7281 /* FIXME deal with everything */ 7282 new_crtc_state->use_flipq = 7283 intel_flipq_supported(display) && 7284 !new_crtc_state->do_async_flip && 7285 !new_crtc_state->vrr.enable && 7286 !new_crtc_state->has_psr && 7287 !intel_crtc_needs_modeset(new_crtc_state) && 7288 !intel_crtc_needs_fastset(new_crtc_state) && 7289 !intel_crtc_needs_color_update(new_crtc_state); 7290 7291 new_crtc_state->use_dsb = 7292 !new_crtc_state->use_flipq && 7293 !new_crtc_state->do_async_flip && 7294 (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && 7295 !intel_crtc_needs_modeset(new_crtc_state) && 7296 !intel_crtc_needs_fastset(new_crtc_state); 7297 7298 intel_color_prepare_commit(state, crtc); 7299 } 7300 7301 static void intel_atomic_dsb_finish(struct intel_atomic_state *state, 7302 struct intel_crtc *crtc) 7303 { 7304 struct intel_display *display = to_intel_display(state); 7305 struct intel_crtc_state *new_crtc_state = 7306 intel_atomic_get_new_crtc_state(state, crtc); 7307 unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024; 7308 7309 if (!new_crtc_state->use_flipq && 7310 !new_crtc_state->use_dsb && 7311 !new_crtc_state->dsb_color) 7312 return; 7313 7314 /* 7315 * Rough estimate: 7316 * ~64 registers per each plane * 8 planes = 512 7317 * Double that for pipe stuff and other overhead. 7318 * ~4913 registers for 3DLUT 7319 * ~200 color registers * 3 HDR planes 7320 */ 7321 new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 7322 new_crtc_state->use_dsb || 7323 new_crtc_state->use_flipq ? size : 16); 7324 if (!new_crtc_state->dsb_commit) { 7325 new_crtc_state->use_flipq = false; 7326 new_crtc_state->use_dsb = false; 7327 intel_color_cleanup_commit(new_crtc_state); 7328 return; 7329 } 7330 7331 if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) { 7332 /* Wa_18034343758 */ 7333 if (new_crtc_state->use_flipq) 7334 intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc); 7335 7336 if (new_crtc_state->vrr.dc_balance.enable) { 7337 /* 7338 * Pause the DMC DC balancing for the remainder of 7339 * the commit so that vmin/vmax won't change after 7340 * we've baked them into the DSB vblank evasion 7341 * commands. 7342 * 7343 * FIXME maybe need a small delay here to make sure 7344 * DMC has finished updating the values? Or we need 7345 * a better DMC<->driver protocol that gives is real 7346 * guarantees about that... 7347 */ 7348 intel_pipedmc_dcb_disable(NULL, crtc); 7349 } 7350 7351 if (intel_crtc_needs_color_update(new_crtc_state)) 7352 intel_color_commit_noarm(new_crtc_state->dsb_commit, 7353 new_crtc_state); 7354 intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, 7355 state, crtc); 7356 7357 /* 7358 * Ensure we have "Frame Change" event when PSR state is 7359 * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank 7360 * evasion hangs as PIPEDSL is reading as 0. 7361 */ 7362 intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit, 7363 state, crtc); 7364 7365 intel_psr_wait_for_idle_dsb(new_crtc_state->dsb_commit, 7366 new_crtc_state); 7367 7368 if (new_crtc_state->use_dsb) 7369 intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); 7370 7371 if (intel_crtc_needs_color_update(new_crtc_state)) 7372 intel_color_commit_arm(new_crtc_state->dsb_commit, 7373 new_crtc_state); 7374 bdw_set_pipe_misc(new_crtc_state->dsb_commit, 7375 new_crtc_state); 7376 intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit, 7377 new_crtc_state); 7378 intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, 7379 state, crtc); 7380 7381 if (DISPLAY_VER(display) >= 9) 7382 skl_detach_scalers(new_crtc_state->dsb_commit, 7383 new_crtc_state); 7384 7385 /* Wa_18034343758 */ 7386 if (new_crtc_state->use_flipq) 7387 intel_flipq_unhalt_dmc(new_crtc_state->dsb_commit, crtc); 7388 } 7389 7390 if (intel_color_uses_chained_dsb(new_crtc_state)) 7391 intel_dsb_chain(state, new_crtc_state->dsb_commit, 7392 new_crtc_state->dsb_color, true); 7393 else if (intel_color_uses_gosub_dsb(new_crtc_state)) 7394 intel_dsb_gosub(new_crtc_state->dsb_commit, 7395 new_crtc_state->dsb_color); 7396 7397 if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) { 7398 intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); 7399 7400 intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); 7401 intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); 7402 intel_vrr_check_push_sent(new_crtc_state->dsb_commit, 7403 new_crtc_state); 7404 7405 if (new_crtc_state->vrr.dc_balance.enable) 7406 intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); 7407 7408 intel_dsb_interrupt(new_crtc_state->dsb_commit); 7409 } 7410 7411 intel_dsb_finish(new_crtc_state->dsb_commit); 7412 } 7413 7414 static void intel_atomic_commit_tail(struct intel_atomic_state *state) 7415 { 7416 struct intel_display *display = to_intel_display(state); 7417 struct intel_uncore *uncore = to_intel_uncore(display->drm); 7418 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7419 struct intel_crtc *crtc; 7420 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7421 struct ref_tracker *wakeref = NULL; 7422 int i; 7423 7424 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7425 intel_atomic_dsb_prepare(state, crtc); 7426 7427 intel_atomic_commit_fence_wait(state); 7428 7429 intel_td_flush(display); 7430 7431 intel_atomic_prepare_plane_clear_colors(state); 7432 7433 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7434 intel_fbc_prepare_dirty_rect(state, crtc); 7435 7436 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7437 intel_atomic_dsb_finish(state, crtc); 7438 7439 drm_atomic_helper_wait_for_dependencies(&state->base); 7440 drm_dp_mst_atomic_wait_for_dependencies(&state->base); 7441 intel_atomic_global_state_wait_for_dependencies(state); 7442 7443 /* 7444 * During full modesets we write a lot of registers, wait 7445 * for PLLs, etc. Doing that while DC states are enabled 7446 * is not a good idea. 7447 * 7448 * During fastsets and other updates we also need to 7449 * disable DC states due to the following scenario: 7450 * 1. DC5 exit and PSR exit happen 7451 * 2. Some or all _noarm() registers are written 7452 * 3. Due to some long delay PSR is re-entered 7453 * 4. DC5 entry -> DMC saves the already written new 7454 * _noarm() registers and the old not yet written 7455 * _arm() registers 7456 * 5. DC5 exit -> DMC restores a mixture of old and 7457 * new register values and arms the update 7458 * 6. PSR exit -> hardware latches a mixture of old and 7459 * new register values -> corrupted frame, or worse 7460 * 7. New _arm() registers are finally written 7461 * 8. Hardware finally latches a complete set of new 7462 * register values, and subsequent frames will be OK again 7463 * 7464 * Also note that due to the pipe CSC hardware issues on 7465 * SKL/GLK DC states must remain off until the pipe CSC 7466 * state readout has happened. Otherwise we risk corrupting 7467 * the CSC latched register values with the readout (see 7468 * skl_read_csc() and skl_color_commit_noarm()). 7469 */ 7470 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); 7471 7472 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7473 new_crtc_state, i) { 7474 if (intel_crtc_needs_modeset(new_crtc_state) || 7475 intel_crtc_needs_fastset(new_crtc_state)) 7476 intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]); 7477 } 7478 7479 intel_commit_modeset_disables(state); 7480 7481 intel_dp_tunnel_atomic_alloc_bw(state); 7482 7483 /* FIXME: Eventually get rid of our crtc->config pointer */ 7484 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7485 crtc->config = new_crtc_state; 7486 7487 /* 7488 * In XE_LPD+ Pmdemand combines many parameters such as voltage index, 7489 * plls, cdclk frequency, QGV point selection parameter etc. Voltage 7490 * index, cdclk/ddiclk frequencies are supposed to be configured before 7491 * the cdclk config is set. 7492 */ 7493 intel_pmdemand_pre_plane_update(state); 7494 7495 if (state->modeset) 7496 drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base); 7497 7498 intel_set_cdclk_pre_plane_update(state); 7499 7500 if (state->modeset) 7501 intel_modeset_verify_disabled(state); 7502 7503 intel_sagv_pre_plane_update(state); 7504 7505 /* Complete the events for pipes that have now been disabled */ 7506 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7507 bool modeset = intel_crtc_needs_modeset(new_crtc_state); 7508 7509 /* Complete events for now disable pipes here. */ 7510 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { 7511 spin_lock_irq(&display->drm->event_lock); 7512 drm_crtc_send_vblank_event(&crtc->base, 7513 new_crtc_state->uapi.event); 7514 spin_unlock_irq(&display->drm->event_lock); 7515 7516 new_crtc_state->uapi.event = NULL; 7517 } 7518 } 7519 7520 intel_encoders_update_prepare(state); 7521 7522 intel_dbuf_pre_plane_update(state); 7523 7524 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7525 if (new_crtc_state->do_async_flip) 7526 intel_crtc_enable_flip_done(state, crtc); 7527 } 7528 7529 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7530 display->funcs.display->commit_modeset_enables(state); 7531 7532 /* FIXME probably need to sequence this properly */ 7533 intel_program_dpkgc_latency(state); 7534 7535 intel_wait_for_vblank_workers(state); 7536 7537 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here 7538 * already, but still need the state for the delayed optimization. To 7539 * fix this: 7540 * - wrap the optimization/post_plane_update stuff into a per-crtc work. 7541 * - schedule that vblank worker _before_ calling hw_done 7542 * - at the start of commit_tail, cancel it _synchrously 7543 * - switch over to the vblank wait helper in the core after that since 7544 * we don't need out special handling any more. 7545 */ 7546 drm_atomic_helper_wait_for_flip_done(display->drm, &state->base); 7547 7548 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 7549 if (new_crtc_state->do_async_flip) 7550 intel_crtc_disable_flip_done(state, crtc); 7551 7552 intel_atomic_dsb_wait_commit(new_crtc_state); 7553 7554 if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb) 7555 intel_vrr_check_push_sent(NULL, new_crtc_state); 7556 7557 if (new_crtc_state->use_flipq) 7558 intel_flipq_disable(new_crtc_state); 7559 } 7560 7561 /* 7562 * Now that the vblank has passed, we can go ahead and program the 7563 * optimal watermarks on platforms that need two-step watermark 7564 * programming. 7565 * 7566 * TODO: Move this (and other cleanup) to an async worker eventually. 7567 */ 7568 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, 7569 new_crtc_state, i) { 7570 /* 7571 * Gen2 reports pipe underruns whenever all planes are disabled. 7572 * So re-enable underrun reporting after some planes get enabled. 7573 * 7574 * We do this before .optimize_watermarks() so that we have a 7575 * chance of catching underruns with the intermediate watermarks 7576 * vs. the new plane configuration. 7577 */ 7578 if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) 7579 intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); 7580 7581 intel_optimize_watermarks(state, crtc); 7582 } 7583 7584 intel_dbuf_post_plane_update(state); 7585 7586 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 7587 intel_post_plane_update(state, crtc); 7588 7589 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]); 7590 7591 intel_modeset_verify_crtc(state, crtc); 7592 7593 intel_post_plane_update_after_readout(state, crtc); 7594 7595 /* 7596 * DSB cleanup is done in cleanup_work aligning with framebuffer 7597 * cleanup. So copy and reset the dsb structure to sync with 7598 * commit_done and later do dsb cleanup in cleanup_work. 7599 * 7600 * FIXME get rid of this funny new->old swapping 7601 */ 7602 old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color); 7603 old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit); 7604 } 7605 7606 /* Underruns don't always raise interrupts, so check manually */ 7607 intel_check_cpu_fifo_underruns(display); 7608 intel_check_pch_fifo_underruns(display); 7609 7610 if (state->modeset) 7611 intel_verify_planes(state); 7612 7613 intel_sagv_post_plane_update(state); 7614 intel_set_cdclk_post_plane_update(state); 7615 intel_pmdemand_post_plane_update(state); 7616 7617 drm_atomic_helper_commit_hw_done(&state->base); 7618 intel_atomic_global_state_commit_done(state); 7619 7620 if (state->modeset) { 7621 /* As one of the primary mmio accessors, KMS has a high 7622 * likelihood of triggering bugs in unclaimed access. After we 7623 * finish modesetting, see if an error has been flagged, and if 7624 * so enable debugging for the next modeset - and hope we catch 7625 * the culprit. 7626 */ 7627 intel_uncore_arm_unclaimed_mmio_detection(uncore); 7628 } 7629 /* 7630 * Delay re-enabling DC states by 17 ms to avoid the off->on->off 7631 * toggling overhead at and above 60 FPS. 7632 */ 7633 intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17); 7634 intel_display_rpm_put(display, state->wakeref); 7635 7636 /* 7637 * Defer the cleanup of the old state to a separate worker to not 7638 * impede the current task (userspace for blocking modesets) that 7639 * are executed inline. For out-of-line asynchronous modesets/flips, 7640 * deferring to a new worker seems overkill, but we would place a 7641 * schedule point (cond_resched()) here anyway to keep latencies 7642 * down. 7643 */ 7644 INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work); 7645 queue_work(display->wq.cleanup, &state->cleanup_work); 7646 } 7647 7648 static void intel_atomic_commit_work(struct work_struct *work) 7649 { 7650 struct intel_atomic_state *state = 7651 container_of(work, struct intel_atomic_state, base.commit_work); 7652 7653 intel_atomic_commit_tail(state); 7654 } 7655 7656 static void intel_atomic_track_fbs(struct intel_atomic_state *state) 7657 { 7658 struct intel_plane_state *old_plane_state, *new_plane_state; 7659 struct intel_plane *plane; 7660 int i; 7661 7662 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 7663 new_plane_state, i) 7664 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), 7665 to_intel_frontbuffer(new_plane_state->hw.fb), 7666 plane->frontbuffer_bit); 7667 } 7668 7669 static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock) 7670 { 7671 int ret; 7672 7673 ret = drm_atomic_helper_setup_commit(&state->base, nonblock); 7674 if (ret) 7675 return ret; 7676 7677 ret = intel_atomic_global_state_setup_commit(state); 7678 if (ret) 7679 return ret; 7680 7681 return 0; 7682 } 7683 7684 static int intel_atomic_swap_state(struct intel_atomic_state *state) 7685 { 7686 int ret; 7687 7688 ret = drm_atomic_helper_swap_state(&state->base, true); 7689 if (ret) 7690 return ret; 7691 7692 intel_atomic_swap_global_state(state); 7693 7694 intel_dpll_swap_state(state); 7695 7696 intel_atomic_track_fbs(state); 7697 7698 return 0; 7699 } 7700 7701 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, 7702 bool nonblock) 7703 { 7704 struct intel_display *display = to_intel_display(dev); 7705 struct intel_atomic_state *state = to_intel_atomic_state(_state); 7706 int ret = 0; 7707 7708 state->wakeref = intel_display_rpm_get(display); 7709 7710 /* 7711 * The intel_legacy_cursor_update() fast path takes care 7712 * of avoiding the vblank waits for simple cursor 7713 * movement and flips. For cursor on/off and size changes, 7714 * we want to perform the vblank waits so that watermark 7715 * updates happen during the correct frames. Gen9+ have 7716 * double buffered watermarks and so shouldn't need this. 7717 * 7718 * Unset state->legacy_cursor_update before the call to 7719 * drm_atomic_helper_setup_commit() because otherwise 7720 * drm_atomic_helper_wait_for_flip_done() is a noop and 7721 * we get FIFO underruns because we didn't wait 7722 * for vblank. 7723 * 7724 * FIXME doing watermarks and fb cleanup from a vblank worker 7725 * (assuming we had any) would solve these problems. 7726 */ 7727 if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) { 7728 struct intel_crtc_state *new_crtc_state; 7729 struct intel_crtc *crtc; 7730 int i; 7731 7732 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) 7733 if (new_crtc_state->wm.need_postvbl_update || 7734 new_crtc_state->update_wm_post) 7735 state->base.legacy_cursor_update = false; 7736 } 7737 7738 ret = intel_atomic_prepare_commit(state); 7739 if (ret) { 7740 drm_dbg_atomic(display->drm, 7741 "Preparing state failed with %i\n", ret); 7742 intel_display_rpm_put(display, state->wakeref); 7743 return ret; 7744 } 7745 7746 ret = intel_atomic_setup_commit(state, nonblock); 7747 if (!ret) 7748 ret = intel_atomic_swap_state(state); 7749 7750 if (ret) { 7751 drm_atomic_helper_unprepare_planes(dev, &state->base); 7752 intel_display_rpm_put(display, state->wakeref); 7753 return ret; 7754 } 7755 7756 drm_atomic_state_get(&state->base); 7757 INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); 7758 7759 if (nonblock && state->modeset) { 7760 queue_work(display->wq.modeset, &state->base.commit_work); 7761 } else if (nonblock) { 7762 queue_work(display->wq.flip, &state->base.commit_work); 7763 } else { 7764 if (state->modeset) 7765 flush_workqueue(display->wq.modeset); 7766 intel_atomic_commit_tail(state); 7767 } 7768 7769 return 0; 7770 } 7771 7772 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) 7773 { 7774 struct intel_display *display = to_intel_display(encoder); 7775 struct intel_encoder *source_encoder; 7776 u32 possible_clones = 0; 7777 7778 for_each_intel_encoder(display->drm, source_encoder) { 7779 if (encoders_cloneable(encoder, source_encoder)) 7780 possible_clones |= drm_encoder_mask(&source_encoder->base); 7781 } 7782 7783 return possible_clones; 7784 } 7785 7786 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) 7787 { 7788 struct intel_display *display = to_intel_display(encoder); 7789 struct intel_crtc *crtc; 7790 u32 possible_crtcs = 0; 7791 7792 for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask) 7793 possible_crtcs |= drm_crtc_mask(&crtc->base); 7794 7795 return possible_crtcs; 7796 } 7797 7798 static bool ilk_has_edp_a(struct intel_display *display) 7799 { 7800 if (!display->platform.mobile) 7801 return false; 7802 7803 if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0) 7804 return false; 7805 7806 if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE)) 7807 return false; 7808 7809 return true; 7810 } 7811 7812 static bool intel_ddi_crt_present(struct intel_display *display) 7813 { 7814 if (DISPLAY_VER(display) >= 9) 7815 return false; 7816 7817 if (display->platform.haswell_ult || display->platform.broadwell_ult) 7818 return false; 7819 7820 if (HAS_PCH_LPT_H(display) && 7821 intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) 7822 return false; 7823 7824 /* DDI E can't be used if DDI A requires 4 lanes */ 7825 if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) 7826 return false; 7827 7828 if (!display->vbt.int_crt_support) 7829 return false; 7830 7831 return true; 7832 } 7833 7834 bool assert_port_valid(struct intel_display *display, enum port port) 7835 { 7836 return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)), 7837 "Platform does not support port %c\n", port_name(port)); 7838 } 7839 7840 void intel_setup_outputs(struct intel_display *display) 7841 { 7842 struct intel_encoder *encoder; 7843 bool dpd_is_edp = false; 7844 7845 intel_pps_unlock_regs_wa(display); 7846 7847 if (!HAS_DISPLAY(display)) 7848 return; 7849 7850 if (HAS_DDI(display)) { 7851 if (intel_ddi_crt_present(display)) 7852 intel_crt_init(display); 7853 7854 intel_bios_for_each_encoder(display, intel_ddi_init); 7855 7856 if (display->platform.geminilake || display->platform.broxton) 7857 vlv_dsi_init(display); 7858 } else if (HAS_PCH_SPLIT(display)) { 7859 int found; 7860 7861 /* 7862 * intel_edp_init_connector() depends on this completing first, 7863 * to prevent the registration of both eDP and LVDS and the 7864 * incorrect sharing of the PPS. 7865 */ 7866 intel_lvds_init(display); 7867 intel_crt_init(display); 7868 7869 dpd_is_edp = intel_dp_is_port_edp(display, PORT_D); 7870 7871 if (ilk_has_edp_a(display)) 7872 g4x_dp_init(display, DP_A, PORT_A); 7873 7874 if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) { 7875 /* PCH SDVOB multiplex with HDMIB */ 7876 found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); 7877 if (!found) 7878 g4x_hdmi_init(display, PCH_HDMIB, PORT_B); 7879 if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED)) 7880 g4x_dp_init(display, PCH_DP_B, PORT_B); 7881 } 7882 7883 if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED) 7884 g4x_hdmi_init(display, PCH_HDMIC, PORT_C); 7885 7886 if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED) 7887 g4x_hdmi_init(display, PCH_HDMID, PORT_D); 7888 7889 if (intel_de_read(display, PCH_DP_C) & DP_DETECTED) 7890 g4x_dp_init(display, PCH_DP_C, PORT_C); 7891 7892 if (intel_de_read(display, PCH_DP_D) & DP_DETECTED) 7893 g4x_dp_init(display, PCH_DP_D, PORT_D); 7894 } else if (display->platform.valleyview || display->platform.cherryview) { 7895 bool has_edp, has_port; 7896 7897 if (display->platform.valleyview && display->vbt.int_crt_support) 7898 intel_crt_init(display); 7899 7900 /* 7901 * The DP_DETECTED bit is the latched state of the DDC 7902 * SDA pin at boot. However since eDP doesn't require DDC 7903 * (no way to plug in a DP->HDMI dongle) the DDC pins for 7904 * eDP ports may have been muxed to an alternate function. 7905 * Thus we can't rely on the DP_DETECTED bit alone to detect 7906 * eDP ports. Consult the VBT as well as DP_DETECTED to 7907 * detect eDP ports. 7908 * 7909 * Sadly the straps seem to be missing sometimes even for HDMI 7910 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap 7911 * and VBT for the presence of the port. Additionally we can't 7912 * trust the port type the VBT declares as we've seen at least 7913 * HDMI ports that the VBT claim are DP or eDP. 7914 */ 7915 has_edp = intel_dp_is_port_edp(display, PORT_B); 7916 has_port = intel_bios_is_port_present(display, PORT_B); 7917 if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port) 7918 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); 7919 if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) 7920 g4x_hdmi_init(display, VLV_HDMIB, PORT_B); 7921 7922 has_edp = intel_dp_is_port_edp(display, PORT_C); 7923 has_port = intel_bios_is_port_present(display, PORT_C); 7924 if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port) 7925 has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C); 7926 if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) 7927 g4x_hdmi_init(display, VLV_HDMIC, PORT_C); 7928 7929 if (display->platform.cherryview) { 7930 /* 7931 * eDP not supported on port D, 7932 * so no need to worry about it 7933 */ 7934 has_port = intel_bios_is_port_present(display, PORT_D); 7935 if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port) 7936 g4x_dp_init(display, CHV_DP_D, PORT_D); 7937 if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port) 7938 g4x_hdmi_init(display, CHV_HDMID, PORT_D); 7939 } 7940 7941 vlv_dsi_init(display); 7942 } else if (display->platform.pineview) { 7943 intel_lvds_init(display); 7944 intel_crt_init(display); 7945 } else if (IS_DISPLAY_VER(display, 3, 4)) { 7946 bool found = false; 7947 7948 if (display->platform.mobile) 7949 intel_lvds_init(display); 7950 7951 intel_crt_init(display); 7952 7953 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { 7954 drm_dbg_kms(display->drm, "probing SDVOB\n"); 7955 found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); 7956 if (!found && display->platform.g4x) { 7957 drm_dbg_kms(display->drm, 7958 "probing HDMI on SDVOB\n"); 7959 g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); 7960 } 7961 7962 if (!found && display->platform.g4x) 7963 g4x_dp_init(display, DP_B, PORT_B); 7964 } 7965 7966 /* Before G4X SDVOC doesn't have its own detect register */ 7967 7968 if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { 7969 drm_dbg_kms(display->drm, "probing SDVOC\n"); 7970 found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C); 7971 } 7972 7973 if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) { 7974 7975 if (display->platform.g4x) { 7976 drm_dbg_kms(display->drm, 7977 "probing HDMI on SDVOC\n"); 7978 g4x_hdmi_init(display, GEN4_HDMIC, PORT_C); 7979 } 7980 if (display->platform.g4x) 7981 g4x_dp_init(display, DP_C, PORT_C); 7982 } 7983 7984 if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED)) 7985 g4x_dp_init(display, DP_D, PORT_D); 7986 7987 if (SUPPORTS_TV(display)) 7988 intel_tv_init(display); 7989 } else if (DISPLAY_VER(display) == 2) { 7990 if (display->platform.i85x) 7991 intel_lvds_init(display); 7992 7993 intel_crt_init(display); 7994 intel_dvo_init(display); 7995 } 7996 7997 for_each_intel_encoder(display->drm, encoder) { 7998 encoder->base.possible_crtcs = 7999 intel_encoder_possible_crtcs(encoder); 8000 encoder->base.possible_clones = 8001 intel_encoder_possible_clones(encoder); 8002 } 8003 8004 intel_init_pch_refclk(display); 8005 8006 drm_helper_move_panel_connectors_to_head(display->drm); 8007 } 8008 8009 static int max_dotclock(struct intel_display *display) 8010 { 8011 int max_dotclock = display->cdclk.max_dotclk_freq; 8012 8013 if (HAS_ULTRAJOINER(display)) 8014 max_dotclock *= 4; 8015 else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display)) 8016 max_dotclock *= 2; 8017 8018 return max_dotclock; 8019 } 8020 8021 enum drm_mode_status intel_mode_valid(struct drm_device *dev, 8022 const struct drm_display_mode *mode) 8023 { 8024 struct intel_display *display = to_intel_display(dev); 8025 int hdisplay_max, htotal_max; 8026 int vdisplay_max, vtotal_max; 8027 8028 /* 8029 * Can't reject DBLSCAN here because Xorg ddxen can add piles 8030 * of DBLSCAN modes to the output's mode list when they detect 8031 * the scaling mode property on the connector. And they don't 8032 * ask the kernel to validate those modes in any way until 8033 * modeset time at which point the client gets a protocol error. 8034 * So in order to not upset those clients we silently ignore the 8035 * DBLSCAN flag on such connectors. For other connectors we will 8036 * reject modes with the DBLSCAN flag in encoder->compute_config(). 8037 * And we always reject DBLSCAN modes in connector->mode_valid() 8038 * as we never want such modes on the connector's mode list. 8039 */ 8040 8041 if (mode->vscan > 1) 8042 return MODE_NO_VSCAN; 8043 8044 if (mode->flags & DRM_MODE_FLAG_HSKEW) 8045 return MODE_H_ILLEGAL; 8046 8047 if (mode->flags & (DRM_MODE_FLAG_CSYNC | 8048 DRM_MODE_FLAG_NCSYNC | 8049 DRM_MODE_FLAG_PCSYNC)) 8050 return MODE_HSYNC; 8051 8052 if (mode->flags & (DRM_MODE_FLAG_BCAST | 8053 DRM_MODE_FLAG_PIXMUX | 8054 DRM_MODE_FLAG_CLKDIV2)) 8055 return MODE_BAD; 8056 8057 /* 8058 * Reject clearly excessive dotclocks early to 8059 * avoid having to worry about huge integers later. 8060 */ 8061 if (mode->clock > max_dotclock(display)) 8062 return MODE_CLOCK_HIGH; 8063 8064 /* Transcoder timing limits */ 8065 if (DISPLAY_VER(display) >= 11) { 8066 hdisplay_max = 16384; 8067 vdisplay_max = 8192; 8068 htotal_max = 16384; 8069 vtotal_max = 8192; 8070 } else if (DISPLAY_VER(display) >= 9 || 8071 display->platform.broadwell || display->platform.haswell) { 8072 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ 8073 vdisplay_max = 4096; 8074 htotal_max = 8192; 8075 vtotal_max = 8192; 8076 } else if (DISPLAY_VER(display) >= 3) { 8077 hdisplay_max = 4096; 8078 vdisplay_max = 4096; 8079 htotal_max = 8192; 8080 vtotal_max = 8192; 8081 } else { 8082 hdisplay_max = 2048; 8083 vdisplay_max = 2048; 8084 htotal_max = 4096; 8085 vtotal_max = 4096; 8086 } 8087 8088 if (mode->hdisplay > hdisplay_max || 8089 mode->hsync_start > htotal_max || 8090 mode->hsync_end > htotal_max || 8091 mode->htotal > htotal_max) 8092 return MODE_H_ILLEGAL; 8093 8094 if (mode->vdisplay > vdisplay_max || 8095 mode->vsync_start > vtotal_max || 8096 mode->vsync_end > vtotal_max || 8097 mode->vtotal > vtotal_max) 8098 return MODE_V_ILLEGAL; 8099 8100 /* 8101 * WM_LINETIME only goes up to (almost) 64 usec, and also 8102 * knowing that the linetime is always bounded will ease the 8103 * mind during various calculations. 8104 */ 8105 if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64) 8106 return MODE_H_ILLEGAL; 8107 8108 return MODE_OK; 8109 } 8110 8111 enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display, 8112 const struct drm_display_mode *mode) 8113 { 8114 /* 8115 * Additional transcoder timing limits, 8116 * excluding BXT/GLK DSI transcoders. 8117 */ 8118 if (DISPLAY_VER(display) >= 5) { 8119 if (mode->hdisplay < 64 || 8120 mode->htotal - mode->hdisplay < 32) 8121 return MODE_H_ILLEGAL; 8122 8123 if (mode->vtotal - mode->vdisplay < 5) 8124 return MODE_V_ILLEGAL; 8125 } else { 8126 if (mode->htotal - mode->hdisplay < 32) 8127 return MODE_H_ILLEGAL; 8128 8129 if (mode->vtotal - mode->vdisplay < 3) 8130 return MODE_V_ILLEGAL; 8131 } 8132 8133 /* 8134 * Cantiga+ cannot handle modes with a hsync front porch of 0. 8135 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. 8136 */ 8137 if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) && 8138 mode->hsync_start == mode->hdisplay) 8139 return MODE_H_ILLEGAL; 8140 8141 return MODE_OK; 8142 } 8143 8144 enum drm_mode_status 8145 intel_mode_valid_max_plane_size(struct intel_display *display, 8146 const struct drm_display_mode *mode, 8147 int num_joined_pipes) 8148 { 8149 int plane_width_max, plane_height_max; 8150 8151 /* 8152 * intel_mode_valid() should be 8153 * sufficient on older platforms. 8154 */ 8155 if (DISPLAY_VER(display) < 9) 8156 return MODE_OK; 8157 8158 /* 8159 * Most people will probably want a fullscreen 8160 * plane so let's not advertize modes that are 8161 * too big for that. 8162 */ 8163 if (DISPLAY_VER(display) >= 30) { 8164 plane_width_max = 6144 * num_joined_pipes; 8165 plane_height_max = 4800; 8166 } else if (DISPLAY_VER(display) >= 11) { 8167 plane_width_max = 5120 * num_joined_pipes; 8168 plane_height_max = 4320; 8169 } else { 8170 plane_width_max = 5120; 8171 plane_height_max = 4096; 8172 } 8173 8174 if (mode->hdisplay > plane_width_max) 8175 return MODE_H_ILLEGAL; 8176 8177 if (mode->vdisplay > plane_height_max) 8178 return MODE_V_ILLEGAL; 8179 8180 return MODE_OK; 8181 } 8182 8183 static const struct intel_display_funcs skl_display_funcs = { 8184 .get_pipe_config = hsw_get_pipe_config, 8185 .crtc_enable = hsw_crtc_enable, 8186 .crtc_disable = hsw_crtc_disable, 8187 .commit_modeset_enables = skl_commit_modeset_enables, 8188 .get_initial_plane_config = skl_get_initial_plane_config, 8189 .fixup_initial_plane_config = skl_fixup_initial_plane_config, 8190 }; 8191 8192 static const struct intel_display_funcs ddi_display_funcs = { 8193 .get_pipe_config = hsw_get_pipe_config, 8194 .crtc_enable = hsw_crtc_enable, 8195 .crtc_disable = hsw_crtc_disable, 8196 .commit_modeset_enables = intel_commit_modeset_enables, 8197 .get_initial_plane_config = i9xx_get_initial_plane_config, 8198 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8199 }; 8200 8201 static const struct intel_display_funcs pch_split_display_funcs = { 8202 .get_pipe_config = ilk_get_pipe_config, 8203 .crtc_enable = ilk_crtc_enable, 8204 .crtc_disable = ilk_crtc_disable, 8205 .commit_modeset_enables = intel_commit_modeset_enables, 8206 .get_initial_plane_config = i9xx_get_initial_plane_config, 8207 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8208 }; 8209 8210 static const struct intel_display_funcs vlv_display_funcs = { 8211 .get_pipe_config = i9xx_get_pipe_config, 8212 .crtc_enable = valleyview_crtc_enable, 8213 .crtc_disable = i9xx_crtc_disable, 8214 .commit_modeset_enables = intel_commit_modeset_enables, 8215 .get_initial_plane_config = i9xx_get_initial_plane_config, 8216 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8217 }; 8218 8219 static const struct intel_display_funcs i9xx_display_funcs = { 8220 .get_pipe_config = i9xx_get_pipe_config, 8221 .crtc_enable = i9xx_crtc_enable, 8222 .crtc_disable = i9xx_crtc_disable, 8223 .commit_modeset_enables = intel_commit_modeset_enables, 8224 .get_initial_plane_config = i9xx_get_initial_plane_config, 8225 .fixup_initial_plane_config = i9xx_fixup_initial_plane_config, 8226 }; 8227 8228 /** 8229 * intel_init_display_hooks - initialize the display modesetting hooks 8230 * @display: display device private 8231 */ 8232 void intel_init_display_hooks(struct intel_display *display) 8233 { 8234 if (DISPLAY_VER(display) >= 9) { 8235 display->funcs.display = &skl_display_funcs; 8236 } else if (HAS_DDI(display)) { 8237 display->funcs.display = &ddi_display_funcs; 8238 } else if (HAS_PCH_SPLIT(display)) { 8239 display->funcs.display = &pch_split_display_funcs; 8240 } else if (display->platform.cherryview || 8241 display->platform.valleyview) { 8242 display->funcs.display = &vlv_display_funcs; 8243 } else { 8244 display->funcs.display = &i9xx_display_funcs; 8245 } 8246 } 8247 8248 int intel_initial_commit(struct intel_display *display) 8249 { 8250 struct drm_atomic_state *state = NULL; 8251 struct drm_modeset_acquire_ctx ctx; 8252 struct intel_crtc *crtc; 8253 int ret = 0; 8254 8255 state = drm_atomic_state_alloc(display->drm); 8256 if (!state) 8257 return -ENOMEM; 8258 8259 drm_modeset_acquire_init(&ctx, 0); 8260 8261 state->acquire_ctx = &ctx; 8262 to_intel_atomic_state(state)->internal = true; 8263 8264 retry: 8265 for_each_intel_crtc(display->drm, crtc) { 8266 struct intel_crtc_state *crtc_state = 8267 intel_atomic_get_crtc_state(state, crtc); 8268 8269 if (IS_ERR(crtc_state)) { 8270 ret = PTR_ERR(crtc_state); 8271 goto out; 8272 } 8273 8274 if (!crtc_state->hw.active) 8275 crtc_state->inherited = false; 8276 8277 if (crtc_state->hw.active) { 8278 struct intel_encoder *encoder; 8279 8280 ret = drm_atomic_add_affected_planes(state, &crtc->base); 8281 if (ret) 8282 goto out; 8283 8284 /* 8285 * FIXME hack to force a LUT update to avoid the 8286 * plane update forcing the pipe gamma on without 8287 * having a proper LUT loaded. Remove once we 8288 * have readout for pipe gamma enable. 8289 */ 8290 crtc_state->uapi.color_mgmt_changed = true; 8291 8292 for_each_intel_encoder_mask(display->drm, encoder, 8293 crtc_state->uapi.encoder_mask) { 8294 if (encoder->initial_fastset_check && 8295 !encoder->initial_fastset_check(encoder, crtc_state)) { 8296 ret = drm_atomic_add_affected_connectors(state, 8297 &crtc->base); 8298 if (ret) 8299 goto out; 8300 } 8301 } 8302 } 8303 } 8304 8305 ret = drm_atomic_commit(state); 8306 8307 out: 8308 if (ret == -EDEADLK) { 8309 drm_atomic_state_clear(state); 8310 drm_modeset_backoff(&ctx); 8311 goto retry; 8312 } 8313 8314 drm_atomic_state_put(state); 8315 8316 drm_modeset_drop_locks(&ctx); 8317 drm_modeset_acquire_fini(&ctx); 8318 8319 return ret; 8320 } 8321 8322 void i830_enable_pipe(struct intel_display *display, enum pipe pipe) 8323 { 8324 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 8325 enum transcoder cpu_transcoder = (enum transcoder)pipe; 8326 /* 640x480@60Hz, ~25175 kHz */ 8327 struct dpll clock = { 8328 .m1 = 18, 8329 .m2 = 7, 8330 .p1 = 13, 8331 .p2 = 4, 8332 .n = 2, 8333 }; 8334 u32 dpll, fp; 8335 int i; 8336 8337 drm_WARN_ON(display->drm, 8338 i9xx_calc_dpll_params(48000, &clock) != 25154); 8339 8340 drm_dbg_kms(display->drm, 8341 "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", 8342 pipe_name(pipe), clock.vco, clock.dot); 8343 8344 fp = i9xx_dpll_compute_fp(&clock); 8345 dpll = DPLL_DVO_2X_MODE | 8346 DPLL_VGA_MODE_DIS | 8347 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | 8348 PLL_P2_DIVIDE_BY_4 | 8349 PLL_REF_INPUT_DREFCLK | 8350 DPLL_VCO_ENABLE; 8351 8352 intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), 8353 HACTIVE(640 - 1) | HTOTAL(800 - 1)); 8354 intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), 8355 HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); 8356 intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), 8357 HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); 8358 intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), 8359 VACTIVE(480 - 1) | VTOTAL(525 - 1)); 8360 intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), 8361 VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); 8362 intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), 8363 VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); 8364 intel_de_write(display, PIPESRC(display, pipe), 8365 PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); 8366 8367 intel_de_write(display, FP0(pipe), fp); 8368 intel_de_write(display, FP1(pipe), fp); 8369 8370 /* 8371 * Apparently we need to have VGA mode enabled prior to changing 8372 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 8373 * dividers, even though the register value does change. 8374 */ 8375 intel_de_write(display, DPLL(display, pipe), 8376 dpll & ~DPLL_VGA_MODE_DIS); 8377 intel_de_write(display, DPLL(display, pipe), dpll); 8378 8379 /* Wait for the clocks to stabilize. */ 8380 intel_de_posting_read(display, DPLL(display, pipe)); 8381 udelay(150); 8382 8383 /* The pixel multiplier can only be updated once the 8384 * DPLL is enabled and the clocks are stable. 8385 * 8386 * So write it again. 8387 */ 8388 intel_de_write(display, DPLL(display, pipe), dpll); 8389 8390 /* We do this three times for luck */ 8391 for (i = 0; i < 3 ; i++) { 8392 intel_de_write(display, DPLL(display, pipe), dpll); 8393 intel_de_posting_read(display, DPLL(display, pipe)); 8394 udelay(150); /* wait for warmup */ 8395 } 8396 8397 intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE); 8398 intel_de_posting_read(display, TRANSCONF(display, pipe)); 8399 8400 intel_wait_for_pipe_scanline_moving(crtc); 8401 } 8402 8403 void i830_disable_pipe(struct intel_display *display, enum pipe pipe) 8404 { 8405 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 8406 8407 drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n", 8408 pipe_name(pipe)); 8409 8410 drm_WARN_ON(display->drm, 8411 intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE); 8412 drm_WARN_ON(display->drm, 8413 intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE); 8414 drm_WARN_ON(display->drm, 8415 intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE); 8416 drm_WARN_ON(display->drm, 8417 intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK); 8418 drm_WARN_ON(display->drm, 8419 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); 8420 8421 intel_de_write(display, TRANSCONF(display, pipe), 0); 8422 intel_de_posting_read(display, TRANSCONF(display, pipe)); 8423 8424 intel_wait_for_pipe_scanline_stopped(crtc); 8425 8426 intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); 8427 intel_de_posting_read(display, DPLL(display, pipe)); 8428 } 8429 8430 bool intel_scanout_needs_vtd_wa(struct intel_display *display) 8431 { 8432 return IS_DISPLAY_VER(display, 6, 11) && intel_display_vtd_active(display); 8433 } 8434