1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
4 *
5 * Authors: Manish Narani <manish.narani@xilinx.com>
6 * Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/clk.h>
13 #include <linux/of.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/of_platform.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/of_address.h>
21 #include <linux/delay.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/io.h>
24
25 #include <linux/phy/phy.h>
26
27 /* USB phy reset mask register */
28 #define XLNX_USB_PHY_RST_EN 0x001C
29 #define XLNX_PHY_RST_MASK 0x1
30
31 /* Xilinx USB 3.0 IP Register */
32 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
33 #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
34
35 #define XLNX_USB_FPD_PIPE_CLK 0x7c
36 #define PIPE_CLK_DESELECT 1
37 #define PIPE_CLK_SELECT 0
38 #define XLNX_USB_FPD_POWER_PRSNT 0x80
39 #define FPD_POWER_PRSNT_OPTION BIT(0)
40
41 struct dwc3_xlnx {
42 int num_clocks;
43 struct clk_bulk_data *clks;
44 struct device *dev;
45 void __iomem *regs;
46 int (*pltfm_init)(struct dwc3_xlnx *data);
47 struct phy *usb3_phy;
48 };
49
dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx * priv_data,bool mask)50 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
51 {
52 u32 reg;
53
54 /*
55 * Enable or disable ULPI PHY reset from USB Controller.
56 * This does not actually reset the phy, but just controls
57 * whether USB controller can or cannot reset ULPI PHY.
58 */
59 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN);
60
61 if (mask)
62 reg &= ~XLNX_PHY_RST_MASK;
63 else
64 reg |= XLNX_PHY_RST_MASK;
65
66 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
67 }
68
dwc3_xlnx_init_versal(struct dwc3_xlnx * priv_data)69 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
70 {
71 struct device *dev = priv_data->dev;
72 struct reset_control *crst;
73 int ret;
74
75 crst = devm_reset_control_get_exclusive(dev, NULL);
76 if (IS_ERR(crst))
77 return dev_err_probe(dev, PTR_ERR(crst), "failed to get reset signal\n");
78
79 dwc3_xlnx_mask_phy_rst(priv_data, false);
80
81 /* Assert and De-assert reset */
82 ret = reset_control_assert(crst);
83 if (ret < 0) {
84 dev_err_probe(dev, ret, "failed to assert Reset\n");
85 return ret;
86 }
87
88 ret = reset_control_deassert(crst);
89 if (ret < 0) {
90 dev_err_probe(dev, ret, "failed to De-assert Reset\n");
91 return ret;
92 }
93
94 dwc3_xlnx_mask_phy_rst(priv_data, true);
95
96 return 0;
97 }
98
dwc3_xlnx_init_zynqmp(struct dwc3_xlnx * priv_data)99 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
100 {
101 struct device *dev = priv_data->dev;
102 struct reset_control *crst, *hibrst, *apbrst;
103 struct gpio_desc *reset_gpio;
104 int ret = 0;
105 u32 reg;
106
107 priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
108 if (IS_ERR(priv_data->usb3_phy)) {
109 ret = PTR_ERR(priv_data->usb3_phy);
110 dev_err_probe(dev, ret,
111 "failed to get USB3 PHY\n");
112 goto err;
113 }
114
115 /*
116 * The following core resets are not required unless a USB3 PHY
117 * is used, and the subsequent register settings are not required
118 * unless a core reset is performed (they should be set properly
119 * by the first-stage boot loader, but may be reverted by a core
120 * reset). They may also break the configuration if USB3 is actually
121 * in use but the usb3-phy entry is missing from the device tree.
122 * Therefore, skip these operations in this case.
123 */
124 if (!priv_data->usb3_phy)
125 goto skip_usb3_phy;
126
127 crst = devm_reset_control_get_exclusive(dev, "usb_crst");
128 if (IS_ERR(crst)) {
129 ret = PTR_ERR(crst);
130 dev_err_probe(dev, ret,
131 "failed to get core reset signal\n");
132 goto err;
133 }
134
135 hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst");
136 if (IS_ERR(hibrst)) {
137 ret = PTR_ERR(hibrst);
138 dev_err_probe(dev, ret,
139 "failed to get hibernation reset signal\n");
140 goto err;
141 }
142
143 apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst");
144 if (IS_ERR(apbrst)) {
145 ret = PTR_ERR(apbrst);
146 dev_err_probe(dev, ret,
147 "failed to get APB reset signal\n");
148 goto err;
149 }
150
151 ret = reset_control_assert(crst);
152 if (ret < 0) {
153 dev_err(dev, "Failed to assert core reset\n");
154 goto err;
155 }
156
157 ret = reset_control_assert(hibrst);
158 if (ret < 0) {
159 dev_err(dev, "Failed to assert hibernation reset\n");
160 goto err;
161 }
162
163 ret = reset_control_assert(apbrst);
164 if (ret < 0) {
165 dev_err(dev, "Failed to assert APB reset\n");
166 goto err;
167 }
168
169 ret = phy_init(priv_data->usb3_phy);
170 if (ret < 0) {
171 phy_exit(priv_data->usb3_phy);
172 goto err;
173 }
174
175 ret = reset_control_deassert(apbrst);
176 if (ret < 0) {
177 dev_err(dev, "Failed to release APB reset\n");
178 goto err;
179 }
180
181 /* Set PIPE Power Present signal in FPD Power Present Register*/
182 writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);
183
184 /* Set the PIPE Clock Select bit in FPD PIPE Clock register */
185 writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
186
187 ret = reset_control_deassert(crst);
188 if (ret < 0) {
189 dev_err(dev, "Failed to release core reset\n");
190 goto err;
191 }
192
193 ret = reset_control_deassert(hibrst);
194 if (ret < 0) {
195 dev_err(dev, "Failed to release hibernation reset\n");
196 goto err;
197 }
198
199 ret = phy_power_on(priv_data->usb3_phy);
200 if (ret < 0) {
201 phy_exit(priv_data->usb3_phy);
202 goto err;
203 }
204
205 skip_usb3_phy:
206 /* ulpi reset via gpio-modepin or gpio-framework driver */
207 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
208 if (IS_ERR(reset_gpio)) {
209 return dev_err_probe(dev, PTR_ERR(reset_gpio),
210 "Failed to request reset GPIO\n");
211 }
212
213 if (reset_gpio) {
214 /* Toggle ulpi to reset the phy. */
215 gpiod_set_value_cansleep(reset_gpio, 1);
216 usleep_range(5000, 10000);
217 gpiod_set_value_cansleep(reset_gpio, 0);
218 usleep_range(5000, 10000);
219 }
220
221 /*
222 * This routes the USB DMA traffic to go through FPD path instead
223 * of reaching DDR directly. This traffic routing is needed to
224 * make SMMU and CCI work with USB DMA.
225 */
226 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
227 reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
228 reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
229 writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
230 }
231
232 err:
233 return ret;
234 }
235
236 static const struct of_device_id dwc3_xlnx_of_match[] = {
237 {
238 .compatible = "xlnx,zynqmp-dwc3",
239 .data = &dwc3_xlnx_init_zynqmp,
240 },
241 {
242 .compatible = "xlnx,versal-dwc3",
243 .data = &dwc3_xlnx_init_versal,
244 },
245 { /* Sentinel */ }
246 };
247 MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
248
dwc3_set_swnode(struct device * dev)249 static int dwc3_set_swnode(struct device *dev)
250 {
251 struct device_node *np = dev->of_node, *dwc3_np;
252 struct property_entry props[2];
253 int prop_idx = 0, ret = 0;
254
255 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
256 if (!dwc3_np) {
257 ret = -ENODEV;
258 dev_err(dev, "failed to find dwc3 core child\n");
259 return ret;
260 }
261
262 memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
263 if (of_dma_is_coherent(dwc3_np))
264 props[prop_idx++] = PROPERTY_ENTRY_U16("snps,gsbuscfg0-reqinfo",
265 0xffff);
266 of_node_put(dwc3_np);
267
268 if (prop_idx)
269 ret = device_create_managed_software_node(dev, props, NULL);
270
271 return ret;
272 }
273
dwc3_xlnx_probe(struct platform_device * pdev)274 static int dwc3_xlnx_probe(struct platform_device *pdev)
275 {
276 struct dwc3_xlnx *priv_data;
277 struct device *dev = &pdev->dev;
278 struct device_node *np = dev->of_node;
279 const struct of_device_id *match;
280 void __iomem *regs;
281 int ret;
282
283 priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
284 if (!priv_data)
285 return -ENOMEM;
286
287 regs = devm_platform_ioremap_resource(pdev, 0);
288 if (IS_ERR(regs))
289 return dev_err_probe(dev, PTR_ERR(regs), "failed to map registers\n");
290
291 match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);
292
293 priv_data->pltfm_init = match->data;
294 priv_data->regs = regs;
295 priv_data->dev = dev;
296
297 platform_set_drvdata(pdev, priv_data);
298
299 ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks);
300 if (ret < 0)
301 return ret;
302
303 priv_data->num_clocks = ret;
304
305 ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks);
306 if (ret)
307 return ret;
308
309 ret = priv_data->pltfm_init(priv_data);
310 if (ret)
311 goto err_clk_put;
312
313 ret = dwc3_set_swnode(dev);
314 if (ret)
315 goto err_clk_put;
316
317 ret = of_platform_populate(np, NULL, NULL, dev);
318 if (ret)
319 goto err_clk_put;
320
321 pm_runtime_set_active(dev);
322 ret = devm_pm_runtime_enable(dev);
323 if (ret < 0)
324 goto err_pm_set_suspended;
325
326 pm_suspend_ignore_children(dev, false);
327 ret = pm_runtime_resume_and_get(dev);
328 if (ret < 0)
329 goto err_pm_set_suspended;
330
331 return 0;
332
333 err_pm_set_suspended:
334 of_platform_depopulate(dev);
335 pm_runtime_set_suspended(dev);
336
337 err_clk_put:
338 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
339
340 return ret;
341 }
342
dwc3_xlnx_remove(struct platform_device * pdev)343 static void dwc3_xlnx_remove(struct platform_device *pdev)
344 {
345 struct dwc3_xlnx *priv_data = platform_get_drvdata(pdev);
346 struct device *dev = &pdev->dev;
347
348 of_platform_depopulate(dev);
349
350 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
351 priv_data->num_clocks = 0;
352
353 pm_runtime_put_noidle(dev);
354 pm_runtime_set_suspended(dev);
355 }
356
dwc3_xlnx_runtime_suspend(struct device * dev)357 static int __maybe_unused dwc3_xlnx_runtime_suspend(struct device *dev)
358 {
359 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
360
361 clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
362
363 return 0;
364 }
365
dwc3_xlnx_runtime_resume(struct device * dev)366 static int __maybe_unused dwc3_xlnx_runtime_resume(struct device *dev)
367 {
368 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
369
370 return clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
371 }
372
dwc3_xlnx_runtime_idle(struct device * dev)373 static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev)
374 {
375 pm_runtime_mark_last_busy(dev);
376 pm_runtime_autosuspend(dev);
377
378 return 0;
379 }
380
dwc3_xlnx_suspend(struct device * dev)381 static int __maybe_unused dwc3_xlnx_suspend(struct device *dev)
382 {
383 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
384
385 phy_exit(priv_data->usb3_phy);
386
387 /* Disable the clocks */
388 clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
389
390 return 0;
391 }
392
dwc3_xlnx_resume(struct device * dev)393 static int __maybe_unused dwc3_xlnx_resume(struct device *dev)
394 {
395 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
396 int ret;
397
398 ret = clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
399 if (ret)
400 return ret;
401
402 ret = phy_init(priv_data->usb3_phy);
403 if (ret < 0)
404 return ret;
405
406 ret = phy_power_on(priv_data->usb3_phy);
407 if (ret < 0) {
408 phy_exit(priv_data->usb3_phy);
409 return ret;
410 }
411
412 return 0;
413 }
414
415 static const struct dev_pm_ops dwc3_xlnx_dev_pm_ops = {
416 SET_SYSTEM_SLEEP_PM_OPS(dwc3_xlnx_suspend, dwc3_xlnx_resume)
417 SET_RUNTIME_PM_OPS(dwc3_xlnx_runtime_suspend,
418 dwc3_xlnx_runtime_resume, dwc3_xlnx_runtime_idle)
419 };
420
421 static struct platform_driver dwc3_xlnx_driver = {
422 .probe = dwc3_xlnx_probe,
423 .remove_new = dwc3_xlnx_remove,
424 .driver = {
425 .name = "dwc3-xilinx",
426 .of_match_table = dwc3_xlnx_of_match,
427 .pm = &dwc3_xlnx_dev_pm_ops,
428 },
429 };
430
431 module_platform_driver(dwc3_xlnx_driver);
432
433 MODULE_LICENSE("GPL v2");
434 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver");
435 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>");
436 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>");
437