1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/platform_device.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/seq_file.h> 23 #include <linux/spinlock.h> 24 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 #include <linux/pinctrl/pinconf.h> 28 #include <linux/pinctrl/pinctrl.h> 29 #include <linux/pinctrl/pinmux.h> 30 31 #include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h> 32 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h> 33 #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h> 34 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 35 36 #include "../core.h" 37 #include "../pinconf.h" 38 #include "../pinmux.h" 39 40 #define DRV_NAME "pinctrl-rzg2l" 41 42 /* 43 * Use 16 lower bits [15:0] for pin identifier 44 * Use 16 higher bits [31:16] for pin mux function 45 */ 46 #define MUX_PIN_ID_MASK GENMASK(15, 0) 47 #define MUX_FUNC_MASK GENMASK(31, 16) 48 49 /* PIN capabilities */ 50 #define PIN_CFG_IOLH_A BIT(0) 51 #define PIN_CFG_IOLH_B BIT(1) 52 #define PIN_CFG_SR BIT(2) 53 #define PIN_CFG_IEN BIT(3) 54 #define PIN_CFG_PUPD BIT(4) 55 #define PIN_CFG_IO_VMC_SD0 BIT(5) 56 #define PIN_CFG_IO_VMC_SD1 BIT(6) 57 #define PIN_CFG_IO_VMC_QSPI BIT(7) 58 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 59 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 60 #define PIN_CFG_NF BIT(10) /* Digital noise filter */ 61 #define PIN_CFG_IOLH_C BIT(11) 62 #define PIN_CFG_SOFT_PS BIT(12) 63 #define PIN_CFG_OEN BIT(13) 64 #define PIN_CFG_NOGPIO_INT BIT(14) 65 #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */ 66 #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ 67 #define PIN_CFG_ELC BIT(17) 68 #define PIN_CFG_IOLH_RZV2H BIT(18) 69 #define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ 70 #define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ 71 #define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ 72 73 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ 74 #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ 75 76 #define PIN_CFG_OTHER_POC_MASK \ 77 (PIN_CFG_PVDD1833_OTH_AWO_POC | \ 78 PIN_CFG_PVDD1833_OTH_ISO_POC | \ 79 PIN_CFG_WDTOVF_N_POC) 80 81 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ 82 (PIN_CFG_IOLH_##group | \ 83 PIN_CFG_PUPD | \ 84 PIN_CFG_NF) 85 86 #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \ 87 PIN_CFG_SR) 88 89 #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ 90 PIN_CFG_SOFT_PS) 91 92 #define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \ 93 PIN_CFG_NOD | \ 94 PIN_CFG_SR | \ 95 PIN_CFG_SMT) 96 97 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF) 98 99 #define RZG3L_MPXED_ETH_PIN_FUNCS(ether) \ 100 (PIN_CFG_IO_VMC_##ether | \ 101 PIN_CFG_IOLH_C | \ 102 PIN_CFG_PUPD | \ 103 PIN_CFG_NF) 104 105 #define RZG3L_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ 106 PIN_CFG_SOFT_PS) 107 108 #define RZG3L_MPXED_PIN_FUNCS_POC(grp, poc) (RZG2L_MPXED_COMMON_PIN_FUNCS(grp) | \ 109 PIN_CFG_PVDD1833_OTH_##poc##_POC) 110 111 #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) 112 #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) 113 #define PIN_CFG_MASK GENMASK_ULL(31, 0) 114 115 /* 116 * m indicates the bitmap of supported pins, a is the register index 117 * and f is pin configuration capabilities supported. 118 */ 119 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ 120 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ 121 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 122 #define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \ 123 (RZG2L_VARIABLE_CFG | \ 124 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0)) 125 126 /* 127 * n indicates number of pins in the port, a is the register index 128 * and f is pin configuration capabilities supported. 129 */ 130 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) 131 #define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \ 132 RZG2L_GPIO_PORT_PACK(n, a, 0)) 133 134 #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) 135 #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) 136 /* 137 * p is the register index while referencing to SR/IEN/IOLH/FILxx 138 * registers, b is the register bits (b * 8) and f is the pin 139 * configuration capabilities supported. 140 */ 141 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 142 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ 143 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ 144 FIELD_PREP_CONST(PIN_CFG_MASK, (f))) 145 146 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ 147 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ 148 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) 149 150 #define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52) 151 #define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47) 152 #define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \ 153 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \ 154 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \ 155 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg))) 156 157 #define RZG3L_CLONE_CHANNEL_PIN_MASK GENMASK(31, 24) 158 #define RZG3L_CLONE_CHANNEL_PORT_MASK GENMASK(23, 19) 159 #define RZG3L_CLONE_CHANNEL_BIT_MASK GENMASK(12, 9) 160 #define RZG3L_CLONE_CHANNEL_VAL_MASK BIT(8) 161 #define RZG3L_CLONE_CHANNEL_PFC_MASK GENMASK(7, 0) 162 #define RZG3L_CLONE_CHANNEL_DATA(port, pins, bit, val, pfc) \ 163 (FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PIN_MASK, (pins)) | \ 164 FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PORT_MASK, (port)) | \ 165 FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_BIT_MASK, (bit)) | \ 166 FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_VAL_MASK, (val)) | \ 167 FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PFC_MASK, (pfc))) 168 169 #define P(off) (0x0000 + (off)) 170 #define PM(off) (0x0100 + (off) * 2) 171 #define PMC(off) (0x0200 + (off)) 172 #define PFC(off) (0x0400 + (off) * 4) 173 #define PIN(off) (0x0800 + (off)) 174 #define IOLH(off) (0x1000 + (off) * 8) 175 #define SR(off) (0x1400 + (off) * 8) 176 #define IEN(off) (0x1800 + (off) * 8) 177 #define PUPD(off) (0x1C00 + (off) * 8) 178 #define ISEL(off) (0x2C00 + (off) * 8) 179 #define NOD(off) (0x3000 + (off) * 8) 180 #define SMT(off) (0x3400 + (off) * 8) 181 #define SD_CH(off, ch) ((off) + (ch) * 4) 182 #define ETH_POC(off, ch) ((off) + (ch) * 4) 183 #define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ 184 #define OTHER_POC (0x3028) /* known on RZ/G3L only */ 185 186 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ 187 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 188 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 189 190 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 191 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 192 #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */ 193 #define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */ 194 195 #define PM_MASK 0x03 196 #define PFC_MASK 0x0f 197 #define IEN_MASK 0x01 198 #define IOLH_MASK 0x03 199 #define SR_MASK 0x01 200 #define PUPD_MASK 0x03 201 #define NOD_MASK 0x01 202 #define SMT_MASK 0x01 203 204 #define PM_INPUT 0x1 205 #define PM_OUTPUT 0x2 206 207 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 208 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 209 210 #define RZG2L_TINT_MAX_INTERRUPT 32 211 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 212 213 /* Custom pinconf parameters */ 214 #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1) 215 216 static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = { 217 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 }, 218 }; 219 220 #ifdef CONFIG_DEBUG_FS 221 static const struct pin_config_item renesas_rzv2h_conf_items[] = { 222 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true), 223 }; 224 #endif 225 226 /* Read/write 8 bits register */ 227 #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ 228 do { \ 229 if (_read) \ 230 _val = readb(_addr); \ 231 else \ 232 writeb(_val, _addr); \ 233 } while (0) 234 235 /* Read/write 16 bits register */ 236 #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \ 237 do { \ 238 if (_read) \ 239 _val = readw(_addr); \ 240 else \ 241 writew(_val, _addr); \ 242 } while (0) 243 244 /* Read/write 32 bits register */ 245 #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \ 246 do { \ 247 if (_read) \ 248 _val = readl(_addr); \ 249 else \ 250 writel(_val, _addr); \ 251 } while (0) 252 253 /** 254 * struct rzg2l_register_offsets - specific register offsets 255 * @pwpr: PWPR register offset 256 * @sd_ch: SD_CH register offset 257 * @eth_poc: ETH_POC register offset 258 * @oen: OEN register offset 259 * @qspi: QSPI register offset 260 * @other_poc: OTHER_POC register offset 261 */ 262 struct rzg2l_register_offsets { 263 u16 pwpr; 264 u16 sd_ch; 265 u16 eth_poc; 266 u16 oen; 267 u16 qspi; 268 u16 other_poc; 269 }; 270 271 /** 272 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays 273 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source 274 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source 275 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source 276 * @RZG2L_IOLH_IDX_MAX: maximum index 277 */ 278 enum rzg2l_iolh_index { 279 RZG2L_IOLH_IDX_1V8 = 0, 280 RZG2L_IOLH_IDX_2V5 = 4, 281 RZG2L_IOLH_IDX_3V3 = 8, 282 RZG2L_IOLH_IDX_MAX = 12, 283 }; 284 285 /* Maximum number of driver strength entries per power source. */ 286 #define RZG2L_IOLH_MAX_DS_ENTRIES (4) 287 288 /** 289 * struct rzg2l_hwcfg - hardware configuration data structure 290 * @regs: hardware specific register offsets 291 * @iolh_groupa_ua: IOLH group A uA specific values 292 * @iolh_groupb_ua: IOLH group B uA specific values 293 * @iolh_groupc_ua: IOLH group C uA specific values 294 * @iolh_groupb_oi: IOLH group B output impedance specific values 295 * @tint_start_index: the start index for the TINT interrupts 296 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) 297 * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR 298 * @func_base: base number for port function (see register PFC) 299 * @oen_max_pin: the maximum pin number supporting output enable 300 * @oen_max_port: the maximum port number supporting output enable 301 */ 302 struct rzg2l_hwcfg { 303 const struct rzg2l_register_offsets regs; 304 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; 305 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX]; 306 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX]; 307 u16 iolh_groupb_oi[4]; 308 u16 tint_start_index; 309 bool drive_strength_ua; 310 bool oen_pwpr_lock; 311 u8 func_base; 312 u8 oen_max_pin; 313 u8 oen_max_port; 314 }; 315 316 struct rzg2l_dedicated_configs { 317 const char *name; 318 u64 config; 319 }; 320 321 struct rzg2l_pinctrl; 322 323 struct rzg2l_pinctrl_data { 324 const char * const *port_pins; 325 const u64 *port_pin_configs; 326 unsigned int n_ports; 327 const struct rzg2l_dedicated_configs *dedicated_pins; 328 unsigned int n_port_pins; 329 unsigned int n_dedicated_pins; 330 const u32 *clone_channel_data; 331 unsigned int n_clone_channel_data; 332 const struct rzg2l_hwcfg *hwcfg; 333 const u64 *variable_pin_cfg; 334 unsigned int n_variable_pin_cfg; 335 unsigned int num_custom_params; 336 const struct pinconf_generic_params *custom_params; 337 #ifdef CONFIG_DEBUG_FS 338 const struct pin_config_item *custom_conf_items; 339 #endif 340 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); 341 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); 342 int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); 343 int (*hw_to_bias_param)(unsigned int val); 344 int (*bias_param_to_hw)(enum pin_config_param param); 345 }; 346 347 /** 348 * struct rzg2l_pinctrl_pin_settings - pin data 349 * @power_source: power source 350 * @drive_strength_ua: drive strength (in micro amps) 351 */ 352 struct rzg2l_pinctrl_pin_settings { 353 u16 power_source; 354 u16 drive_strength_ua; 355 }; 356 357 /** 358 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) 359 * @p: P registers cache 360 * @pm: PM registers cache 361 * @pmc: PMC registers cache 362 * @pfc: PFC registers cache 363 * @iolh: IOLH registers cache 364 * @ien: IEN registers cache 365 * @pupd: PUPD registers cache 366 * @smt: SMT registers cache 367 * @sr: SR registers cache 368 * @nod: NOD registers cache 369 * @clone: Clone register cache 370 * @sd_ch: SD_CH registers cache 371 * @eth_poc: ET_POC registers cache 372 * @oen: Output Enable register cache 373 * @other_poc: OTHER_POC register cache 374 * @qspi: QSPI registers cache 375 */ 376 struct rzg2l_pinctrl_reg_cache { 377 u8 *p; 378 u16 *pm; 379 u8 *pmc; 380 u32 *pfc; 381 u32 *iolh[2]; 382 u32 *ien[2]; 383 u32 *pupd[2]; 384 u32 *smt[2]; 385 u32 *sr[2]; 386 u32 *nod[2]; 387 u32 clone; 388 u8 sd_ch[2]; 389 u8 eth_poc[2]; 390 u8 oen; 391 u8 other_poc; 392 u8 qspi; 393 }; 394 395 struct rzg2l_pinctrl { 396 struct pinctrl_dev *pctl; 397 struct pinctrl_desc desc; 398 struct pinctrl_pin_desc *pins; 399 400 const struct rzg2l_pinctrl_data *data; 401 void __iomem *base; 402 struct device *dev; 403 404 struct clk *clk; 405 406 struct regmap *syscon; 407 408 struct gpio_chip gpio_chip; 409 struct pinctrl_gpio_range gpio_range; 410 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 411 spinlock_t bitmap_lock; /* protect tint_slot bitmap */ 412 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 413 414 raw_spinlock_t lock; /* lock read/write registers */ 415 struct mutex mutex; /* serialize adding groups and functions */ 416 417 struct rzg2l_pinctrl_pin_settings *settings; 418 struct rzg2l_pinctrl_reg_cache *cache; 419 struct rzg2l_pinctrl_reg_cache *dedicated_cache; 420 atomic_t wakeup_path; 421 u32 clone_offset; 422 }; 423 424 static const u16 available_ps[] = { 1800, 2500, 3300 }; 425 426 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, 427 u64 pincfg, 428 unsigned int port, 429 u8 pin) 430 { 431 unsigned int i; 432 433 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { 434 u64 cfg = pctrl->data->variable_pin_cfg[i]; 435 436 if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port && 437 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin) 438 return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg); 439 } 440 441 return 0; 442 } 443 444 static const u64 r9a08g046_variable_pin_cfg[] = { 445 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN), 446 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 447 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 448 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 449 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 450 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 451 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN), 452 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 453 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 454 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_OEN), 455 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 456 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 457 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 458 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 459 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 460 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), 461 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_IEN), 462 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 463 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 464 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 465 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 466 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 467 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 468 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 469 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 470 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_OEN), 471 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 472 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 473 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 474 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 475 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 476 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), 477 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)), 478 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 479 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 480 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 481 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 482 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 483 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), 484 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), 485 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)), 486 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 487 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 488 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 489 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 490 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), 491 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_CFG_IEN), 492 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)), 493 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)), 494 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 3, RZG3L_MPXED_PIN_FUNCS(A)), 495 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 4, RZG3L_MPXED_PIN_FUNCS(A)), 496 }; 497 498 static const u64 r9a09g047_variable_pin_cfg[] = { 499 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 500 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), 501 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS), 502 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS), 503 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS), 504 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS), 505 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS), 506 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS), 507 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS), 508 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 509 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS), 510 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS), 511 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS), 512 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS), 513 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS), 514 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS), 515 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 516 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS), 517 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS), 518 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS), 519 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS), 520 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS), 521 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS), 522 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS), 523 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS), 524 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 525 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS), 526 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS), 527 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS), 528 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS), 529 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS), 530 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS), 531 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS), 532 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 533 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 534 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 535 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 536 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 537 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS), 538 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS), 539 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS), 540 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 541 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 542 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 543 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 544 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 545 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 546 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS), 547 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS), 548 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS), 549 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS), 550 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 551 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 552 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 553 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS), 554 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_OEN), 555 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS), 556 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS), 557 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS), 558 }; 559 560 static const u64 r9a09g057_variable_pin_cfg[] = { 561 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS), 562 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 563 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 564 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 565 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 566 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), 567 }; 568 569 #ifdef CONFIG_RISCV 570 static const u64 r9a07g043f_variable_pin_cfg[] = { 571 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 572 PIN_CFG_NF | 573 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 574 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 575 PIN_CFG_NF | 576 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 577 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 578 PIN_CFG_NF | 579 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 580 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 581 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 582 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 583 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 584 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 585 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 586 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 587 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 588 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 589 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), 590 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 591 PIN_CFG_NOGPIO_INT), 592 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 593 PIN_CFG_NOGPIO_INT), 594 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 595 PIN_CFG_NOGPIO_INT), 596 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 597 PIN_CFG_NOGPIO_INT), 598 RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 599 RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT), 600 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 601 PIN_CFG_NOGPIO_INT), 602 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 603 PIN_CFG_NOGPIO_INT), 604 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 605 PIN_CFG_NOGPIO_INT), 606 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 607 PIN_CFG_NOGPIO_INT), 608 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 609 PIN_CFG_NF | 610 PIN_CFG_NOGPIO_INT), 611 }; 612 #endif 613 614 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 615 { 616 writeb(val, pctrl->base + offset); 617 } 618 619 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset) 620 { 621 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 622 u8 pwpr; 623 624 pwpr = readb(pctrl->base + regs->pwpr); 625 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr); 626 writeb(val, pctrl->base + offset); 627 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 628 } 629 630 static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl, 631 u64 cfg, u32 port, u8 bit) 632 { 633 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 634 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 635 u64 data; 636 637 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) 638 return -EINVAL; 639 640 data = pctrl->data->port_pin_configs[port]; 641 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data)) 642 return -EINVAL; 643 644 return 0; 645 } 646 647 static int rzg2l_pinctrl_set_clone_mode(struct rzg2l_pinctrl *pctrl, 648 u8 port, u8 pin, u8 func) 649 { 650 unsigned int i; 651 652 if (!pctrl->data->clone_channel_data) 653 return 0; 654 655 switch (func) { 656 case 2: 657 case 4 ... 7: 658 break; 659 default: 660 return 0; 661 } 662 663 for (i = 0; i < pctrl->data->n_clone_channel_data; i++) { 664 u32 pin_data = pctrl->data->clone_channel_data[i]; 665 unsigned int pin_func_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PFC_MASK, pin_data); 666 unsigned int pin_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PIN_MASK, pin_data); 667 u32 bit, val; 668 669 if (!(pin_func_mask & BIT(func)) || 670 FIELD_GET(RZG3L_CLONE_CHANNEL_PORT_MASK, pin_data) != port) 671 continue; 672 673 if (!(pin_mask & BIT(pin))) 674 continue; 675 676 bit = FIELD_GET(RZG3L_CLONE_CHANNEL_BIT_MASK, pin_data); 677 val = FIELD_GET(RZG3L_CLONE_CHANNEL_VAL_MASK, pin_data); 678 679 return regmap_update_bits(pctrl->syscon, pctrl->clone_offset, 680 BIT(bit), val << bit); 681 } 682 683 return 0; 684 } 685 686 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 687 u8 pin, u8 off, u8 func) 688 { 689 unsigned long flags; 690 u32 reg, pfc; 691 692 /* Switching to GPIO is not required if reset value is same as func */ 693 raw_spin_lock_irqsave(&pctrl->lock, flags); 694 reg = readb(pctrl->base + PMC(off)); 695 pfc = readl(pctrl->base + PFC(off)); 696 if ((reg & BIT(pin)) && (((pfc >> (pin * 4)) & PFC_MASK) == func)) { 697 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 698 return; 699 } 700 701 /* Set pin to 'Non-use (Hi-Z input protection)' */ 702 reg = readw(pctrl->base + PM(off)); 703 reg &= ~(PM_MASK << (pin * 2)); 704 writew(reg, pctrl->base + PM(off)); 705 706 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 707 708 /* Temporarily switch to GPIO mode with PMC register */ 709 reg = readb(pctrl->base + PMC(off)); 710 writeb(reg & ~BIT(pin), pctrl->base + PMC(off)); 711 712 /* Select Pin function mode with PFC register */ 713 pfc &= ~(PFC_MASK << (pin * 4)); 714 writel(pfc | (func << (pin * 4)), pctrl->base + PFC(off)); 715 716 /* Switch to Peripheral pin function with PMC register */ 717 reg = readb(pctrl->base + PMC(off)); 718 writeb(reg | BIT(pin), pctrl->base + PMC(off)); 719 720 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 721 722 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 723 } 724 725 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 726 unsigned int func_selector, 727 unsigned int group_selector) 728 { 729 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 730 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 731 const struct function_desc *func; 732 unsigned int i, *psel_val; 733 struct group_desc *group; 734 const unsigned int *pins; 735 int ret; 736 737 func = pinmux_generic_get_function(pctldev, func_selector); 738 if (!func) 739 return -EINVAL; 740 group = pinctrl_generic_get_group(pctldev, group_selector); 741 if (!group) 742 return -EINVAL; 743 744 psel_val = func->data; 745 pins = group->grp.pins; 746 747 for (i = 0; i < group->grp.npins; i++) { 748 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; 749 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 750 u32 port = RZG2L_PIN_ID_TO_PORT(pins[i]); 751 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); 752 unsigned int func; 753 754 ret = rzg2l_validate_pin(pctrl, *pin_data, port, pin); 755 if (ret) 756 return ret; 757 758 func = psel_val[i] - hwcfg->func_base; 759 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", port, pin, off, func); 760 761 ret = rzg2l_pinctrl_set_clone_mode(pctrl, port, pin, func); 762 if (ret) 763 return ret; 764 765 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func); 766 } 767 768 return 0; 769 } 770 771 static int rzg2l_map_add_config(struct pinctrl_map *map, 772 const char *group_or_pin, 773 enum pinctrl_map_type type, 774 unsigned long *configs, 775 unsigned int num_configs) 776 { 777 unsigned long *cfgs; 778 779 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL); 780 if (!cfgs) 781 return -ENOMEM; 782 783 map->type = type; 784 map->data.configs.group_or_pin = group_or_pin; 785 map->data.configs.configs = cfgs; 786 map->data.configs.num_configs = num_configs; 787 788 return 0; 789 } 790 791 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 792 struct device_node *np, 793 struct device_node *parent, 794 struct pinctrl_map **map, 795 unsigned int *num_maps, 796 unsigned int *index) 797 { 798 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 799 struct pinctrl_map *maps = *map; 800 unsigned int nmaps = *num_maps; 801 unsigned long *configs = NULL; 802 unsigned int *pins, *psel_val; 803 unsigned int num_pinmux = 0; 804 unsigned int idx = *index; 805 unsigned int num_pins, i; 806 unsigned int num_configs; 807 struct property *pinmux; 808 struct property *prop; 809 int ret, gsel, fsel; 810 const char **pin_fn; 811 const char *name; 812 const char *pin; 813 814 pinmux = of_find_property(np, "pinmux", NULL); 815 if (pinmux) 816 num_pinmux = pinmux->length / sizeof(u32); 817 818 ret = of_property_count_strings(np, "pins"); 819 if (ret == -EINVAL) { 820 num_pins = 0; 821 } else if (ret < 0) { 822 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 823 return ret; 824 } else { 825 num_pins = ret; 826 } 827 828 if (!num_pinmux && !num_pins) 829 return 0; 830 831 if (num_pinmux && num_pins) { 832 dev_err(pctrl->dev, 833 "DT node must contain either a pinmux or pins and not both\n"); 834 return -EINVAL; 835 } 836 837 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs); 838 if (ret < 0) 839 return ret; 840 841 if (num_pins && !num_configs) { 842 dev_err(pctrl->dev, "DT node must contain a config\n"); 843 ret = -ENODEV; 844 goto done; 845 } 846 847 if (num_pinmux) { 848 nmaps += 1; 849 if (num_configs) 850 nmaps += 1; 851 } 852 853 if (num_pins) 854 nmaps += num_pins; 855 856 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 857 if (!maps) { 858 ret = -ENOMEM; 859 goto done; 860 } 861 862 *map = maps; 863 *num_maps = nmaps; 864 if (num_pins) { 865 of_property_for_each_string(np, "pins", prop, pin) { 866 ret = rzg2l_map_add_config(&maps[idx], pin, 867 PIN_MAP_TYPE_CONFIGS_PIN, 868 configs, num_configs); 869 if (ret < 0) 870 goto done; 871 872 idx++; 873 } 874 ret = 0; 875 goto done; 876 } 877 878 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 879 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 880 GFP_KERNEL); 881 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 882 if (!pins || !psel_val || !pin_fn) { 883 ret = -ENOMEM; 884 goto done; 885 } 886 887 /* Collect pin locations and mux settings from DT properties */ 888 for (i = 0; i < num_pinmux; ++i) { 889 u32 value; 890 891 ret = of_property_read_u32_index(np, "pinmux", i, &value); 892 if (ret) 893 goto done; 894 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); 895 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); 896 } 897 898 if (parent) { 899 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 900 parent, np); 901 if (!name) { 902 ret = -ENOMEM; 903 goto done; 904 } 905 } else { 906 name = np->name; 907 } 908 909 if (num_configs) { 910 ret = rzg2l_map_add_config(&maps[idx], name, 911 PIN_MAP_TYPE_CONFIGS_GROUP, 912 configs, num_configs); 913 if (ret < 0) 914 goto done; 915 916 idx++; 917 } 918 919 mutex_lock(&pctrl->mutex); 920 921 /* Register a single pin group listing all the pins we read from DT */ 922 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 923 if (gsel < 0) { 924 ret = gsel; 925 goto unlock; 926 } 927 928 /* 929 * Register a single group function where the 'data' is an array PSEL 930 * register values read from DT. 931 */ 932 pin_fn[0] = name; 933 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 934 if (fsel < 0) { 935 ret = fsel; 936 goto remove_group; 937 } 938 939 mutex_unlock(&pctrl->mutex); 940 941 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 942 maps[idx].data.mux.group = name; 943 maps[idx].data.mux.function = name; 944 idx++; 945 946 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 947 ret = 0; 948 goto done; 949 950 remove_group: 951 pinctrl_generic_remove_group(pctldev, gsel); 952 unlock: 953 mutex_unlock(&pctrl->mutex); 954 done: 955 *index = idx; 956 kfree(configs); 957 return ret; 958 } 959 960 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 961 struct pinctrl_map *map, 962 unsigned int num_maps) 963 { 964 unsigned int i; 965 966 if (!map) 967 return; 968 969 for (i = 0; i < num_maps; ++i) { 970 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 971 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 972 kfree(map[i].data.configs.configs); 973 } 974 kfree(map); 975 } 976 977 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 978 struct device_node *np, 979 struct pinctrl_map **map, 980 unsigned int *num_maps) 981 { 982 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 983 unsigned int index; 984 int ret; 985 986 *map = NULL; 987 *num_maps = 0; 988 index = 0; 989 990 for_each_child_of_node_scoped(np, child) { 991 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, 992 num_maps, &index); 993 if (ret < 0) 994 goto done; 995 } 996 997 if (*num_maps == 0) { 998 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, 999 num_maps, &index); 1000 if (ret < 0) 1001 goto done; 1002 } 1003 1004 if (*num_maps) 1005 return 0; 1006 1007 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 1008 ret = -EINVAL; 1009 1010 done: 1011 rzg2l_dt_free_map(pctldev, *map, *num_maps); 1012 1013 return ret; 1014 } 1015 1016 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 1017 u8 bit, u32 mask) 1018 { 1019 void __iomem *addr = pctrl->base + offset; 1020 1021 /* handle _L/_H for 32-bit register read/write */ 1022 if (bit >= 4) { 1023 bit -= 4; 1024 addr += 4; 1025 } 1026 1027 return (readl(addr) >> (bit * 8)) & mask; 1028 } 1029 1030 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 1031 u8 bit, u32 mask, u32 val) 1032 { 1033 void __iomem *addr = pctrl->base + offset; 1034 unsigned long flags; 1035 u32 reg; 1036 1037 /* handle _L/_H for 32-bit register read/write */ 1038 if (bit >= 4) { 1039 bit -= 4; 1040 addr += 4; 1041 } 1042 1043 raw_spin_lock_irqsave(&pctrl->lock, flags); 1044 reg = readl(addr) & ~(mask << (bit * 8)); 1045 writel(reg | (val << (bit * 8)), addr); 1046 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1047 } 1048 1049 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, 1050 u32 caps, u8 *mask) 1051 { 1052 if (caps & PIN_CFG_IO_VMC_SD0) 1053 return SD_CH(regs->sd_ch, 0); 1054 if (caps & PIN_CFG_IO_VMC_SD1) 1055 return SD_CH(regs->sd_ch, 1); 1056 if (caps & PIN_CFG_IO_VMC_ETH0) 1057 return ETH_POC(regs->eth_poc, 0); 1058 if (caps & PIN_CFG_IO_VMC_ETH1) 1059 return ETH_POC(regs->eth_poc, 1); 1060 if (caps & PIN_CFG_IO_VMC_QSPI) 1061 return QSPI; 1062 if (caps & PIN_CFG_OTHER_POC_MASK) { 1063 if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) 1064 *mask = BIT(0); 1065 else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) 1066 *mask = BIT(1); 1067 else 1068 *mask = BIT(2); 1069 1070 return OTHER_POC; 1071 } 1072 1073 return -EINVAL; 1074 } 1075 1076 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps) 1077 { 1078 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1079 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 1080 u8 val, mask; 1081 int pwr_reg; 1082 1083 if (caps & PIN_CFG_SOFT_PS) 1084 return pctrl->settings[pin].power_source; 1085 1086 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask); 1087 if (pwr_reg < 0) 1088 return pwr_reg; 1089 1090 val = readb(pctrl->base + pwr_reg); 1091 if (pwr_reg == OTHER_POC) 1092 val = field_get(mask, val); 1093 1094 switch (val) { 1095 case PVDD_1800: 1096 return 1800; 1097 case PVDD_2500: 1098 return 2500; 1099 case PVDD_3300: 1100 return 3300; 1101 default: 1102 /* Should not happen. */ 1103 return -EINVAL; 1104 } 1105 } 1106 1107 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) 1108 { 1109 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1110 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 1111 u8 poc_val, val, mask; 1112 int pwr_reg; 1113 1114 if (caps & PIN_CFG_SOFT_PS) { 1115 pctrl->settings[pin].power_source = ps; 1116 return 0; 1117 } 1118 1119 switch (ps) { 1120 case 1800: 1121 poc_val = PVDD_1800; 1122 break; 1123 case 2500: 1124 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) 1125 return -EINVAL; 1126 poc_val = PVDD_2500; 1127 break; 1128 case 3300: 1129 poc_val = PVDD_3300; 1130 break; 1131 default: 1132 return -EINVAL; 1133 } 1134 1135 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask); 1136 if (pwr_reg < 0) 1137 return pwr_reg; 1138 1139 if (pwr_reg == OTHER_POC) { 1140 scoped_guard(raw_spinlock_irqsave, &pctrl->lock) { 1141 val = readb(pctrl->base + pwr_reg); 1142 if (poc_val) 1143 val |= mask; 1144 else 1145 val &= ~mask; 1146 writeb(val, pctrl->base + pwr_reg); 1147 } 1148 } else { 1149 writeb(poc_val, pctrl->base + pwr_reg); 1150 } 1151 1152 pctrl->settings[pin].power_source = ps; 1153 1154 return 0; 1155 } 1156 1157 static bool rzg2l_ps_is_supported(u16 ps) 1158 { 1159 unsigned int i; 1160 1161 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 1162 if (available_ps[i] == ps) 1163 return true; 1164 } 1165 1166 return false; 1167 } 1168 1169 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps) 1170 { 1171 unsigned int i; 1172 1173 for (i = 0; i < ARRAY_SIZE(available_ps); i++) { 1174 if (available_ps[i] == ps) 1175 break; 1176 } 1177 1178 /* 1179 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have 1180 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source 1181 */ 1182 return i * RZG2L_IOLH_MAX_DS_ENTRIES; 1183 } 1184 1185 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val) 1186 { 1187 if (caps & PIN_CFG_IOLH_A) 1188 return hwcfg->iolh_groupa_ua[val]; 1189 1190 if (caps & PIN_CFG_IOLH_B) 1191 return hwcfg->iolh_groupb_ua[val]; 1192 1193 if (caps & PIN_CFG_IOLH_C) 1194 return hwcfg->iolh_groupc_ua[val]; 1195 1196 /* Should not happen. */ 1197 return 0; 1198 } 1199 1200 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps, 1201 enum rzg2l_iolh_index ps_index, u16 ua) 1202 { 1203 const u16 *array = NULL; 1204 unsigned int i; 1205 1206 if (caps & PIN_CFG_IOLH_A) 1207 array = &hwcfg->iolh_groupa_ua[ps_index]; 1208 1209 if (caps & PIN_CFG_IOLH_B) 1210 array = &hwcfg->iolh_groupb_ua[ps_index]; 1211 1212 if (caps & PIN_CFG_IOLH_C) 1213 array = &hwcfg->iolh_groupc_ua[ps_index]; 1214 1215 if (!array) 1216 return -EINVAL; 1217 1218 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 1219 if (array[i] == ua) 1220 return i; 1221 } 1222 1223 return -EINVAL; 1224 } 1225 1226 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, 1227 enum rzg2l_iolh_index iolh_idx, 1228 u16 ds) 1229 { 1230 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1231 const u16 *array = NULL; 1232 unsigned int i; 1233 1234 if (caps & PIN_CFG_IOLH_A) 1235 array = hwcfg->iolh_groupa_ua; 1236 1237 if (caps & PIN_CFG_IOLH_B) 1238 array = hwcfg->iolh_groupb_ua; 1239 1240 if (caps & PIN_CFG_IOLH_C) 1241 array = hwcfg->iolh_groupc_ua; 1242 1243 /* Should not happen. */ 1244 if (!array) 1245 return false; 1246 1247 if (!array[iolh_idx]) 1248 return false; 1249 1250 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) { 1251 if (array[iolh_idx + i] == ds) 1252 return true; 1253 } 1254 1255 return false; 1256 } 1257 1258 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1259 { 1260 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1261 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); 1262 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1263 1264 if (pin != pctrl->data->hwcfg->oen_max_pin) 1265 return -EINVAL; 1266 1267 /* 1268 * We can determine which Ethernet interface we're dealing with from 1269 * the caps. 1270 */ 1271 if (caps & PIN_CFG_IO_VMC_ETH0) 1272 return 0; 1273 if (caps & PIN_CFG_IO_VMC_ETH1) 1274 return 1; 1275 1276 return -EINVAL; 1277 } 1278 1279 static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1280 { 1281 int bit; 1282 1283 if (!pctrl->data->pin_to_oen_bit) 1284 return -ENOTSUPP; 1285 1286 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); 1287 if (bit < 0) 1288 return -EINVAL; 1289 1290 return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); 1291 } 1292 1293 /** 1294 * rzg2l_oen_write_with_pwpr - Write to OEN register with PWPR protection 1295 * @pctrl: pinctrl driver data 1296 * @val: value to write to OEN register 1297 * 1298 * Writes to the OEN register, handling PWPR write protection if required 1299 * by the hardware configuration. Must be called with pctrl->lock held. 1300 */ 1301 static void rzg2l_oen_write_with_pwpr(struct rzg2l_pinctrl *pctrl, u8 val) 1302 { 1303 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 1304 u16 oen_offset = pctrl->data->hwcfg->regs.oen; 1305 u8 pwpr; 1306 1307 if (pctrl->data->hwcfg->oen_pwpr_lock) { 1308 pwpr = readb(pctrl->base + regs->pwpr); 1309 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1310 } 1311 1312 writeb(val, pctrl->base + oen_offset); 1313 1314 if (pctrl->data->hwcfg->oen_pwpr_lock) 1315 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1316 } 1317 1318 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1319 { 1320 u16 oen_offset = pctrl->data->hwcfg->regs.oen; 1321 unsigned long flags; 1322 int bit; 1323 u8 val; 1324 1325 if (!pctrl->data->pin_to_oen_bit) 1326 return -ENOTSUPP; 1327 1328 bit = pctrl->data->pin_to_oen_bit(pctrl, _pin); 1329 if (bit < 0) 1330 return -EINVAL; 1331 1332 raw_spin_lock_irqsave(&pctrl->lock, flags); 1333 val = readb(pctrl->base + oen_offset); 1334 if (oen) 1335 val &= ~BIT(bit); 1336 else 1337 val |= BIT(bit); 1338 1339 rzg2l_oen_write_with_pwpr(pctrl, val); 1340 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1341 1342 return 0; 1343 } 1344 1345 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1346 { 1347 u64 *pin_data = pctrl->desc.pins[_pin].drv_data; 1348 u8 port, pin, bit; 1349 1350 if (*pin_data & RZG2L_SINGLE_PIN) 1351 return -EINVAL; 1352 1353 port = RZG2L_PIN_ID_TO_PORT(_pin); 1354 pin = RZG2L_PIN_ID_TO_PIN(_pin); 1355 if (pin > pctrl->data->hwcfg->oen_max_pin) 1356 return -EINVAL; 1357 1358 bit = pin * 2; 1359 if (port == pctrl->data->hwcfg->oen_max_port) 1360 bit += 1; 1361 1362 return bit; 1363 } 1364 1365 static int rzg2l_hw_to_bias_param(unsigned int bias) 1366 { 1367 switch (bias) { 1368 case 0: 1369 return PIN_CONFIG_BIAS_DISABLE; 1370 case 1: 1371 return PIN_CONFIG_BIAS_PULL_UP; 1372 case 2: 1373 return PIN_CONFIG_BIAS_PULL_DOWN; 1374 default: 1375 break; 1376 } 1377 1378 return -EINVAL; 1379 } 1380 1381 static int rzg2l_bias_param_to_hw(enum pin_config_param param) 1382 { 1383 switch (param) { 1384 case PIN_CONFIG_BIAS_DISABLE: 1385 return 0; 1386 case PIN_CONFIG_BIAS_PULL_UP: 1387 return 1; 1388 case PIN_CONFIG_BIAS_PULL_DOWN: 1389 return 2; 1390 default: 1391 break; 1392 } 1393 1394 return -EINVAL; 1395 } 1396 1397 static int rzv2h_hw_to_bias_param(unsigned int bias) 1398 { 1399 switch (bias) { 1400 case 0: 1401 case 1: 1402 return PIN_CONFIG_BIAS_DISABLE; 1403 case 2: 1404 return PIN_CONFIG_BIAS_PULL_DOWN; 1405 case 3: 1406 return PIN_CONFIG_BIAS_PULL_UP; 1407 default: 1408 break; 1409 } 1410 1411 return -EINVAL; 1412 } 1413 1414 static int rzv2h_bias_param_to_hw(enum pin_config_param param) 1415 { 1416 switch (param) { 1417 case PIN_CONFIG_BIAS_DISABLE: 1418 return 0; 1419 case PIN_CONFIG_BIAS_PULL_DOWN: 1420 return 2; 1421 case PIN_CONFIG_BIAS_PULL_UP: 1422 return 3; 1423 default: 1424 break; 1425 } 1426 1427 return -EINVAL; 1428 } 1429 1430 static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin, 1431 const char * const pin_names[], unsigned int count) 1432 { 1433 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin]; 1434 unsigned int i; 1435 1436 for (i = 0; i < count; i++) { 1437 if (!strcmp(pin_desc->name, pin_names[i])) 1438 return i; 1439 } 1440 1441 return -EINVAL; 1442 } 1443 1444 static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1445 { 1446 static const char * const pin_names[] = { 1447 "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", 1448 "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP" 1449 }; 1450 1451 return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names)); 1452 } 1453 1454 static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) 1455 { 1456 static const char * const pin_names[] = { 1457 "PB1", "PE1", "PL4", "PL1", "PL2", "PL0" 1458 }; 1459 1460 return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_names)); 1461 } 1462 1463 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 1464 unsigned int _pin, 1465 unsigned long *config) 1466 { 1467 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1468 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1469 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1470 u32 param = pinconf_to_config_param(*config); 1471 u64 *pin_data = pin->drv_data; 1472 unsigned int arg = 0; 1473 u32 off; 1474 u32 cfg; 1475 int ret; 1476 u8 bit; 1477 1478 if (!pin_data) 1479 return -EINVAL; 1480 1481 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1482 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1483 if (*pin_data & RZG2L_SINGLE_PIN) { 1484 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1485 } else { 1486 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1487 1488 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1489 return -EINVAL; 1490 } 1491 1492 switch (param) { 1493 case PIN_CONFIG_INPUT_ENABLE: 1494 if (!(cfg & PIN_CFG_IEN)) 1495 return -EINVAL; 1496 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK); 1497 if (!arg) 1498 return -EINVAL; 1499 break; 1500 1501 case PIN_CONFIG_OUTPUT_ENABLE: 1502 if (!(cfg & PIN_CFG_OEN)) 1503 return -EINVAL; 1504 ret = rzg2l_read_oen(pctrl, _pin); 1505 if (ret < 0) 1506 return ret; 1507 arg = ret; 1508 break; 1509 1510 case PIN_CONFIG_POWER_SOURCE: 1511 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1512 if (ret < 0) 1513 return ret; 1514 arg = ret; 1515 break; 1516 1517 case PIN_CONFIG_SLEW_RATE: 1518 if (!(cfg & PIN_CFG_SR)) 1519 return -EINVAL; 1520 1521 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK); 1522 break; 1523 1524 case PIN_CONFIG_BIAS_DISABLE: 1525 case PIN_CONFIG_BIAS_PULL_UP: 1526 case PIN_CONFIG_BIAS_PULL_DOWN: 1527 if (!(cfg & PIN_CFG_PUPD)) 1528 return -EINVAL; 1529 1530 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK); 1531 ret = pctrl->data->hw_to_bias_param(arg); 1532 if (ret < 0) 1533 return ret; 1534 1535 if (ret != param) 1536 return -EINVAL; 1537 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ 1538 arg = 1; 1539 break; 1540 1541 case PIN_CONFIG_DRIVE_STRENGTH: { 1542 unsigned int index; 1543 1544 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1545 return -EINVAL; 1546 1547 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1548 /* 1549 * Drive strenght mA is supported only by group A and only 1550 * for 3V3 port source. 1551 */ 1552 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000; 1553 break; 1554 } 1555 1556 case PIN_CONFIG_DRIVE_STRENGTH_UA: { 1557 enum rzg2l_iolh_index iolh_idx; 1558 u8 val; 1559 1560 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1561 !hwcfg->drive_strength_ua) 1562 return -EINVAL; 1563 1564 ret = rzg2l_get_power_source(pctrl, _pin, cfg); 1565 if (ret < 0) 1566 return ret; 1567 iolh_idx = rzg2l_ps_to_iolh_idx(ret); 1568 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1569 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val); 1570 break; 1571 } 1572 1573 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 1574 unsigned int index; 1575 1576 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1577 return -EINVAL; 1578 1579 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1580 arg = hwcfg->iolh_groupb_oi[index]; 1581 break; 1582 } 1583 1584 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1585 case PIN_CONFIG_DRIVE_PUSH_PULL: 1586 if (!(cfg & PIN_CFG_NOD)) 1587 return -EINVAL; 1588 1589 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK); 1590 if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL) 1591 return -EINVAL; 1592 if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN) 1593 return -EINVAL; 1594 break; 1595 1596 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1597 if (!(cfg & PIN_CFG_SMT)) 1598 return -EINVAL; 1599 1600 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK); 1601 if (!arg) 1602 return -EINVAL; 1603 break; 1604 1605 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1606 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1607 return -EINVAL; 1608 1609 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK); 1610 break; 1611 1612 default: 1613 return -ENOTSUPP; 1614 } 1615 1616 *config = pinconf_to_config_packed(param, arg); 1617 1618 return 0; 1619 } 1620 1621 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 1622 unsigned int _pin, 1623 unsigned long *_configs, 1624 unsigned int num_configs) 1625 { 1626 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 1627 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 1628 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 1629 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; 1630 u64 *pin_data = pin->drv_data; 1631 unsigned int i, arg, index; 1632 u32 off, param; 1633 u32 cfg; 1634 int ret; 1635 u8 bit; 1636 1637 if (!pin_data) 1638 return -EINVAL; 1639 1640 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1641 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); 1642 if (*pin_data & RZG2L_SINGLE_PIN) { 1643 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); 1644 } else { 1645 bit = RZG2L_PIN_ID_TO_PIN(_pin); 1646 1647 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 1648 return -EINVAL; 1649 } 1650 1651 for (i = 0; i < num_configs; i++) { 1652 param = pinconf_to_config_param(_configs[i]); 1653 arg = pinconf_to_config_argument(_configs[i]); 1654 switch (param) { 1655 case PIN_CONFIG_INPUT_ENABLE: 1656 if (!(cfg & PIN_CFG_IEN)) 1657 return -EINVAL; 1658 1659 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); 1660 break; 1661 1662 case PIN_CONFIG_OUTPUT_ENABLE: 1663 if (!(cfg & PIN_CFG_OEN)) 1664 return -EINVAL; 1665 ret = rzg2l_write_oen(pctrl, _pin, !!arg); 1666 if (ret) 1667 return ret; 1668 break; 1669 1670 case PIN_CONFIG_POWER_SOURCE: 1671 settings.power_source = arg; 1672 break; 1673 1674 case PIN_CONFIG_SLEW_RATE: 1675 if (!(cfg & PIN_CFG_SR) || arg > 1) 1676 return -EINVAL; 1677 1678 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg); 1679 break; 1680 1681 case PIN_CONFIG_BIAS_DISABLE: 1682 case PIN_CONFIG_BIAS_PULL_UP: 1683 case PIN_CONFIG_BIAS_PULL_DOWN: 1684 if (!(cfg & PIN_CFG_PUPD)) 1685 return -EINVAL; 1686 1687 ret = pctrl->data->bias_param_to_hw(param); 1688 if (ret < 0) 1689 return ret; 1690 1691 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret); 1692 break; 1693 1694 case PIN_CONFIG_DRIVE_STRENGTH: 1695 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) 1696 return -EINVAL; 1697 1698 for (index = RZG2L_IOLH_IDX_3V3; 1699 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) { 1700 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) 1701 break; 1702 } 1703 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES)) 1704 return -EINVAL; 1705 1706 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1707 break; 1708 1709 case PIN_CONFIG_DRIVE_STRENGTH_UA: 1710 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || 1711 !hwcfg->drive_strength_ua) 1712 return -EINVAL; 1713 1714 settings.drive_strength_ua = arg; 1715 break; 1716 1717 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: 1718 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) 1719 return -EINVAL; 1720 1721 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) { 1722 if (arg == hwcfg->iolh_groupb_oi[index]) 1723 break; 1724 } 1725 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi)) 1726 return -EINVAL; 1727 1728 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); 1729 break; 1730 1731 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1732 case PIN_CONFIG_DRIVE_PUSH_PULL: 1733 if (!(cfg & PIN_CFG_NOD)) 1734 return -EINVAL; 1735 1736 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK, 1737 param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0); 1738 break; 1739 1740 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1741 if (!(cfg & PIN_CFG_SMT)) 1742 return -EINVAL; 1743 1744 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg); 1745 break; 1746 1747 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE: 1748 if (!(cfg & PIN_CFG_IOLH_RZV2H)) 1749 return -EINVAL; 1750 1751 if (arg > 3) 1752 return -EINVAL; 1753 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg); 1754 break; 1755 1756 default: 1757 return -ENOTSUPP; 1758 } 1759 } 1760 1761 /* Apply power source. */ 1762 if (settings.power_source != pctrl->settings[_pin].power_source) { 1763 ret = rzg2l_ps_is_supported(settings.power_source); 1764 if (!ret) 1765 return -EINVAL; 1766 1767 /* Apply power source. */ 1768 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source); 1769 if (ret) 1770 return ret; 1771 } 1772 1773 /* Apply drive strength. */ 1774 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) { 1775 enum rzg2l_iolh_index iolh_idx; 1776 int val; 1777 1778 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source); 1779 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx, 1780 settings.drive_strength_ua); 1781 if (!ret) 1782 return -EINVAL; 1783 1784 /* Get register value for this PS/DS tuple. */ 1785 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua); 1786 if (val < 0) 1787 return val; 1788 1789 /* Apply drive strength. */ 1790 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val); 1791 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua; 1792 } 1793 1794 return 0; 1795 } 1796 1797 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 1798 unsigned int group, 1799 unsigned long *configs, 1800 unsigned int num_configs) 1801 { 1802 const unsigned int *pins; 1803 unsigned int i, npins; 1804 int ret; 1805 1806 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1807 if (ret) 1808 return ret; 1809 1810 for (i = 0; i < npins; i++) { 1811 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 1812 num_configs); 1813 if (ret) 1814 return ret; 1815 } 1816 1817 return 0; 1818 } 1819 1820 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 1821 unsigned int group, 1822 unsigned long *config) 1823 { 1824 unsigned long prev_config = 0; 1825 const unsigned int *pins; 1826 unsigned int i, npins; 1827 int ret; 1828 1829 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 1830 if (ret) 1831 return ret; 1832 1833 for (i = 0; i < npins; i++) { 1834 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 1835 if (ret) 1836 return ret; 1837 1838 /* Check config matching between to pin */ 1839 if (i && prev_config != *config) 1840 return -ENOTSUPP; 1841 1842 prev_config = *config; 1843 } 1844 1845 return 0; 1846 } 1847 1848 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 1849 .get_groups_count = pinctrl_generic_get_group_count, 1850 .get_group_name = pinctrl_generic_get_group_name, 1851 .get_group_pins = pinctrl_generic_get_group_pins, 1852 .dt_node_to_map = rzg2l_dt_node_to_map, 1853 .dt_free_map = rzg2l_dt_free_map, 1854 }; 1855 1856 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 1857 .get_functions_count = pinmux_generic_get_function_count, 1858 .get_function_name = pinmux_generic_get_function_name, 1859 .get_function_groups = pinmux_generic_get_function_groups, 1860 .set_mux = rzg2l_pinctrl_set_mux, 1861 .strict = true, 1862 }; 1863 1864 static const struct pinconf_ops rzg2l_pinctrl_confops = { 1865 .is_generic = true, 1866 .pin_config_get = rzg2l_pinctrl_pinconf_get, 1867 .pin_config_set = rzg2l_pinctrl_pinconf_set, 1868 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 1869 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 1870 .pin_config_config_dbg_show = pinconf_generic_dump_config, 1871 }; 1872 1873 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 1874 { 1875 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1876 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1877 u64 *pin_data = pin_desc->drv_data; 1878 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1879 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 1880 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1881 unsigned long flags; 1882 u8 reg8; 1883 int ret; 1884 1885 ret = rzg2l_validate_pin(pctrl, *pin_data, port, bit); 1886 if (ret) 1887 return ret; 1888 1889 ret = pinctrl_gpio_request(chip, offset); 1890 if (ret) 1891 return ret; 1892 1893 raw_spin_lock_irqsave(&pctrl->lock, flags); 1894 1895 /* Select GPIO mode in PMC Register */ 1896 reg8 = readb(pctrl->base + PMC(off)); 1897 reg8 &= ~BIT(bit); 1898 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off)); 1899 1900 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1901 1902 return 0; 1903 } 1904 1905 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, 1906 bool output) 1907 { 1908 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1909 u64 *pin_data = pin_desc->drv_data; 1910 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1911 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1912 unsigned long flags; 1913 u16 reg16; 1914 1915 raw_spin_lock_irqsave(&pctrl->lock, flags); 1916 1917 reg16 = readw(pctrl->base + PM(off)); 1918 reg16 &= ~(PM_MASK << (bit * 2)); 1919 1920 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 1921 writew(reg16, pctrl->base + PM(off)); 1922 1923 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1924 } 1925 1926 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1927 { 1928 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1929 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1930 u64 *pin_data = pin_desc->drv_data; 1931 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1932 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1933 1934 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) { 1935 u16 reg16; 1936 1937 reg16 = readw(pctrl->base + PM(off)); 1938 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 1939 if (reg16 == PM_OUTPUT) 1940 return GPIO_LINE_DIRECTION_OUT; 1941 } 1942 1943 return GPIO_LINE_DIRECTION_IN; 1944 } 1945 1946 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 1947 unsigned int offset) 1948 { 1949 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1950 1951 rzg2l_gpio_set_direction(pctrl, offset, false); 1952 1953 return 0; 1954 } 1955 1956 static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 1957 int value) 1958 { 1959 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1960 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1961 u64 *pin_data = pin_desc->drv_data; 1962 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1963 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1964 unsigned long flags; 1965 u8 reg8; 1966 1967 raw_spin_lock_irqsave(&pctrl->lock, flags); 1968 1969 reg8 = readb(pctrl->base + P(off)); 1970 1971 if (value) 1972 writeb(reg8 | BIT(bit), pctrl->base + P(off)); 1973 else 1974 writeb(reg8 & ~BIT(bit), pctrl->base + P(off)); 1975 1976 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1977 1978 return 0; 1979 } 1980 1981 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 1982 unsigned int offset, int value) 1983 { 1984 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1985 1986 rzg2l_gpio_set(chip, offset, value); 1987 rzg2l_gpio_set_direction(pctrl, offset, true); 1988 1989 return 0; 1990 } 1991 1992 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 1993 { 1994 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 1995 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 1996 u64 *pin_data = pin_desc->drv_data; 1997 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 1998 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 1999 u16 reg16; 2000 2001 reg16 = readw(pctrl->base + PM(off)); 2002 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 2003 2004 if (reg16 == PM_INPUT) 2005 return !!(readb(pctrl->base + PIN(off)) & BIT(bit)); 2006 else if (reg16 == PM_OUTPUT) 2007 return !!(readb(pctrl->base + P(off)) & BIT(bit)); 2008 else 2009 return -EINVAL; 2010 } 2011 2012 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 2013 { 2014 unsigned int virq; 2015 2016 pinctrl_gpio_free(chip, offset); 2017 2018 virq = irq_find_mapping(chip->irq.domain, offset); 2019 if (virq) 2020 irq_dispose_mapping(virq); 2021 2022 /* 2023 * Set the GPIO as an input to ensure that the next GPIO request won't 2024 * drive the GPIO pin as an output. 2025 */ 2026 rzg2l_gpio_direction_input(chip, offset); 2027 } 2028 2029 static const char * const rzg2l_gpio_names[] = { 2030 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 2031 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 2032 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 2033 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 2034 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 2035 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 2036 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 2037 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 2038 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 2039 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 2040 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 2041 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 2042 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 2043 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 2044 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 2045 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 2046 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 2047 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 2048 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 2049 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 2050 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 2051 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 2052 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 2053 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 2054 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 2055 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 2056 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 2057 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 2058 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 2059 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 2060 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 2061 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 2062 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 2063 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 2064 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 2065 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 2066 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 2067 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 2068 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 2069 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 2070 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 2071 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 2072 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 2073 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 2074 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 2075 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 2076 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 2077 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 2078 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 2079 }; 2080 2081 static const u64 r9a07g044_gpio_configs[] = { 2082 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 2083 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 2084 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 2085 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 2086 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 2087 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 2088 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 2089 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 2090 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 2091 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 2092 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 2093 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 2094 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 2095 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 2096 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 2097 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 2098 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 2099 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 2100 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 2101 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 2102 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 2103 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2104 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2105 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2106 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2107 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2108 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2109 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2110 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2111 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 2112 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2113 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2114 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2115 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2116 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2117 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2118 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2119 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2120 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 2121 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 2122 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 2123 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 2124 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 2125 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 2126 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 2127 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 2128 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 2129 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 2130 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 2131 }; 2132 2133 static const u64 r9a07g043_gpio_configs[] = { 2134 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 2135 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN), 2136 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2137 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2138 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 2139 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 2140 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 2141 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN), 2142 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2143 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2144 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 2145 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 2146 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 2147 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 2148 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 2149 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 2150 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 2151 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 2152 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 2153 #ifdef CONFIG_RISCV 2154 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ 2155 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 2156 PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ 2157 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */ 2158 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 2159 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ 2160 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | 2161 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ 2162 RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */ 2163 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */ 2164 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF | 2165 PIN_CFG_NOGPIO_INT), /* P25 */ 2166 0x0, /* P26 */ 2167 0x0, /* P27 */ 2168 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ 2169 #endif 2170 }; 2171 2172 static const u64 r9a08g045_gpio_configs[] = { 2173 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ 2174 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2175 PIN_CFG_IO_VMC_ETH0)) | 2176 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ 2177 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2178 PIN_CFG_IO_VMC_ETH0)), /* P2 */ 2179 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2180 PIN_CFG_IO_VMC_ETH0)), /* P3 */ 2181 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2182 PIN_CFG_IO_VMC_ETH0)), /* P4 */ 2183 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ 2184 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ 2185 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2186 PIN_CFG_IO_VMC_ETH1)) | 2187 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ 2188 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2189 PIN_CFG_IO_VMC_ETH1)), /* P8 */ 2190 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2191 PIN_CFG_IO_VMC_ETH1)), /* P9 */ 2192 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | 2193 PIN_CFG_IO_VMC_ETH1)), /* P10 */ 2194 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */ 2195 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */ 2196 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */ 2197 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */ 2198 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */ 2199 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */ 2200 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */ 2201 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */ 2202 }; 2203 2204 static const char * const rzg3e_gpio_names[] = { 2205 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", 2206 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", 2207 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 2208 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 2209 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", 2210 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 2211 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 2212 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 2213 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 2214 "", "", "", "", "", "", "", "", 2215 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 2216 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 2217 "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", 2218 "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 2219 "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", 2220 "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", 2221 "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", 2222 "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", 2223 "", "", "", "", "", "", "", "", 2224 "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", 2225 "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", 2226 "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", 2227 "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", 2228 "", "", "", "", "", "", "", "", 2229 "", "", "", "", "", "", "", "", 2230 "", "", "", "", "", "", "", "", 2231 "", "", "", "", "", "", "", "", 2232 "", "", "", "", "", "", "", "", 2233 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", 2234 }; 2235 2236 static const u64 r9a09g047_gpio_configs[] = { 2237 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ 2238 RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS | 2239 PIN_CFG_ELC), /* P1 */ 2240 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | 2241 PIN_CFG_NOD), /* P2 */ 2242 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ 2243 RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ 2244 RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ 2245 RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */ 2246 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS | 2247 PIN_CFG_ELC), /* P7 */ 2248 RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ 2249 0x0, 2250 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ 2251 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ 2252 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ 2253 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ 2254 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ 2255 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ 2256 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ 2257 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ 2258 0x0, 2259 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ 2260 RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ 2261 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */ 2262 RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ 2263 0x0, 2264 0x0, 2265 0x0, 2266 0x0, 2267 0x0, 2268 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ 2269 }; 2270 2271 static const char * const rzg3l_gpio_names[] = { 2272 "", "", "", "", "", "", "", "", 2273 "", "", "", "", "", "", "", "", 2274 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 2275 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 2276 "", "", "", "", "", "", "", "", 2277 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 2278 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 2279 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 2280 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 2281 "", "", "", "", "", "", "", "", 2282 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 2283 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 2284 "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", 2285 "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 2286 "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", 2287 "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", 2288 "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", 2289 "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", 2290 "", "", "", "", "", "", "", "", 2291 "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", 2292 "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", 2293 "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", 2294 "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", 2295 "", "", "", "", "", "", "", "", 2296 "", "", "", "", "", "", "", "", 2297 "", "", "", "", "", "", "", "", 2298 "", "", "", "", "", "", "", "", 2299 "", "", "", "", "", "", "", "", 2300 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", 2301 }; 2302 2303 static const u64 r9a08g046_gpio_configs[] = { 2304 0x0, 2305 0x0, 2306 RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN), /* P2 */ 2307 RZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */ 2308 0x0, 2309 RZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P5 */ 2310 RZG2L_GPIO_PORT_PACK(7, 0x26, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P6 */ 2311 RZG2L_GPIO_PORT_PACK(8, 0x27, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P7 */ 2312 RZG2L_GPIO_PORT_PACK(6, 0x28, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P8 */ 2313 0x0, 2314 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ 2315 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ 2316 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), /* PC */ 2317 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ 2318 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ 2319 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), /* PF */ 2320 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ 2321 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ 2322 0x0, 2323 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ 2324 RZG2L_GPIO_PORT_PACK(4, 0x34, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), /* PK */ 2325 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG3L_MPXED_PIN_FUNCS(C)), /* PL */ 2326 RZG2L_GPIO_PORT_PACK(8, 0x36, RZG3L_MPXED_PIN_FUNCS(C)), /* PM */ 2327 0x0, 2328 0x0, 2329 0x0, 2330 0x0, 2331 0x0, 2332 RZG2L_GPIO_PORT_PACK(2, 0x3c, RZG3L_MPXED_PIN_FUNCS(A)), /* PS */ 2333 }; 2334 2335 static const char * const rzv2h_gpio_names[] = { 2336 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", 2337 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", 2338 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", 2339 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", 2340 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47", 2341 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", 2342 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", 2343 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", 2344 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", 2345 "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97", 2346 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", 2347 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", 2348 }; 2349 2350 static const u64 r9a09g057_gpio_configs[] = { 2351 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */ 2352 RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */ 2353 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | 2354 PIN_CFG_NOD), /* P2 */ 2355 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */ 2356 RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */ 2357 RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */ 2358 RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS | 2359 PIN_CFG_ELC), /* P6 */ 2360 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */ 2361 RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS | 2362 PIN_CFG_ELC), /* P8 */ 2363 RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */ 2364 RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */ 2365 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */ 2366 }; 2367 2368 static const struct { 2369 struct rzg2l_dedicated_configs common[35]; 2370 struct rzg2l_dedicated_configs rzg2l_pins[7]; 2371 } rzg2l_dedicated_pins = { 2372 .common = { 2373 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, 2374 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 2375 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 2376 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 2377 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 2378 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 2379 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 2380 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 2381 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 2382 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 2383 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2384 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 2385 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 2386 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 2387 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2388 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 2389 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2390 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 2391 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2392 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 2393 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2394 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 2395 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2396 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 2397 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2398 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 2399 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2400 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 2401 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 2402 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 2403 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 2404 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 2405 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2406 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 2407 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2408 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2409 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2410 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 2411 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2412 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 2413 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 2414 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 2415 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2416 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 2417 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2418 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 2419 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2420 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 2421 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2422 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 2423 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2424 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 2425 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2426 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 2427 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2428 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 2429 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2430 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 2431 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 2432 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 2433 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 2434 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 2435 }, 2436 .rzg2l_pins = { 2437 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2438 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 2439 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2440 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 2441 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2442 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 2443 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2444 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 2445 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2446 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 2447 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2448 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 2449 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 2450 } 2451 }; 2452 2453 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { 2454 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) }, 2455 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN | 2456 PIN_CFG_SOFT_PS)) }, 2457 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) }, 2458 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) }, 2459 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) }, 2460 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) }, 2461 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2462 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2463 PIN_CFG_IO_VMC_SD0)) }, 2464 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) }, 2465 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2466 PIN_CFG_IO_VMC_SD0)) }, 2467 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2468 PIN_CFG_IO_VMC_SD0)) }, 2469 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2470 PIN_CFG_IO_VMC_SD0)) }, 2471 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2472 PIN_CFG_IO_VMC_SD0)) }, 2473 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2474 PIN_CFG_IO_VMC_SD0)) }, 2475 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2476 PIN_CFG_IO_VMC_SD0)) }, 2477 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2478 PIN_CFG_IO_VMC_SD0)) }, 2479 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2480 PIN_CFG_IO_VMC_SD0)) }, 2481 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) }, 2482 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2483 PIN_CFG_IO_VMC_SD1)) }, 2484 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2485 PIN_CFG_IO_VMC_SD1)) }, 2486 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2487 PIN_CFG_IO_VMC_SD1)) }, 2488 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2489 PIN_CFG_IO_VMC_SD1)) }, 2490 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN | 2491 PIN_CFG_IO_VMC_SD1)) }, 2492 }; 2493 2494 static const struct { 2495 struct rzg2l_dedicated_configs common[77]; 2496 struct rzg2l_dedicated_configs pcie1[1]; 2497 } rzv2h_dedicated_pins = { 2498 .common = { 2499 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) }, 2500 { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2501 PIN_CFG_IEN)) }, 2502 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2503 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2504 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2505 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2506 PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2507 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2508 PIN_CFG_PUPD)) }, 2509 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2510 PIN_CFG_PUPD)) }, 2511 { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2512 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2513 { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2514 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2515 { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2516 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2517 { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2518 PIN_CFG_PUPD)) }, 2519 { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2520 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2521 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) }, 2522 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) }, 2523 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) }, 2524 { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2525 PIN_CFG_PUPD)) }, 2526 { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2527 PIN_CFG_PUPD)) }, 2528 { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2529 PIN_CFG_PUPD)) }, 2530 { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2531 PIN_CFG_PUPD)) }, 2532 { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2533 PIN_CFG_PUPD)) }, 2534 { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2535 PIN_CFG_PUPD)) }, 2536 { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2537 PIN_CFG_PUPD)) }, 2538 { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2539 PIN_CFG_PUPD)) }, 2540 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2541 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2542 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2543 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2544 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2545 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2546 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2547 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2548 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2549 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2550 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2551 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2552 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2553 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2554 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2555 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2556 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2557 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2558 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2559 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2560 { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2561 { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2562 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2563 { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2564 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2565 { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2566 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2567 { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2568 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2569 { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2570 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2571 { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | 2572 PIN_CFG_SR)) }, 2573 { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2574 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2575 { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2576 PIN_CFG_PUPD)) }, 2577 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) }, 2578 { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | 2579 PIN_CFG_SR | 2580 PIN_CFG_PUPD)) }, 2581 { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2582 PIN_CFG_PUPD)) }, 2583 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) }, 2584 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) }, 2585 { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2586 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2587 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) }, 2588 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) }, 2589 { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2590 PIN_CFG_PUPD)) }, 2591 { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2592 PIN_CFG_PUPD)) }, 2593 { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2594 PIN_CFG_PUPD)) }, 2595 { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2596 PIN_CFG_PUPD)) }, 2597 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) }, 2598 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) }, 2599 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) }, 2600 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) }, 2601 { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2602 PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2603 { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2604 PIN_CFG_PUPD)) }, 2605 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) }, 2606 { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | 2607 PIN_CFG_SR | 2608 PIN_CFG_PUPD)) }, 2609 { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2610 PIN_CFG_PUPD)) }, 2611 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) }, 2612 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) }, 2613 { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2614 PIN_CFG_PUPD | PIN_CFG_OEN)) }, 2615 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) }, 2616 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) }, 2617 { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2618 PIN_CFG_PUPD)) }, 2619 { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2620 PIN_CFG_PUPD)) }, 2621 { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2622 PIN_CFG_PUPD)) }, 2623 { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | 2624 PIN_CFG_PUPD)) }, 2625 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) }, 2626 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, 2627 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, 2628 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, 2629 }, 2630 .pcie1 = { 2631 { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | 2632 PIN_CFG_SR)) }, 2633 }, 2634 }; 2635 2636 static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { 2637 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, 2638 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2639 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, 2640 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) }, 2641 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, 2642 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, 2643 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 2644 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) }, 2645 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, 2646 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2647 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2648 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2649 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, 2650 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2651 { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3, 2652 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2653 { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4, 2654 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) }, 2655 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, 2656 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2657 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, 2658 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2659 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, 2660 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2661 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, 2662 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2663 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, 2664 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2665 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, 2666 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2667 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, 2668 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2669 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, 2670 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2671 }; 2672 2673 static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = { 2674 { "WDTOVF_N", RZG2L_SINGLE_PIN_PACK(0x5, 0, 2675 (PIN_CFG_IOLH_A | PIN_CFG_WDTOVF_N_POC)) }, 2676 { "SCIF0_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, 2677 (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, 2678 { "SCIF0_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 2679 (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, 2680 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) }, 2681 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, 2682 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2683 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) }, 2684 { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5, 2685 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2686 { "SD0_DAT0", RZG2L_SINGLE_PIN_PACK(0x0a, 0, 2687 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2688 { "SD0_DAT1", RZG2L_SINGLE_PIN_PACK(0x0a, 1, 2689 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2690 { "SD0_DAT2", RZG2L_SINGLE_PIN_PACK(0x0a, 2, 2691 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2692 { "SD0_DAT3", RZG2L_SINGLE_PIN_PACK(0x0a, 3, 2693 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2694 { "SD0_DAT4", RZG2L_SINGLE_PIN_PACK(0x0a, 4, 2695 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2696 { "SD0_DAT5", RZG2L_SINGLE_PIN_PACK(0x0a, 5, 2697 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2698 { "SD0_DAT6", RZG2L_SINGLE_PIN_PACK(0x0a, 6, 2699 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2700 { "SD0_DAT7", RZG2L_SINGLE_PIN_PACK(0x0a, 7, 2701 (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, 2702 }; 2703 2704 static const u32 r9a08g046_clone_channel_data[] = { 2705 /* I2C ch2 Bit:0 Value:0 PFC:4 */ 2706 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(7, 6), 0, 0, BIT(4)), 2707 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 2), 0, 0, BIT(4)), 2708 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(1, 0), 0, 0, BIT(4)), 2709 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)), 2710 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)), 2711 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 0, 0, BIT(4)), 2712 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)), 2713 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)), 2714 /* I2C ch2 Bit:0 Value:1 PFC:4 */ 2715 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)), 2716 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(2, 1), 0, 1, BIT(4)), 2717 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)), 2718 /* I2C ch3 Bit:1 Value:0 PFC:4 */ 2719 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 1, 0, BIT(4)), 2720 /* I2C ch3 Bit:1 Value:1 PFC:4 */ 2721 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P2, GENMASK(1, 0), 1, 1, BIT(4)), 2722 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6) | GENMASK(3, 2), 1, 1, BIT(4)), 2723 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 3) | BIT(0), 1, 1, BIT(4)), 2724 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6), 1, 1, BIT(4)), 2725 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(3, 2), 1, 1, BIT(4)), 2726 /* SCIF ch3 Bit:4 Value:0 PFC:{6,7} */ 2727 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(6, 4), 4, 0, BIT(6)), 2728 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 3), 4, 0, BIT(7)), 2729 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(4, 2), 4, 0, BIT(7)), 2730 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 3), 4, 0, BIT(7)), 2731 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(2, 0), 4, 0, BIT(7)), 2732 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 1), 4, 0, BIT(7)), 2733 /* SCIF ch3 Bit:4 Value:1 PFC:7 */ 2734 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(2, 0), 4, 1, BIT(7)), 2735 /* SCIF ch4 Bit:5 Value:0 PFC:7 */ 2736 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(2, 0), 5, 0, BIT(7)), 2737 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 5), 5, 0, BIT(7)), 2738 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 5, 0, BIT(7)), 2739 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, BIT(0), 5, 0, BIT(7)), 2740 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(5, 3), 5, 0, BIT(7)), 2741 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(6, 4), 5, 0, BIT(7)), 2742 /* SCIF ch4 Bit:5 Value:1 PFC:7 */ 2743 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 3), 5, 1, BIT(7)), 2744 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 2), 5, 1, BIT(7)), 2745 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 5), 5, 1, BIT(7)), 2746 /* SCIF ch5 Bit:6 Value:0 PFC:7 */ 2747 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, BIT(7), 6, 0, BIT(7)), 2748 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 6, 0, BIT(7)), 2749 /* SCIF ch5 Bit:6 Value:1 PFC:7 */ 2750 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6), 6, 1, BIT(7)), 2751 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(1, 0), 6, 1, BIT(7)), 2752 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(4, 2) | BIT(0), 6, 1, BIT(7)), 2753 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(2, 0), 6, 1, BIT(7)), 2754 /* RSPI ch1 Bit:8 Value:0 PFC:2 */ 2755 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 0), 8, 0, BIT(2)), 2756 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 5), 8, 0, BIT(2)), 2757 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 8, 0, BIT(2)), 2758 /* RSPI ch1 Bit:8 Value:1 PFC:2 */ 2759 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 0), 8, 1, BIT(2)), 2760 /* RSPI ch2 Bit:9 Value:0 PFC:2 */ 2761 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 4), 9, 0, BIT(2)), 2762 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(2, 0), 9, 0, BIT(2)), 2763 /* RSPI ch2 Bit:9 Value:1 PFC:2 */ 2764 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 0), 9, 1, BIT(2)), 2765 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, BIT(7), 9, 1, BIT(2)), 2766 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 0), 9, 1, BIT(2)), 2767 /* RSCI ch1 Bit:12 Value:0 PFC:{5,6} shared pins based on RSCI mode */ 2768 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(3, 0), 12, 0, GENMASK(6, 5)), 2769 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(3, 0), 12, 0, GENMASK(6, 5)), 2770 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 12, 0, GENMASK(6, 5)), 2771 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 12, 0, GENMASK(6, 5)), 2772 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 4), 12, 0, GENMASK(6, 5)), 2773 /* RSCI ch1 Bit:12 Value:1 PFC:{5,6} shared pins based on RSCI mode */ 2774 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(3, 0), 12, 1, GENMASK(6, 5)), 2775 /* RSCI ch2 Bit:13 Value:0 PFC:{5,6} shared pins based on RSCI mode */ 2776 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), 2777 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), 2778 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 4), 13, 0, GENMASK(6, 5)), 2779 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), 2780 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), 2781 /* RSCI ch2 Bit:13 Value:1 PFC:{5,6} shared pins based on RSCI mode */ 2782 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 4), 13, 1, GENMASK(6, 5)), 2783 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | BIT(0), 13, 1, GENMASK(6, 5)), 2784 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6) | GENMASK(1, 0), 13, 1, GENMASK(6, 5)), 2785 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(1, 0), 13, 1, GENMASK(6, 5)), 2786 /* RSCI ch3 Bit:14 Value:0 PFC:{5,6} shared pins based on RSCI mode */ 2787 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6), 14, 0, GENMASK(6, 5)), 2788 RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 14, 0, GENMASK(6, 5)), 2789 /* RSCI ch3 Bit:14 Value:1 PFC:{5,6} shared pins based on RSCI mode */ 2790 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 1), 14, 1, GENMASK(6, 5)), 2791 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(5, 2), 14, 1, GENMASK(6, 5)), 2792 RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 2), 14, 1, GENMASK(6, 5)), 2793 }; 2794 2795 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) 2796 { 2797 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; 2798 const struct rzg2l_pinctrl_data *data = pctrl->data; 2799 u64 *pin_data = pin_desc->drv_data; 2800 unsigned int gpioint; 2801 unsigned int i; 2802 u32 port, bit; 2803 2804 if (*pin_data & PIN_CFG_NOGPIO_INT) 2805 return -EINVAL; 2806 2807 port = virq / 8; 2808 bit = virq % 8; 2809 2810 if (port >= data->n_ports || 2811 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) 2812 return -EINVAL; 2813 2814 gpioint = bit; 2815 for (i = 0; i < port; i++) 2816 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); 2817 2818 return gpioint; 2819 } 2820 2821 static void __rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, 2822 unsigned int hwirq, bool enable) 2823 { 2824 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; 2825 u64 *pin_data = pin_desc->drv_data; 2826 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2827 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 2828 void __iomem *addr; 2829 2830 addr = pctrl->base + ISEL(off); 2831 if (bit >= 4) { 2832 bit -= 4; 2833 addr += 4; 2834 } 2835 2836 if (enable) 2837 writel(readl(addr) | BIT(bit * 8), addr); 2838 else 2839 writel(readl(addr) & ~BIT(bit * 8), addr); 2840 } 2841 2842 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, 2843 unsigned int hwirq, bool enable) 2844 { 2845 unsigned long flags; 2846 2847 raw_spin_lock_irqsave(&pctrl->lock, flags); 2848 __rzg2l_gpio_irq_endisable(pctrl, hwirq, enable); 2849 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 2850 } 2851 2852 static void rzg2l_gpio_irq_disable(struct irq_data *d) 2853 { 2854 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2855 unsigned int hwirq = irqd_to_hwirq(d); 2856 2857 irq_chip_disable_parent(d); 2858 gpiochip_disable_irq(gc, hwirq); 2859 } 2860 2861 static void __rzg2l_gpio_irq_enable(struct irq_data *d, bool lock) 2862 { 2863 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 2864 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2865 unsigned int hwirq = irqd_to_hwirq(d); 2866 2867 gpiochip_enable_irq(gc, hwirq); 2868 if (lock) 2869 rzg2l_gpio_irq_endisable(pctrl, hwirq, true); 2870 else 2871 __rzg2l_gpio_irq_endisable(pctrl, hwirq, true); 2872 irq_chip_enable_parent(d); 2873 } 2874 2875 static void rzg2l_gpio_irq_enable(struct irq_data *d) 2876 { 2877 __rzg2l_gpio_irq_enable(d, true); 2878 } 2879 2880 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 2881 { 2882 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2883 2884 seq_puts(p, dev_name(gc->parent)); 2885 } 2886 2887 static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) 2888 { 2889 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 2890 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 2891 int ret; 2892 2893 /* It should not happen. */ 2894 if (!data->parent_data) 2895 return -EOPNOTSUPP; 2896 2897 ret = irq_chip_set_wake_parent(data, on); 2898 if (ret) 2899 return ret; 2900 2901 if (on) 2902 atomic_inc(&pctrl->wakeup_path); 2903 else 2904 atomic_dec(&pctrl->wakeup_path); 2905 2906 return 0; 2907 } 2908 2909 static const struct irq_chip rzg2l_gpio_irqchip = { 2910 .name = "rzg2l-gpio", 2911 .irq_disable = rzg2l_gpio_irq_disable, 2912 .irq_enable = rzg2l_gpio_irq_enable, 2913 .irq_mask = irq_chip_mask_parent, 2914 .irq_unmask = irq_chip_unmask_parent, 2915 .irq_set_type = irq_chip_set_type_parent, 2916 .irq_eoi = irq_chip_eoi_parent, 2917 .irq_print_chip = rzg2l_gpio_irq_print_chip, 2918 .irq_set_affinity = irq_chip_set_affinity_parent, 2919 .irq_set_wake = rzg2l_gpio_irq_set_wake, 2920 .flags = IRQCHIP_IMMUTABLE, 2921 GPIOCHIP_IRQ_RESOURCE_HELPERS, 2922 }; 2923 2924 static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) 2925 { 2926 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 2927 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; 2928 u64 *pin_data = pin_desc->drv_data; 2929 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); 2930 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 2931 u8 reg8; 2932 int ret; 2933 2934 reg8 = readb(pctrl->base + PMC(off)); 2935 if (reg8 & BIT(bit)) { 2936 ret = rzg2l_gpio_request(chip, offset); 2937 if (ret) 2938 return ret; 2939 } 2940 2941 return rzg2l_gpio_direction_input(chip, offset); 2942 } 2943 2944 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 2945 unsigned int child, 2946 unsigned int child_type, 2947 unsigned int *parent, 2948 unsigned int *parent_type) 2949 { 2950 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 2951 unsigned long flags; 2952 int gpioint, irq; 2953 int ret; 2954 2955 gpioint = rzg2l_gpio_get_gpioint(child, pctrl); 2956 if (gpioint < 0) 2957 return gpioint; 2958 2959 ret = rzg2l_gpio_interrupt_input_mode(gc, child); 2960 if (ret) 2961 return ret; 2962 2963 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 2964 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 2965 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 2966 if (irq < 0) { 2967 ret = -ENOSPC; 2968 goto err; 2969 } 2970 2971 rzg2l_gpio_irq_endisable(pctrl, child, true); 2972 pctrl->hwirq[irq] = child; 2973 irq += pctrl->data->hwcfg->tint_start_index; 2974 2975 /* All these interrupts are level high in the CPU */ 2976 *parent_type = IRQ_TYPE_LEVEL_HIGH; 2977 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 2978 return 0; 2979 2980 err: 2981 rzg2l_gpio_free(gc, child); 2982 return ret; 2983 } 2984 2985 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) 2986 { 2987 struct irq_domain *domain = pctrl->gpio_chip.irq.domain; 2988 2989 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 2990 struct irq_data *data; 2991 unsigned long flags; 2992 unsigned int virq; 2993 int ret; 2994 2995 if (!pctrl->hwirq[i]) 2996 continue; 2997 2998 virq = irq_find_mapping(domain, pctrl->hwirq[i]); 2999 if (!virq) { 3000 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", 3001 pctrl->hwirq[i]); 3002 continue; 3003 } 3004 3005 data = irq_domain_get_irq_data(domain, virq); 3006 if (!data) { 3007 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); 3008 continue; 3009 } 3010 3011 /* 3012 * This has to be atomically executed to protect against a concurrent 3013 * interrupt. 3014 */ 3015 raw_spin_lock_irqsave(&pctrl->lock, flags); 3016 ret = irq_chip_set_type_parent(data, irqd_get_trigger_type(data)); 3017 if (!ret && !irqd_irq_disabled(data)) 3018 __rzg2l_gpio_irq_enable(data, false); 3019 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 3020 3021 if (ret) 3022 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq); 3023 } 3024 } 3025 3026 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 3027 unsigned int nr_irqs) 3028 { 3029 struct irq_data *d; 3030 3031 d = irq_domain_get_irq_data(domain, virq); 3032 if (d) { 3033 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 3034 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 3035 irq_hw_number_t hwirq = irqd_to_hwirq(d); 3036 unsigned long flags; 3037 unsigned int i; 3038 3039 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 3040 if (pctrl->hwirq[i] == hwirq) { 3041 rzg2l_gpio_irq_endisable(pctrl, hwirq, false); 3042 rzg2l_gpio_free(gc, hwirq); 3043 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 3044 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 3045 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 3046 pctrl->hwirq[i] = 0; 3047 break; 3048 } 3049 } 3050 } 3051 irq_domain_free_irqs_common(domain, virq, nr_irqs); 3052 } 3053 3054 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 3055 unsigned long *valid_mask, 3056 unsigned int ngpios) 3057 { 3058 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 3059 struct gpio_chip *chip = &pctrl->gpio_chip; 3060 unsigned int offset; 3061 3062 /* Forbid unused lines to be mapped as IRQs */ 3063 for (offset = 0; offset < chip->ngpio; offset++) { 3064 u32 port, bit; 3065 3066 port = offset / 8; 3067 bit = offset % 8; 3068 3069 if (port >= pctrl->data->n_ports || 3070 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, 3071 pctrl->data->port_pin_configs[port]))) 3072 clear_bit(offset, valid_mask); 3073 } 3074 } 3075 3076 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) 3077 { 3078 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 3079 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache; 3080 3081 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); 3082 if (!cache) 3083 return -ENOMEM; 3084 3085 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); 3086 if (!dedicated_cache) 3087 return -ENOMEM; 3088 3089 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); 3090 if (!cache->p) 3091 return -ENOMEM; 3092 3093 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); 3094 if (!cache->pm) 3095 return -ENOMEM; 3096 3097 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); 3098 if (!cache->pmc) 3099 return -ENOMEM; 3100 3101 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); 3102 if (!cache->pfc) 3103 return -ENOMEM; 3104 3105 for (u8 i = 0; i < 2; i++) { 3106 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; 3107 3108 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), 3109 GFP_KERNEL); 3110 if (!cache->iolh[i]) 3111 return -ENOMEM; 3112 3113 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), 3114 GFP_KERNEL); 3115 if (!cache->ien[i]) 3116 return -ENOMEM; 3117 3118 cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]), 3119 GFP_KERNEL); 3120 if (!cache->pupd[i]) 3121 return -ENOMEM; 3122 3123 cache->smt[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt[i]), 3124 GFP_KERNEL); 3125 if (!cache->smt[i]) 3126 return -ENOMEM; 3127 3128 cache->sr[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr[i]), 3129 GFP_KERNEL); 3130 if (!cache->sr[i]) 3131 return -ENOMEM; 3132 3133 cache->nod[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->nod[i]), 3134 GFP_KERNEL); 3135 if (!cache->nod[i]) 3136 return -ENOMEM; 3137 3138 /* Allocate dedicated cache. */ 3139 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 3140 sizeof(*dedicated_cache->iolh[i]), 3141 GFP_KERNEL); 3142 if (!dedicated_cache->iolh[i]) 3143 return -ENOMEM; 3144 3145 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 3146 sizeof(*dedicated_cache->ien[i]), 3147 GFP_KERNEL); 3148 if (!dedicated_cache->ien[i]) 3149 return -ENOMEM; 3150 3151 dedicated_cache->sr[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 3152 sizeof(*dedicated_cache->sr[i]), 3153 GFP_KERNEL); 3154 if (!dedicated_cache->sr[i]) 3155 return -ENOMEM; 3156 3157 dedicated_cache->nod[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 3158 sizeof(*dedicated_cache->nod[i]), 3159 GFP_KERNEL); 3160 if (!dedicated_cache->nod[i]) 3161 return -ENOMEM; 3162 3163 dedicated_cache->pupd[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, 3164 sizeof(*dedicated_cache->pupd[i]), 3165 GFP_KERNEL); 3166 if (!dedicated_cache->pupd[i]) 3167 return -ENOMEM; 3168 } 3169 3170 pctrl->cache = cache; 3171 pctrl->dedicated_cache = dedicated_cache; 3172 3173 return 0; 3174 } 3175 3176 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 3177 { 3178 struct device_node *np = pctrl->dev->of_node; 3179 struct gpio_chip *chip = &pctrl->gpio_chip; 3180 const char *name = dev_name(pctrl->dev); 3181 struct irq_domain *parent_domain; 3182 struct of_phandle_args of_args; 3183 struct device_node *parent_np; 3184 struct gpio_irq_chip *girq; 3185 int ret; 3186 3187 parent_np = of_irq_find_parent(np); 3188 if (!parent_np) 3189 return -ENXIO; 3190 3191 parent_domain = irq_find_host(parent_np); 3192 of_node_put(parent_np); 3193 if (!parent_domain) 3194 return -EPROBE_DEFER; 3195 3196 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 3197 if (ret) 3198 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n"); 3199 3200 of_node_put(of_args.np); 3201 3202 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 3203 of_args.args[2] != pctrl->data->n_port_pins) 3204 return dev_err_probe(pctrl->dev, -EINVAL, 3205 "gpio-ranges does not match selected SOC\n"); 3206 3207 chip->names = pctrl->data->port_pins; 3208 chip->request = rzg2l_gpio_request; 3209 chip->free = rzg2l_gpio_free; 3210 chip->get_direction = rzg2l_gpio_get_direction; 3211 chip->direction_input = rzg2l_gpio_direction_input; 3212 chip->direction_output = rzg2l_gpio_direction_output; 3213 chip->get = rzg2l_gpio_get; 3214 chip->set = rzg2l_gpio_set; 3215 chip->set_config = gpiochip_generic_config; 3216 chip->label = name; 3217 chip->parent = pctrl->dev; 3218 chip->owner = THIS_MODULE; 3219 chip->base = -1; 3220 chip->ngpio = of_args.args[2]; 3221 3222 girq = &chip->irq; 3223 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 3224 girq->fwnode = dev_fwnode(pctrl->dev); 3225 girq->parent_domain = parent_domain; 3226 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 3227 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell; 3228 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 3229 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 3230 3231 pctrl->gpio_range.id = 0; 3232 pctrl->gpio_range.pin_base = 0; 3233 pctrl->gpio_range.base = 0; 3234 pctrl->gpio_range.npins = chip->ngpio; 3235 pctrl->gpio_range.name = chip->label; 3236 pctrl->gpio_range.gc = chip; 3237 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 3238 if (ret) 3239 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n"); 3240 3241 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 3242 3243 return 0; 3244 } 3245 3246 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 3247 { 3248 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 3249 struct pinctrl_pin_desc *pins; 3250 unsigned int i, j; 3251 u64 *pin_data; 3252 int ret; 3253 3254 pctrl->desc.name = DRV_NAME; 3255 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 3256 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 3257 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 3258 pctrl->desc.confops = &rzg2l_pinctrl_confops; 3259 pctrl->desc.owner = THIS_MODULE; 3260 if (pctrl->data->num_custom_params) { 3261 pctrl->desc.num_custom_params = pctrl->data->num_custom_params; 3262 pctrl->desc.custom_params = pctrl->data->custom_params; 3263 #ifdef CONFIG_DEBUG_FS 3264 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items; 3265 #endif 3266 } 3267 3268 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 3269 if (!pins) 3270 return -ENOMEM; 3271 3272 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 3273 sizeof(*pin_data), GFP_KERNEL); 3274 if (!pin_data) 3275 return -ENOMEM; 3276 3277 pctrl->pins = pins; 3278 pctrl->desc.pins = pins; 3279 3280 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 3281 pins[i].number = i; 3282 pins[i].name = pctrl->data->port_pins[i]; 3283 if (i && !(i % RZG2L_PINS_PER_PORT)) 3284 j++; 3285 pin_data[i] = pctrl->data->port_pin_configs[j]; 3286 if (pin_data[i] & RZG2L_VARIABLE_CFG) 3287 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, 3288 pin_data[i], 3289 j, 3290 i % RZG2L_PINS_PER_PORT); 3291 pins[i].drv_data = &pin_data[i]; 3292 } 3293 3294 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 3295 unsigned int index = pctrl->data->n_port_pins + i; 3296 3297 pins[index].number = index; 3298 pins[index].name = pctrl->data->dedicated_pins[i].name; 3299 pin_data[index] = pctrl->data->dedicated_pins[i].config; 3300 pins[index].drv_data = &pin_data[index]; 3301 } 3302 3303 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings), 3304 GFP_KERNEL); 3305 if (!pctrl->settings) 3306 return -ENOMEM; 3307 3308 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) { 3309 if (pin_data[i] & PIN_CFG_SOFT_PS) { 3310 pctrl->settings[i].power_source = 3300; 3311 } else { 3312 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]); 3313 if (ret < 0) 3314 continue; 3315 pctrl->settings[i].power_source = ret; 3316 } 3317 } 3318 3319 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); 3320 if (ret) 3321 return ret; 3322 3323 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 3324 &pctrl->pctl); 3325 if (ret) 3326 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n"); 3327 3328 ret = pinctrl_enable(pctrl->pctl); 3329 if (ret) 3330 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n"); 3331 3332 ret = rzg2l_gpio_register(pctrl); 3333 if (ret) 3334 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n"); 3335 3336 return 0; 3337 } 3338 3339 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 3340 { 3341 struct rzg2l_pinctrl *pctrl; 3342 int ret; 3343 3344 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > 3345 ARRAY_SIZE(rzg2l_gpio_names)); 3346 3347 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 3348 ARRAY_SIZE(rzg2l_gpio_names)); 3349 3350 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > 3351 ARRAY_SIZE(rzg2l_gpio_names)); 3352 3353 BUILD_BUG_ON(ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT > 3354 ARRAY_SIZE(rzg3l_gpio_names)); 3355 3356 BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > 3357 ARRAY_SIZE(rzg3e_gpio_names)); 3358 3359 BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT > 3360 ARRAY_SIZE(rzv2h_gpio_names)); 3361 3362 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 3363 if (!pctrl) 3364 return -ENOMEM; 3365 3366 pctrl->dev = &pdev->dev; 3367 3368 pctrl->data = of_device_get_match_data(&pdev->dev); 3369 if (!pctrl->data) 3370 return -EINVAL; 3371 3372 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 3373 if (IS_ERR(pctrl->base)) 3374 return PTR_ERR(pctrl->base); 3375 3376 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); 3377 if (IS_ERR(pctrl->clk)) { 3378 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), 3379 "failed to enable GPIO clk\n"); 3380 } 3381 3382 if (pctrl->data->clone_channel_data) { 3383 struct device_node *np = pctrl->dev->of_node; 3384 3385 pctrl->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,clonech", 3386 1, &pctrl->clone_offset); 3387 if (IS_ERR(pctrl->syscon)) 3388 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->syscon), 3389 "Failed to parse renesas,clonech\n"); 3390 } 3391 3392 raw_spin_lock_init(&pctrl->lock); 3393 spin_lock_init(&pctrl->bitmap_lock); 3394 mutex_init(&pctrl->mutex); 3395 atomic_set(&pctrl->wakeup_path, 0); 3396 3397 platform_set_drvdata(pdev, pctrl); 3398 3399 ret = rzg2l_pinctrl_register(pctrl); 3400 if (ret) 3401 return ret; 3402 3403 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 3404 return 0; 3405 } 3406 3407 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 3408 { 3409 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 3410 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3411 3412 for (u32 port = 0; port < nports; port++) { 3413 bool has_iolh, has_ien, has_pupd, has_smt, has_sr, has_nod; 3414 u32 off, caps; 3415 u8 pincnt; 3416 u64 cfg; 3417 3418 cfg = pctrl->data->port_pin_configs[port]; 3419 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 3420 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); 3421 3422 if (cfg & RZG2L_VARIABLE_CFG) { 3423 unsigned int pin = port * RZG2L_PINS_PER_PORT; 3424 3425 for (unsigned int i = 0; i < RZG2L_PINS_PER_PORT; i++) 3426 cfg |= *(u64 *)pctrl->desc.pins[pin + i].drv_data; 3427 } 3428 3429 caps = FIELD_GET(PIN_CFG_MASK, cfg); 3430 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); 3431 has_ien = !!(caps & PIN_CFG_IEN); 3432 has_pupd = !!(caps & PIN_CFG_PUPD); 3433 has_smt = !!(caps & PIN_CFG_SMT); 3434 has_sr = !!(caps & PIN_CFG_SR); 3435 has_nod = !!(caps & PIN_CFG_NOD); 3436 3437 if (suspend) 3438 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); 3439 3440 /* 3441 * Now cache the registers or set them in the order suggested by 3442 * HW manual (section "Operation for GPIO Function"). 3443 */ 3444 if (suspend) 3445 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); 3446 else 3447 pctrl->data->pmc_writeb(pctrl, cache->pmc[port], PMC(off)); 3448 3449 if (has_iolh) { 3450 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 3451 cache->iolh[0][port]); 3452 if (pincnt >= 4) { 3453 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, 3454 cache->iolh[1][port]); 3455 } 3456 } 3457 3458 if (has_pupd) { 3459 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), 3460 cache->pupd[0][port]); 3461 if (pincnt >= 4) { 3462 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off) + 4, 3463 cache->pupd[1][port]); 3464 } 3465 } 3466 3467 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); 3468 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); 3469 3470 if (has_ien) { 3471 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 3472 cache->ien[0][port]); 3473 if (pincnt >= 4) { 3474 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, 3475 cache->ien[1][port]); 3476 } 3477 } 3478 3479 if (has_smt) { 3480 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), 3481 cache->smt[0][port]); 3482 if (pincnt >= 4) { 3483 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off) + 4, 3484 cache->smt[1][port]); 3485 } 3486 } 3487 3488 if (has_sr) { 3489 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), 3490 cache->sr[0][port]); 3491 if (pincnt >= 4) { 3492 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off) + 4, 3493 cache->sr[1][port]); 3494 } 3495 } 3496 3497 if (has_nod) { 3498 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), 3499 cache->nod[0][port]); 3500 if (pincnt >= 4) { 3501 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off) + 4, 3502 cache->nod[1][port]); 3503 } 3504 } 3505 } 3506 } 3507 3508 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) 3509 { 3510 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; 3511 u32 caps; 3512 u32 i; 3513 3514 /* 3515 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same 3516 * port offset are close together. 3517 */ 3518 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { 3519 bool has_iolh, has_ien, has_sr, has_nod, has_pupd; 3520 u32 off, next_off = 0; 3521 u64 cfg, next_cfg; 3522 u8 pincnt; 3523 3524 cfg = pctrl->data->dedicated_pins[i].config; 3525 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 3526 if (i + 1 < pctrl->data->n_dedicated_pins) { 3527 next_cfg = pctrl->data->dedicated_pins[i + 1].config; 3528 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg); 3529 } 3530 3531 if (off == next_off) { 3532 /* Gather caps of all port pins. */ 3533 caps |= FIELD_GET(PIN_CFG_MASK, cfg); 3534 continue; 3535 } 3536 3537 /* And apply them in a single shot. */ 3538 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | 3539 PIN_CFG_IOLH_C | PIN_CFG_IOLH_RZV2H)); 3540 has_ien = !!(caps & PIN_CFG_IEN); 3541 has_sr = !!(caps & PIN_CFG_SR); 3542 has_nod = !!(caps & PIN_CFG_NOD); 3543 has_pupd = !!(caps & PIN_CFG_PUPD); 3544 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); 3545 3546 if (has_iolh) { 3547 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), 3548 cache->iolh[0][i]); 3549 } 3550 if (has_ien) { 3551 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), 3552 cache->ien[0][i]); 3553 } 3554 if (has_sr) { 3555 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), 3556 cache->sr[0][i]); 3557 } 3558 if (has_nod) { 3559 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), 3560 cache->nod[0][i]); 3561 } 3562 if (has_pupd) { 3563 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), 3564 cache->pupd[0][i]); 3565 } 3566 3567 if (pincnt >= 4) { 3568 if (has_iolh) { 3569 RZG2L_PCTRL_REG_ACCESS32(suspend, 3570 pctrl->base + IOLH(off) + 4, 3571 cache->iolh[1][i]); 3572 } 3573 if (has_ien) { 3574 RZG2L_PCTRL_REG_ACCESS32(suspend, 3575 pctrl->base + IEN(off) + 4, 3576 cache->ien[1][i]); 3577 } 3578 if (has_sr) { 3579 RZG2L_PCTRL_REG_ACCESS32(suspend, 3580 pctrl->base + SR(off) + 4, 3581 cache->sr[1][i]); 3582 } 3583 if (has_nod) { 3584 RZG2L_PCTRL_REG_ACCESS32(suspend, 3585 pctrl->base + NOD(off) + 4, 3586 cache->nod[1][i]); 3587 } 3588 if (has_pupd) { 3589 RZG2L_PCTRL_REG_ACCESS32(suspend, 3590 pctrl->base + PUPD(off) + 4, 3591 cache->pupd[1][i]); 3592 } 3593 } 3594 caps = 0; 3595 } 3596 } 3597 3598 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) 3599 { 3600 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; 3601 unsigned long flags; 3602 3603 raw_spin_lock_irqsave(&pctrl->lock, flags); 3604 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false); 3605 3606 /* Restore port registers. */ 3607 for (u32 port = 0; port < nports; port++) { 3608 unsigned long pinmap; 3609 u8 pmc = 0, max_pin; 3610 u32 off, pfc = 0; 3611 u64 cfg; 3612 u16 pm; 3613 u8 pin; 3614 3615 cfg = pctrl->data->port_pin_configs[port]; 3616 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); 3617 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); 3618 max_pin = fls(pinmap); 3619 3620 pm = readw(pctrl->base + PM(off)); 3621 for_each_set_bit(pin, &pinmap, max_pin) { 3622 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3623 u32 pfc_val, pfc_mask; 3624 3625 /* Nothing to do if PFC was not configured before. */ 3626 if (!(cache->pmc[port] & BIT(pin))) 3627 continue; 3628 3629 pfc_val = readl(pctrl->base + PFC(off)); 3630 pfc_mask = PFC_MASK << (pin * 4); 3631 /* Nothing to do if reset value of the pin is same as cached value */ 3632 if ((cache->pfc[port] & pfc_mask) == (pfc_val & pfc_mask)) 3633 continue; 3634 3635 /* Set pin to 'Non-use (Hi-Z input protection)' */ 3636 pm &= ~(PM_MASK << (pin * 2)); 3637 writew(pm, pctrl->base + PM(off)); 3638 3639 /* Temporarily switch to GPIO mode with PMC register */ 3640 pmc &= ~BIT(pin); 3641 writeb(pmc, pctrl->base + PMC(off)); 3642 3643 /* Select Pin function mode. */ 3644 pfc &= ~pfc_mask; 3645 pfc |= (cache->pfc[port] & pfc_mask); 3646 writel(pfc, pctrl->base + PFC(off)); 3647 3648 /* Switch to Peripheral pin function. */ 3649 pmc |= BIT(pin); 3650 writeb(pmc, pctrl->base + PMC(off)); 3651 } 3652 } 3653 3654 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true); 3655 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 3656 } 3657 3658 static int rzg2l_pinctrl_suspend_noirq(struct device *dev) 3659 { 3660 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 3661 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 3662 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 3663 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3664 3665 rzg2l_pinctrl_pm_setup_regs(pctrl, true); 3666 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); 3667 3668 for (u8 i = 0; i < 2; i++) { 3669 if (regs->sd_ch) 3670 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); 3671 if (regs->eth_poc) 3672 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); 3673 } 3674 3675 if (regs->qspi) 3676 cache->qspi = readb(pctrl->base + regs->qspi); 3677 cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen); 3678 if (regs->other_poc) 3679 cache->other_poc = readb(pctrl->base + regs->other_poc); 3680 3681 if (pctrl->syscon) { 3682 int ret; 3683 3684 ret = regmap_read(pctrl->syscon, pctrl->clone_offset, &cache->clone); 3685 if (ret) 3686 return ret; 3687 } 3688 3689 if (!atomic_read(&pctrl->wakeup_path)) 3690 clk_disable_unprepare(pctrl->clk); 3691 else 3692 device_set_wakeup_path(dev); 3693 3694 return 0; 3695 } 3696 3697 static int rzg2l_pinctrl_resume_noirq(struct device *dev) 3698 { 3699 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); 3700 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; 3701 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 3702 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3703 unsigned long flags; 3704 int ret; 3705 3706 if (pctrl->syscon) { 3707 ret = regmap_write(pctrl->syscon, pctrl->clone_offset, cache->clone); 3708 if (ret) 3709 return ret; 3710 } 3711 3712 if (!atomic_read(&pctrl->wakeup_path)) { 3713 ret = clk_prepare_enable(pctrl->clk); 3714 if (ret) 3715 return ret; 3716 } 3717 3718 if (regs->qspi) 3719 writeb(cache->qspi, pctrl->base + regs->qspi); 3720 if (regs->other_poc) 3721 writeb(cache->other_poc, pctrl->base + regs->other_poc); 3722 3723 raw_spin_lock_irqsave(&pctrl->lock, flags); 3724 rzg2l_oen_write_with_pwpr(pctrl, cache->oen); 3725 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 3726 3727 for (u8 i = 0; i < 2; i++) { 3728 if (regs->sd_ch) 3729 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); 3730 if (regs->eth_poc) 3731 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); 3732 } 3733 3734 rzg2l_pinctrl_pm_setup_pfc(pctrl); 3735 rzg2l_pinctrl_pm_setup_regs(pctrl, false); 3736 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); 3737 rzg2l_gpio_irq_restore(pctrl); 3738 3739 return 0; 3740 } 3741 3742 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3743 { 3744 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3745 3746 if (lock) { 3747 /* Set the PWPR register to be write-protected */ 3748 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3749 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ 3750 } else { 3751 /* Set the PWPR register to allow PFC register to write */ 3752 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ 3753 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ 3754 } 3755 } 3756 3757 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock) 3758 { 3759 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 3760 u8 pwpr; 3761 3762 if (lock) { 3763 /* Set the PWPR register to be write-protected */ 3764 pwpr = readb(pctrl->base + regs->pwpr); 3765 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr); 3766 } else { 3767 /* Set the PWPR register to allow PFC and PMC register to write */ 3768 pwpr = readb(pctrl->base + regs->pwpr); 3769 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr); 3770 } 3771 } 3772 3773 static const struct rzg2l_hwcfg rzg2l_hwcfg = { 3774 .regs = { 3775 .pwpr = 0x3014, 3776 .sd_ch = 0x3000, 3777 .eth_poc = 0x300c, 3778 .oen = 0x3018, 3779 .qspi = QSPI, 3780 }, 3781 .iolh_groupa_ua = { 3782 /* 3v3 power source */ 3783 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000, 3784 }, 3785 .iolh_groupb_oi = { 100, 66, 50, 33, }, 3786 .tint_start_index = 9, 3787 .oen_max_pin = 0, 3788 }; 3789 3790 static const struct rzg2l_hwcfg rzg3l_hwcfg = { 3791 .regs = { 3792 .pwpr = 0x3000, 3793 .sd_ch = 0x3004, 3794 .eth_poc = 0x3010, 3795 .oen = 0x3018, 3796 .other_poc = OTHER_POC, 3797 }, 3798 .iolh_groupa_ua = { 3799 /* 1v8 power source */ 3800 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, 3801 /* 3v3 power source */ 3802 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, 3803 }, 3804 .iolh_groupb_ua = { 3805 /* 1v8 power source */ 3806 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, 3807 /* 3v3 power source */ 3808 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, 3809 }, 3810 .iolh_groupc_ua = { 3811 /* 1v8 power source */ 3812 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, 3813 /* 2v5 source */ 3814 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, 3815 /* 3v3 power source */ 3816 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, 3817 }, 3818 .tint_start_index = 17, 3819 .drive_strength_ua = true, 3820 .func_base = 0, 3821 .oen_max_pin = 1, /* Pin 1 of P{B,E}1_ISO is the maximum OEN pin. */ 3822 }; 3823 3824 static const struct rzg2l_hwcfg rzg3s_hwcfg = { 3825 .regs = { 3826 .pwpr = 0x3000, 3827 .sd_ch = 0x3004, 3828 .eth_poc = 0x3010, 3829 .oen = 0x3018, 3830 }, 3831 .iolh_groupa_ua = { 3832 /* 1v8 power source */ 3833 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, 3834 /* 3v3 power source */ 3835 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, 3836 }, 3837 .iolh_groupb_ua = { 3838 /* 1v8 power source */ 3839 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, 3840 /* 3v3 power source */ 3841 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, 3842 }, 3843 .iolh_groupc_ua = { 3844 /* 1v8 power source */ 3845 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, 3846 /* 2v5 source */ 3847 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, 3848 /* 3v3 power source */ 3849 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, 3850 }, 3851 .tint_start_index = 9, 3852 .drive_strength_ua = true, 3853 .func_base = 1, 3854 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ 3855 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ 3856 }; 3857 3858 static const struct rzg2l_hwcfg rzv2h_hwcfg = { 3859 .regs = { 3860 .pwpr = 0x3c04, 3861 .oen = 0x3c40, 3862 }, 3863 .tint_start_index = 17, 3864 .oen_pwpr_lock = true, 3865 }; 3866 3867 static struct rzg2l_pinctrl_data r9a07g043_data = { 3868 .port_pins = rzg2l_gpio_names, 3869 .port_pin_configs = r9a07g043_gpio_configs, 3870 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 3871 .dedicated_pins = rzg2l_dedicated_pins.common, 3872 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 3873 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 3874 .hwcfg = &rzg2l_hwcfg, 3875 #ifdef CONFIG_RISCV 3876 .variable_pin_cfg = r9a07g043f_variable_pin_cfg, 3877 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), 3878 #endif 3879 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3880 .pmc_writeb = &rzg2l_pmc_writeb, 3881 .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3882 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3883 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3884 }; 3885 3886 static struct rzg2l_pinctrl_data r9a07g044_data = { 3887 .port_pins = rzg2l_gpio_names, 3888 .port_pin_configs = r9a07g044_gpio_configs, 3889 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs), 3890 .dedicated_pins = rzg2l_dedicated_pins.common, 3891 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT, 3892 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 3893 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 3894 .hwcfg = &rzg2l_hwcfg, 3895 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3896 .pmc_writeb = &rzg2l_pmc_writeb, 3897 .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3898 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3899 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3900 }; 3901 3902 static struct rzg2l_pinctrl_data r9a08g045_data = { 3903 .port_pins = rzg2l_gpio_names, 3904 .port_pin_configs = r9a08g045_gpio_configs, 3905 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs), 3906 .dedicated_pins = rzg3s_dedicated_pins, 3907 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT, 3908 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins), 3909 .hwcfg = &rzg3s_hwcfg, 3910 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3911 .pmc_writeb = &rzg2l_pmc_writeb, 3912 .pin_to_oen_bit = &rzg3s_pin_to_oen_bit, 3913 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3914 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3915 }; 3916 3917 static struct rzg2l_pinctrl_data r9a08g046_data = { 3918 .port_pins = rzg3l_gpio_names, 3919 .port_pin_configs = r9a08g046_gpio_configs, 3920 .n_ports = ARRAY_SIZE(r9a08g046_gpio_configs), 3921 .variable_pin_cfg = r9a08g046_variable_pin_cfg, 3922 .n_variable_pin_cfg = ARRAY_SIZE(r9a08g046_variable_pin_cfg), 3923 .dedicated_pins = rzg3l_dedicated_pins, 3924 .n_port_pins = ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT, 3925 .n_dedicated_pins = ARRAY_SIZE(rzg3l_dedicated_pins), 3926 .clone_channel_data = r9a08g046_clone_channel_data, 3927 .n_clone_channel_data = ARRAY_SIZE(r9a08g046_clone_channel_data), 3928 .hwcfg = &rzg3l_hwcfg, 3929 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, 3930 .pmc_writeb = &rzg2l_pmc_writeb, 3931 .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, 3932 .hw_to_bias_param = &rzg2l_hw_to_bias_param, 3933 .bias_param_to_hw = &rzg2l_bias_param_to_hw, 3934 }; 3935 3936 static struct rzg2l_pinctrl_data r9a09g047_data = { 3937 .port_pins = rzg3e_gpio_names, 3938 .port_pin_configs = r9a09g047_gpio_configs, 3939 .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs), 3940 .dedicated_pins = rzg3e_dedicated_pins, 3941 .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT, 3942 .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins), 3943 .hwcfg = &rzv2h_hwcfg, 3944 .variable_pin_cfg = r9a09g047_variable_pin_cfg, 3945 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg), 3946 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3947 .custom_params = renesas_rzv2h_custom_bindings, 3948 #ifdef CONFIG_DEBUG_FS 3949 .custom_conf_items = renesas_rzv2h_conf_items, 3950 #endif 3951 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3952 .pmc_writeb = &rzv2h_pmc_writeb, 3953 .pin_to_oen_bit = &rzg3e_pin_to_oen_bit, 3954 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3955 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3956 }; 3957 3958 static struct rzg2l_pinctrl_data r9a09g056_data = { 3959 .port_pins = rzv2h_gpio_names, 3960 .port_pin_configs = r9a09g057_gpio_configs, 3961 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), 3962 .dedicated_pins = rzv2h_dedicated_pins.common, 3963 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, 3964 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common), 3965 .hwcfg = &rzv2h_hwcfg, 3966 .variable_pin_cfg = r9a09g057_variable_pin_cfg, 3967 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), 3968 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3969 .custom_params = renesas_rzv2h_custom_bindings, 3970 #ifdef CONFIG_DEBUG_FS 3971 .custom_conf_items = renesas_rzv2h_conf_items, 3972 #endif 3973 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3974 .pmc_writeb = &rzv2h_pmc_writeb, 3975 .pin_to_oen_bit = &rzv2h_pin_to_oen_bit, 3976 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 3977 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 3978 }; 3979 3980 static struct rzg2l_pinctrl_data r9a09g057_data = { 3981 .port_pins = rzv2h_gpio_names, 3982 .port_pin_configs = r9a09g057_gpio_configs, 3983 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs), 3984 .dedicated_pins = rzv2h_dedicated_pins.common, 3985 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, 3986 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) + 3987 ARRAY_SIZE(rzv2h_dedicated_pins.pcie1), 3988 .hwcfg = &rzv2h_hwcfg, 3989 .variable_pin_cfg = r9a09g057_variable_pin_cfg, 3990 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg), 3991 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings), 3992 .custom_params = renesas_rzv2h_custom_bindings, 3993 #ifdef CONFIG_DEBUG_FS 3994 .custom_conf_items = renesas_rzv2h_conf_items, 3995 #endif 3996 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock, 3997 .pmc_writeb = &rzv2h_pmc_writeb, 3998 .pin_to_oen_bit = &rzv2h_pin_to_oen_bit, 3999 .hw_to_bias_param = &rzv2h_hw_to_bias_param, 4000 .bias_param_to_hw = &rzv2h_bias_param_to_hw, 4001 }; 4002 4003 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 4004 { 4005 .compatible = "renesas,r9a07g043-pinctrl", 4006 .data = &r9a07g043_data, 4007 }, 4008 { 4009 .compatible = "renesas,r9a07g044-pinctrl", 4010 .data = &r9a07g044_data, 4011 }, 4012 { 4013 .compatible = "renesas,r9a08g045-pinctrl", 4014 .data = &r9a08g045_data, 4015 }, 4016 { 4017 .compatible = "renesas,r9a08g046-pinctrl", 4018 .data = &r9a08g046_data, 4019 }, 4020 { 4021 .compatible = "renesas,r9a09g047-pinctrl", 4022 .data = &r9a09g047_data, 4023 }, 4024 { 4025 .compatible = "renesas,r9a09g056-pinctrl", 4026 .data = &r9a09g056_data, 4027 }, 4028 { 4029 .compatible = "renesas,r9a09g057-pinctrl", 4030 .data = &r9a09g057_data, 4031 }, 4032 { /* sentinel */ } 4033 }; 4034 4035 static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = { 4036 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq) 4037 }; 4038 4039 static struct platform_driver rzg2l_pinctrl_driver = { 4040 .driver = { 4041 .name = DRV_NAME, 4042 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 4043 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops), 4044 .suppress_bind_attrs = true, 4045 }, 4046 .probe = rzg2l_pinctrl_probe, 4047 }; 4048 4049 static int __init rzg2l_pinctrl_init(void) 4050 { 4051 return platform_driver_register(&rzg2l_pinctrl_driver); 4052 } 4053 core_initcall(rzg2l_pinctrl_init); 4054 4055 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 4056 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 4057