1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Driver for Microsemi VSC85xx PHYs 4 * 5 * Copyright (c) 2016 Microsemi Corporation 6 */ 7 8 #ifndef _MSCC_PHY_H_ 9 #define _MSCC_PHY_H_ 10 11 #if IS_ENABLED(CONFIG_MACSEC) 12 #include "mscc_macsec.h" 13 #endif 14 15 enum rgmii_clock_delay { 16 RGMII_CLK_DELAY_0_2_NS = 0, 17 RGMII_CLK_DELAY_0_8_NS = 1, 18 RGMII_CLK_DELAY_1_1_NS = 2, 19 RGMII_CLK_DELAY_1_7_NS = 3, 20 RGMII_CLK_DELAY_2_0_NS = 4, 21 RGMII_CLK_DELAY_2_3_NS = 5, 22 RGMII_CLK_DELAY_2_6_NS = 6, 23 RGMII_CLK_DELAY_3_4_NS = 7 24 }; 25 26 /* Microsemi VSC85xx PHY registers */ 27 /* IEEE 802. Std Registers */ 28 #define MSCC_PHY_BYPASS_CONTROL 18 29 #define DISABLE_HP_AUTO_MDIX_MASK 0x0080 30 #define DISABLE_PAIR_SWAP_CORR_MASK 0x0020 31 #define DISABLE_POLARITY_CORR_MASK 0x0010 32 #define PARALLEL_DET_IGNORE_ADVERTISED 0x0008 33 34 #define MSCC_PHY_EXT_CNTL_STATUS 22 35 #define SMI_BROADCAST_WR_EN 0x0001 36 37 #define MSCC_PHY_ERR_RX_CNT 19 38 #define MSCC_PHY_ERR_FALSE_CARRIER_CNT 20 39 #define MSCC_PHY_ERR_LINK_DISCONNECT_CNT 21 40 #define ERR_CNT_MASK GENMASK(7, 0) 41 42 #define MSCC_PHY_EXT_PHY_CNTL_1 23 43 #define MAC_IF_SELECTION_MASK 0x1800 44 #define MAC_IF_SELECTION_GMII 0 45 #define MAC_IF_SELECTION_RMII 1 46 #define MAC_IF_SELECTION_RGMII 2 47 #define MAC_IF_SELECTION_POS 11 48 #define VSC8584_MAC_IF_SELECTION_MASK 0x1000 49 #define VSC8584_MAC_IF_SELECTION_SGMII 0 50 #define VSC8584_MAC_IF_SELECTION_1000BASEX 1 51 #define VSC8584_MAC_IF_SELECTION_POS 12 52 #define FAR_END_LOOPBACK_MODE_MASK 0x0008 53 #define MEDIA_OP_MODE_MASK 0x0700 54 #define MEDIA_OP_MODE_COPPER 0 55 #define MEDIA_OP_MODE_SERDES 1 56 #define MEDIA_OP_MODE_1000BASEX 2 57 #define MEDIA_OP_MODE_100BASEFX 3 58 #define MEDIA_OP_MODE_AMS_COPPER_SERDES 5 59 #define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6 60 #define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7 61 #define MEDIA_OP_MODE_POS 8 62 63 #define MSCC_PHY_EXT_PHY_CNTL_2 24 64 65 #define MII_VSC85XX_INT_MASK 25 66 #define MII_VSC85XX_INT_MASK_MDINT BIT(15) 67 #define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13) 68 #define MII_VSC85XX_INT_MASK_WOL BIT(6) 69 #define MII_VSC85XX_INT_MASK_EXT BIT(5) 70 #define MII_VSC85XX_INT_STATUS 26 71 72 #define MII_VSC85XX_INT_MASK_MASK (MII_VSC85XX_INT_MASK_MDINT | \ 73 MII_VSC85XX_INT_MASK_LINK_CHG | \ 74 MII_VSC85XX_INT_MASK_EXT) 75 76 #define MSCC_PHY_WOL_MAC_CONTROL 27 77 #define EDGE_RATE_CNTL_POS 5 78 #define EDGE_RATE_CNTL_MASK 0x00E0 79 80 #define MSCC_PHY_DEV_AUX_CNTL 28 81 #define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000 82 83 #define MSCC_PHY_LED_MODE_SEL 29 84 #define LED_MODE_SEL_POS(x) ((x) * 4) 85 #define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x)) 86 #define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x)) 87 88 #define MSCC_PHY_LED_BEHAVIOR 30 89 #define LED_COMBINE_DIS_MASK(x) BIT(x) 90 #define LED_COMBINE_DIS(x, dis) (((dis) ? 1 : 0) << (x)) 91 92 #define MSCC_EXT_PAGE_CSR_CNTL_17 17 93 #define MSCC_EXT_PAGE_CSR_CNTL_18 18 94 95 #define MSCC_EXT_PAGE_CSR_CNTL_19 19 96 #define MSCC_PHY_CSR_CNTL_19_REG_ADDR(x) (x) 97 #define MSCC_PHY_CSR_CNTL_19_TARGET(x) ((x) << 12) 98 #define MSCC_PHY_CSR_CNTL_19_READ BIT(14) 99 #define MSCC_PHY_CSR_CNTL_19_CMD BIT(15) 100 101 #define MSCC_EXT_PAGE_CSR_CNTL_20 20 102 #define MSCC_PHY_CSR_CNTL_20_TARGET(x) (x) 103 104 #define PHY_MCB_TARGET 0x07 105 #define PHY_MCB_S6G_WRITE BIT(31) 106 #define PHY_MCB_S6G_READ BIT(30) 107 108 #define PHY_S6G_PLL5G_CFG0 0x06 109 #define PHY_S6G_PLL5G_CFG2 0x08 110 #define PHY_S6G_LCPLL_CFG 0x11 111 #define PHY_S6G_PLL_CFG 0x2b 112 #define PHY_S6G_COMMON_CFG 0x2c 113 #define PHY_S6G_GPC_CFG 0x2e 114 #define PHY_S6G_MISC_CFG 0x3b 115 #define PHY_MCB_S6G_CFG 0x3f 116 #define PHY_S6G_DFT_CFG2 0x3e 117 #define PHY_S6G_PLL_STATUS 0x31 118 #define PHY_S6G_IB_STATUS0 0x2f 119 120 #define PHY_S6G_SYS_RST_POS 31 121 #define PHY_S6G_ENA_LANE_POS 18 122 #define PHY_S6G_ENA_LOOP_POS 8 123 #define PHY_S6G_QRATE_POS 6 124 #define PHY_S6G_IF_MODE_POS 4 125 #define PHY_S6G_PLL_ENA_OFFS_POS 21 126 #define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8 127 #define PHY_S6G_PLL_FSM_ENA_POS 7 128 129 #define PHY_S6G_CFG2_FSM_DIS 1 130 #define PHY_S6G_CFG2_FSM_CLK_BP 23 131 132 #define MSCC_EXT_PAGE_ACCESS 31 133 #define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */ 134 #define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */ 135 #define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */ 136 #define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */ 137 #define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */ 138 #define MSCC_PHY_PAGE_CSR_CNTL MSCC_PHY_PAGE_EXTENDED_4 139 #define MSCC_PHY_PAGE_MACSEC MSCC_PHY_PAGE_EXTENDED_4 140 /* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs 141 * in the same package. 142 */ 143 #define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */ 144 #define MSCC_PHY_PAGE_1588 0x1588 /* PTP (1588) */ 145 #define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */ 146 #define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */ 147 #define MSCC_PHY_GPIO_CONTROL_2 14 148 149 #define MSCC_PHY_COMA_MODE 0x2000 /* input(1) / output(0) */ 150 #define MSCC_PHY_COMA_OUTPUT 0x1000 /* value to output */ 151 152 /* Extended Page 1 Registers */ 153 #define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT 18 154 #define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0) 155 156 #define MSCC_PHY_EXT_MODE_CNTL 19 157 #define FORCE_MDI_CROSSOVER_MASK 0x000C 158 #define FORCE_MDI_CROSSOVER_MDIX 0x000C 159 #define FORCE_MDI_CROSSOVER_MDI 0x0008 160 161 #define MSCC_PHY_ACTIPHY_CNTL 20 162 #define PHY_ADDR_REVERSED 0x0200 163 #define DOWNSHIFT_CNTL_MASK 0x001C 164 #define DOWNSHIFT_EN 0x0010 165 #define DOWNSHIFT_CNTL_POS 2 166 167 #define MSCC_PHY_EXT_PHY_CNTL_4 23 168 #define PHY_CNTL_4_ADDR_POS 11 169 170 #define MSCC_PHY_VERIPHY_CNTL_2 25 171 172 #define MSCC_PHY_VERIPHY_CNTL_3 26 173 174 /* Extended Page 2 Registers */ 175 #define MSCC_PHY_CU_PMD_TX_CNTL 16 176 177 /* RGMII setting controls at address 18E2, for VSC8572 and similar */ 178 #define VSC8572_RGMII_CNTL 18 179 #define VSC8572_RGMII_RX_DELAY_MASK 0x000E 180 #define VSC8572_RGMII_TX_DELAY_MASK 0x0070 181 182 /* RGMII controls at address 20E2, for VSC8502 and similar */ 183 #define VSC8502_RGMII_CNTL 20 184 #define VSC8502_RGMII_RX_DELAY_MASK 0x0070 185 #define VSC8502_RGMII_TX_DELAY_MASK 0x0007 186 #define VSC8502_RGMII_RX_CLK_DISABLE 0x0800 187 188 #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21 189 #define MSCC_PHY_WOL_MID_MAC_ADDR 22 190 #define MSCC_PHY_WOL_UPPER_MAC_ADDR 23 191 #define MSCC_PHY_WOL_LOWER_PASSWD 24 192 #define MSCC_PHY_WOL_MID_PASSWD 25 193 #define MSCC_PHY_WOL_UPPER_PASSWD 26 194 195 #define MSCC_PHY_WOL_MAC_CONTROL 27 196 #define SECURE_ON_ENABLE 0x8000 197 #define SECURE_ON_PASSWD_LEN_4 0x4000 198 199 #define MSCC_PHY_EXTENDED_INT 28 200 #define MSCC_PHY_EXTENDED_INT_MS_EGR BIT(9) 201 202 /* Extended Page 3 Registers */ 203 #define MSCC_PHY_SERDES_PCS_CTRL 16 204 #define MSCC_PHY_SERDES_ANEG BIT(7) 205 206 #define MSCC_PHY_SERDES_TX_VALID_CNT 21 207 #define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22 208 #define MSCC_PHY_SERDES_RX_VALID_CNT 28 209 #define MSCC_PHY_SERDES_RX_CRC_ERR_CNT 29 210 211 /* Extended page GPIO Registers */ 212 #define MSCC_DW8051_CNTL_STATUS 0 213 #define MICRO_NSOFT_RESET 0x8000 214 #define RUN_FROM_INT_ROM 0x4000 215 #define AUTOINC_ADDR 0x2000 216 #define PATCH_RAM_CLK 0x1000 217 #define MICRO_PATCH_EN 0x0080 218 #define DW8051_CLK_EN 0x0010 219 #define MICRO_CLK_EN 0x0008 220 #define MICRO_CLK_DIVIDE(x) ((x) >> 1) 221 #define MSCC_DW8051_VLD_MASK 0xf1ff 222 223 /* x Address in range 1-4 */ 224 #define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1) 225 #define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2) 226 #define MSCC_INT_MEM_ADDR 11 227 228 #define MSCC_INT_MEM_CNTL 12 229 #define READ_SFR 0x6000 230 #define READ_PRAM 0x4000 231 #define READ_ROM 0x2000 232 #define READ_RAM 0x0000 233 #define INT_MEM_WRITE_EN 0x1000 234 #define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1)) 235 #define INT_MEM_DATA_M 0x00ff 236 #define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x)) 237 238 #define MSCC_PHY_PROC_CMD 18 239 #define PROC_CMD_NCOMPLETED 0x8000 240 #define PROC_CMD_FAILED 0x4000 241 #define PROC_CMD_SGMII_PORT(x) ((x) << 8) 242 #define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4) 243 #define PROC_CMD_QSGMII_PORT 0x0c00 244 #define PROC_CMD_RST_CONF_PORT 0x0080 245 #define PROC_CMD_RECONF_PORT 0x0000 246 #define PROC_CMD_READ_MOD_WRITE_PORT 0x0040 247 #define PROC_CMD_WRITE 0x0040 248 #define PROC_CMD_READ 0x0000 249 #define PROC_CMD_FIBER_DISABLE 0x0020 250 #define PROC_CMD_FIBER_100BASE_FX 0x0010 251 #define PROC_CMD_FIBER_1000BASE_X 0x0000 252 #define PROC_CMD_SGMII_MAC 0x0030 253 #define PROC_CMD_QSGMII_MAC 0x0020 254 #define PROC_CMD_NO_MAC_CONF 0x0000 255 #define PROC_CMD_1588_DEFAULT_INIT 0x0010 256 #define PROC_CMD_NOP 0x000f 257 #define PROC_CMD_PHY_INIT 0x000a 258 #define PROC_CMD_CRC16 0x0008 259 #define PROC_CMD_FIBER_MEDIA_CONF 0x0001 260 #define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000 261 #define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500 262 263 #define MSCC_PHY_MAC_CFG_FASTLINK 19 264 #define MAC_CFG_MASK 0xc000 265 #define MAC_CFG_SGMII 0x0000 266 #define MAC_CFG_QSGMII 0x4000 267 #define MAC_CFG_RGMII 0x8000 268 269 /* Test page Registers */ 270 #define MSCC_PHY_TEST_PAGE_5 5 271 #define MSCC_PHY_TEST_PAGE_8 8 272 #define TR_CLK_DISABLE 0x8000 273 #define MSCC_PHY_TEST_PAGE_9 9 274 #define MSCC_PHY_TEST_PAGE_20 20 275 #define MSCC_PHY_TEST_PAGE_24 24 276 277 /* Token ring page Registers */ 278 #define MSCC_PHY_TR_CNTL 16 279 #define TR_WRITE 0x8000 280 #define TR_ADDR(x) (0x7fff & (x)) 281 #define MSCC_PHY_TR_LSB 17 282 #define MSCC_PHY_TR_MSB 18 283 284 /* Microsemi PHY ID's 285 * Code assumes lowest nibble is 0 286 */ 287 #define PHY_ID_VSC8501 0x00070530 288 #define PHY_ID_VSC8502 0x00070630 289 #define PHY_ID_VSC8504 0x000704c0 290 #define PHY_ID_VSC8514 0x00070670 291 #define PHY_ID_VSC8530 0x00070560 292 #define PHY_ID_VSC8531 0x00070570 293 #define PHY_ID_VSC8540 0x00070760 294 #define PHY_ID_VSC8541 0x00070770 295 #define PHY_ID_VSC8552 0x000704e0 296 #define PHY_ID_VSC856X 0x000707e1 297 #define PHY_ID_VSC8572 0x000704d0 298 #define PHY_ID_VSC8574 0x000704a0 299 #define PHY_ID_VSC8575 0x000707d1 300 #define PHY_ID_VSC8582 0x000707b1 301 #define PHY_ID_VSC8584 0x000707c1 302 #define PHY_VENDOR_MSCC 0x00070400 303 304 #define MSCC_VDDMAC_1500 1500 305 #define MSCC_VDDMAC_1800 1800 306 #define MSCC_VDDMAC_2500 2500 307 #define MSCC_VDDMAC_3300 3300 308 309 #define DOWNSHIFT_COUNT_MAX 5 310 311 #define MAX_LEDS 4 312 313 #define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \ 314 BIT(VSC8531_LINK_1000_ACTIVITY) | \ 315 BIT(VSC8531_LINK_100_ACTIVITY) | \ 316 BIT(VSC8531_LINK_10_ACTIVITY) | \ 317 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \ 318 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \ 319 BIT(VSC8531_LINK_10_100_ACTIVITY) | \ 320 BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \ 321 BIT(VSC8531_DUPLEX_COLLISION) | \ 322 BIT(VSC8531_COLLISION) | \ 323 BIT(VSC8531_ACTIVITY) | \ 324 BIT(VSC8584_100FX_1000X_ACTIVITY) | \ 325 BIT(VSC8531_AUTONEG_FAULT) | \ 326 BIT(VSC8531_SERIAL_MODE) | \ 327 BIT(VSC8531_FORCE_LED_OFF) | \ 328 BIT(VSC8531_FORCE_LED_ON)) 329 330 #define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \ 331 BIT(VSC8531_LINK_1000_ACTIVITY) | \ 332 BIT(VSC8531_LINK_100_ACTIVITY) | \ 333 BIT(VSC8531_LINK_10_ACTIVITY) | \ 334 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \ 335 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \ 336 BIT(VSC8531_LINK_10_100_ACTIVITY) | \ 337 BIT(VSC8531_DUPLEX_COLLISION) | \ 338 BIT(VSC8531_COLLISION) | \ 339 BIT(VSC8531_ACTIVITY) | \ 340 BIT(VSC8531_AUTONEG_FAULT) | \ 341 BIT(VSC8531_SERIAL_MODE) | \ 342 BIT(VSC8531_FORCE_LED_OFF) | \ 343 BIT(VSC8531_FORCE_LED_ON)) 344 345 #define MSCC_VSC8584_REVB_INT8051_FW "microchip/mscc_vsc8584_revb_int8051_fb48.bin" 346 #define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800 347 #define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48 348 349 #define MSCC_VSC8574_REVB_INT8051_FW "microchip/mscc_vsc8574_revb_int8051_29e8.bin" 350 #define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000 351 #define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8 352 353 #define VSC8584_REVB 0x0001 354 #define MSCC_DEV_REV_MASK GENMASK(3, 0) 355 356 #define MSCC_ROM_TRAP_SERDES_6G_CFG 0x1E48 357 #define MSCC_RAM_TRAP_SERDES_6G_CFG 0x1E4F 358 #define PATCH_VEC_ZERO_EN 0x0100 359 360 struct reg_val { 361 u16 reg; 362 u32 val; 363 }; 364 365 struct vsc85xx_hw_stat { 366 const char *string; 367 u8 reg; 368 u16 page; 369 u16 mask; 370 }; 371 372 struct vsc8531_skb_cb { 373 u32 ns; 374 }; 375 376 #define VSC8531_SKB_CB(skb) \ 377 ((struct vsc8531_skb_cb *)((skb)->cb)) 378 379 struct vsc8531_private { 380 int rate_magic; 381 u16 supp_led_modes; 382 u32 leds_mode[MAX_LEDS]; 383 u8 nleds; 384 const struct vsc85xx_hw_stat *hw_stats; 385 u64 *stats; 386 int nstats; 387 /* PHY address within the package. */ 388 u8 addr; 389 /* For multiple port PHYs; the MDIO address of the base PHY in the 390 * package. 391 */ 392 unsigned int base_addr; 393 394 #if IS_ENABLED(CONFIG_MACSEC) 395 /* MACsec fields: 396 * - One SecY per device (enforced at the s/w implementation level) 397 * - macsec_flows: list of h/w flows 398 * - ingr_flows: bitmap of ingress flows 399 * - egr_flows: bitmap of egress flows 400 */ 401 struct macsec_secy *secy; 402 struct list_head macsec_flows; 403 unsigned long ingr_flows; 404 unsigned long egr_flows; 405 #endif 406 407 struct mii_timestamper mii_ts; 408 409 bool input_clk_init; 410 struct vsc85xx_ptp *ptp; 411 /* LOAD/SAVE GPIO pin, used for retrieving or setting time to the PHC. */ 412 struct gpio_desc *load_save; 413 414 /* For multiple port PHYs; the MDIO address of the base PHY in the 415 * pair of two PHYs that share a 1588 engine. PHY0 and PHY2 are coupled. 416 * PHY1 and PHY3 as well. PHY0 and PHY1 are base PHYs for their 417 * respective pair. 418 */ 419 unsigned int ts_base_addr; 420 u8 ts_base_phy; 421 422 /* ts_lock: used for per-PHY timestamping operations. 423 * phc_lock: used for per-PHY PHC opertations. 424 */ 425 struct mutex ts_lock; 426 struct mutex phc_lock; 427 428 /* list of skbs that were received and need timestamp information but it 429 * didn't received it yet 430 */ 431 struct sk_buff_head rx_skbs_list; 432 }; 433 434 /* Shared structure between the PHYs of the same package. 435 * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO 436 * is shared. 437 */ 438 439 enum vsc85xx_global_phy { 440 VSC88XX_BASE_ADDR = 0, 441 }; 442 443 struct vsc85xx_shared_private { 444 struct mutex gpio_lock; 445 }; 446 447 #if IS_ENABLED(CONFIG_OF_MDIO) 448 struct vsc8531_edge_rate_table { 449 u32 vddmac; 450 u32 slowdown[8]; 451 }; 452 #endif /* CONFIG_OF_MDIO */ 453 454 enum csr_target { 455 MACRO_CTRL = 0x07, 456 }; 457 458 u32 vsc85xx_csr_read(struct phy_device *phydev, 459 enum csr_target target, u32 reg); 460 461 int vsc85xx_csr_write(struct phy_device *phydev, 462 enum csr_target target, u32 reg, u32 val); 463 464 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val); 465 int phy_base_read(struct phy_device *phydev, u32 regnum); 466 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb); 467 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb); 468 int vsc8584_cmd(struct phy_device *phydev, u16 val); 469 470 #if IS_ENABLED(CONFIG_MACSEC) 471 int vsc8584_macsec_init(struct phy_device *phydev); 472 void vsc8584_handle_macsec_interrupt(struct phy_device *phydev); 473 void vsc8584_config_macsec_intr(struct phy_device *phydev); 474 #else 475 static inline int vsc8584_macsec_init(struct phy_device *phydev) 476 { 477 return 0; 478 } 479 static inline void vsc8584_handle_macsec_interrupt(struct phy_device *phydev) 480 { 481 } 482 static inline void vsc8584_config_macsec_intr(struct phy_device *phydev) 483 { 484 } 485 #endif 486 487 #if IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING) 488 void vsc85xx_link_change_notify(struct phy_device *phydev); 489 void vsc8584_config_ts_intr(struct phy_device *phydev); 490 int vsc8584_ptp_init(struct phy_device *phydev); 491 void vsc8584_ptp_deinit(struct phy_device *phydev); 492 int vsc8584_ptp_probe_once(struct phy_device *phydev); 493 int vsc8584_ptp_probe(struct phy_device *phydev); 494 irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev); 495 #else 496 static inline void vsc85xx_link_change_notify(struct phy_device *phydev) 497 { 498 } 499 static inline void vsc8584_config_ts_intr(struct phy_device *phydev) 500 { 501 } 502 static inline int vsc8584_ptp_init(struct phy_device *phydev) 503 { 504 return 0; 505 } 506 static inline void vsc8584_ptp_deinit(struct phy_device *phydev) 507 { 508 } 509 static inline int vsc8584_ptp_probe_once(struct phy_device *phydev) 510 { 511 return 0; 512 } 513 static inline int vsc8584_ptp_probe(struct phy_device *phydev) 514 { 515 return 0; 516 } 517 static inline irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev) 518 { 519 return IRQ_NONE; 520 } 521 #endif 522 523 #endif /* _MSCC_PHY_H_ */ 524