1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * SpacemiT K1 USB 2.0 PHY driver
4 *
5 * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd
6 * Copyright (C) 2025 Ze Huang <huang.ze@linux.dev>
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/iopoll.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/usb/of.h>
15
16 #define PHY_RST_MODE_CTRL 0x04
17 #define PHY_PLL_RDY BIT(0)
18 #define PHY_CLK_CDR_EN BIT(1)
19 #define PHY_CLK_PLL_EN BIT(2)
20 #define PHY_CLK_MAC_EN BIT(3)
21 #define PHY_MAC_RSTN BIT(5)
22 #define PHY_CDR_RSTN BIT(6)
23 #define PHY_PLL_RSTN BIT(7)
24 /*
25 * hs line state sel (Bit 13):
26 * - 1 (Default): Internal HS line state is set to 01 when usb_hs_tx_en is valid.
27 * - 0: Internal HS line state is always driven by usb_hs_lstate.
28 *
29 * fs line state sel (Bit 14):
30 * - 1 (Default): FS line state is determined by the output data
31 * (usb_fs_datain/b).
32 * - 0: FS line state is always determined by the input data (dmo/dpo).
33 */
34 #define PHY_HS_LINE_TX_MODE BIT(13)
35 #define PHY_FS_LINE_TX_MODE BIT(14)
36
37 #define PHY_INIT_MODE_BITS (PHY_FS_LINE_TX_MODE | PHY_HS_LINE_TX_MODE)
38 #define PHY_CLK_ENABLE_BITS (PHY_CLK_PLL_EN | PHY_CLK_CDR_EN | \
39 PHY_CLK_MAC_EN)
40 #define PHY_DEASSERT_RST_BITS (PHY_PLL_RSTN | PHY_CDR_RSTN | \
41 PHY_MAC_RSTN)
42
43 #define PHY_TX_HOST_CTRL 0x10
44 #define PHY_HST_DISC_AUTO_CLR BIT(2) /* autoclear hs host disc when re-connect */
45
46 #define PHY_HSTXP_HW_CTRL 0x34
47 #define PHY_HSTXP_RSTN BIT(2) /* generate reset for clock hstxp */
48 #define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */
49 #define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */
50
51 #define PHY_K1_HS_HOST_DISC 0x40
52 #define PHY_K1_HS_HOST_DISC_CLR BIT(0)
53
54 #define PHY_PLL_DIV_CFG 0x98
55 #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)
56 #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)
57 #define PHY_FDIV_FRACT_20_21 BIT(12) /* fdiv_reg<21>, <20>, bit21 == bit20 */
58 /*
59 * freq_sel<1:0>
60 * if ref clk freq=24.0MHz-->freq_sel<2:0> == 3b'001, then internal divider value == 80
61 */
62 #define PHY_FDIV_FRACT_0_1 GENMASK(14, 13)
63 /*
64 * pll divider value selection
65 * 1: divider value will choose internal default value ,dependent on freq_sel<1:0>
66 * 0: divider value will be over ride by fdiv_reg<21:0>
67 */
68 #define PHY_DIV_LOCAL_EN BIT(15)
69
70 #define PHY_SEL_FREQ_24MHZ 0x01
71 #define FDIV_REG_MASK (PHY_FDIV_FRACT_20_21 | PHY_FDIV_FRACT_16_19 | \
72 PHY_FDIV_FRACT_8_15)
73 #define FDIV_REG_VAL 0x1ec4 /* 0x100 selects 24MHz, rest are default */
74
75 #define K1_USB2PHY_RESET_TIME_MS 50
76
77 struct spacemit_usb2phy {
78 struct phy *phy;
79 struct clk *clk;
80 struct regmap *regmap_base;
81 };
82
83 static const struct regmap_config phy_regmap_config = {
84 .reg_bits = 32,
85 .val_bits = 32,
86 .reg_stride = 4,
87 .max_register = 0x200,
88 };
89
spacemit_usb2phy_init(struct phy * phy)90 static int spacemit_usb2phy_init(struct phy *phy)
91 {
92 struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
93 struct regmap *map = sphy->regmap_base;
94 u32 val;
95 int ret;
96
97 ret = clk_enable(sphy->clk);
98 if (ret) {
99 dev_err(&phy->dev, "failed to enable clock\n");
100 return ret;
101 }
102
103 /*
104 * make sure the usb controller is not under reset process before
105 * any configuration
106 */
107 usleep_range(150, 200);
108
109 /* 24M ref clk */
110 val = FIELD_PREP(FDIV_REG_MASK, FDIV_REG_VAL) |
111 FIELD_PREP(PHY_FDIV_FRACT_0_1, PHY_SEL_FREQ_24MHZ) |
112 PHY_DIV_LOCAL_EN;
113 regmap_write(map, PHY_PLL_DIV_CFG, val);
114
115 ret = regmap_read_poll_timeout(map, PHY_RST_MODE_CTRL, val,
116 (val & PHY_PLL_RDY),
117 500, K1_USB2PHY_RESET_TIME_MS * 1000);
118 if (ret) {
119 dev_err(&phy->dev, "wait PLLREADY timeout\n");
120 clk_disable(sphy->clk);
121 return ret;
122 }
123
124 /* release usb2 phy internal reset and enable clock gating */
125 val = (PHY_INIT_MODE_BITS | PHY_CLK_ENABLE_BITS | PHY_DEASSERT_RST_BITS);
126 regmap_write(map, PHY_RST_MODE_CTRL, val);
127
128 val = (PHY_HSTXP_RSTN | PHY_CLK_HSTXP_EN | PHY_HSTXP_MODE);
129 regmap_write(map, PHY_HSTXP_HW_CTRL, val);
130
131 /* auto clear host disc */
132 regmap_update_bits(map, PHY_TX_HOST_CTRL, PHY_HST_DISC_AUTO_CLR,
133 PHY_HST_DISC_AUTO_CLR);
134
135 return 0;
136 }
137
spacemit_usb2phy_exit(struct phy * phy)138 static int spacemit_usb2phy_exit(struct phy *phy)
139 {
140 struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
141
142 clk_disable(sphy->clk);
143
144 return 0;
145 }
146
spacemit_usb2phy_disconnect(struct phy * phy,int port)147 static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
148 {
149 struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
150
151 regmap_update_bits(sphy->regmap_base, PHY_K1_HS_HOST_DISC,
152 PHY_K1_HS_HOST_DISC_CLR, PHY_K1_HS_HOST_DISC_CLR);
153
154 return 0;
155 }
156
157 static const struct phy_ops spacemit_usb2phy_ops = {
158 .init = spacemit_usb2phy_init,
159 .exit = spacemit_usb2phy_exit,
160 .disconnect = spacemit_usb2phy_disconnect,
161 .owner = THIS_MODULE,
162 };
163
spacemit_usb2phy_probe(struct platform_device * pdev)164 static int spacemit_usb2phy_probe(struct platform_device *pdev)
165 {
166 struct phy_provider *phy_provider;
167 struct device *dev = &pdev->dev;
168 struct spacemit_usb2phy *sphy;
169 void __iomem *base;
170
171 sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
172 if (!sphy)
173 return -ENOMEM;
174
175 sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL);
176 if (IS_ERR(sphy->clk))
177 return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n");
178
179 base = devm_platform_ioremap_resource(pdev, 0);
180 if (IS_ERR(base))
181 return PTR_ERR(base);
182
183 sphy->regmap_base = devm_regmap_init_mmio(dev, base, &phy_regmap_config);
184 if (IS_ERR(sphy->regmap_base))
185 return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n");
186
187 sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops);
188 if (IS_ERR(sphy->phy))
189 return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n");
190
191 phy_set_drvdata(sphy->phy, sphy);
192 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
193
194 return PTR_ERR_OR_ZERO(phy_provider);
195 }
196
197 static const struct of_device_id spacemit_usb2phy_dt_match[] = {
198 { .compatible = "spacemit,k1-usb2-phy", },
199 { /* sentinel */ }
200 };
201 MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match);
202
203 static struct platform_driver spacemit_usb2_phy_driver = {
204 .probe = spacemit_usb2phy_probe,
205 .driver = {
206 .name = "spacemit-usb2-phy",
207 .of_match_table = spacemit_usb2phy_dt_match,
208 },
209 };
210 module_platform_driver(spacemit_usb2_phy_driver);
211
212 MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver");
213 MODULE_LICENSE("GPL");
214