1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2021 Maxlinear Corporation
3 * Copyright (C) 2020 Intel Corporation
4 *
5 * Drivers for Maxlinear Ethernet GPY
6 *
7 */
8
9 #include <linux/module.h>
10 #include <linux/bitfield.h>
11 #include <linux/hwmon.h>
12 #include <linux/mutex.h>
13 #include <linux/phy.h>
14 #include <linux/polynomial.h>
15 #include <linux/property.h>
16 #include <linux/netdevice.h>
17
18 /* PHY ID */
19 #define PHY_ID_GPYx15B_MASK 0xFFFFFFFC
20 #define PHY_ID_GPY21xB_MASK 0xFFFFFFF9
21 #define PHY_ID_GPY2xx 0x67C9DC00
22 #define PHY_ID_GPY115B 0x67C9DF00
23 #define PHY_ID_GPY115C 0x67C9DF10
24 #define PHY_ID_GPY211B 0x67C9DE08
25 #define PHY_ID_GPY211C 0x67C9DE10
26 #define PHY_ID_GPY212B 0x67C9DE09
27 #define PHY_ID_GPY212C 0x67C9DE20
28 #define PHY_ID_GPY215B 0x67C9DF04
29 #define PHY_ID_GPY215C 0x67C9DF20
30 #define PHY_ID_GPY241B 0x67C9DE40
31 #define PHY_ID_GPY241BM 0x67C9DE80
32 #define PHY_ID_GPY245B 0x67C9DEC0
33
34 #define PHY_CTL1 0x13
35 #define PHY_CTL1_MDICD BIT(3)
36 #define PHY_CTL1_MDIAB BIT(2)
37 #define PHY_CTL1_AMDIX BIT(0)
38 #define PHY_MIISTAT 0x18 /* MII state */
39 #define PHY_IMASK 0x19 /* interrupt mask */
40 #define PHY_ISTAT 0x1A /* interrupt status */
41 #define PHY_FWV 0x1E /* firmware version */
42
43 #define PHY_MIISTAT_SPD_MASK GENMASK(2, 0)
44 #define PHY_MIISTAT_DPX BIT(3)
45 #define PHY_MIISTAT_LS BIT(10)
46
47 #define PHY_MIISTAT_SPD_10 0
48 #define PHY_MIISTAT_SPD_100 1
49 #define PHY_MIISTAT_SPD_1000 2
50 #define PHY_MIISTAT_SPD_2500 4
51
52 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
53 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
54 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
55 #define PHY_IMASK_DXMC BIT(2) /* Duplex mode change */
56 #define PHY_IMASK_LSPC BIT(1) /* Link speed change */
57 #define PHY_IMASK_LSTC BIT(0) /* Link state change */
58 #define PHY_IMASK_MASK (PHY_IMASK_LSTC | \
59 PHY_IMASK_LSPC | \
60 PHY_IMASK_DXMC | \
61 PHY_IMASK_ADSC | \
62 PHY_IMASK_ANC)
63
64 #define PHY_FWV_REL_MASK BIT(15)
65 #define PHY_FWV_MAJOR_MASK GENMASK(11, 8)
66 #define PHY_FWV_MINOR_MASK GENMASK(7, 0)
67
68 #define PHY_PMA_MGBT_POLARITY 0x82
69 #define PHY_MDI_MDI_X_MASK GENMASK(1, 0)
70 #define PHY_MDI_MDI_X_NORMAL 0x3
71 #define PHY_MDI_MDI_X_AB 0x2
72 #define PHY_MDI_MDI_X_CD 0x1
73 #define PHY_MDI_MDI_X_CROSS 0x0
74
75 /* SGMII */
76 #define VSPEC1_SGMII_CTRL 0x08
77 #define VSPEC1_SGMII_CTRL_ANEN BIT(12) /* Aneg enable */
78 #define VSPEC1_SGMII_CTRL_ANRS BIT(9) /* Restart Aneg */
79 #define VSPEC1_SGMII_ANEN_ANRS (VSPEC1_SGMII_CTRL_ANEN | \
80 VSPEC1_SGMII_CTRL_ANRS)
81
82 /* Temperature sensor */
83 #define VSPEC1_TEMP_STA 0x0E
84 #define VSPEC1_TEMP_STA_DATA GENMASK(9, 0)
85
86 /* Mailbox */
87 #define VSPEC1_MBOX_DATA 0x5
88 #define VSPEC1_MBOX_ADDRLO 0x6
89 #define VSPEC1_MBOX_CMD 0x7
90 #define VSPEC1_MBOX_CMD_ADDRHI GENMASK(7, 0)
91 #define VSPEC1_MBOX_CMD_RD (0 << 8)
92 #define VSPEC1_MBOX_CMD_READY BIT(15)
93
94 /* WoL */
95 #define VPSPEC2_WOL_CTL 0x0E06
96 #define VPSPEC2_WOL_AD01 0x0E08
97 #define VPSPEC2_WOL_AD23 0x0E09
98 #define VPSPEC2_WOL_AD45 0x0E0A
99 #define WOL_EN BIT(0)
100
101 /* Internal registers, access via mbox */
102 #define REG_GPIO0_OUT 0xd3ce00
103
104 struct gpy_priv {
105 /* serialize mailbox acesses */
106 struct mutex mbox_lock;
107
108 u8 fw_major;
109 u8 fw_minor;
110 u32 wolopts;
111
112 /* It takes 3 seconds to fully switch out of loopback mode before
113 * it can safely re-enter loopback mode. Record the time when
114 * loopback is disabled. Check and wait if necessary before loopback
115 * is enabled.
116 */
117 u64 lb_dis_to;
118 };
119
120 static const struct {
121 int major;
122 int minor;
123 } ver_need_sgmii_reaneg[] = {
124 {7, 0x6D},
125 {8, 0x6D},
126 {9, 0x73},
127 };
128
129 #if IS_ENABLED(CONFIG_HWMON)
130 /* The original translation formulae of the temperature (in degrees of Celsius)
131 * are as follows:
132 *
133 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
134 * 3.0762e-1*(N^1) + -5.2156e1
135 *
136 * where [-52.156, 137.961]C and N = [0, 1023].
137 *
138 * They must be accordingly altered to be suitable for the integer arithmetics.
139 * The technique is called 'factor redistribution', which just makes sure the
140 * multiplications and divisions are made so to have a result of the operations
141 * within the integer numbers limit. In addition we need to translate the
142 * formulae to accept millidegrees of Celsius. Here what it looks like after
143 * the alterations:
144 *
145 * T = -25761e-12*(N^4) + 97332e-9*(N^3) + -191650e-6*(N^2) +
146 * 307620e-3*(N^1) + -52156
147 *
148 * where T = [-52156, 137961]mC and N = [0, 1023].
149 */
150 static const struct polynomial poly_N_to_temp = {
151 .terms = {
152 {4, -25761, 1000, 1},
153 {3, 97332, 1000, 1},
154 {2, -191650, 1000, 1},
155 {1, 307620, 1000, 1},
156 {0, -52156, 1, 1}
157 }
158 };
159
gpy_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)160 static int gpy_hwmon_read(struct device *dev,
161 enum hwmon_sensor_types type,
162 u32 attr, int channel, long *value)
163 {
164 struct phy_device *phydev = dev_get_drvdata(dev);
165 int ret;
166
167 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_TEMP_STA);
168 if (ret < 0)
169 return ret;
170 if (!ret)
171 return -ENODATA;
172
173 *value = polynomial_calc(&poly_N_to_temp,
174 FIELD_GET(VSPEC1_TEMP_STA_DATA, ret));
175
176 return 0;
177 }
178
gpy_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)179 static umode_t gpy_hwmon_is_visible(const void *data,
180 enum hwmon_sensor_types type,
181 u32 attr, int channel)
182 {
183 return 0444;
184 }
185
186 static const struct hwmon_channel_info * const gpy_hwmon_info[] = {
187 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
188 NULL
189 };
190
191 static const struct hwmon_ops gpy_hwmon_hwmon_ops = {
192 .is_visible = gpy_hwmon_is_visible,
193 .read = gpy_hwmon_read,
194 };
195
196 static const struct hwmon_chip_info gpy_hwmon_chip_info = {
197 .ops = &gpy_hwmon_hwmon_ops,
198 .info = gpy_hwmon_info,
199 };
200
gpy_hwmon_register(struct phy_device * phydev)201 static int gpy_hwmon_register(struct phy_device *phydev)
202 {
203 struct device *dev = &phydev->mdio.dev;
204 struct device *hwmon_dev;
205 char *hwmon_name;
206
207 hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
208 if (IS_ERR(hwmon_name))
209 return PTR_ERR(hwmon_name);
210
211 hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
212 phydev,
213 &gpy_hwmon_chip_info,
214 NULL);
215
216 return PTR_ERR_OR_ZERO(hwmon_dev);
217 }
218 #else
gpy_hwmon_register(struct phy_device * phydev)219 static int gpy_hwmon_register(struct phy_device *phydev)
220 {
221 return 0;
222 }
223 #endif
224
gpy_ack_interrupt(struct phy_device * phydev)225 static int gpy_ack_interrupt(struct phy_device *phydev)
226 {
227 int ret;
228
229 /* Clear all pending interrupts */
230 ret = phy_read(phydev, PHY_ISTAT);
231 return ret < 0 ? ret : 0;
232 }
233
gpy_mbox_read(struct phy_device * phydev,u32 addr)234 static int gpy_mbox_read(struct phy_device *phydev, u32 addr)
235 {
236 struct gpy_priv *priv = phydev->priv;
237 int val, ret;
238 u16 cmd;
239
240 mutex_lock(&priv->mbox_lock);
241
242 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_ADDRLO,
243 addr);
244 if (ret)
245 goto out;
246
247 cmd = VSPEC1_MBOX_CMD_RD;
248 cmd |= FIELD_PREP(VSPEC1_MBOX_CMD_ADDRHI, addr >> 16);
249
250 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_CMD, cmd);
251 if (ret)
252 goto out;
253
254 /* The mbox read is used in the interrupt workaround. It was observed
255 * that a read might take up to 2.5ms. This is also the time for which
256 * the interrupt line is stuck low. To be on the safe side, poll the
257 * ready bit for 10ms.
258 */
259 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
260 VSPEC1_MBOX_CMD, val,
261 (val & VSPEC1_MBOX_CMD_READY),
262 500, 10000, false);
263 if (ret)
264 goto out;
265
266 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_MBOX_DATA);
267
268 out:
269 mutex_unlock(&priv->mbox_lock);
270 return ret;
271 }
272
gpy_config_init(struct phy_device * phydev)273 static int gpy_config_init(struct phy_device *phydev)
274 {
275 /* Nothing to configure. Configuration Requirement Placeholder */
276 return 0;
277 }
278
gpy21x_config_init(struct phy_device * phydev)279 static int gpy21x_config_init(struct phy_device *phydev)
280 {
281 __set_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces);
282 __set_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces);
283
284 return gpy_config_init(phydev);
285 }
286
gpy_probe(struct phy_device * phydev)287 static int gpy_probe(struct phy_device *phydev)
288 {
289 struct device *dev = &phydev->mdio.dev;
290 struct gpy_priv *priv;
291 int fw_version;
292 int ret;
293
294 if (!phydev->is_c45) {
295 ret = phy_get_c45_ids(phydev);
296 if (ret < 0)
297 return ret;
298 }
299
300 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
301 if (!priv)
302 return -ENOMEM;
303 phydev->priv = priv;
304 mutex_init(&priv->mbox_lock);
305
306 if (!device_property_present(dev, "maxlinear,use-broken-interrupts"))
307 phydev->dev_flags |= PHY_F_NO_IRQ;
308
309 fw_version = phy_read(phydev, PHY_FWV);
310 if (fw_version < 0)
311 return fw_version;
312 priv->fw_major = FIELD_GET(PHY_FWV_MAJOR_MASK, fw_version);
313 priv->fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_version);
314
315 ret = gpy_hwmon_register(phydev);
316 if (ret)
317 return ret;
318
319 /* Show GPY PHY FW version in dmesg */
320 phydev_info(phydev, "Firmware Version: %d.%d (0x%04X%s)\n",
321 priv->fw_major, priv->fw_minor, fw_version,
322 fw_version & PHY_FWV_REL_MASK ? "" : " test version");
323
324 return 0;
325 }
326
gpy_sgmii_need_reaneg(struct phy_device * phydev)327 static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
328 {
329 struct gpy_priv *priv = phydev->priv;
330 size_t i;
331
332 for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
333 if (priv->fw_major != ver_need_sgmii_reaneg[i].major)
334 continue;
335 if (priv->fw_minor < ver_need_sgmii_reaneg[i].minor)
336 return true;
337 break;
338 }
339
340 return false;
341 }
342
gpy_2500basex_chk(struct phy_device * phydev)343 static bool gpy_2500basex_chk(struct phy_device *phydev)
344 {
345 int ret;
346
347 ret = phy_read(phydev, PHY_MIISTAT);
348 if (ret < 0) {
349 phydev_err(phydev, "Error: MDIO register access failed: %d\n",
350 ret);
351 return false;
352 }
353
354 if (!(ret & PHY_MIISTAT_LS) ||
355 FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
356 return false;
357
358 phydev->speed = SPEED_2500;
359 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
360 phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
361 VSPEC1_SGMII_CTRL_ANEN, 0);
362 return true;
363 }
364
gpy_sgmii_aneg_en(struct phy_device * phydev)365 static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
366 {
367 int ret;
368
369 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
370 if (ret < 0) {
371 phydev_err(phydev, "Error: MMD register access failed: %d\n",
372 ret);
373 return true;
374 }
375
376 return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
377 }
378
gpy_config_mdix(struct phy_device * phydev,u8 ctrl)379 static int gpy_config_mdix(struct phy_device *phydev, u8 ctrl)
380 {
381 int ret;
382 u16 val;
383
384 switch (ctrl) {
385 case ETH_TP_MDI_AUTO:
386 val = PHY_CTL1_AMDIX;
387 break;
388 case ETH_TP_MDI_X:
389 val = (PHY_CTL1_MDIAB | PHY_CTL1_MDICD);
390 break;
391 case ETH_TP_MDI:
392 val = 0;
393 break;
394 default:
395 return 0;
396 }
397
398 ret = phy_modify(phydev, PHY_CTL1, PHY_CTL1_AMDIX | PHY_CTL1_MDIAB |
399 PHY_CTL1_MDICD, val);
400 if (ret < 0)
401 return ret;
402
403 return genphy_c45_restart_aneg(phydev);
404 }
405
gpy_config_aneg(struct phy_device * phydev)406 static int gpy_config_aneg(struct phy_device *phydev)
407 {
408 bool changed = false;
409 u32 adv;
410 int ret;
411
412 if (phydev->autoneg == AUTONEG_DISABLE) {
413 /* Configure half duplex with genphy_setup_forced,
414 * because genphy_c45_pma_setup_forced does not support.
415 */
416 return phydev->duplex != DUPLEX_FULL
417 ? genphy_setup_forced(phydev)
418 : genphy_c45_pma_setup_forced(phydev);
419 }
420
421 ret = gpy_config_mdix(phydev, phydev->mdix_ctrl);
422 if (ret < 0)
423 return ret;
424
425 ret = genphy_c45_an_config_aneg(phydev);
426 if (ret < 0)
427 return ret;
428 if (ret > 0)
429 changed = true;
430
431 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
432 ret = phy_modify_changed(phydev, MII_CTRL1000,
433 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
434 adv);
435 if (ret < 0)
436 return ret;
437 if (ret > 0)
438 changed = true;
439
440 ret = genphy_c45_check_and_restart_aneg(phydev, changed);
441 if (ret < 0)
442 return ret;
443
444 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
445 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
446 return 0;
447
448 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
449 * disabled.
450 */
451 if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
452 !gpy_sgmii_aneg_en(phydev))
453 return 0;
454
455 /* There is a design constraint in GPY2xx device where SGMII AN is
456 * only triggered when there is change of speed. If, PHY link
457 * partner`s speed is still same even after PHY TPI is down and up
458 * again, SGMII AN is not triggered and hence no new in-band message
459 * from GPY to MAC side SGMII.
460 * This could cause an issue during power up, when PHY is up prior to
461 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
462 * wouldn`t receive new in-band message from GPY with correct link
463 * status, speed and duplex info.
464 *
465 * 1) If PHY is already up and TPI link status is still down (such as
466 * hard reboot), TPI link status is polled for 4 seconds before
467 * retriggerring SGMII AN.
468 * 2) If PHY is already up and TPI link status is also up (such as soft
469 * reboot), polling of TPI link status is not needed and SGMII AN is
470 * immediately retriggered.
471 * 3) Other conditions such as PHY is down, speed change etc, skip
472 * retriggering SGMII AN. Note: in case of speed change, GPY FW will
473 * initiate SGMII AN.
474 */
475
476 if (phydev->state != PHY_UP)
477 return 0;
478
479 ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
480 20000, 4000000, false);
481 if (ret == -ETIMEDOUT)
482 return 0;
483 else if (ret < 0)
484 return ret;
485
486 /* Trigger SGMII AN. */
487 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
488 VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
489 }
490
gpy_update_mdix(struct phy_device * phydev)491 static int gpy_update_mdix(struct phy_device *phydev)
492 {
493 int ret;
494
495 ret = phy_read(phydev, PHY_CTL1);
496 if (ret < 0)
497 return ret;
498
499 if (ret & PHY_CTL1_AMDIX)
500 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
501 else
502 if (ret & PHY_CTL1_MDICD || ret & PHY_CTL1_MDIAB)
503 phydev->mdix_ctrl = ETH_TP_MDI_X;
504 else
505 phydev->mdix_ctrl = ETH_TP_MDI;
506
507 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PHY_PMA_MGBT_POLARITY);
508 if (ret < 0)
509 return ret;
510
511 if ((ret & PHY_MDI_MDI_X_MASK) < PHY_MDI_MDI_X_NORMAL)
512 phydev->mdix = ETH_TP_MDI_X;
513 else
514 phydev->mdix = ETH_TP_MDI;
515
516 return 0;
517 }
518
gpy_update_interface(struct phy_device * phydev)519 static int gpy_update_interface(struct phy_device *phydev)
520 {
521 int ret;
522
523 /* Interface mode is fixed for USXGMII and integrated PHY */
524 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
525 phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
526 return -EINVAL;
527
528 /* Automatically switch SERDES interface between SGMII and 2500-BaseX
529 * according to speed. Disable ANEG in 2500-BaseX mode.
530 */
531 switch (phydev->speed) {
532 case SPEED_2500:
533 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
534 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
535 VSPEC1_SGMII_CTRL_ANEN, 0);
536 if (ret < 0) {
537 phydev_err(phydev,
538 "Error: Disable of SGMII ANEG failed: %d\n",
539 ret);
540 return ret;
541 }
542 break;
543 case SPEED_1000:
544 case SPEED_100:
545 case SPEED_10:
546 phydev->interface = PHY_INTERFACE_MODE_SGMII;
547 if (gpy_sgmii_aneg_en(phydev))
548 break;
549 /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
550 * if ANEG is disabled (in 2500-BaseX mode).
551 */
552 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
553 VSPEC1_SGMII_ANEN_ANRS,
554 VSPEC1_SGMII_ANEN_ANRS);
555 if (ret < 0) {
556 phydev_err(phydev,
557 "Error: Enable of SGMII ANEG failed: %d\n",
558 ret);
559 return ret;
560 }
561 break;
562 }
563
564 if (phydev->speed == SPEED_2500 || phydev->speed == SPEED_1000) {
565 ret = genphy_read_master_slave(phydev);
566 if (ret < 0)
567 return ret;
568 }
569
570 return gpy_update_mdix(phydev);
571 }
572
gpy_read_status(struct phy_device * phydev)573 static int gpy_read_status(struct phy_device *phydev)
574 {
575 int ret;
576
577 ret = genphy_update_link(phydev);
578 if (ret)
579 return ret;
580
581 phydev->speed = SPEED_UNKNOWN;
582 phydev->duplex = DUPLEX_UNKNOWN;
583 phydev->pause = 0;
584 phydev->asym_pause = 0;
585
586 if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
587 ret = genphy_c45_read_lpa(phydev);
588 if (ret < 0)
589 return ret;
590
591 /* Read the link partner's 1G advertisement */
592 ret = phy_read(phydev, MII_STAT1000);
593 if (ret < 0)
594 return ret;
595 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
596 } else if (phydev->autoneg == AUTONEG_DISABLE) {
597 linkmode_zero(phydev->lp_advertising);
598 }
599
600 ret = phy_read(phydev, PHY_MIISTAT);
601 if (ret < 0)
602 return ret;
603
604 phydev->link = (ret & PHY_MIISTAT_LS) ? 1 : 0;
605 phydev->duplex = (ret & PHY_MIISTAT_DPX) ? DUPLEX_FULL : DUPLEX_HALF;
606 switch (FIELD_GET(PHY_MIISTAT_SPD_MASK, ret)) {
607 case PHY_MIISTAT_SPD_10:
608 phydev->speed = SPEED_10;
609 break;
610 case PHY_MIISTAT_SPD_100:
611 phydev->speed = SPEED_100;
612 break;
613 case PHY_MIISTAT_SPD_1000:
614 phydev->speed = SPEED_1000;
615 break;
616 case PHY_MIISTAT_SPD_2500:
617 phydev->speed = SPEED_2500;
618 break;
619 }
620
621 if (phydev->link) {
622 ret = gpy_update_interface(phydev);
623 if (ret < 0)
624 return ret;
625 }
626
627 return 0;
628 }
629
gpy_config_intr(struct phy_device * phydev)630 static int gpy_config_intr(struct phy_device *phydev)
631 {
632 struct gpy_priv *priv = phydev->priv;
633 u16 mask = 0;
634 int ret;
635
636 ret = gpy_ack_interrupt(phydev);
637 if (ret)
638 return ret;
639
640 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
641 mask = PHY_IMASK_MASK;
642
643 if (priv->wolopts & WAKE_MAGIC)
644 mask |= PHY_IMASK_WOL;
645
646 if (priv->wolopts & WAKE_PHY)
647 mask |= PHY_IMASK_LSTC;
648
649 return phy_write(phydev, PHY_IMASK, mask);
650 }
651
gpy_handle_interrupt(struct phy_device * phydev)652 static irqreturn_t gpy_handle_interrupt(struct phy_device *phydev)
653 {
654 int reg;
655
656 reg = phy_read(phydev, PHY_ISTAT);
657 if (reg < 0) {
658 phy_error(phydev);
659 return IRQ_NONE;
660 }
661
662 if (!(reg & PHY_IMASK_MASK))
663 return IRQ_NONE;
664
665 /* The PHY might leave the interrupt line asserted even after PHY_ISTAT
666 * is read. To avoid interrupt storms, delay the interrupt handling as
667 * long as the PHY drives the interrupt line. An internal bus read will
668 * stall as long as the interrupt line is asserted, thus just read a
669 * random register here.
670 * Because we cannot access the internal bus at all while the interrupt
671 * is driven by the PHY, there is no way to make the interrupt line
672 * unstuck (e.g. by changing the pinmux to GPIO input) during that time
673 * frame. Therefore, polling is the best we can do and won't do any more
674 * harm.
675 * It was observed that this bug happens on link state and link speed
676 * changes independent of the firmware version.
677 */
678 if (reg & (PHY_IMASK_LSTC | PHY_IMASK_LSPC)) {
679 reg = gpy_mbox_read(phydev, REG_GPIO0_OUT);
680 if (reg < 0) {
681 phy_error(phydev);
682 return IRQ_NONE;
683 }
684 }
685
686 phy_trigger_machine(phydev);
687
688 return IRQ_HANDLED;
689 }
690
gpy_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)691 static int gpy_set_wol(struct phy_device *phydev,
692 struct ethtool_wolinfo *wol)
693 {
694 struct net_device *attach_dev = phydev->attached_dev;
695 struct gpy_priv *priv = phydev->priv;
696 int ret;
697
698 if (wol->wolopts & WAKE_MAGIC) {
699 /* MAC address - Byte0:Byte1:Byte2:Byte3:Byte4:Byte5
700 * VPSPEC2_WOL_AD45 = Byte0:Byte1
701 * VPSPEC2_WOL_AD23 = Byte2:Byte3
702 * VPSPEC2_WOL_AD01 = Byte4:Byte5
703 */
704 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
705 VPSPEC2_WOL_AD45,
706 ((attach_dev->dev_addr[0] << 8) |
707 attach_dev->dev_addr[1]));
708 if (ret < 0)
709 return ret;
710
711 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
712 VPSPEC2_WOL_AD23,
713 ((attach_dev->dev_addr[2] << 8) |
714 attach_dev->dev_addr[3]));
715 if (ret < 0)
716 return ret;
717
718 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
719 VPSPEC2_WOL_AD01,
720 ((attach_dev->dev_addr[4] << 8) |
721 attach_dev->dev_addr[5]));
722 if (ret < 0)
723 return ret;
724
725 /* Enable the WOL interrupt */
726 ret = phy_write(phydev, PHY_IMASK, PHY_IMASK_WOL);
727 if (ret < 0)
728 return ret;
729
730 /* Enable magic packet matching */
731 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
732 VPSPEC2_WOL_CTL,
733 WOL_EN);
734 if (ret < 0)
735 return ret;
736
737 /* Clear the interrupt status register.
738 * Only WoL is enabled so clear all.
739 */
740 ret = phy_read(phydev, PHY_ISTAT);
741 if (ret < 0)
742 return ret;
743
744 priv->wolopts |= WAKE_MAGIC;
745 } else {
746 /* Disable magic packet matching */
747 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
748 VPSPEC2_WOL_CTL,
749 WOL_EN);
750 if (ret < 0)
751 return ret;
752
753 /* Disable the WOL interrupt */
754 ret = phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_WOL);
755 if (ret < 0)
756 return ret;
757
758 priv->wolopts &= ~WAKE_MAGIC;
759 }
760
761 if (wol->wolopts & WAKE_PHY) {
762 /* Enable the link state change interrupt */
763 ret = phy_set_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
764 if (ret < 0)
765 return ret;
766
767 /* Clear the interrupt status register */
768 ret = phy_read(phydev, PHY_ISTAT);
769 if (ret < 0)
770 return ret;
771
772 if (ret & (PHY_IMASK_MASK & ~PHY_IMASK_LSTC))
773 phy_trigger_machine(phydev);
774
775 priv->wolopts |= WAKE_PHY;
776 return 0;
777 }
778
779 priv->wolopts &= ~WAKE_PHY;
780 /* Disable the link state change interrupt */
781 return phy_clear_bits(phydev, PHY_IMASK, PHY_IMASK_LSTC);
782 }
783
gpy_get_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)784 static void gpy_get_wol(struct phy_device *phydev,
785 struct ethtool_wolinfo *wol)
786 {
787 struct gpy_priv *priv = phydev->priv;
788
789 wol->supported = WAKE_MAGIC | WAKE_PHY;
790 wol->wolopts = priv->wolopts;
791 }
792
gpy_loopback(struct phy_device * phydev,bool enable)793 static int gpy_loopback(struct phy_device *phydev, bool enable)
794 {
795 struct gpy_priv *priv = phydev->priv;
796 u16 set = 0;
797 int ret;
798
799 if (enable) {
800 u64 now = get_jiffies_64();
801
802 /* wait until 3 seconds from last disable */
803 if (time_before64(now, priv->lb_dis_to))
804 msleep(jiffies64_to_msecs(priv->lb_dis_to - now));
805
806 set = BMCR_LOOPBACK;
807 }
808
809 ret = phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, set);
810 if (ret <= 0)
811 return ret;
812
813 if (enable) {
814 /* It takes some time for PHY device to switch into
815 * loopback mode.
816 */
817 msleep(100);
818 } else {
819 priv->lb_dis_to = get_jiffies_64() + HZ * 3;
820 }
821
822 return 0;
823 }
824
gpy115_loopback(struct phy_device * phydev,bool enable)825 static int gpy115_loopback(struct phy_device *phydev, bool enable)
826 {
827 struct gpy_priv *priv = phydev->priv;
828
829 if (enable)
830 return gpy_loopback(phydev, enable);
831
832 if (priv->fw_minor > 0x76)
833 return gpy_loopback(phydev, 0);
834
835 return genphy_soft_reset(phydev);
836 }
837
838 static struct phy_driver gpy_drivers[] = {
839 {
840 PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx),
841 .name = "Maxlinear Ethernet GPY2xx",
842 .get_features = genphy_c45_pma_read_abilities,
843 .config_init = gpy_config_init,
844 .probe = gpy_probe,
845 .suspend = genphy_suspend,
846 .resume = genphy_resume,
847 .config_aneg = gpy_config_aneg,
848 .aneg_done = genphy_c45_aneg_done,
849 .read_status = gpy_read_status,
850 .config_intr = gpy_config_intr,
851 .handle_interrupt = gpy_handle_interrupt,
852 .set_wol = gpy_set_wol,
853 .get_wol = gpy_get_wol,
854 .set_loopback = gpy_loopback,
855 },
856 {
857 .phy_id = PHY_ID_GPY115B,
858 .phy_id_mask = PHY_ID_GPYx15B_MASK,
859 .name = "Maxlinear Ethernet GPY115B",
860 .get_features = genphy_c45_pma_read_abilities,
861 .config_init = gpy_config_init,
862 .probe = gpy_probe,
863 .suspend = genphy_suspend,
864 .resume = genphy_resume,
865 .config_aneg = gpy_config_aneg,
866 .aneg_done = genphy_c45_aneg_done,
867 .read_status = gpy_read_status,
868 .config_intr = gpy_config_intr,
869 .handle_interrupt = gpy_handle_interrupt,
870 .set_wol = gpy_set_wol,
871 .get_wol = gpy_get_wol,
872 .set_loopback = gpy115_loopback,
873 },
874 {
875 PHY_ID_MATCH_MODEL(PHY_ID_GPY115C),
876 .name = "Maxlinear Ethernet GPY115C",
877 .get_features = genphy_c45_pma_read_abilities,
878 .config_init = gpy_config_init,
879 .probe = gpy_probe,
880 .suspend = genphy_suspend,
881 .resume = genphy_resume,
882 .config_aneg = gpy_config_aneg,
883 .aneg_done = genphy_c45_aneg_done,
884 .read_status = gpy_read_status,
885 .config_intr = gpy_config_intr,
886 .handle_interrupt = gpy_handle_interrupt,
887 .set_wol = gpy_set_wol,
888 .get_wol = gpy_get_wol,
889 .set_loopback = gpy115_loopback,
890 },
891 {
892 .phy_id = PHY_ID_GPY211B,
893 .phy_id_mask = PHY_ID_GPY21xB_MASK,
894 .name = "Maxlinear Ethernet GPY211B",
895 .get_features = genphy_c45_pma_read_abilities,
896 .config_init = gpy21x_config_init,
897 .probe = gpy_probe,
898 .suspend = genphy_suspend,
899 .resume = genphy_resume,
900 .config_aneg = gpy_config_aneg,
901 .aneg_done = genphy_c45_aneg_done,
902 .read_status = gpy_read_status,
903 .config_intr = gpy_config_intr,
904 .handle_interrupt = gpy_handle_interrupt,
905 .set_wol = gpy_set_wol,
906 .get_wol = gpy_get_wol,
907 .set_loopback = gpy_loopback,
908 },
909 {
910 PHY_ID_MATCH_MODEL(PHY_ID_GPY211C),
911 .name = "Maxlinear Ethernet GPY211C",
912 .get_features = genphy_c45_pma_read_abilities,
913 .config_init = gpy21x_config_init,
914 .probe = gpy_probe,
915 .suspend = genphy_suspend,
916 .resume = genphy_resume,
917 .config_aneg = gpy_config_aneg,
918 .aneg_done = genphy_c45_aneg_done,
919 .read_status = gpy_read_status,
920 .config_intr = gpy_config_intr,
921 .handle_interrupt = gpy_handle_interrupt,
922 .set_wol = gpy_set_wol,
923 .get_wol = gpy_get_wol,
924 .set_loopback = gpy_loopback,
925 },
926 {
927 .phy_id = PHY_ID_GPY212B,
928 .phy_id_mask = PHY_ID_GPY21xB_MASK,
929 .name = "Maxlinear Ethernet GPY212B",
930 .get_features = genphy_c45_pma_read_abilities,
931 .config_init = gpy21x_config_init,
932 .probe = gpy_probe,
933 .suspend = genphy_suspend,
934 .resume = genphy_resume,
935 .config_aneg = gpy_config_aneg,
936 .aneg_done = genphy_c45_aneg_done,
937 .read_status = gpy_read_status,
938 .config_intr = gpy_config_intr,
939 .handle_interrupt = gpy_handle_interrupt,
940 .set_wol = gpy_set_wol,
941 .get_wol = gpy_get_wol,
942 .set_loopback = gpy_loopback,
943 },
944 {
945 PHY_ID_MATCH_MODEL(PHY_ID_GPY212C),
946 .name = "Maxlinear Ethernet GPY212C",
947 .get_features = genphy_c45_pma_read_abilities,
948 .config_init = gpy21x_config_init,
949 .probe = gpy_probe,
950 .suspend = genphy_suspend,
951 .resume = genphy_resume,
952 .config_aneg = gpy_config_aneg,
953 .aneg_done = genphy_c45_aneg_done,
954 .read_status = gpy_read_status,
955 .config_intr = gpy_config_intr,
956 .handle_interrupt = gpy_handle_interrupt,
957 .set_wol = gpy_set_wol,
958 .get_wol = gpy_get_wol,
959 .set_loopback = gpy_loopback,
960 },
961 {
962 .phy_id = PHY_ID_GPY215B,
963 .phy_id_mask = PHY_ID_GPYx15B_MASK,
964 .name = "Maxlinear Ethernet GPY215B",
965 .get_features = genphy_c45_pma_read_abilities,
966 .config_init = gpy21x_config_init,
967 .probe = gpy_probe,
968 .suspend = genphy_suspend,
969 .resume = genphy_resume,
970 .config_aneg = gpy_config_aneg,
971 .aneg_done = genphy_c45_aneg_done,
972 .read_status = gpy_read_status,
973 .config_intr = gpy_config_intr,
974 .handle_interrupt = gpy_handle_interrupt,
975 .set_wol = gpy_set_wol,
976 .get_wol = gpy_get_wol,
977 .set_loopback = gpy_loopback,
978 },
979 {
980 PHY_ID_MATCH_MODEL(PHY_ID_GPY215C),
981 .name = "Maxlinear Ethernet GPY215C",
982 .get_features = genphy_c45_pma_read_abilities,
983 .config_init = gpy21x_config_init,
984 .probe = gpy_probe,
985 .suspend = genphy_suspend,
986 .resume = genphy_resume,
987 .config_aneg = gpy_config_aneg,
988 .aneg_done = genphy_c45_aneg_done,
989 .read_status = gpy_read_status,
990 .config_intr = gpy_config_intr,
991 .handle_interrupt = gpy_handle_interrupt,
992 .set_wol = gpy_set_wol,
993 .get_wol = gpy_get_wol,
994 .set_loopback = gpy_loopback,
995 },
996 {
997 PHY_ID_MATCH_MODEL(PHY_ID_GPY241B),
998 .name = "Maxlinear Ethernet GPY241B",
999 .get_features = genphy_c45_pma_read_abilities,
1000 .config_init = gpy_config_init,
1001 .probe = gpy_probe,
1002 .suspend = genphy_suspend,
1003 .resume = genphy_resume,
1004 .config_aneg = gpy_config_aneg,
1005 .aneg_done = genphy_c45_aneg_done,
1006 .read_status = gpy_read_status,
1007 .config_intr = gpy_config_intr,
1008 .handle_interrupt = gpy_handle_interrupt,
1009 .set_wol = gpy_set_wol,
1010 .get_wol = gpy_get_wol,
1011 .set_loopback = gpy_loopback,
1012 },
1013 {
1014 PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM),
1015 .name = "Maxlinear Ethernet GPY241BM",
1016 .get_features = genphy_c45_pma_read_abilities,
1017 .config_init = gpy_config_init,
1018 .probe = gpy_probe,
1019 .suspend = genphy_suspend,
1020 .resume = genphy_resume,
1021 .config_aneg = gpy_config_aneg,
1022 .aneg_done = genphy_c45_aneg_done,
1023 .read_status = gpy_read_status,
1024 .config_intr = gpy_config_intr,
1025 .handle_interrupt = gpy_handle_interrupt,
1026 .set_wol = gpy_set_wol,
1027 .get_wol = gpy_get_wol,
1028 .set_loopback = gpy_loopback,
1029 },
1030 {
1031 PHY_ID_MATCH_MODEL(PHY_ID_GPY245B),
1032 .name = "Maxlinear Ethernet GPY245B",
1033 .get_features = genphy_c45_pma_read_abilities,
1034 .config_init = gpy_config_init,
1035 .probe = gpy_probe,
1036 .suspend = genphy_suspend,
1037 .resume = genphy_resume,
1038 .config_aneg = gpy_config_aneg,
1039 .aneg_done = genphy_c45_aneg_done,
1040 .read_status = gpy_read_status,
1041 .config_intr = gpy_config_intr,
1042 .handle_interrupt = gpy_handle_interrupt,
1043 .set_wol = gpy_set_wol,
1044 .get_wol = gpy_get_wol,
1045 .set_loopback = gpy_loopback,
1046 },
1047 };
1048 module_phy_driver(gpy_drivers);
1049
1050 static struct mdio_device_id __maybe_unused gpy_tbl[] = {
1051 {PHY_ID_MATCH_MODEL(PHY_ID_GPY2xx)},
1052 {PHY_ID_GPY115B, PHY_ID_GPYx15B_MASK},
1053 {PHY_ID_MATCH_MODEL(PHY_ID_GPY115C)},
1054 {PHY_ID_GPY211B, PHY_ID_GPY21xB_MASK},
1055 {PHY_ID_MATCH_MODEL(PHY_ID_GPY211C)},
1056 {PHY_ID_GPY212B, PHY_ID_GPY21xB_MASK},
1057 {PHY_ID_MATCH_MODEL(PHY_ID_GPY212C)},
1058 {PHY_ID_GPY215B, PHY_ID_GPYx15B_MASK},
1059 {PHY_ID_MATCH_MODEL(PHY_ID_GPY215C)},
1060 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241B)},
1061 {PHY_ID_MATCH_MODEL(PHY_ID_GPY241BM)},
1062 {PHY_ID_MATCH_MODEL(PHY_ID_GPY245B)},
1063 { }
1064 };
1065 MODULE_DEVICE_TABLE(mdio, gpy_tbl);
1066
1067 MODULE_DESCRIPTION("Maxlinear Ethernet GPY Driver");
1068 MODULE_AUTHOR("Xu Liang");
1069 MODULE_LICENSE("GPL");
1070