1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2021, Intel Corporation. */
3
4 #ifndef _ICE_PTP_HW_H_
5 #define _ICE_PTP_HW_H_
6 #include <linux/dpll.h>
7
8 enum ice_ptp_tmr_cmd {
9 ICE_PTP_INIT_TIME,
10 ICE_PTP_INIT_INCVAL,
11 ICE_PTP_ADJ_TIME,
12 ICE_PTP_ADJ_TIME_AT_TIME,
13 ICE_PTP_READ_TIME,
14 ICE_PTP_NOP,
15 };
16
17 enum ice_ptp_serdes {
18 ICE_PTP_SERDES_1G,
19 ICE_PTP_SERDES_10G,
20 ICE_PTP_SERDES_25G,
21 ICE_PTP_SERDES_40G,
22 ICE_PTP_SERDES_50G,
23 ICE_PTP_SERDES_100G
24 };
25
26 enum ice_ptp_link_spd {
27 ICE_PTP_LNK_SPD_1G,
28 ICE_PTP_LNK_SPD_10G,
29 ICE_PTP_LNK_SPD_25G,
30 ICE_PTP_LNK_SPD_25G_RS,
31 ICE_PTP_LNK_SPD_40G,
32 ICE_PTP_LNK_SPD_50G,
33 ICE_PTP_LNK_SPD_50G_RS,
34 ICE_PTP_LNK_SPD_100G_RS,
35 NUM_ICE_PTP_LNK_SPD /* Must be last */
36 };
37
38 enum ice_ptp_fec_mode {
39 ICE_PTP_FEC_MODE_NONE,
40 ICE_PTP_FEC_MODE_CLAUSE74,
41 ICE_PTP_FEC_MODE_RS_FEC
42 };
43
44 enum eth56g_res_type {
45 ETH56G_PHY_REG_PTP,
46 ETH56G_PHY_MEM_PTP,
47 ETH56G_PHY_REG_XPCS,
48 ETH56G_PHY_REG_MAC,
49 ETH56G_PHY_REG_GPCS,
50 NUM_ETH56G_PHY_RES
51 };
52
53 enum ice_eth56g_link_spd {
54 ICE_ETH56G_LNK_SPD_1G,
55 ICE_ETH56G_LNK_SPD_2_5G,
56 ICE_ETH56G_LNK_SPD_10G,
57 ICE_ETH56G_LNK_SPD_25G,
58 ICE_ETH56G_LNK_SPD_40G,
59 ICE_ETH56G_LNK_SPD_50G,
60 ICE_ETH56G_LNK_SPD_50G2,
61 ICE_ETH56G_LNK_SPD_100G,
62 ICE_ETH56G_LNK_SPD_100G2,
63 NUM_ICE_ETH56G_LNK_SPD /* Must be last */
64 };
65
66 /**
67 * struct ice_phy_reg_info_eth56g - ETH56G PHY register parameters
68 * @base_addr: base address for each PHY block
69 * @step: step between PHY lanes
70 *
71 * Characteristic information for the various PHY register parameters in the
72 * ETH56G devices
73 */
74 struct ice_phy_reg_info_eth56g {
75 u32 base_addr;
76 u32 step;
77 };
78
79 /**
80 * struct ice_time_ref_info_e82x
81 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
82 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
83 *
84 * Characteristic information for the various TIME_REF sources possible in the
85 * E822 devices
86 */
87 struct ice_time_ref_info_e82x {
88 u64 pll_freq;
89 u64 nominal_incval;
90 };
91
92 /**
93 * struct ice_vernier_info_e82x
94 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
95 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
96 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
97 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
98 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
99 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
100 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
101 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
102 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
103 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
104 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
105 *
106 * Table of constants used during as part of the Vernier calibration of the Tx
107 * and Rx timestamps. This includes frequency values used to compute TUs per
108 * PAR/PCS clock cycle, and static delay values measured during hardware
109 * design.
110 *
111 * Note that some values are not used for all link speeds, and the
112 * P_REG_DESK_PAR* registers may represent different clock markers at
113 * different link speeds, either the deskew marker for multi-lane link speeds
114 * or the Reed Solomon gearbox marker for RS-FEC.
115 */
116 struct ice_vernier_info_e82x {
117 u32 tx_par_clk;
118 u32 rx_par_clk;
119 u32 tx_pcs_clk;
120 u32 rx_pcs_clk;
121 u32 tx_desk_rsgb_par;
122 u32 rx_desk_rsgb_par;
123 u32 tx_desk_rsgb_pcs;
124 u32 rx_desk_rsgb_pcs;
125 u32 tx_fixed_delay;
126 u32 pmd_adj_divisor;
127 u32 rx_fixed_delay;
128 };
129
130 #define ICE_ETH56G_MAC_CFG_RX_OFFSET_INT GENMASK(19, 9)
131 #define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)
132 #define ICE_ETH56G_MAC_CFG_FRAC_W 9
133 /**
134 * struct ice_eth56g_mac_reg_cfg - MAC config values for specific PTP registers
135 * @tx_mode: Tx timestamp compensation mode
136 * @tx_mk_dly: Tx timestamp marker start strobe delay
137 * @tx_cw_dly: Tx timestamp codeword start strobe delay
138 * @rx_mode: Rx timestamp compensation mode
139 * @rx_mk_dly: Rx timestamp marker start strobe delay
140 * @rx_cw_dly: Rx timestamp codeword start strobe delay
141 * @blks_per_clk: number of blocks transferred per clock cycle
142 * @blktime: block time, fixed point
143 * @mktime: marker time, fixed point
144 * @tx_offset: total Tx offset, fixed point
145 * @rx_offset: total Rx offset, contains value for bitslip/deskew, fixed point
146 *
147 * All fixed point registers except Rx offset are 23 bit unsigned ints with
148 * a 9 bit fractional.
149 * Rx offset is 11 bit unsigned int with a 9 bit fractional.
150 */
151 struct ice_eth56g_mac_reg_cfg {
152 struct {
153 u8 def;
154 u8 rs;
155 } tx_mode;
156 u8 tx_mk_dly;
157 struct {
158 u8 def;
159 u8 onestep;
160 } tx_cw_dly;
161 struct {
162 u8 def;
163 u8 rs;
164 } rx_mode;
165 struct {
166 u8 def;
167 u8 rs;
168 } rx_mk_dly;
169 struct {
170 u8 def;
171 u8 rs;
172 } rx_cw_dly;
173 u8 blks_per_clk;
174 u16 blktime;
175 u16 mktime;
176 struct {
177 u32 serdes;
178 u32 no_fec;
179 u32 fc;
180 u32 rs;
181 u32 sfd;
182 u32 onestep;
183 } tx_offset;
184 struct {
185 u32 serdes;
186 u32 no_fec;
187 u32 fc;
188 u32 rs;
189 u32 sfd;
190 u32 bs_ds;
191 } rx_offset;
192 };
193
194 extern
195 const struct ice_eth56g_mac_reg_cfg eth56g_mac_cfg[NUM_ICE_ETH56G_LNK_SPD];
196
197 /**
198 * struct ice_cgu_pll_params_e82x - E82X CGU parameters
199 * @refclk_pre_div: Reference clock pre-divisor
200 * @feedback_div: Feedback divisor
201 * @frac_n_div: Fractional divisor
202 * @post_pll_div: Post PLL divisor
203 *
204 * Clock Generation Unit parameters used to program the PLL based on the
205 * selected TIME_REF frequency.
206 */
207 struct ice_cgu_pll_params_e82x {
208 u32 refclk_pre_div;
209 u32 feedback_div;
210 u32 frac_n_div;
211 u32 post_pll_div;
212 };
213
214 #define E810C_QSFP_C827_0_HANDLE 2
215 #define E810C_QSFP_C827_1_HANDLE 3
216 enum ice_e810_c827_idx {
217 C827_0,
218 C827_1
219 };
220
221 enum ice_phy_rclk_pins {
222 ICE_RCLKA_PIN = 0, /* SCL pin */
223 ICE_RCLKB_PIN, /* SDA pin */
224 };
225
226 #define ICE_E810_RCLK_PINS_NUM (ICE_RCLKB_PIN + 1)
227 #define ICE_E82X_RCLK_PINS_NUM (ICE_RCLKA_PIN + 1)
228 #define E810T_CGU_INPUT_C827(_phy, _pin) ((_phy) * ICE_E810_RCLK_PINS_NUM + \
229 (_pin) + ZL_REF1P)
230
231 enum ice_zl_cgu_in_pins {
232 ZL_REF0P = 0,
233 ZL_REF0N,
234 ZL_REF1P,
235 ZL_REF1N,
236 ZL_REF2P,
237 ZL_REF2N,
238 ZL_REF3P,
239 ZL_REF3N,
240 ZL_REF4P,
241 ZL_REF4N,
242 NUM_ZL_CGU_INPUT_PINS
243 };
244
245 enum ice_zl_cgu_out_pins {
246 ZL_OUT0 = 0,
247 ZL_OUT1,
248 ZL_OUT2,
249 ZL_OUT3,
250 ZL_OUT4,
251 ZL_OUT5,
252 ZL_OUT6,
253 NUM_ZL_CGU_OUTPUT_PINS
254 };
255
256 enum ice_si_cgu_in_pins {
257 SI_REF0P = 0,
258 SI_REF0N,
259 SI_REF1P,
260 SI_REF1N,
261 SI_REF2P,
262 SI_REF2N,
263 SI_REF3,
264 SI_REF4,
265 NUM_SI_CGU_INPUT_PINS
266 };
267
268 enum ice_si_cgu_out_pins {
269 SI_OUT0 = 0,
270 SI_OUT1,
271 SI_OUT2,
272 SI_OUT3,
273 SI_OUT4,
274 NUM_SI_CGU_OUTPUT_PINS
275 };
276
277 struct ice_cgu_pin_desc {
278 char *name;
279 u8 index;
280 enum dpll_pin_type type;
281 u32 freq_supp_num;
282 struct dpll_pin_frequency *freq_supp;
283 };
284
285 extern const struct
286 ice_cgu_pll_params_e82x e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
287
288 /**
289 * struct ice_cgu_pll_params_e825c - E825C CGU parameters
290 * @tspll_ck_refclkfreq: tspll_ck_refclkfreq selection
291 * @tspll_ndivratio: ndiv ratio that goes directly to the pll
292 * @tspll_fbdiv_intgr: TS PLL integer feedback divide
293 * @tspll_fbdiv_frac: TS PLL fractional feedback divide
294 * @ref1588_ck_div: clock divider for tspll ref
295 *
296 * Clock Generation Unit parameters used to program the PLL based on the
297 * selected TIME_REF/TCXO frequency.
298 */
299 struct ice_cgu_pll_params_e825c {
300 u32 tspll_ck_refclkfreq;
301 u32 tspll_ndivratio;
302 u32 tspll_fbdiv_intgr;
303 u32 tspll_fbdiv_frac;
304 u32 ref1588_ck_div;
305 };
306
307 extern const struct
308 ice_cgu_pll_params_e825c e825c_cgu_params[NUM_ICE_TIME_REF_FREQ];
309
310 #define E810C_QSFP_C827_0_HANDLE 2
311 #define E810C_QSFP_C827_1_HANDLE 3
312
313 /* Table of constants related to possible ETH56G PHY resources */
314 extern const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES];
315
316 /* Table of constants related to possible TIME_REF sources */
317 extern const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ];
318
319 /* Table of constants for Vernier calibration on E822 */
320 extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD];
321
322 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
323 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
324 */
325 #define ICE_E810_PLL_FREQ 812500000
326 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
327 #define ICE_E810_E830_SYNC_DELAY 0
328
329 /* Device agnostic functions */
330 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
331 int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable);
332 bool ice_ptp_lock(struct ice_hw *hw);
333 void ice_ptp_unlock(struct ice_hw *hw);
334 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
335 int ice_ptp_init_time(struct ice_hw *hw, u64 time);
336 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
337 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
338 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
339 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw);
340 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
341 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
342 void ice_ptp_reset_ts_memory(struct ice_hw *hw);
343 int ice_ptp_init_phc(struct ice_hw *hw);
344 void ice_ptp_init_hw(struct ice_hw *hw);
345 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
346 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,
347 enum ice_ptp_tmr_cmd configured_cmd);
348
349 /* E822 family functions */
350 int ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
351 int ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
352 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad);
353
354 /**
355 * ice_e82x_time_ref - Get the current TIME_REF from capabilities
356 * @hw: pointer to the HW structure
357 *
358 * Returns the current TIME_REF from the capabilities structure.
359 */
ice_e82x_time_ref(const struct ice_hw * hw)360 static inline enum ice_time_ref_freq ice_e82x_time_ref(const struct ice_hw *hw)
361 {
362 return hw->func_caps.ts_func_info.time_ref;
363 }
364
365 /**
366 * ice_set_e82x_time_ref - Set new TIME_REF
367 * @hw: pointer to the HW structure
368 * @time_ref: new TIME_REF to set
369 *
370 * Update the TIME_REF in the capabilities structure in response to some
371 * change, such as an update to the CGU registers.
372 */
373 static inline void
ice_set_e82x_time_ref(struct ice_hw * hw,enum ice_time_ref_freq time_ref)374 ice_set_e82x_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
375 {
376 hw->func_caps.ts_func_info.time_ref = time_ref;
377 }
378
ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)379 static inline u64 ice_e82x_pll_freq(enum ice_time_ref_freq time_ref)
380 {
381 return e82x_time_ref[time_ref].pll_freq;
382 }
383
ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)384 static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref)
385 {
386 return e82x_time_ref[time_ref].nominal_incval;
387 }
388
389 /* E822 Vernier calibration functions */
390 int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset);
391 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
392 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
393 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
394 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold);
395
396 /* E810 family functions */
397 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data);
398 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data);
399 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries);
400 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input);
401 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
402 struct dpll_pin_frequency *
403 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
404 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
405 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
406 enum dpll_lock_status last_dpll_state, u8 *pin,
407 u8 *ref_state, u8 *eec_mode, s64 *phase_offset,
408 enum dpll_lock_status *dpll_state);
409 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num);
410 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id,
411 unsigned long *caps);
412
413 /* ETH56G family functions */
414 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
415 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
416 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port);
417 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold);
418 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port);
419
420 #define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
421 #define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL
422 #define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL
423 #define ICE_ETH56G_NOMINAL_THRESH4 0x7777
424 #define ICE_ETH56G_NOMINAL_TX_THRESH 0x6
425
426 /**
427 * ice_get_base_incval - Get base clock increment value
428 * @hw: pointer to the HW struct
429 *
430 * Return: base clock increment value for supported PHYs, 0 otherwise
431 */
ice_get_base_incval(struct ice_hw * hw)432 static inline u64 ice_get_base_incval(struct ice_hw *hw)
433 {
434 switch (hw->mac_type) {
435 case ICE_MAC_E810:
436 case ICE_MAC_E830:
437 return ICE_PTP_NOMINAL_INCVAL_E810;
438 case ICE_MAC_GENERIC:
439 return ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
440 case ICE_MAC_GENERIC_3K_E825:
441 return ICE_ETH56G_NOMINAL_INCVAL;
442 default:
443 return 0;
444 }
445 }
446
ice_is_dual(struct ice_hw * hw)447 static inline bool ice_is_dual(struct ice_hw *hw)
448 {
449 return !!(hw->dev_caps.nac_topo.mode & ICE_NAC_TOPO_DUAL_M);
450 }
451
452 #define PFTSYN_SEM_BYTES 4
453
454 #define ICE_PTP_CLOCK_INDEX_0 0x00
455 #define ICE_PTP_CLOCK_INDEX_1 0x01
456
457 /* PHY timer commands */
458 #define SEL_CPK_SRC 8
459 #define SEL_PHY_SRC 3
460
461 /* Time Sync command Definitions */
462 #define GLTSYN_CMD_INIT_TIME BIT(0)
463 #define GLTSYN_CMD_INIT_INCVAL BIT(1)
464 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
465 #define GLTSYN_CMD_ADJ_TIME BIT(2)
466 #define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
467 #define GLTSYN_CMD_READ_TIME BIT(7)
468
469 /* PHY port Time Sync command definitions */
470 #define PHY_CMD_INIT_TIME BIT(0)
471 #define PHY_CMD_INIT_INCVAL BIT(1)
472 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
473 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
474 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
475
476 #define TS_CMD_MASK_E810 0xFF
477 #define TS_CMD_MASK 0xF
478 #define SYNC_EXEC_CMD 0x3
479 #define TS_CMD_RX_TYPE ICE_M(0x18, 0x4)
480
481 /* Macros to derive port low and high addresses on both quads */
482 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
483 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
484 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
485 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
486
487 /* PHY QUAD register base addresses */
488 #define Q_0_BASE 0x94000
489 #define Q_1_BASE 0x114000
490
491 /* Timestamp memory reset registers */
492 #define Q_REG_TS_CTRL 0x618
493 #define Q_REG_TS_CTRL_S 0
494 #define Q_REG_TS_CTRL_M BIT(0)
495
496 /* Timestamp availability status registers */
497 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
498 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
499
500 /* Tx FIFO status registers */
501 #define Q_REG_FIFO23_STATUS 0xCF8
502 #define Q_REG_FIFO01_STATUS 0xCFC
503 #define Q_REG_FIFO02_S 0
504 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
505 #define Q_REG_FIFO13_S 10
506 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
507
508 /* Interrupt control Config registers */
509 #define Q_REG_TX_MEM_GBL_CFG 0xC08
510 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
511 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
512 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
513 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
514 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
515
516 /* Tx Timestamp data registers */
517 #define Q_REG_TX_MEMORY_BANK_START 0xA00
518
519 /* PHY port register base addresses */
520 #define P_0_BASE 0x80000
521 #define P_4_BASE 0x106000
522
523 /* Timestamp init registers */
524 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
525 #define P_REG_RX_TIMER_INC_PRE_U 0x470
526 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
527 #define P_REG_TX_TIMER_INC_PRE_U 0x450
528
529 /* Timestamp match and adjust target registers */
530 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
531 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
532 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
533 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
534
535 /* Timestamp capture registers */
536 #define P_REG_RX_CAPTURE_L 0x4D8
537 #define P_REG_RX_CAPTURE_U 0x4DC
538 #define P_REG_TX_CAPTURE_L 0x4B4
539 #define P_REG_TX_CAPTURE_U 0x4B8
540
541 /* Timestamp PHY incval registers */
542 #define P_REG_TIMETUS_L 0x410
543 #define P_REG_TIMETUS_U 0x414
544
545 #define P_REG_40B_LOW_M GENMASK(7, 0)
546 #define P_REG_40B_HIGH_S 8
547
548 /* PHY window length registers */
549 #define P_REG_WL 0x40C
550
551 #define PTP_VERNIER_WL 0x111ed
552
553 /* PHY start registers */
554 #define P_REG_PS 0x408
555 #define P_REG_PS_START_S 0
556 #define P_REG_PS_START_M BIT(0)
557 #define P_REG_PS_BYPASS_MODE_S 1
558 #define P_REG_PS_BYPASS_MODE_M BIT(1)
559 #define P_REG_PS_ENA_CLK_S 2
560 #define P_REG_PS_ENA_CLK_M BIT(2)
561 #define P_REG_PS_LOAD_OFFSET_S 3
562 #define P_REG_PS_LOAD_OFFSET_M BIT(3)
563 #define P_REG_PS_SFT_RESET_S 11
564 #define P_REG_PS_SFT_RESET_M BIT(11)
565
566 /* PHY offset valid registers */
567 #define P_REG_TX_OV_STATUS 0x4D4
568 #define P_REG_TX_OV_STATUS_OV_S 0
569 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
570 #define P_REG_RX_OV_STATUS 0x4F8
571 #define P_REG_RX_OV_STATUS_OV_S 0
572 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
573
574 /* PHY offset ready registers */
575 #define P_REG_TX_OR 0x45C
576 #define P_REG_RX_OR 0x47C
577
578 /* PHY total offset registers */
579 #define P_REG_TOTAL_RX_OFFSET_L 0x460
580 #define P_REG_TOTAL_RX_OFFSET_U 0x464
581 #define P_REG_TOTAL_TX_OFFSET_L 0x440
582 #define P_REG_TOTAL_TX_OFFSET_U 0x444
583
584 /* Timestamp PAR/PCS registers */
585 #define P_REG_UIX66_10G_40G_L 0x480
586 #define P_REG_UIX66_10G_40G_U 0x484
587 #define P_REG_UIX66_25G_100G_L 0x488
588 #define P_REG_UIX66_25G_100G_U 0x48C
589 #define P_REG_DESK_PAR_RX_TUS_L 0x490
590 #define P_REG_DESK_PAR_RX_TUS_U 0x494
591 #define P_REG_DESK_PAR_TX_TUS_L 0x498
592 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
593 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
594 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
595 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
596 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
597 #define P_REG_PAR_RX_TUS_L 0x420
598 #define P_REG_PAR_RX_TUS_U 0x424
599 #define P_REG_PAR_TX_TUS_L 0x428
600 #define P_REG_PAR_TX_TUS_U 0x42C
601 #define P_REG_PCS_RX_TUS_L 0x430
602 #define P_REG_PCS_RX_TUS_U 0x434
603 #define P_REG_PCS_TX_TUS_L 0x438
604 #define P_REG_PCS_TX_TUS_U 0x43C
605 #define P_REG_PAR_RX_TIME_L 0x4F0
606 #define P_REG_PAR_RX_TIME_U 0x4F4
607 #define P_REG_PAR_TX_TIME_L 0x4CC
608 #define P_REG_PAR_TX_TIME_U 0x4D0
609 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
610 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
611 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
612 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
613 #define P_REG_LINK_SPEED 0x4FC
614 #define P_REG_LINK_SPEED_SERDES_S 0
615 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
616 #define P_REG_LINK_SPEED_FEC_MODE_S 3
617 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
618 #define P_REG_LINK_SPEED_FEC_MODE(reg) \
619 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
620 P_REG_LINK_SPEED_FEC_MODE_S)
621
622 /* PHY timestamp related registers */
623 #define P_REG_PMD_ALIGNMENT 0x0FC
624 #define P_REG_RX_80_TO_160_CNT 0x6FC
625 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
626 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
627 #define P_REG_RX_40_TO_160_CNT 0x8FC
628 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
629 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
630
631 /* Rx FIFO status registers */
632 #define P_REG_RX_OV_FS 0x4F8
633 #define P_REG_RX_OV_FS_FIFO_STATUS_S 2
634 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
635
636 /* Timestamp command registers */
637 #define P_REG_TX_TMR_CMD 0x448
638 #define P_REG_RX_TMR_CMD 0x468
639
640 /* E810 timesync enable register */
641 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
642
643 /* E810 shadow init time registers */
644 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
645 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
646
647 /* E810 shadow time adjust registers */
648 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
649 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
650
651 /* E810 timer command register */
652 #define E810_ETH_GLTSYN_CMD 0x03000344
653
654 /* E830 timer command register */
655 #define E830_ETH_GLTSYN_CMD 0x00088814
656
657 /* E810 PHC time register */
658 #define E830_GLTSYN_TIME_L(_tmr_idx) (0x0008A000 + 0x1000 * (_tmr_idx))
659
660 /* Source timer incval macros */
661 #define INCVAL_HIGH_M 0xFF
662
663 /* PHY 40b registers macros */
664 #define PHY_EXT_40B_LOW_M GENMASK(31, 0)
665 #define PHY_EXT_40B_HIGH_M GENMASK_ULL(39, 32)
666 #define PHY_40B_LOW_M GENMASK(7, 0)
667 #define PHY_40B_HIGH_M GENMASK_ULL(39, 8)
668 #define TS_VALID BIT(0)
669 #define TS_LOW_M 0xFFFFFFFF
670 #define TS_HIGH_M 0xFF
671 #define TS_HIGH_S 32
672
673 #define BYTES_PER_IDX_ADDR_L_U 8
674 #define BYTES_PER_IDX_ADDR_L 4
675
676 /* Tx timestamp low latency read definitions */
677 #define REG_LL_PROXY_H_TIMEOUT_US 2000
678 #define REG_LL_PROXY_H_PHY_TMR_CMD_M GENMASK(7, 6)
679 #define REG_LL_PROXY_H_PHY_TMR_CMD_ADJ 0x1
680 #define REG_LL_PROXY_H_PHY_TMR_CMD_FREQ 0x2
681 #define REG_LL_PROXY_H_TS_HIGH GENMASK(23, 16)
682 #define REG_LL_PROXY_H_PHY_TMR_IDX_M BIT(24)
683 #define REG_LL_PROXY_H_TS_IDX GENMASK(29, 24)
684 #define REG_LL_PROXY_H_TS_INTR_ENA BIT(30)
685 #define REG_LL_PROXY_H_EXEC BIT(31)
686
687 #define REG_LL_PROXY_L PF_SB_ATQBAH
688 #define REG_LL_PROXY_H PF_SB_ATQBAL
689
690 /* Internal PHY timestamp address */
691 #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
692 #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
693 BYTES_PER_IDX_ADDR_L))
694
695 /* External PHY timestamp address */
696 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
697 ((idx) * BYTES_PER_IDX_ADDR_L_U))
698
699 #define LOW_TX_MEMORY_BANK_START 0x03090000
700 #define HIGH_TX_MEMORY_BANK_START 0x03090004
701
702 /* SMA controller pin control */
703 #define ICE_SMA1_DIR_EN BIT(4)
704 #define ICE_SMA1_TX_EN BIT(5)
705 #define ICE_SMA2_UFL2_RX_DIS BIT(3)
706 #define ICE_SMA2_DIR_EN BIT(6)
707 #define ICE_SMA2_TX_EN BIT(7)
708
709 #define ICE_SMA1_MASK (ICE_SMA1_DIR_EN | ICE_SMA1_TX_EN)
710 #define ICE_SMA2_MASK (ICE_SMA2_UFL2_RX_DIS | ICE_SMA2_DIR_EN | \
711 ICE_SMA2_TX_EN)
712 #define ICE_ALL_SMA_MASK (ICE_SMA1_MASK | ICE_SMA2_MASK)
713
714 #define ICE_SMA_MIN_BIT 3
715 #define ICE_SMA_MAX_BIT 7
716 #define ICE_PCA9575_P1_OFFSET 8
717
718 /* PCA9575 IO controller registers */
719 #define ICE_PCA9575_P0_IN 0x0
720
721 /* PCA9575 IO controller pin control */
722 #define ICE_P0_GNSS_PRSNT_N BIT(4)
723
724 /* ETH56G PHY register addresses */
725 /* Timestamp PHY incval registers */
726 #define PHY_REG_TIMETUS_L 0x8
727 #define PHY_REG_TIMETUS_U 0xC
728
729 /* Timestamp PCS registers */
730 #define PHY_PCS_REF_TUS_L 0x18
731 #define PHY_PCS_REF_TUS_U 0x1C
732
733 /* Timestamp PCS ref incval registers */
734 #define PHY_PCS_REF_INC_L 0x20
735 #define PHY_PCS_REF_INC_U 0x24
736
737 /* Timestamp init registers */
738 #define PHY_REG_RX_TIMER_INC_PRE_L 0x64
739 #define PHY_REG_RX_TIMER_INC_PRE_U 0x68
740 #define PHY_REG_TX_TIMER_INC_PRE_L 0x44
741 #define PHY_REG_TX_TIMER_INC_PRE_U 0x48
742
743 /* Timestamp match and adjust target registers */
744 #define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C
745 #define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70
746 #define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C
747 #define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50
748
749 /* Timestamp command registers */
750 #define PHY_REG_TX_TMR_CMD 0x40
751 #define PHY_REG_RX_TMR_CMD 0x60
752
753 /* Phy offset ready registers */
754 #define PHY_REG_TX_OFFSET_READY 0x54
755 #define PHY_REG_RX_OFFSET_READY 0x74
756
757 /* Phy total offset registers */
758 #define PHY_REG_TOTAL_TX_OFFSET_L 0x38
759 #define PHY_REG_TOTAL_TX_OFFSET_U 0x3C
760 #define PHY_REG_TOTAL_RX_OFFSET_L 0x58
761 #define PHY_REG_TOTAL_RX_OFFSET_U 0x5C
762
763 /* Timestamp capture registers */
764 #define PHY_REG_TX_CAPTURE_L 0x78
765 #define PHY_REG_TX_CAPTURE_U 0x7C
766 #define PHY_REG_RX_CAPTURE_L 0x8C
767 #define PHY_REG_RX_CAPTURE_U 0x90
768
769 /* Memory status registers */
770 #define PHY_REG_TX_MEMORY_STATUS_L 0x80
771 #define PHY_REG_TX_MEMORY_STATUS_U 0x84
772
773 /* Interrupt config register */
774 #define PHY_REG_TS_INT_CONFIG 0x88
775
776 /* XIF mode config register */
777 #define PHY_MAC_XIF_MODE 0x24
778 #define PHY_MAC_XIF_1STEP_ENA_M ICE_M(0x1, 5)
779 #define PHY_MAC_XIF_TS_BIN_MODE_M ICE_M(0x1, 11)
780 #define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20)
781 #define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21)
782
783 #define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0)
784 #define PHY_TS_INT_CONFIG_ENA_M BIT(6)
785
786 /* Macros to derive offsets for TimeStampLow and TimeStampHigh */
787 #define PHY_TSTAMP_L(x) (((x) * 8) + 0)
788 #define PHY_TSTAMP_U(x) (((x) * 8) + 4)
789
790 #define PHY_REG_DESKEW_0 0x94
791 #define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0)
792 #define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7)
793 #define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3
794 #define PHY_REG_DESKEW_0_VALID GENMASK(10, 10)
795
796 #define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset))
797 #define PHY_REVISION_ETH56G 0x10200
798 #define PHY_VENDOR_TXLANE_THRESH 0x2000C
799
800 #define PHY_MAC_TSU_CONFIG 0x40
801 #define PHY_MAC_TSU_CFG_RX_MODE_M ICE_M(0x7, 0)
802 #define PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M ICE_M(0x7, 4)
803 #define PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M ICE_M(0x7, 8)
804 #define PHY_MAC_TSU_CFG_TX_MODE_M ICE_M(0x7, 12)
805 #define PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M ICE_M(0x1F, 16)
806 #define PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M ICE_M(0x1F, 21)
807 #define PHY_MAC_TSU_CFG_BLKS_PER_CLK_M ICE_M(0x1, 28)
808 #define PHY_MAC_RX_MODULO 0x44
809 #define PHY_MAC_RX_OFFSET 0x48
810 #define PHY_MAC_RX_OFFSET_M ICE_M(0xFFFFFF, 0)
811 #define PHY_MAC_TX_MODULO 0x4C
812 #define PHY_MAC_BLOCKTIME 0x50
813 #define PHY_MAC_MARKERTIME 0x54
814 #define PHY_MAC_TX_OFFSET 0x58
815 #define PHY_GPCS_BITSLIP 0x5C
816
817 #define PHY_PTP_INT_STATUS 0x7FD140
818
819 /* ETH56G registers shared per quad */
820 /* GPCS config register */
821 #define PHY_GPCS_CONFIG_REG0 0x268
822 #define PHY_GPCS_CONFIG_REG0_TX_THR_M GENMASK(27, 24)
823 /* 1-step PTP config */
824 #define PHY_PTP_1STEP_CONFIG 0x270
825 #define PHY_PTP_1STEP_T1S_UP64_M GENMASK(7, 4)
826 #define PHY_PTP_1STEP_T1S_DELTA_M GENMASK(11, 8)
827 #define PHY_PTP_1STEP_PEER_DELAY(_quad_lane) (0x274 + 4 * (_quad_lane))
828 #define PHY_PTP_1STEP_PD_ADD_PD_M BIT(0)
829 #define PHY_PTP_1STEP_PD_DELAY_M GENMASK(30, 1)
830 #define PHY_PTP_1STEP_PD_DLY_V_M BIT(31)
831
832 #endif /* _ICE_PTP_HW_H_ */
833