1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2018, Google LLC. 4 */ 5 6 #ifndef SELFTEST_KVM_PROCESSOR_H 7 #define SELFTEST_KVM_PROCESSOR_H 8 9 #include <assert.h> 10 #include <stdint.h> 11 #include <syscall.h> 12 13 #include <asm/msr-index.h> 14 #include <asm/prctl.h> 15 16 #include <linux/kvm_para.h> 17 #include <linux/stringify.h> 18 19 #include "kvm_util.h" 20 #include "ucall_common.h" 21 22 extern bool host_cpu_is_intel; 23 extern bool host_cpu_is_amd; 24 extern bool host_cpu_is_hygon; 25 extern bool host_cpu_is_amd_compatible; 26 extern u64 guest_tsc_khz; 27 28 #ifndef MAX_NR_CPUID_ENTRIES 29 #define MAX_NR_CPUID_ENTRIES 100 30 #endif 31 32 #define NONCANONICAL 0xaaaaaaaaaaaaaaaaull 33 34 /* Forced emulation prefix, used to invoke the emulator unconditionally. */ 35 #define KVM_FEP "ud2; .byte 'k', 'v', 'm';" 36 37 #define NMI_VECTOR 0x02 38 39 const char *ex_str(int vector); 40 41 #define X86_EFLAGS_CF BIT(0) /* Carry Flag */ 42 #define X86_EFLAGS_FIXED BIT(1) /* Bit 1 - always on */ 43 #define X86_EFLAGS_PF BIT(2) /* Parity Flag */ 44 #define X86_EFLAGS_AF BIT(4) /* Auxiliary carry Flag */ 45 #define X86_EFLAGS_ZF BIT(6) /* Zero Flag */ 46 #define X86_EFLAGS_SF BIT(7) /* Sign Flag */ 47 #define X86_EFLAGS_TF BIT(8) /* Trap Flag */ 48 #define X86_EFLAGS_IF BIT(9) /* Interrupt Flag */ 49 #define X86_EFLAGS_DF BIT(10) /* Direction Flag */ 50 #define X86_EFLAGS_OF BIT(11) /* Overflow Flag */ 51 #define X86_EFLAGS_IOPL BIT(12) /* I/O Privilege Level (2 bits) */ 52 #define X86_EFLAGS_NT BIT(14) /* Nested Task */ 53 #define X86_EFLAGS_RF BIT(16) /* Resume Flag */ 54 #define X86_EFLAGS_VM BIT(17) /* Virtual Mode */ 55 #define X86_EFLAGS_AC BIT(18) /* Alignment Check/Access Control */ 56 #define X86_EFLAGS_VIF BIT(19) /* Virtual Interrupt Flag */ 57 #define X86_EFLAGS_VIP BIT(20) /* Virtual Interrupt Pending */ 58 #define X86_EFLAGS_ID BIT(21) /* CPUID detection */ 59 60 #define X86_CR4_VME (1ul << 0) 61 #define X86_CR4_PVI (1ul << 1) 62 #define X86_CR4_TSD (1ul << 2) 63 #define X86_CR4_DE (1ul << 3) 64 #define X86_CR4_PSE (1ul << 4) 65 #define X86_CR4_PAE (1ul << 5) 66 #define X86_CR4_MCE (1ul << 6) 67 #define X86_CR4_PGE (1ul << 7) 68 #define X86_CR4_PCE (1ul << 8) 69 #define X86_CR4_OSFXSR (1ul << 9) 70 #define X86_CR4_OSXMMEXCPT (1ul << 10) 71 #define X86_CR4_UMIP (1ul << 11) 72 #define X86_CR4_LA57 (1ul << 12) 73 #define X86_CR4_VMXE (1ul << 13) 74 #define X86_CR4_SMXE (1ul << 14) 75 #define X86_CR4_FSGSBASE (1ul << 16) 76 #define X86_CR4_PCIDE (1ul << 17) 77 #define X86_CR4_OSXSAVE (1ul << 18) 78 #define X86_CR4_SMEP (1ul << 20) 79 #define X86_CR4_SMAP (1ul << 21) 80 #define X86_CR4_PKE (1ul << 22) 81 82 struct xstate_header { 83 u64 xstate_bv; 84 u64 xcomp_bv; 85 u64 reserved[6]; 86 } __attribute__((packed)); 87 88 struct xstate { 89 u8 i387[512]; 90 struct xstate_header header; 91 u8 extended_state_area[0]; 92 } __attribute__ ((packed, aligned (64))); 93 94 #define XFEATURE_MASK_FP BIT_ULL(0) 95 #define XFEATURE_MASK_SSE BIT_ULL(1) 96 #define XFEATURE_MASK_YMM BIT_ULL(2) 97 #define XFEATURE_MASK_BNDREGS BIT_ULL(3) 98 #define XFEATURE_MASK_BNDCSR BIT_ULL(4) 99 #define XFEATURE_MASK_OPMASK BIT_ULL(5) 100 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6) 101 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7) 102 #define XFEATURE_MASK_PT BIT_ULL(8) 103 #define XFEATURE_MASK_PKRU BIT_ULL(9) 104 #define XFEATURE_MASK_PASID BIT_ULL(10) 105 #define XFEATURE_MASK_CET_USER BIT_ULL(11) 106 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12) 107 #define XFEATURE_MASK_LBR BIT_ULL(15) 108 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) 109 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) 110 111 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ 112 XFEATURE_MASK_ZMM_Hi256 | \ 113 XFEATURE_MASK_Hi16_ZMM) 114 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \ 115 XFEATURE_MASK_XTILE_CFG) 116 117 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */ 118 enum cpuid_output_regs { 119 KVM_CPUID_EAX, 120 KVM_CPUID_EBX, 121 KVM_CPUID_ECX, 122 KVM_CPUID_EDX 123 }; 124 125 /* 126 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be 127 * passed by value with no overhead. 128 */ 129 struct kvm_x86_cpu_feature { 130 u32 function; 131 u16 index; 132 u8 reg; 133 u8 bit; 134 }; 135 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \ 136 ({ \ 137 struct kvm_x86_cpu_feature feature = { \ 138 .function = fn, \ 139 .index = idx, \ 140 .reg = KVM_CPUID_##gpr, \ 141 .bit = __bit, \ 142 }; \ 143 \ 144 kvm_static_assert((fn & 0xc0000000) == 0 || \ 145 (fn & 0xc0000000) == 0x40000000 || \ 146 (fn & 0xc0000000) == 0x80000000 || \ 147 (fn & 0xc0000000) == 0xc0000000); \ 148 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \ 149 feature; \ 150 }) 151 152 /* 153 * Basic Leafs, a.k.a. Intel defined 154 */ 155 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3) 156 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5) 157 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6) 158 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15) 159 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17) 160 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21) 161 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22) 162 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24) 163 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26) 164 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27) 165 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30) 166 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31) 167 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6) 168 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7) 169 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9) 170 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19) 171 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25) 172 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26) 173 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0) 174 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1) 175 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2) 176 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4) 177 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7) 178 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10) 179 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11) 180 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14) 181 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20) 182 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22) 183 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23) 184 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24) 185 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2) 186 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3) 187 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4) 188 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16) 189 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22) 190 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30) 191 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7) 192 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20) 193 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24) 194 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26) 195 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29) 196 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31) 197 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17) 198 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18) 199 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3) 200 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4) 201 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2) 202 203 /* 204 * Extended Leafs, a.k.a. AMD defined 205 */ 206 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2) 207 #define X86_FEATURE_PERFCTR_CORE KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 23) 208 #define X86_FEATURE_PERFCTR_NB KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 24) 209 #define X86_FEATURE_PERFCTR_LLC KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 28) 210 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20) 211 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26) 212 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27) 213 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29) 214 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8) 215 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4) 216 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12) 217 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0) 218 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1) 219 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3) 220 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4) 221 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10) 222 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12) 223 #define X86_FEATURE_V_VMSAVE_VMLOAD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 15) 224 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16) 225 #define X86_FEATURE_IDLE_HLT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 30) 226 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1) 227 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3) 228 #define X86_FEATURE_SEV_SNP KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 4) 229 #define X86_FEATURE_GP_ON_USER_CPUID KVM_X86_CPU_FEATURE(0x80000021, 0, EAX, 17) 230 #define X86_FEATURE_PERFMON_V2 KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 0) 231 #define X86_FEATURE_LBR_PMC_FREEZE KVM_X86_CPU_FEATURE(0x80000022, 0, EAX, 2) 232 233 /* 234 * KVM defined paravirt features. 235 */ 236 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0) 237 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1) 238 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2) 239 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3) 240 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4) 241 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5) 242 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6) 243 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7) 244 /* Bit 8 apparently isn't used?!?! */ 245 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9) 246 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10) 247 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11) 248 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12) 249 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13) 250 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14) 251 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15) 252 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16) 253 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17) 254 255 /* 256 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit 257 * value/property as opposed to a single-bit feature. Again, pack the info 258 * into a 64-bit value to pass by value with no overhead. 259 */ 260 struct kvm_x86_cpu_property { 261 u32 function; 262 u8 index; 263 u8 reg; 264 u8 lo_bit; 265 u8 hi_bit; 266 }; 267 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \ 268 ({ \ 269 struct kvm_x86_cpu_property property = { \ 270 .function = fn, \ 271 .index = idx, \ 272 .reg = KVM_CPUID_##gpr, \ 273 .lo_bit = low_bit, \ 274 .hi_bit = high_bit, \ 275 }; \ 276 \ 277 kvm_static_assert(low_bit < high_bit); \ 278 kvm_static_assert((fn & 0xc0000000) == 0 || \ 279 (fn & 0xc0000000) == 0x40000000 || \ 280 (fn & 0xc0000000) == 0x80000000 || \ 281 (fn & 0xc0000000) == 0xc0000000); \ 282 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \ 283 property; \ 284 }) 285 286 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) 287 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7) 288 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15) 289 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23) 290 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31) 291 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 12) 292 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31) 293 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4) 294 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12) 295 296 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31) 297 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) 298 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) 299 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31) 300 301 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) 302 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31) 303 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31) 304 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15) 305 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31) 306 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15) 307 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31) 308 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15) 309 310 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31) 311 312 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31) 313 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7) 314 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15) 315 #define X86_PROPERTY_GUEST_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 16, 23) 316 #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5) 317 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11) 318 #define X86_PROPERTY_NR_PERFCTR_CORE KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 0, 3) 319 #define X86_PROPERTY_NR_PERFCTR_NB KVM_X86_CPU_PROPERTY(0x80000022, 0, EBX, 10, 15) 320 321 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31) 322 323 /* 324 * Intel's architectural PMU events are bizarre. They have a "feature" bit 325 * that indicates the feature is _not_ supported, and a property that states 326 * the length of the bit mask of unsupported features. A feature is supported 327 * if the size of the bit mask is larger than the "unavailable" bit, and said 328 * bit is not set. Fixed counters also bizarre enumeration, but inverted from 329 * arch events for general purpose counters. Fixed counters are supported if a 330 * feature flag is set **OR** the total number of fixed counters is greater 331 * than index of the counter. 332 * 333 * Wrap the events for general purpose and fixed counters to simplify checking 334 * whether or not a given architectural event is supported. 335 */ 336 struct kvm_x86_pmu_feature { 337 struct kvm_x86_cpu_feature f; 338 }; 339 #define KVM_X86_PMU_FEATURE(__reg, __bit) \ 340 ({ \ 341 struct kvm_x86_pmu_feature feature = { \ 342 .f = KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \ 343 }; \ 344 \ 345 kvm_static_assert(KVM_CPUID_##__reg == KVM_CPUID_EBX || \ 346 KVM_CPUID_##__reg == KVM_CPUID_ECX); \ 347 feature; \ 348 }) 349 350 #define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0) 351 #define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1) 352 #define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2) 353 #define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3) 354 #define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4) 355 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5) 356 #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6) 357 #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7) 358 #define X86_PMU_FEATURE_TOPDOWN_BE_BOUND KVM_X86_PMU_FEATURE(EBX, 8) 359 #define X86_PMU_FEATURE_TOPDOWN_BAD_SPEC KVM_X86_PMU_FEATURE(EBX, 9) 360 #define X86_PMU_FEATURE_TOPDOWN_FE_BOUND KVM_X86_PMU_FEATURE(EBX, 10) 361 #define X86_PMU_FEATURE_TOPDOWN_RETIRING KVM_X86_PMU_FEATURE(EBX, 11) 362 #define X86_PMU_FEATURE_LBR_INSERTS KVM_X86_PMU_FEATURE(EBX, 12) 363 364 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0) 365 #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1) 366 #define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2) 367 #define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3) 368 369 static inline unsigned int x86_family(unsigned int eax) 370 { 371 unsigned int x86; 372 373 x86 = (eax >> 8) & 0xf; 374 375 if (x86 == 0xf) 376 x86 += (eax >> 20) & 0xff; 377 378 return x86; 379 } 380 381 static inline unsigned int x86_model(unsigned int eax) 382 { 383 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); 384 } 385 386 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12) 387 388 #define PAGE_SHIFT 12 389 #define PAGE_SIZE (1ULL << PAGE_SHIFT) 390 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK) 391 392 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9)) 393 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x)) 394 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK) 395 396 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK) 397 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT) 398 399 /* General Registers in 64-Bit Mode */ 400 struct gpr64_regs { 401 u64 rax; 402 u64 rcx; 403 u64 rdx; 404 u64 rbx; 405 u64 rsp; 406 u64 rbp; 407 u64 rsi; 408 u64 rdi; 409 u64 r8; 410 u64 r9; 411 u64 r10; 412 u64 r11; 413 u64 r12; 414 u64 r13; 415 u64 r14; 416 u64 r15; 417 }; 418 419 struct desc64 { 420 u16 limit0; 421 u16 base0; 422 unsigned base1:8, type:4, s:1, dpl:2, p:1; 423 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8; 424 u32 base3; 425 u32 zero1; 426 } __attribute__((packed)); 427 428 struct desc_ptr { 429 u16 size; 430 u64 address; 431 } __attribute__((packed)); 432 433 struct kvm_x86_state { 434 struct kvm_xsave *xsave; 435 struct kvm_vcpu_events events; 436 struct kvm_mp_state mp_state; 437 struct kvm_regs regs; 438 struct kvm_xcrs xcrs; 439 struct kvm_sregs sregs; 440 struct kvm_debugregs debugregs; 441 union { 442 struct kvm_nested_state nested; 443 char nested_[16384]; 444 }; 445 struct kvm_msrs msrs; 446 }; 447 448 static inline u64 get_desc64_base(const struct desc64 *desc) 449 { 450 return (u64)desc->base3 << 32 | 451 (u64)desc->base2 << 24 | 452 (u64)desc->base1 << 16 | 453 (u64)desc->base0; 454 } 455 456 static inline u64 rdtsc(void) 457 { 458 u32 eax, edx; 459 u64 tsc_val; 460 /* 461 * The lfence is to wait (on Intel CPUs) until all previous 462 * instructions have been executed. If software requires RDTSC to be 463 * executed prior to execution of any subsequent instruction, it can 464 * execute LFENCE immediately after RDTSC 465 */ 466 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx)); 467 tsc_val = ((u64)edx) << 32 | eax; 468 return tsc_val; 469 } 470 471 static inline u64 rdtscp(u32 *aux) 472 { 473 u32 eax, edx; 474 475 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux)); 476 return ((u64)edx) << 32 | eax; 477 } 478 479 static inline u64 rdmsr(u32 msr) 480 { 481 u32 a, d; 482 483 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory"); 484 485 return a | ((u64)d << 32); 486 } 487 488 static inline void wrmsr(u32 msr, u64 value) 489 { 490 u32 a = value; 491 u32 d = value >> 32; 492 493 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory"); 494 } 495 496 497 static inline u16 inw(u16 port) 498 { 499 u16 tmp; 500 501 __asm__ __volatile__("in %%dx, %%ax" 502 : /* output */ "=a" (tmp) 503 : /* input */ "d" (port)); 504 505 return tmp; 506 } 507 508 static inline u16 get_es(void) 509 { 510 u16 es; 511 512 __asm__ __volatile__("mov %%es, %[es]" 513 : /* output */ [es]"=rm"(es)); 514 return es; 515 } 516 517 static inline u16 get_cs(void) 518 { 519 u16 cs; 520 521 __asm__ __volatile__("mov %%cs, %[cs]" 522 : /* output */ [cs]"=rm"(cs)); 523 return cs; 524 } 525 526 static inline u16 get_ss(void) 527 { 528 u16 ss; 529 530 __asm__ __volatile__("mov %%ss, %[ss]" 531 : /* output */ [ss]"=rm"(ss)); 532 return ss; 533 } 534 535 static inline u16 get_ds(void) 536 { 537 u16 ds; 538 539 __asm__ __volatile__("mov %%ds, %[ds]" 540 : /* output */ [ds]"=rm"(ds)); 541 return ds; 542 } 543 544 static inline u16 get_fs(void) 545 { 546 u16 fs; 547 548 __asm__ __volatile__("mov %%fs, %[fs]" 549 : /* output */ [fs]"=rm"(fs)); 550 return fs; 551 } 552 553 static inline u16 get_gs(void) 554 { 555 u16 gs; 556 557 __asm__ __volatile__("mov %%gs, %[gs]" 558 : /* output */ [gs]"=rm"(gs)); 559 return gs; 560 } 561 562 static inline u16 get_tr(void) 563 { 564 u16 tr; 565 566 __asm__ __volatile__("str %[tr]" 567 : /* output */ [tr]"=rm"(tr)); 568 return tr; 569 } 570 571 static inline u64 get_cr0(void) 572 { 573 u64 cr0; 574 575 __asm__ __volatile__("mov %%cr0, %[cr0]" 576 : /* output */ [cr0]"=r"(cr0)); 577 return cr0; 578 } 579 580 static inline void set_cr0(u64 val) 581 { 582 __asm__ __volatile__("mov %0, %%cr0" : : "r" (val) : "memory"); 583 } 584 585 static inline u64 get_cr3(void) 586 { 587 u64 cr3; 588 589 __asm__ __volatile__("mov %%cr3, %[cr3]" 590 : /* output */ [cr3]"=r"(cr3)); 591 return cr3; 592 } 593 594 static inline void set_cr3(u64 val) 595 { 596 __asm__ __volatile__("mov %0, %%cr3" : : "r" (val) : "memory"); 597 } 598 599 static inline u64 get_cr4(void) 600 { 601 u64 cr4; 602 603 __asm__ __volatile__("mov %%cr4, %[cr4]" 604 : /* output */ [cr4]"=r"(cr4)); 605 return cr4; 606 } 607 608 static inline void set_cr4(u64 val) 609 { 610 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory"); 611 } 612 613 static inline u64 get_cr8(void) 614 { 615 u64 cr8; 616 617 __asm__ __volatile__("mov %%cr8, %[cr8]" : [cr8]"=r"(cr8)); 618 return cr8; 619 } 620 621 static inline void set_cr8(u64 val) 622 { 623 __asm__ __volatile__("mov %0, %%cr8" : : "r" (val) : "memory"); 624 } 625 626 static inline void set_idt(const struct desc_ptr *idt_desc) 627 { 628 __asm__ __volatile__("lidt %0"::"m"(*idt_desc)); 629 } 630 631 static inline u64 xgetbv(u32 index) 632 { 633 u32 eax, edx; 634 635 __asm__ __volatile__("xgetbv;" 636 : "=a" (eax), "=d" (edx) 637 : "c" (index)); 638 return eax | ((u64)edx << 32); 639 } 640 641 static inline void xsetbv(u32 index, u64 value) 642 { 643 u32 eax = value; 644 u32 edx = value >> 32; 645 646 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index)); 647 } 648 649 static inline void wrpkru(u32 pkru) 650 { 651 /* Note, ECX and EDX are architecturally required to be '0'. */ 652 asm volatile(".byte 0x0f,0x01,0xef\n\t" 653 : : "a" (pkru), "c"(0), "d"(0)); 654 } 655 656 static inline struct desc_ptr get_gdt(void) 657 { 658 struct desc_ptr gdt; 659 __asm__ __volatile__("sgdt %[gdt]" 660 : /* output */ [gdt]"=m"(gdt)); 661 return gdt; 662 } 663 664 static inline struct desc_ptr get_idt(void) 665 { 666 struct desc_ptr idt; 667 __asm__ __volatile__("sidt %[idt]" 668 : /* output */ [idt]"=m"(idt)); 669 return idt; 670 } 671 672 static inline void outl(u16 port, u32 value) 673 { 674 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value)); 675 } 676 677 static inline void __cpuid(u32 function, u32 index, 678 u32 *eax, u32 *ebx, 679 u32 *ecx, u32 *edx) 680 { 681 *eax = function; 682 *ecx = index; 683 684 asm volatile("cpuid" 685 : "=a" (*eax), 686 "=b" (*ebx), 687 "=c" (*ecx), 688 "=d" (*edx) 689 : "0" (*eax), "2" (*ecx) 690 : "memory"); 691 } 692 693 static inline void cpuid(u32 function, 694 u32 *eax, u32 *ebx, 695 u32 *ecx, u32 *edx) 696 { 697 return __cpuid(function, 0, eax, ebx, ecx, edx); 698 } 699 700 static inline u32 this_cpu_fms(void) 701 { 702 u32 eax, ebx, ecx, edx; 703 704 cpuid(1, &eax, &ebx, &ecx, &edx); 705 return eax; 706 } 707 708 static inline u32 this_cpu_family(void) 709 { 710 return x86_family(this_cpu_fms()); 711 } 712 713 static inline u32 this_cpu_model(void) 714 { 715 return x86_model(this_cpu_fms()); 716 } 717 718 static inline bool this_cpu_vendor_string_is(const char *vendor) 719 { 720 const u32 *chunk = (const u32 *)vendor; 721 u32 eax, ebx, ecx, edx; 722 723 cpuid(0, &eax, &ebx, &ecx, &edx); 724 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]); 725 } 726 727 static inline bool this_cpu_is_intel(void) 728 { 729 return this_cpu_vendor_string_is("GenuineIntel"); 730 } 731 732 /* 733 * Exclude early K5 samples with a vendor string of "AMDisbetter!" 734 */ 735 static inline bool this_cpu_is_amd(void) 736 { 737 return this_cpu_vendor_string_is("AuthenticAMD"); 738 } 739 740 static inline bool this_cpu_is_hygon(void) 741 { 742 return this_cpu_vendor_string_is("HygonGenuine"); 743 } 744 745 static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi) 746 { 747 u32 gprs[4]; 748 749 __cpuid(function, index, 750 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX], 751 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]); 752 753 return (gprs[reg] & GENMASK(hi, lo)) >> lo; 754 } 755 756 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature) 757 { 758 return __this_cpu_has(feature.function, feature.index, 759 feature.reg, feature.bit, feature.bit); 760 } 761 762 static inline u32 this_cpu_property(struct kvm_x86_cpu_property property) 763 { 764 return __this_cpu_has(property.function, property.index, 765 property.reg, property.lo_bit, property.hi_bit); 766 } 767 768 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property) 769 { 770 u32 max_leaf; 771 772 switch (property.function & 0xc0000000) { 773 case 0: 774 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 775 break; 776 case 0x40000000: 777 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 778 break; 779 case 0x80000000: 780 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 781 break; 782 case 0xc0000000: 783 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 784 } 785 return max_leaf >= property.function; 786 } 787 788 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature) 789 { 790 u32 nr_bits; 791 792 if (feature.f.reg == KVM_CPUID_EBX) { 793 nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 794 return nr_bits > feature.f.bit && !this_cpu_has(feature.f); 795 } 796 797 GUEST_ASSERT(feature.f.reg == KVM_CPUID_ECX); 798 nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 799 return nr_bits > feature.f.bit || this_cpu_has(feature.f); 800 } 801 802 static __always_inline u64 this_cpu_supported_xcr0(void) 803 { 804 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 805 return 0; 806 807 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 808 ((u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 809 } 810 811 typedef u32 __attribute__((vector_size(16))) sse128_t; 812 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; } 813 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; }) 814 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; }) 815 816 static inline void read_sse_reg(int reg, sse128_t *data) 817 { 818 switch (reg) { 819 case 0: 820 asm("movdqa %%xmm0, %0" : "=m"(*data)); 821 break; 822 case 1: 823 asm("movdqa %%xmm1, %0" : "=m"(*data)); 824 break; 825 case 2: 826 asm("movdqa %%xmm2, %0" : "=m"(*data)); 827 break; 828 case 3: 829 asm("movdqa %%xmm3, %0" : "=m"(*data)); 830 break; 831 case 4: 832 asm("movdqa %%xmm4, %0" : "=m"(*data)); 833 break; 834 case 5: 835 asm("movdqa %%xmm5, %0" : "=m"(*data)); 836 break; 837 case 6: 838 asm("movdqa %%xmm6, %0" : "=m"(*data)); 839 break; 840 case 7: 841 asm("movdqa %%xmm7, %0" : "=m"(*data)); 842 break; 843 default: 844 BUG(); 845 } 846 } 847 848 static inline void write_sse_reg(int reg, const sse128_t *data) 849 { 850 switch (reg) { 851 case 0: 852 asm("movdqa %0, %%xmm0" : : "m"(*data)); 853 break; 854 case 1: 855 asm("movdqa %0, %%xmm1" : : "m"(*data)); 856 break; 857 case 2: 858 asm("movdqa %0, %%xmm2" : : "m"(*data)); 859 break; 860 case 3: 861 asm("movdqa %0, %%xmm3" : : "m"(*data)); 862 break; 863 case 4: 864 asm("movdqa %0, %%xmm4" : : "m"(*data)); 865 break; 866 case 5: 867 asm("movdqa %0, %%xmm5" : : "m"(*data)); 868 break; 869 case 6: 870 asm("movdqa %0, %%xmm6" : : "m"(*data)); 871 break; 872 case 7: 873 asm("movdqa %0, %%xmm7" : : "m"(*data)); 874 break; 875 default: 876 BUG(); 877 } 878 } 879 880 static inline void cpu_relax(void) 881 { 882 asm volatile("rep; nop" ::: "memory"); 883 } 884 885 static inline void udelay(unsigned long usec) 886 { 887 u64 start, now, cycles; 888 889 GUEST_ASSERT(guest_tsc_khz); 890 cycles = guest_tsc_khz / 1000 * usec; 891 892 /* 893 * Deliberately don't PAUSE, a.k.a. cpu_relax(), so that the delay is 894 * as accurate as possible, e.g. doesn't trigger PAUSE-Loop VM-Exits. 895 */ 896 start = rdtsc(); 897 do { 898 now = rdtsc(); 899 } while (now - start < cycles); 900 } 901 902 #define ud2() \ 903 __asm__ __volatile__( \ 904 "ud2\n" \ 905 ) 906 907 #define hlt() \ 908 __asm__ __volatile__( \ 909 "hlt\n" \ 910 ) 911 912 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu); 913 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state); 914 void kvm_x86_state_cleanup(struct kvm_x86_state *state); 915 916 const struct kvm_msr_list *kvm_get_msr_index_list(void); 917 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void); 918 bool kvm_msr_is_in_save_restore_list(u32 msr_index); 919 u64 kvm_get_feature_msr(u64 msr_index); 920 921 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu, 922 struct kvm_msrs *msrs) 923 { 924 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs); 925 926 TEST_ASSERT(r == msrs->nmsrs, 927 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)", 928 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 929 } 930 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs) 931 { 932 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs); 933 934 TEST_ASSERT(r == msrs->nmsrs, 935 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)", 936 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index); 937 } 938 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu, 939 struct kvm_debugregs *debugregs) 940 { 941 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs); 942 } 943 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu, 944 struct kvm_debugregs *debugregs) 945 { 946 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs); 947 } 948 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu, 949 struct kvm_xsave *xsave) 950 { 951 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave); 952 } 953 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu, 954 struct kvm_xsave *xsave) 955 { 956 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave); 957 } 958 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu, 959 struct kvm_xsave *xsave) 960 { 961 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave); 962 } 963 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu, 964 struct kvm_xcrs *xcrs) 965 { 966 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs); 967 } 968 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs) 969 { 970 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs); 971 } 972 973 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid, 974 u32 function, u32 index); 975 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void); 976 977 static inline u32 kvm_cpu_fms(void) 978 { 979 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax; 980 } 981 982 static inline u32 kvm_cpu_family(void) 983 { 984 return x86_family(kvm_cpu_fms()); 985 } 986 987 static inline u32 kvm_cpu_model(void) 988 { 989 return x86_model(kvm_cpu_fms()); 990 } 991 992 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid, 993 struct kvm_x86_cpu_feature feature); 994 995 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature) 996 { 997 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature); 998 } 999 1000 u32 kvm_cpuid_property(const struct kvm_cpuid2 *cpuid, 1001 struct kvm_x86_cpu_property property); 1002 1003 static inline u32 kvm_cpu_property(struct kvm_x86_cpu_property property) 1004 { 1005 return kvm_cpuid_property(kvm_get_supported_cpuid(), property); 1006 } 1007 1008 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property) 1009 { 1010 u32 max_leaf; 1011 1012 switch (property.function & 0xc0000000) { 1013 case 0: 1014 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF); 1015 break; 1016 case 0x40000000: 1017 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF); 1018 break; 1019 case 0x80000000: 1020 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF); 1021 break; 1022 case 0xc0000000: 1023 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF); 1024 } 1025 return max_leaf >= property.function; 1026 } 1027 1028 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature) 1029 { 1030 u32 nr_bits; 1031 1032 if (feature.f.reg == KVM_CPUID_EBX) { 1033 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH); 1034 return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f); 1035 } 1036 1037 TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX); 1038 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS); 1039 return nr_bits > feature.f.bit || kvm_cpu_has(feature.f); 1040 } 1041 1042 static __always_inline u64 kvm_cpu_supported_xcr0(void) 1043 { 1044 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO)) 1045 return 0; 1046 1047 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) | 1048 ((u64)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32); 1049 } 1050 1051 static inline size_t kvm_cpuid2_size(int nr_entries) 1052 { 1053 return sizeof(struct kvm_cpuid2) + 1054 sizeof(struct kvm_cpuid_entry2) * nr_entries; 1055 } 1056 1057 /* 1058 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of 1059 * entries sized to hold @nr_entries. The caller is responsible for freeing 1060 * the struct. 1061 */ 1062 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries) 1063 { 1064 struct kvm_cpuid2 *cpuid; 1065 1066 cpuid = malloc(kvm_cpuid2_size(nr_entries)); 1067 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2"); 1068 1069 cpuid->nent = nr_entries; 1070 1071 return cpuid; 1072 } 1073 1074 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid); 1075 1076 static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu) 1077 { 1078 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid); 1079 } 1080 1081 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1082 u32 function, 1083 u32 index) 1084 { 1085 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)"); 1086 1087 vcpu_get_cpuid(vcpu); 1088 1089 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid, 1090 function, index); 1091 } 1092 1093 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu, 1094 u32 function) 1095 { 1096 return __vcpu_get_cpuid_entry(vcpu, function, 0); 1097 } 1098 1099 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1100 { 1101 int r; 1102 1103 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1104 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1105 if (r) 1106 return r; 1107 1108 /* On success, refresh the cache to pick up adjustments made by KVM. */ 1109 vcpu_get_cpuid(vcpu); 1110 return 0; 1111 } 1112 1113 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu) 1114 { 1115 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first"); 1116 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid); 1117 1118 /* Refresh the cache to pick up adjustments made by KVM. */ 1119 vcpu_get_cpuid(vcpu); 1120 } 1121 1122 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu, 1123 struct kvm_x86_cpu_property property, 1124 u32 value); 1125 void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, u8 maxphyaddr); 1126 1127 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, u32 function); 1128 1129 static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu, 1130 struct kvm_x86_cpu_feature feature) 1131 { 1132 struct kvm_cpuid_entry2 *entry; 1133 1134 entry = __vcpu_get_cpuid_entry(vcpu, feature.function, feature.index); 1135 return *((&entry->eax) + feature.reg) & BIT(feature.bit); 1136 } 1137 1138 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1139 struct kvm_x86_cpu_feature feature, 1140 bool set); 1141 1142 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu, 1143 struct kvm_x86_cpu_feature feature) 1144 { 1145 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true); 1146 1147 } 1148 1149 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu, 1150 struct kvm_x86_cpu_feature feature) 1151 { 1152 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false); 1153 } 1154 1155 u64 vcpu_get_msr(struct kvm_vcpu *vcpu, u64 msr_index); 1156 int _vcpu_set_msr(struct kvm_vcpu *vcpu, u64 msr_index, u64 msr_value); 1157 1158 /* 1159 * Assert on an MSR access(es) and pretty print the MSR name when possible. 1160 * Note, the caller provides the stringified name so that the name of macro is 1161 * printed, not the value the macro resolves to (due to macro expansion). 1162 */ 1163 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \ 1164 do { \ 1165 if (__builtin_constant_p(msr)) { \ 1166 TEST_ASSERT(cond, fmt, str, args); \ 1167 } else if (!(cond)) { \ 1168 char buf[16]; \ 1169 \ 1170 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \ 1171 TEST_ASSERT(cond, fmt, buf, args); \ 1172 } \ 1173 } while (0) 1174 1175 /* 1176 * Returns true if KVM should return the last written value when reading an MSR 1177 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that 1178 * is changing, etc. This is NOT an exhaustive list! The intent is to filter 1179 * out MSRs that are not durable _and_ that a selftest wants to write. 1180 */ 1181 static inline bool is_durable_msr(u32 msr) 1182 { 1183 return msr != MSR_IA32_TSC; 1184 } 1185 1186 #define vcpu_set_msr(vcpu, msr, val) \ 1187 do { \ 1188 u64 r, v = val; \ 1189 \ 1190 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \ 1191 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \ 1192 if (!is_durable_msr(msr)) \ 1193 break; \ 1194 r = vcpu_get_msr(vcpu, msr); \ 1195 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\ 1196 } while (0) 1197 1198 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); 1199 void kvm_init_vm_address_properties(struct kvm_vm *vm); 1200 1201 struct ex_regs { 1202 u64 rax, rcx, rdx, rbx; 1203 u64 rbp, rsi, rdi; 1204 u64 r8, r9, r10, r11; 1205 u64 r12, r13, r14, r15; 1206 u64 vector; 1207 u64 error_code; 1208 u64 rip; 1209 u64 cs; 1210 u64 rflags; 1211 }; 1212 1213 struct idt_entry { 1214 u16 offset0; 1215 u16 selector; 1216 u16 ist : 3; 1217 u16 : 5; 1218 u16 type : 4; 1219 u16 : 1; 1220 u16 dpl : 2; 1221 u16 p : 1; 1222 u16 offset1; 1223 u32 offset2; u32 reserved; 1224 }; 1225 1226 void vm_install_exception_handler(struct kvm_vm *vm, int vector, 1227 void (*handler)(struct ex_regs *)); 1228 1229 /* 1230 * Exception fixup morphs #DE to an arbitrary magic vector so that '0' can be 1231 * used to signal "no expcetion". 1232 */ 1233 #define KVM_MAGIC_DE_VECTOR 0xff 1234 1235 /* If a toddler were to say "abracadabra". */ 1236 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL 1237 1238 /* 1239 * KVM selftest exception fixup uses registers to coordinate with the exception 1240 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory 1241 * per-CPU data. Using only registers avoids having to map memory into the 1242 * guest, doesn't require a valid, stable GS.base, and reduces the risk of 1243 * for recursive faults when accessing memory in the handler. The downside to 1244 * using registers is that it restricts what registers can be used by the actual 1245 * instruction. But, selftests are 64-bit only, making register* pressure a 1246 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved 1247 * by the callee, and except for r11 are not implicit parameters to any 1248 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit 1249 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V 1250 * is higher priority than testing non-faulting SYSCALL/SYSRET. 1251 * 1252 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector 1253 * is guaranteed to be non-zero on fault. 1254 * 1255 * REGISTER INPUTS: 1256 * r9 = MAGIC 1257 * r10 = RIP 1258 * r11 = new RIP on fault 1259 * 1260 * REGISTER OUTPUTS: 1261 * r9 = exception vector (non-zero) 1262 * r10 = error code 1263 */ 1264 #define __KVM_ASM_SAFE(insn, fep) \ 1265 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \ 1266 "lea 1f(%%rip), %%r10\n\t" \ 1267 "lea 2f(%%rip), %%r11\n\t" \ 1268 fep "1: " insn "\n\t" \ 1269 "xor %%r9, %%r9\n\t" \ 1270 "2:\n\t" \ 1271 "mov %%r9b, %[vector]\n\t" \ 1272 "mov %%r10, %[error_code]\n\t" 1273 1274 #define KVM_ASM_SAFE(insn) __KVM_ASM_SAFE(insn, "") 1275 #define KVM_ASM_SAFE_FEP(insn) __KVM_ASM_SAFE(insn, KVM_FEP) 1276 1277 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec) 1278 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11" 1279 1280 #define kvm_asm_safe(insn, inputs...) \ 1281 ({ \ 1282 u64 ign_error_code; \ 1283 u8 vector; \ 1284 \ 1285 asm volatile(KVM_ASM_SAFE(insn) \ 1286 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1287 : inputs \ 1288 : KVM_ASM_SAFE_CLOBBERS); \ 1289 vector; \ 1290 }) 1291 1292 #define kvm_asm_safe_ec(insn, error_code, inputs...) \ 1293 ({ \ 1294 u8 vector; \ 1295 \ 1296 asm volatile(KVM_ASM_SAFE(insn) \ 1297 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1298 : inputs \ 1299 : KVM_ASM_SAFE_CLOBBERS); \ 1300 vector; \ 1301 }) 1302 1303 #define kvm_asm_safe_fep(insn, inputs...) \ 1304 ({ \ 1305 u64 ign_error_code; \ 1306 u8 vector; \ 1307 \ 1308 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1309 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \ 1310 : inputs \ 1311 : KVM_ASM_SAFE_CLOBBERS); \ 1312 vector; \ 1313 }) 1314 1315 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \ 1316 ({ \ 1317 u8 vector; \ 1318 \ 1319 asm volatile(KVM_ASM_SAFE_FEP(insn) \ 1320 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1321 : inputs \ 1322 : KVM_ASM_SAFE_CLOBBERS); \ 1323 vector; \ 1324 }) 1325 1326 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1327 static inline u8 insn##_safe ##_fep(u32 idx, u64 *val) \ 1328 { \ 1329 u64 error_code; \ 1330 u8 vector; \ 1331 u32 a, d; \ 1332 \ 1333 asm volatile(KVM_ASM_SAFE##_FEP(#insn) \ 1334 : "=a"(a), "=d"(d), \ 1335 KVM_ASM_SAFE_OUTPUTS(vector, error_code) \ 1336 : "c"(idx) \ 1337 : KVM_ASM_SAFE_CLOBBERS); \ 1338 \ 1339 *val = (u64)a | ((u64)d << 32); \ 1340 return vector; \ 1341 } 1342 1343 /* 1344 * Generate {insn}_safe() and {insn}_safe_fep() helpers for instructions that 1345 * use ECX as in input index, and EDX:EAX as a 64-bit output. 1346 */ 1347 #define BUILD_READ_U64_SAFE_HELPERS(insn) \ 1348 BUILD_READ_U64_SAFE_HELPER(insn, , ) \ 1349 BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \ 1350 1351 BUILD_READ_U64_SAFE_HELPERS(rdmsr) 1352 BUILD_READ_U64_SAFE_HELPERS(rdpmc) 1353 BUILD_READ_U64_SAFE_HELPERS(xgetbv) 1354 1355 static inline u8 wrmsr_safe(u32 msr, u64 val) 1356 { 1357 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr)); 1358 } 1359 1360 static inline u8 xsetbv_safe(u32 index, u64 value) 1361 { 1362 u32 eax = value; 1363 u32 edx = value >> 32; 1364 1365 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index)); 1366 } 1367 1368 bool kvm_is_tdp_enabled(void); 1369 1370 static inline bool get_kvm_intel_param_bool(const char *param) 1371 { 1372 return kvm_get_module_param_bool("kvm_intel", param); 1373 } 1374 1375 static inline bool get_kvm_amd_param_bool(const char *param) 1376 { 1377 return kvm_get_module_param_bool("kvm_amd", param); 1378 } 1379 1380 static inline int get_kvm_intel_param_integer(const char *param) 1381 { 1382 return kvm_get_module_param_integer("kvm_intel", param); 1383 } 1384 1385 static inline int get_kvm_amd_param_integer(const char *param) 1386 { 1387 return kvm_get_module_param_integer("kvm_amd", param); 1388 } 1389 1390 static inline bool kvm_is_pmu_enabled(void) 1391 { 1392 return get_kvm_param_bool("enable_pmu"); 1393 } 1394 1395 static inline bool kvm_is_forced_emulation_enabled(void) 1396 { 1397 return !!get_kvm_param_integer("force_emulation_prefix"); 1398 } 1399 1400 static inline bool kvm_is_unrestricted_guest_enabled(void) 1401 { 1402 return get_kvm_intel_param_bool("unrestricted_guest"); 1403 } 1404 1405 static inline bool kvm_is_ignore_msrs(void) 1406 { 1407 return get_kvm_param_bool("ignore_msrs"); 1408 } 1409 1410 static inline bool kvm_is_lbrv_enabled(void) 1411 { 1412 return !!get_kvm_amd_param_integer("lbrv"); 1413 } 1414 1415 u64 *vm_get_pte(struct kvm_vm *vm, gva_t gva); 1416 1417 u64 kvm_hypercall(u64 nr, u64 a0, u64 a1, u64 a2, u64 a3); 1418 u64 __xen_hypercall(u64 nr, u64 a0, void *a1); 1419 void xen_hypercall(u64 nr, u64 a0, void *a1); 1420 1421 static inline u64 __kvm_hypercall_map_gpa_range(gpa_t gpa, u64 size, u64 flags) 1422 { 1423 return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0); 1424 } 1425 1426 static inline void kvm_hypercall_map_gpa_range(gpa_t gpa, u64 size, u64 flags) 1427 { 1428 u64 ret = __kvm_hypercall_map_gpa_range(gpa, size, flags); 1429 1430 GUEST_ASSERT(!ret); 1431 } 1432 1433 /* 1434 * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's 1435 * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, 1436 * except for a few oddballs that KVM is unlikely to run on, block IRQs for one 1437 * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may 1438 * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. 1439 */ 1440 static inline void safe_halt(void) 1441 { 1442 asm volatile("sti; hlt"); 1443 } 1444 1445 /* 1446 * Enable interrupts and ensure that interrupts are evaluated upon return from 1447 * this function, i.e. execute a nop to consume the STi interrupt shadow. 1448 */ 1449 static inline void sti_nop(void) 1450 { 1451 asm volatile ("sti; nop"); 1452 } 1453 1454 /* 1455 * Enable interrupts for one instruction (nop), to allow the CPU to process all 1456 * interrupts that are already pending. 1457 */ 1458 static inline void sti_nop_cli(void) 1459 { 1460 asm volatile ("sti; nop; cli"); 1461 } 1462 1463 static inline void sti(void) 1464 { 1465 asm volatile("sti"); 1466 } 1467 1468 static inline void cli(void) 1469 { 1470 asm volatile ("cli"); 1471 } 1472 1473 void __vm_xsave_require_permission(u64 xfeature, const char *name); 1474 1475 #define vm_xsave_require_permission(xfeature) \ 1476 __vm_xsave_require_permission(xfeature, #xfeature) 1477 1478 enum pg_level { 1479 PG_LEVEL_NONE, 1480 PG_LEVEL_4K, 1481 PG_LEVEL_2M, 1482 PG_LEVEL_1G, 1483 PG_LEVEL_512G, 1484 PG_LEVEL_256T 1485 }; 1486 1487 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12) 1488 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level)) 1489 1490 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K) 1491 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M) 1492 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G) 1493 1494 #define PTE_PRESENT_MASK(mmu) ((mmu)->arch.pte_masks.present) 1495 #define PTE_WRITABLE_MASK(mmu) ((mmu)->arch.pte_masks.writable) 1496 #define PTE_USER_MASK(mmu) ((mmu)->arch.pte_masks.user) 1497 #define PTE_READABLE_MASK(mmu) ((mmu)->arch.pte_masks.readable) 1498 #define PTE_EXECUTABLE_MASK(mmu) ((mmu)->arch.pte_masks.executable) 1499 #define PTE_ACCESSED_MASK(mmu) ((mmu)->arch.pte_masks.accessed) 1500 #define PTE_DIRTY_MASK(mmu) ((mmu)->arch.pte_masks.dirty) 1501 #define PTE_HUGE_MASK(mmu) ((mmu)->arch.pte_masks.huge) 1502 #define PTE_NX_MASK(mmu) ((mmu)->arch.pte_masks.nx) 1503 #define PTE_C_BIT_MASK(mmu) ((mmu)->arch.pte_masks.c) 1504 #define PTE_S_BIT_MASK(mmu) ((mmu)->arch.pte_masks.s) 1505 #define PTE_ALWAYS_SET_MASK(mmu) ((mmu)->arch.pte_masks.always_set) 1506 1507 /* 1508 * For PTEs without a PRESENT bit (i.e. EPT entries), treat the PTE as present 1509 * if it's executable or readable, as EPT supports execute-only PTEs, but not 1510 * write-only PTEs. 1511 */ 1512 #define is_present_pte(mmu, pte) \ 1513 (PTE_PRESENT_MASK(mmu) ? \ 1514 !!(*(pte) & PTE_PRESENT_MASK(mmu)) : \ 1515 !!(*(pte) & (PTE_READABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu)))) 1516 #define is_executable_pte(mmu, pte) \ 1517 ((*(pte) & (PTE_EXECUTABLE_MASK(mmu) | PTE_NX_MASK(mmu))) == PTE_EXECUTABLE_MASK(mmu)) 1518 #define is_writable_pte(mmu, pte) (!!(*(pte) & PTE_WRITABLE_MASK(mmu))) 1519 #define is_user_pte(mmu, pte) (!!(*(pte) & PTE_USER_MASK(mmu))) 1520 #define is_accessed_pte(mmu, pte) (!!(*(pte) & PTE_ACCESSED_MASK(mmu))) 1521 #define is_dirty_pte(mmu, pte) (!!(*(pte) & PTE_DIRTY_MASK(mmu))) 1522 #define is_huge_pte(mmu, pte) (!!(*(pte) & PTE_HUGE_MASK(mmu))) 1523 #define is_nx_pte(mmu, pte) (!is_executable_pte(mmu, pte)) 1524 1525 void tdp_mmu_init(struct kvm_vm *vm, int pgtable_levels, 1526 struct pte_masks *pte_masks); 1527 1528 void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, gva_t gva, 1529 gpa_t gpa, int level); 1530 void virt_map_level(struct kvm_vm *vm, gva_t gva, gpa_t gpa, 1531 u64 nr_bytes, int level); 1532 1533 void vm_enable_tdp(struct kvm_vm *vm); 1534 bool kvm_cpu_has_tdp(void); 1535 void tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size); 1536 void tdp_identity_map_default_memslots(struct kvm_vm *vm); 1537 void tdp_identity_map_1g(struct kvm_vm *vm, u64 addr, u64 size); 1538 u64 *tdp_get_pte(struct kvm_vm *vm, u64 l2_gpa); 1539 1540 /* 1541 * Basic CPU control in CR0 1542 */ 1543 #define X86_CR0_PE (1UL<<0) /* Protection Enable */ 1544 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */ 1545 #define X86_CR0_EM (1UL<<2) /* Emulation */ 1546 #define X86_CR0_TS (1UL<<3) /* Task Switched */ 1547 #define X86_CR0_ET (1UL<<4) /* Extension Type */ 1548 #define X86_CR0_NE (1UL<<5) /* Numeric Error */ 1549 #define X86_CR0_WP (1UL<<16) /* Write Protect */ 1550 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */ 1551 #define X86_CR0_NW (1UL<<29) /* Not Write-through */ 1552 #define X86_CR0_CD (1UL<<30) /* Cache Disable */ 1553 #define X86_CR0_PG (1UL<<31) /* Paging */ 1554 1555 #define PFERR_PRESENT_BIT 0 1556 #define PFERR_WRITE_BIT 1 1557 #define PFERR_USER_BIT 2 1558 #define PFERR_RSVD_BIT 3 1559 #define PFERR_FETCH_BIT 4 1560 #define PFERR_PK_BIT 5 1561 #define PFERR_SGX_BIT 15 1562 #define PFERR_GUEST_FINAL_BIT 32 1563 #define PFERR_GUEST_PAGE_BIT 33 1564 #define PFERR_IMPLICIT_ACCESS_BIT 48 1565 1566 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) 1567 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) 1568 #define PFERR_USER_MASK BIT(PFERR_USER_BIT) 1569 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT) 1570 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT) 1571 #define PFERR_PK_MASK BIT(PFERR_PK_BIT) 1572 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT) 1573 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) 1574 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) 1575 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) 1576 1577 #define EPT_VIOLATION_ACC_READ BIT(0) 1578 #define EPT_VIOLATION_ACC_WRITE BIT(1) 1579 #define EPT_VIOLATION_ACC_INSTR BIT(2) 1580 #define EPT_VIOLATION_PROT_READ BIT(3) 1581 #define EPT_VIOLATION_PROT_WRITE BIT(4) 1582 #define EPT_VIOLATION_PROT_EXEC BIT(5) 1583 #define EPT_VIOLATION_GVA_IS_VALID BIT(7) 1584 #define EPT_VIOLATION_GVA_TRANSLATED BIT(8) 1585 1586 bool sys_clocksource_is_based_on_tsc(void); 1587 1588 #endif /* SELFTEST_KVM_PROCESSOR_H */ 1589