1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 MediaTek Inc. 4 */ 5 6 #ifndef _UFS_MEDIATEK_H 7 #define _UFS_MEDIATEK_H 8 9 #include <linux/bitops.h> 10 11 /* 12 * MCQ define and struct 13 */ 14 #define UFSHCD_MAX_Q_NR 8 15 #define MTK_MCQ_INVALID_IRQ 0xFFFF 16 17 /* REG_UFS_MMIO_OPT_CTRL_0 160h */ 18 #define EHS_EN BIT(0) 19 #define PFM_IMPV BIT(1) 20 #define MCQ_MULTI_INTR_EN BIT(2) 21 #define MCQ_CMB_INTR_EN BIT(3) 22 #define MCQ_AH8 BIT(4) 23 24 #define MCQ_INTR_EN_MSK (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN) 25 26 /* 27 * Vendor specific UFSHCI Registers 28 */ 29 #define REG_UFS_XOUFS_CTRL 0x140 30 #define REG_UFS_REFCLK_CTRL 0x144 31 #define REG_UFS_MMIO_OPT_CTRL_0 0x160 32 #define REG_UFS_EXTREG 0x2100 33 #define REG_UFS_MPHYCTRL 0x2200 34 #define REG_UFS_MTK_IP_VER 0x2240 35 #define REG_UFS_REJECT_MON 0x22AC 36 #define REG_UFS_DEBUG_SEL 0x22C0 37 #define REG_UFS_PROBE 0x22C8 38 #define REG_UFS_DEBUG_SEL_B0 0x22D0 39 #define REG_UFS_DEBUG_SEL_B1 0x22D4 40 #define REG_UFS_DEBUG_SEL_B2 0x22D8 41 #define REG_UFS_DEBUG_SEL_B3 0x22DC 42 43 #define REG_UFS_MTK_SQD 0x2800 44 #define REG_UFS_MTK_SQIS 0x2814 45 #define REG_UFS_MTK_CQD 0x281C 46 #define REG_UFS_MTK_CQIS 0x2824 47 48 #define REG_UFS_MCQ_STRIDE 0x30 49 50 /* 51 * Ref-clk control 52 * 53 * Values for register REG_UFS_REFCLK_CTRL 54 */ 55 #define REFCLK_RELEASE 0x0 56 #define REFCLK_REQUEST BIT(0) 57 #define REFCLK_ACK BIT(1) 58 59 #define REFCLK_REQ_TIMEOUT_US 3000 60 #define REFCLK_DEFAULT_WAIT_US 32 61 62 /* 63 * Other attributes 64 */ 65 #define VS_DEBUGCLOCKENABLE 0xD0A1 66 #define VS_SAVEPOWERCONTROL 0xD0A6 67 #define VS_UNIPROPOWERDOWNCONTROL 0xD0A8 68 69 /* 70 * Vendor specific link state 71 */ 72 enum { 73 VS_LINK_DISABLED = 0, 74 VS_LINK_DOWN = 1, 75 VS_LINK_UP = 2, 76 VS_LINK_HIBERN8 = 3, 77 VS_LINK_LOST = 4, 78 VS_LINK_CFG = 5, 79 }; 80 81 /* 82 * Vendor specific host controller state 83 */ 84 enum { 85 VS_HCE_RESET = 0, 86 VS_HCE_BASE = 1, 87 VS_HCE_OOCPR_WAIT = 2, 88 VS_HCE_DME_RESET = 3, 89 VS_HCE_MIDDLE = 4, 90 VS_HCE_DME_ENABLE = 5, 91 VS_HCE_DEFAULTS = 6, 92 VS_HIB_IDLEEN = 7, 93 VS_HIB_ENTER = 8, 94 VS_HIB_ENTER_CONF = 9, 95 VS_HIB_MIDDLE = 10, 96 VS_HIB_WAITTIMER = 11, 97 VS_HIB_EXIT_CONF = 12, 98 VS_HIB_EXIT = 13, 99 }; 100 101 /* 102 * VS_DEBUGCLOCKENABLE 103 */ 104 enum { 105 TX_SYMBOL_CLK_REQ_FORCE = 5, 106 }; 107 108 /* 109 * VS_SAVEPOWERCONTROL 110 */ 111 enum { 112 RX_SYMBOL_CLK_GATE_EN = 0, 113 SYS_CLK_GATE_EN = 2, 114 TX_CLK_GATE_EN = 3, 115 }; 116 117 /* 118 * Host capability 119 */ 120 enum ufs_mtk_host_caps { 121 UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0, 122 UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1, 123 UFS_MTK_CAP_DISABLE_AH8 = 1 << 2, 124 UFS_MTK_CAP_BROKEN_VCC = 1 << 3, 125 126 /* 127 * Override UFS_MTK_CAP_BROKEN_VCC's behavior to 128 * allow vccqx upstream to enter LPM 129 */ 130 UFS_MTK_CAP_ALLOW_VCCQX_LPM = 1 << 5, 131 UFS_MTK_CAP_PMC_VIA_FASTAUTO = 1 << 6, 132 UFS_MTK_CAP_TX_SKEW_FIX = 1 << 7, 133 UFS_MTK_CAP_DISABLE_MCQ = 1 << 8, 134 /* Control MTCMOS with RTFF */ 135 UFS_MTK_CAP_RTFF_MTCMOS = 1 << 9, 136 }; 137 138 struct ufs_mtk_crypt_cfg { 139 struct regulator *reg_vcore; 140 struct clk *clk_crypt_perf; 141 struct clk *clk_crypt_mux; 142 struct clk *clk_crypt_lp; 143 int vcore_volt; 144 }; 145 146 struct ufs_mtk_clk { 147 struct ufs_clk_info *ufs_sel_clki; /* Mux */ 148 struct ufs_clk_info *ufs_sel_max_clki; /* Max src */ 149 struct ufs_clk_info *ufs_sel_min_clki; /* Min src */ 150 }; 151 152 struct ufs_mtk_hw_ver { 153 u8 step; 154 u8 minor; 155 u8 major; 156 }; 157 158 struct ufs_mtk_mcq_intr_info { 159 struct ufs_hba *hba; 160 u32 irq; 161 u8 qid; 162 }; 163 164 struct ufs_mtk_host { 165 struct phy *mphy; 166 struct regulator *reg_va09; 167 struct reset_control *hci_reset; 168 struct reset_control *unipro_reset; 169 struct reset_control *crypto_reset; 170 struct reset_control *mphy_reset; 171 struct ufs_hba *hba; 172 struct ufs_mtk_crypt_cfg *crypt; 173 struct ufs_mtk_clk mclk; 174 struct ufs_mtk_hw_ver hw_ver; 175 enum ufs_mtk_host_caps caps; 176 bool mphy_powered_on; 177 bool unipro_lpm; 178 bool ref_clk_enabled; 179 u16 ref_clk_ungating_wait_us; 180 u16 ref_clk_gating_wait_us; 181 u32 ip_ver; 182 183 bool mcq_set_intr; 184 bool is_mcq_intr_enabled; 185 int mcq_nr_intr; 186 struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR]; 187 }; 188 189 /* MTK delay of autosuspend: 500 ms */ 190 #define MTK_RPM_AUTOSUSPEND_DELAY_MS 500 191 192 /* MTK RTT support number */ 193 #define MTK_MAX_NUM_RTT 2 194 195 #endif /* !_UFS_MEDIATEK_H */ 196