1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Linutronix GmbH, Thomas Gleixner <tglx@kernel.org> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * 43 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 44 * AA: hardware event ID 45 * EEEEEEEE: PMU type ID 46 * 47 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 48 * BB: hardware cache ID 49 * CC: hardware cache op ID 50 * DD: hardware cache op result ID 51 * EEEEEEEE: PMU type ID 52 * 53 * If the PMU type ID is 0, PERF_TYPE_RAW will be applied. 54 */ 55 #define PERF_PMU_TYPE_SHIFT 32 56 #define PERF_HW_EVENT_MASK 0xffffffff 57 58 /* 59 * Generalized performance event event_id types, used by the 60 * attr.event_id parameter of the sys_perf_event_open() 61 * syscall: 62 */ 63 enum perf_hw_id { 64 /* 65 * Common hardware events, generalized by the kernel: 66 */ 67 PERF_COUNT_HW_CPU_CYCLES = 0, 68 PERF_COUNT_HW_INSTRUCTIONS = 1, 69 PERF_COUNT_HW_CACHE_REFERENCES = 2, 70 PERF_COUNT_HW_CACHE_MISSES = 3, 71 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 72 PERF_COUNT_HW_BRANCH_MISSES = 5, 73 PERF_COUNT_HW_BUS_CYCLES = 6, 74 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 75 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 76 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 77 78 PERF_COUNT_HW_MAX, /* non-ABI */ 79 }; 80 81 /* 82 * Generalized hardware cache events: 83 * 84 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 85 * { read, write, prefetch } x 86 * { accesses, misses } 87 */ 88 enum perf_hw_cache_id { 89 PERF_COUNT_HW_CACHE_L1D = 0, 90 PERF_COUNT_HW_CACHE_L1I = 1, 91 PERF_COUNT_HW_CACHE_LL = 2, 92 PERF_COUNT_HW_CACHE_DTLB = 3, 93 PERF_COUNT_HW_CACHE_ITLB = 4, 94 PERF_COUNT_HW_CACHE_BPU = 5, 95 PERF_COUNT_HW_CACHE_NODE = 6, 96 97 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 98 }; 99 100 enum perf_hw_cache_op_id { 101 PERF_COUNT_HW_CACHE_OP_READ = 0, 102 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 103 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 104 105 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 106 }; 107 108 enum perf_hw_cache_op_result_id { 109 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 110 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 111 112 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 113 }; 114 115 /* 116 * Special "software" events provided by the kernel, even if the hardware 117 * does not support performance events. These events measure various 118 * physical and SW events of the kernel (and allow the profiling of them as 119 * well): 120 */ 121 enum perf_sw_ids { 122 PERF_COUNT_SW_CPU_CLOCK = 0, 123 PERF_COUNT_SW_TASK_CLOCK = 1, 124 PERF_COUNT_SW_PAGE_FAULTS = 2, 125 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 126 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 127 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 128 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 129 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 130 PERF_COUNT_SW_EMULATION_FAULTS = 8, 131 PERF_COUNT_SW_DUMMY = 9, 132 PERF_COUNT_SW_BPF_OUTPUT = 10, 133 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 134 135 PERF_COUNT_SW_MAX, /* non-ABI */ 136 }; 137 138 /* 139 * Bits that can be set in attr.sample_type to request information 140 * in the overflow packets. 141 */ 142 enum perf_event_sample_format { 143 PERF_SAMPLE_IP = 1U << 0, 144 PERF_SAMPLE_TID = 1U << 1, 145 PERF_SAMPLE_TIME = 1U << 2, 146 PERF_SAMPLE_ADDR = 1U << 3, 147 PERF_SAMPLE_READ = 1U << 4, 148 PERF_SAMPLE_CALLCHAIN = 1U << 5, 149 PERF_SAMPLE_ID = 1U << 6, 150 PERF_SAMPLE_CPU = 1U << 7, 151 PERF_SAMPLE_PERIOD = 1U << 8, 152 PERF_SAMPLE_STREAM_ID = 1U << 9, 153 PERF_SAMPLE_RAW = 1U << 10, 154 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 155 PERF_SAMPLE_REGS_USER = 1U << 12, 156 PERF_SAMPLE_STACK_USER = 1U << 13, 157 PERF_SAMPLE_WEIGHT = 1U << 14, 158 PERF_SAMPLE_DATA_SRC = 1U << 15, 159 PERF_SAMPLE_IDENTIFIER = 1U << 16, 160 PERF_SAMPLE_TRANSACTION = 1U << 17, 161 PERF_SAMPLE_REGS_INTR = 1U << 18, 162 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 163 PERF_SAMPLE_AUX = 1U << 20, 164 PERF_SAMPLE_CGROUP = 1U << 21, 165 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 166 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 167 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 168 169 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 170 }; 171 172 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 173 174 /* 175 * Values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set. 176 * 177 * If the user does not pass priv level information via branch_sample_type, 178 * the kernel uses the event's priv level. Branch and event priv levels do 179 * not have to match. Branch priv level is checked for permissions. 180 * 181 * The branch types can be combined, however BRANCH_ANY covers all types 182 * of branches and therefore it supersedes all the other types. 183 */ 184 enum perf_branch_sample_type_shift { 185 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 186 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 187 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 188 189 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 190 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 191 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 192 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 193 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 194 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 195 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 196 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 197 198 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* CALL/RET stack */ 199 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 200 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 201 202 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 203 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 204 205 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 206 207 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 208 209 PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18, /* save privilege mode */ 210 211 PERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19, /* save occurrences of events on a branch */ 212 213 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 214 }; 215 216 enum perf_branch_sample_type { 217 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 218 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 219 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 220 221 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 222 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 223 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 224 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 225 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 226 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 227 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 228 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 229 230 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 231 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 232 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 233 234 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 235 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 236 237 PERF_SAMPLE_BRANCH_TYPE_SAVE = 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 238 239 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 240 241 PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT, 242 243 PERF_SAMPLE_BRANCH_COUNTERS = 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT, 244 245 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 246 }; 247 248 /* 249 * Common control flow change classifications: 250 */ 251 enum { 252 PERF_BR_UNKNOWN = 0, /* Unknown */ 253 PERF_BR_COND = 1, /* Conditional */ 254 PERF_BR_UNCOND = 2, /* Unconditional */ 255 PERF_BR_IND = 3, /* Indirect */ 256 PERF_BR_CALL = 4, /* Function call */ 257 PERF_BR_IND_CALL = 5, /* Indirect function call */ 258 PERF_BR_RET = 6, /* Function return */ 259 PERF_BR_SYSCALL = 7, /* Syscall */ 260 PERF_BR_SYSRET = 8, /* Syscall return */ 261 PERF_BR_COND_CALL = 9, /* Conditional function call */ 262 PERF_BR_COND_RET = 10, /* Conditional function return */ 263 PERF_BR_ERET = 11, /* Exception return */ 264 PERF_BR_IRQ = 12, /* IRQ */ 265 PERF_BR_SERROR = 13, /* System error */ 266 PERF_BR_NO_TX = 14, /* Not in transaction */ 267 PERF_BR_EXTEND_ABI = 15, /* Extend ABI */ 268 PERF_BR_MAX, 269 }; 270 271 /* 272 * Common branch speculation outcome classifications: 273 */ 274 enum { 275 PERF_BR_SPEC_NA = 0, /* Not available */ 276 PERF_BR_SPEC_WRONG_PATH = 1, /* Speculative but on wrong path */ 277 PERF_BR_NON_SPEC_CORRECT_PATH = 2, /* Non-speculative but on correct path */ 278 PERF_BR_SPEC_CORRECT_PATH = 3, /* Speculative and on correct path */ 279 PERF_BR_SPEC_MAX, 280 }; 281 282 enum { 283 PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */ 284 PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */ 285 PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */ 286 PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */ 287 PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */ 288 PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */ 289 PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */ 290 PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */ 291 PERF_BR_NEW_MAX, 292 }; 293 294 enum { 295 PERF_BR_PRIV_UNKNOWN = 0, 296 PERF_BR_PRIV_USER = 1, 297 PERF_BR_PRIV_KERNEL = 2, 298 PERF_BR_PRIV_HV = 3, 299 }; 300 301 #define PERF_BR_ARM64_FIQ PERF_BR_NEW_ARCH_1 302 #define PERF_BR_ARM64_DEBUG_HALT PERF_BR_NEW_ARCH_2 303 #define PERF_BR_ARM64_DEBUG_EXIT PERF_BR_NEW_ARCH_3 304 #define PERF_BR_ARM64_DEBUG_INST PERF_BR_NEW_ARCH_4 305 #define PERF_BR_ARM64_DEBUG_DATA PERF_BR_NEW_ARCH_5 306 307 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 308 (PERF_SAMPLE_BRANCH_USER|\ 309 PERF_SAMPLE_BRANCH_KERNEL|\ 310 PERF_SAMPLE_BRANCH_HV) 311 312 /* 313 * Values to determine ABI of the registers dump. 314 */ 315 enum perf_sample_regs_abi { 316 PERF_SAMPLE_REGS_ABI_NONE = 0, 317 PERF_SAMPLE_REGS_ABI_32 = (1 << 0), 318 PERF_SAMPLE_REGS_ABI_64 = (1 << 1), 319 PERF_SAMPLE_REGS_ABI_SIMD = (1 << 2), 320 }; 321 322 /* 323 * Values for the memory transaction event qualifier, mostly for 324 * abort events. Multiple bits can be set. 325 */ 326 enum { 327 PERF_TXN_ELISION = (1 << 0), /* From elision */ 328 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 329 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 330 PERF_TXN_ASYNC = (1 << 3), /* Instruction is not related */ 331 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 332 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 333 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 334 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 335 336 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 337 338 /* Bits 32..63 are reserved for the abort code */ 339 340 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 341 PERF_TXN_ABORT_SHIFT = 32, 342 }; 343 344 /* 345 * The format of the data returned by read() on a perf event fd, 346 * as specified by attr.read_format: 347 * 348 * struct read_format { 349 * { u64 value; 350 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 351 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 352 * { u64 id; } && PERF_FORMAT_ID 353 * { u64 lost; } && PERF_FORMAT_LOST 354 * } && !PERF_FORMAT_GROUP 355 * 356 * { u64 nr; 357 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 358 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 359 * { u64 value; 360 * { u64 id; } && PERF_FORMAT_ID 361 * { u64 lost; } && PERF_FORMAT_LOST 362 * } cntr[nr]; 363 * } && PERF_FORMAT_GROUP 364 * }; 365 */ 366 enum perf_event_read_format { 367 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 368 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 369 PERF_FORMAT_ID = 1U << 2, 370 PERF_FORMAT_GROUP = 1U << 3, 371 PERF_FORMAT_LOST = 1U << 4, 372 373 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 374 }; 375 376 #define PERF_ATTR_SIZE_VER0 64 /* Size of first published 'struct perf_event_attr' */ 377 #define PERF_ATTR_SIZE_VER1 72 /* Add: config2 */ 378 #define PERF_ATTR_SIZE_VER2 80 /* Add: branch_sample_type */ 379 #define PERF_ATTR_SIZE_VER3 96 /* Add: sample_regs_user */ 380 /* Add: sample_stack_user */ 381 #define PERF_ATTR_SIZE_VER4 104 /* Add: sample_regs_intr */ 382 #define PERF_ATTR_SIZE_VER5 112 /* Add: aux_watermark */ 383 #define PERF_ATTR_SIZE_VER6 120 /* Add: aux_sample_size */ 384 #define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */ 385 #define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */ 386 #define PERF_ATTR_SIZE_VER9 144 /* add: config4 */ 387 #define PERF_ATTR_SIZE_VER10 176 /* Add: sample_simd_{vec|pred}_reg_* */ 388 389 /* 390 * 'struct perf_event_attr' contains various attributes that define 391 * a performance event - most of them hardware related configuration 392 * details, but also a lot of behavioral switches and values implemented 393 * by the kernel. 394 */ 395 struct perf_event_attr { 396 397 /* 398 * Major type: hardware/software/tracepoint/etc. 399 */ 400 __u32 type; 401 402 /* 403 * Size of the attr structure, for forward/backwards compatibility. 404 */ 405 __u32 size; 406 407 /* 408 * Type specific configuration information. 409 */ 410 __u64 config; 411 412 union { 413 __u64 sample_period; 414 __u64 sample_freq; 415 }; 416 417 __u64 sample_type; 418 __u64 read_format; 419 420 __u64 disabled : 1, /* off by default */ 421 inherit : 1, /* children inherit it */ 422 pinned : 1, /* must always be on PMU */ 423 exclusive : 1, /* only group on PMU */ 424 exclude_user : 1, /* don't count user */ 425 exclude_kernel : 1, /* ditto kernel */ 426 exclude_hv : 1, /* ditto hypervisor */ 427 exclude_idle : 1, /* don't count when idle */ 428 mmap : 1, /* include mmap data */ 429 comm : 1, /* include comm data */ 430 freq : 1, /* use freq, not period */ 431 inherit_stat : 1, /* per task counts */ 432 enable_on_exec : 1, /* next exec enables */ 433 task : 1, /* trace fork/exit */ 434 watermark : 1, /* wakeup_watermark */ 435 /* 436 * precise_ip: 437 * 438 * 0 - SAMPLE_IP can have arbitrary skid 439 * 1 - SAMPLE_IP must have constant skid 440 * 2 - SAMPLE_IP requested to have 0 skid 441 * 3 - SAMPLE_IP must have 0 skid 442 * 443 * See also PERF_RECORD_MISC_EXACT_IP 444 */ 445 precise_ip : 2, /* skid constraint */ 446 mmap_data : 1, /* non-exec mmap data */ 447 sample_id_all : 1, /* sample_type all events */ 448 449 exclude_host : 1, /* don't count in host */ 450 exclude_guest : 1, /* don't count in guest */ 451 452 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 453 exclude_callchain_user : 1, /* exclude user callchains */ 454 mmap2 : 1, /* include mmap with inode data */ 455 comm_exec : 1, /* flag comm events that are due to an exec */ 456 use_clockid : 1, /* use @clockid for time fields */ 457 context_switch : 1, /* context switch data */ 458 write_backward : 1, /* write ring buffer from end to beginning */ 459 namespaces : 1, /* include namespaces data */ 460 ksymbol : 1, /* include ksymbol events */ 461 bpf_event : 1, /* include BPF events */ 462 aux_output : 1, /* generate AUX records instead of events */ 463 cgroup : 1, /* include cgroup events */ 464 text_poke : 1, /* include text poke events */ 465 build_id : 1, /* use build ID in mmap2 events */ 466 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 467 remove_on_exec : 1, /* event is removed from task on exec */ 468 sigtrap : 1, /* send synchronous SIGTRAP on event */ 469 defer_callchain: 1, /* request PERF_RECORD_CALLCHAIN_DEFERRED records */ 470 defer_output : 1, /* output PERF_RECORD_CALLCHAIN_DEFERRED records */ 471 __reserved_1 : 24; 472 473 union { 474 __u32 wakeup_events; /* wake up every n events */ 475 __u32 wakeup_watermark; /* bytes before wakeup */ 476 }; 477 478 __u32 bp_type; 479 union { 480 __u64 bp_addr; 481 __u64 kprobe_func; /* for perf_kprobe */ 482 __u64 uprobe_path; /* for perf_uprobe */ 483 __u64 config1; /* extension of config */ 484 }; 485 union { 486 __u64 bp_len; 487 __u64 kprobe_addr; /* when kprobe_func == NULL */ 488 __u64 probe_offset; /* for perf_[k,u]probe */ 489 __u64 config2; /* extension of config1 */ 490 }; 491 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 492 493 /* 494 * Defines set of user regs to dump on samples. 495 * See asm/perf_regs.h for details. 496 */ 497 __u64 sample_regs_user; 498 499 /* 500 * Defines size of the user stack to dump on samples. 501 */ 502 __u32 sample_stack_user; 503 504 __s32 clockid; 505 /* 506 * Defines set of regs to dump for each sample 507 * state captured on: 508 * - precise = 0: PMU interrupt 509 * - precise > 0: sampled instruction 510 * 511 * See asm/perf_regs.h for details. 512 */ 513 __u64 sample_regs_intr; 514 515 /* 516 * Wakeup watermark for AUX area 517 */ 518 __u32 aux_watermark; 519 520 /* 521 * Max number of frame pointers in a callchain, should be 522 * lower than /proc/sys/kernel/perf_event_max_stack. 523 * 524 * Max number of entries of branch stack should be lower 525 * than the hardware limit. 526 */ 527 __u16 sample_max_stack; 528 529 __u16 __reserved_2; 530 __u32 aux_sample_size; 531 532 union { 533 __u32 aux_action; 534 struct { 535 __u32 aux_start_paused : 1, /* start AUX area tracing paused */ 536 aux_pause : 1, /* on overflow, pause AUX area tracing */ 537 aux_resume : 1, /* on overflow, resume AUX area tracing */ 538 __reserved_3 : 29; 539 }; 540 }; 541 542 /* 543 * User provided data if sigtrap=1, passed back to user via 544 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 545 * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be 546 * truncated accordingly on 32 bit architectures. 547 */ 548 __u64 sig_data; 549 550 __u64 config3; /* extension of config2 */ 551 __u64 config4; /* extension of config3 */ 552 553 /* 554 * Defines the sampling SIMD/PRED(predicate) registers bitmap and 555 * qwords (8 bytes) length. 556 * 557 * sample_simd_regs_enabled != 0 indicates there are SIMD/PRED 558 * registers to be sampled, the SIMD/PRED registers bitmap and 559 * qwords length are represented in 560 * sample_simd_{vec|pred}_reg_{intr|user} and 561 * sample_simd_{vec|pred}_reg_qwords fields separately. 562 * 563 * sample_simd_regs_enabled == 0 indicates no SIMD/PRED registers 564 * are sampled. 565 */ 566 __u16 sample_simd_regs_enabled; 567 __u16 sample_simd_pred_reg_qwords; 568 __u16 sample_simd_vec_reg_qwords; 569 __u16 __reserved_4; 570 571 __u32 sample_simd_pred_reg_intr; 572 __u32 sample_simd_pred_reg_user; 573 __u64 sample_simd_vec_reg_intr; 574 __u64 sample_simd_vec_reg_user; 575 }; 576 577 /* 578 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 579 * to query BPF programs attached to the same perf tracepoint 580 * as the given perf event. 581 */ 582 struct perf_event_query_bpf { 583 /* 584 * The below ids array length 585 */ 586 __u32 ids_len; 587 /* 588 * Set by the kernel to indicate the number of 589 * available programs 590 */ 591 __u32 prog_cnt; 592 /* 593 * User provided buffer to store program ids 594 */ 595 __u32 ids[]; 596 }; 597 598 /* 599 * Ioctls that can be done on a perf event fd: 600 */ 601 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 602 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 603 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 604 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 605 #define PERF_EVENT_IOC_PERIOD _IOW ('$', 4, __u64) 606 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 607 #define PERF_EVENT_IOC_SET_FILTER _IOW ('$', 6, char *) 608 #define PERF_EVENT_IOC_ID _IOR ('$', 7, __u64 *) 609 #define PERF_EVENT_IOC_SET_BPF _IOW ('$', 8, __u32) 610 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW ('$', 9, __u32) 611 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 612 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW ('$', 11, struct perf_event_attr *) 613 614 enum perf_event_ioc_flags { 615 PERF_IOC_FLAG_GROUP = 1U << 0, 616 }; 617 618 /* 619 * Structure of the page that can be mapped via mmap 620 */ 621 struct perf_event_mmap_page { 622 __u32 version; /* version number of this structure */ 623 __u32 compat_version; /* lowest version this is compat with */ 624 625 /* 626 * Bits needed to read the HW events in user-space. 627 * 628 * u32 seq, time_mult, time_shift, index, width; 629 * u64 count, enabled, running; 630 * u64 cyc, time_offset; 631 * s64 pmc = 0; 632 * 633 * do { 634 * seq = pc->lock; 635 * barrier() 636 * 637 * enabled = pc->time_enabled; 638 * running = pc->time_running; 639 * 640 * if (pc->cap_usr_time && enabled != running) { 641 * cyc = rdtsc(); 642 * time_offset = pc->time_offset; 643 * time_mult = pc->time_mult; 644 * time_shift = pc->time_shift; 645 * } 646 * 647 * index = pc->index; 648 * count = pc->offset; 649 * if (pc->cap_user_rdpmc && index) { 650 * width = pc->pmc_width; 651 * pmc = rdpmc(index - 1); 652 * } 653 * 654 * barrier(); 655 * } while (pc->lock != seq); 656 * 657 * NOTE: for obvious reason this only works on self-monitoring 658 * processes. 659 */ 660 __u32 lock; /* seqlock for synchronization */ 661 __u32 index; /* hardware event identifier */ 662 __s64 offset; /* add to hardware event value */ 663 __u64 time_enabled; /* time event active */ 664 __u64 time_running; /* time event on CPU */ 665 union { 666 __u64 capabilities; 667 struct { 668 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 669 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 670 671 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 672 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 673 cap_user_time_zero : 1, /* The time_zero field is used */ 674 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 675 cap_____res : 58; 676 }; 677 }; 678 679 /* 680 * If cap_user_rdpmc this field provides the bit-width of the value 681 * read using the rdpmc() or equivalent instruction. This can be used 682 * to sign extend the result like: 683 * 684 * pmc <<= 64 - width; 685 * pmc >>= 64 - width; // signed shift right 686 * count += pmc; 687 */ 688 __u16 pmc_width; 689 690 /* 691 * If cap_usr_time the below fields can be used to compute the time 692 * delta since time_enabled (in ns) using RDTSC or similar. 693 * 694 * u64 quot, rem; 695 * u64 delta; 696 * 697 * quot = (cyc >> time_shift); 698 * rem = cyc & (((u64)1 << time_shift) - 1); 699 * delta = time_offset + quot * time_mult + 700 * ((rem * time_mult) >> time_shift); 701 * 702 * Where time_offset,time_mult,time_shift and cyc are read in the 703 * seqcount loop described above. This delta can then be added to 704 * enabled and possible running (if index), improving the scaling: 705 * 706 * enabled += delta; 707 * if (index) 708 * running += delta; 709 * 710 * quot = count / running; 711 * rem = count % running; 712 * count = quot * enabled + (rem * enabled) / running; 713 */ 714 __u16 time_shift; 715 __u32 time_mult; 716 __u64 time_offset; 717 /* 718 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 719 * from sample timestamps. 720 * 721 * time = timestamp - time_zero; 722 * quot = time / time_mult; 723 * rem = time % time_mult; 724 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 725 * 726 * And vice versa: 727 * 728 * quot = cyc >> time_shift; 729 * rem = cyc & (((u64)1 << time_shift) - 1); 730 * timestamp = time_zero + quot * time_mult + 731 * ((rem * time_mult) >> time_shift); 732 */ 733 __u64 time_zero; 734 735 __u32 size; /* Header size up to __reserved[] fields. */ 736 __u32 __reserved_1; 737 738 /* 739 * If cap_usr_time_short, the hardware clock is less than 64bit wide 740 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 741 * 742 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 743 * 744 * NOTE: this form is explicitly chosen such that cap_usr_time_short 745 * is a correction on top of cap_usr_time, and code that doesn't 746 * know about cap_usr_time_short still works under the assumption 747 * the counter doesn't wrap. 748 */ 749 __u64 time_cycles; 750 __u64 time_mask; 751 752 /* 753 * Hole for extension of the self monitor capabilities 754 */ 755 756 __u8 __reserved[116*8]; /* align to 1k. */ 757 758 /* 759 * Control data for the mmap() data buffer. 760 * 761 * User-space reading the @data_head value should issue an smp_rmb(), 762 * after reading this value. 763 * 764 * When the mapping is PROT_WRITE the @data_tail value should be 765 * written by user-space to reflect the last read data, after issuing 766 * an smp_mb() to separate the data read from the ->data_tail store. 767 * In this case the kernel will not over-write unread data. 768 * 769 * See perf_output_put_handle() for the data ordering. 770 * 771 * data_{offset,size} indicate the location and size of the perf record 772 * buffer within the mmapped area. 773 */ 774 __u64 data_head; /* head in the data section */ 775 __u64 data_tail; /* user-space written tail */ 776 __u64 data_offset; /* where the buffer starts */ 777 __u64 data_size; /* data buffer size */ 778 779 /* 780 * AUX area is defined by aux_{offset,size} fields that should be set 781 * by the user-space, so that 782 * 783 * aux_offset >= data_offset + data_size 784 * 785 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 786 * 787 * Ring buffer pointers aux_{head,tail} have the same semantics as 788 * data_{head,tail} and same ordering rules apply. 789 */ 790 __u64 aux_head; 791 __u64 aux_tail; 792 __u64 aux_offset; 793 __u64 aux_size; 794 }; 795 796 /* 797 * The current state of perf_event_header::misc bits usage: 798 * ('|' used bit, '-' unused bit) 799 * 800 * 012 CDEF 801 * |||---------|||| 802 * 803 * Where: 804 * 0-2 CPUMODE_MASK 805 * 806 * C PROC_MAP_PARSE_TIMEOUT 807 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 808 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 809 * F (reserved) 810 */ 811 812 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 813 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 814 #define PERF_RECORD_MISC_KERNEL (1 << 0) 815 #define PERF_RECORD_MISC_USER (2 << 0) 816 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 817 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 818 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 819 820 /* 821 * Indicates that /proc/PID/maps parsing are truncated by time out. 822 */ 823 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 824 /* 825 * Following PERF_RECORD_MISC_* are used on different 826 * events, so can reuse the same bit position: 827 * 828 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 829 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 830 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 831 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 832 */ 833 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 834 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 835 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 836 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 837 /* 838 * These PERF_RECORD_MISC_* flags below are safely reused 839 * for the following events: 840 * 841 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 842 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 843 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 844 * 845 * 846 * PERF_RECORD_MISC_EXACT_IP: 847 * Indicates that the content of PERF_SAMPLE_IP points to 848 * the actual instruction that triggered the event. See also 849 * perf_event_attr::precise_ip. 850 * 851 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 852 * Indicates that thread was preempted in TASK_RUNNING state. 853 * 854 * PERF_RECORD_MISC_MMAP_BUILD_ID: 855 * Indicates that mmap2 event carries build ID data. 856 */ 857 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 858 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 859 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 860 /* 861 * Reserve the last bit to indicate some extended misc field 862 */ 863 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 864 865 struct perf_event_header { 866 __u32 type; 867 __u16 misc; 868 __u16 size; 869 }; 870 871 struct perf_ns_link_info { 872 __u64 dev; 873 __u64 ino; 874 }; 875 876 enum { 877 NET_NS_INDEX = 0, 878 UTS_NS_INDEX = 1, 879 IPC_NS_INDEX = 2, 880 PID_NS_INDEX = 3, 881 USER_NS_INDEX = 4, 882 MNT_NS_INDEX = 5, 883 CGROUP_NS_INDEX = 6, 884 885 NR_NAMESPACES, /* number of available namespaces */ 886 }; 887 888 enum perf_event_type { 889 890 /* 891 * If perf_event_attr.sample_id_all is set then all event types will 892 * have the sample_type selected fields related to where/when 893 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 894 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 895 * just after the perf_event_header and the fields already present for 896 * the existing fields, i.e. at the end of the payload. That way a newer 897 * perf.data file will be supported by older perf tools, with these new 898 * optional fields being ignored. 899 * 900 * struct sample_id { 901 * { u32 pid, tid; } && PERF_SAMPLE_TID 902 * { u64 time; } && PERF_SAMPLE_TIME 903 * { u64 id; } && PERF_SAMPLE_ID 904 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 905 * { u32 cpu, res; } && PERF_SAMPLE_CPU 906 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 907 * } && perf_event_attr::sample_id_all 908 * 909 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 910 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 911 * relative to header.size. 912 */ 913 914 /* 915 * The MMAP events record the PROT_EXEC mappings so that we can 916 * correlate user-space IPs to code. They have the following structure: 917 * 918 * struct { 919 * struct perf_event_header header; 920 * 921 * u32 pid, tid; 922 * u64 addr; 923 * u64 len; 924 * u64 pgoff; 925 * char filename[]; 926 * struct sample_id sample_id; 927 * }; 928 */ 929 PERF_RECORD_MMAP = 1, 930 931 /* 932 * struct { 933 * struct perf_event_header header; 934 * u64 id; 935 * u64 lost; 936 * struct sample_id sample_id; 937 * }; 938 */ 939 PERF_RECORD_LOST = 2, 940 941 /* 942 * struct { 943 * struct perf_event_header header; 944 * 945 * u32 pid, tid; 946 * char comm[]; 947 * struct sample_id sample_id; 948 * }; 949 */ 950 PERF_RECORD_COMM = 3, 951 952 /* 953 * struct { 954 * struct perf_event_header header; 955 * u32 pid, ppid; 956 * u32 tid, ptid; 957 * u64 time; 958 * struct sample_id sample_id; 959 * }; 960 */ 961 PERF_RECORD_EXIT = 4, 962 963 /* 964 * struct { 965 * struct perf_event_header header; 966 * u64 time; 967 * u64 id; 968 * u64 stream_id; 969 * struct sample_id sample_id; 970 * }; 971 */ 972 PERF_RECORD_THROTTLE = 5, 973 PERF_RECORD_UNTHROTTLE = 6, 974 975 /* 976 * struct { 977 * struct perf_event_header header; 978 * u32 pid, ppid; 979 * u32 tid, ptid; 980 * u64 time; 981 * struct sample_id sample_id; 982 * }; 983 */ 984 PERF_RECORD_FORK = 7, 985 986 /* 987 * struct { 988 * struct perf_event_header header; 989 * u32 pid, tid; 990 * 991 * struct read_format values; 992 * struct sample_id sample_id; 993 * }; 994 */ 995 PERF_RECORD_READ = 8, 996 997 /* 998 * struct { 999 * struct perf_event_header header; 1000 * 1001 * # 1002 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 1003 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 1004 * # is fixed relative to header. 1005 * # 1006 * 1007 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 1008 * { u64 ip; } && PERF_SAMPLE_IP 1009 * { u32 pid, tid; } && PERF_SAMPLE_TID 1010 * { u64 time; } && PERF_SAMPLE_TIME 1011 * { u64 addr; } && PERF_SAMPLE_ADDR 1012 * { u64 id; } && PERF_SAMPLE_ID 1013 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 1014 * { u32 cpu, res; } && PERF_SAMPLE_CPU 1015 * { u64 period; } && PERF_SAMPLE_PERIOD 1016 * 1017 * { struct read_format values; } && PERF_SAMPLE_READ 1018 * 1019 * { u64 nr, 1020 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 1021 * 1022 * # 1023 * # The RAW record below is opaque data wrt the ABI 1024 * # 1025 * # That is, the ABI doesn't make any promises wrt to 1026 * # the stability of its content, it may vary depending 1027 * # on event, hardware, kernel version and phase of 1028 * # the moon. 1029 * # 1030 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 1031 * # 1032 * 1033 * { u32 size; 1034 * char data[size];}&& PERF_SAMPLE_RAW 1035 * 1036 * { u64 nr; 1037 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 1038 * { u64 from, to, flags } lbr[nr]; 1039 * # 1040 * # The format of the counters is decided by the 1041 * # "branch_counter_nr" and "branch_counter_width", 1042 * # which are defined in the ABI. 1043 * # 1044 * { u64 counters; } cntr[nr] && PERF_SAMPLE_BRANCH_COUNTERS 1045 * } && PERF_SAMPLE_BRANCH_STACK 1046 * 1047 * { u64 abi; # enum perf_sample_regs_abi 1048 * u64 regs[weight(mask)]; 1049 * struct { 1050 * u64 nr_vectors; # 0 ... weight(sample_simd_vec_reg_user) 1051 * u64 vector_qwords; # 0 ... sample_simd_vec_reg_qwords 1052 * u64 nr_pred; # 0 ... weight(sample_simd_pred_reg_user) 1053 * u64 pred_qwords; # 0 ... sample_simd_pred_reg_qwords 1054 * u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords]; 1055 * } && (abi & PERF_SAMPLE_REGS_ABI_SIMD) 1056 * } && PERF_SAMPLE_REGS_USER 1057 * 1058 * { u64 size; 1059 * char data[size]; 1060 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 1061 * 1062 * { union perf_sample_weight 1063 * { 1064 * u64 full; && PERF_SAMPLE_WEIGHT 1065 * #if defined(__LITTLE_ENDIAN_BITFIELD) 1066 * struct { 1067 * u32 var1_dw; 1068 * u16 var2_w; 1069 * u16 var3_w; 1070 * } && PERF_SAMPLE_WEIGHT_STRUCT 1071 * #elif defined(__BIG_ENDIAN_BITFIELD) 1072 * struct { 1073 * u16 var3_w; 1074 * u16 var2_w; 1075 * u32 var1_dw; 1076 * } && PERF_SAMPLE_WEIGHT_STRUCT 1077 * #endif 1078 * } 1079 * } 1080 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 1081 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 1082 * { u64 abi; # enum perf_sample_regs_abi 1083 * u64 regs[weight(mask)]; 1084 * struct { 1085 * u64 nr_vectors; # 0 ... weight(sample_simd_vec_reg_intr) 1086 * u64 vector_qwords; # 0 ... sample_simd_vec_reg_qwords 1087 * u64 nr_pred; # 0 ... weight(sample_simd_pred_reg_intr) 1088 * u64 pred_qwords; # 0 ... sample_simd_pred_reg_qwords 1089 * u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords]; 1090 * } && (abi & PERF_SAMPLE_REGS_ABI_SIMD) 1091 * } && PERF_SAMPLE_REGS_INTR 1092 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 1093 * { u64 cgroup;} && PERF_SAMPLE_CGROUP 1094 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 1095 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 1096 * { u64 size; 1097 * char data[size]; } && PERF_SAMPLE_AUX 1098 * }; 1099 */ 1100 PERF_RECORD_SAMPLE = 9, 1101 1102 /* 1103 * The MMAP2 records are an augmented version of MMAP, they add 1104 * maj, min, ino numbers to be used to uniquely identify each mapping 1105 * 1106 * struct { 1107 * struct perf_event_header header; 1108 * 1109 * u32 pid, tid; 1110 * u64 addr; 1111 * u64 len; 1112 * u64 pgoff; 1113 * union { 1114 * struct { 1115 * u32 maj; 1116 * u32 min; 1117 * u64 ino; 1118 * u64 ino_generation; 1119 * }; 1120 * struct { 1121 * u8 build_id_size; 1122 * u8 __reserved_1; 1123 * u16 __reserved_2; 1124 * u8 build_id[20]; 1125 * }; 1126 * }; 1127 * u32 prot, flags; 1128 * char filename[]; 1129 * struct sample_id sample_id; 1130 * }; 1131 */ 1132 PERF_RECORD_MMAP2 = 10, 1133 1134 /* 1135 * Records that new data landed in the AUX buffer part. 1136 * 1137 * struct { 1138 * struct perf_event_header header; 1139 * 1140 * u64 aux_offset; 1141 * u64 aux_size; 1142 * u64 flags; 1143 * struct sample_id sample_id; 1144 * }; 1145 */ 1146 PERF_RECORD_AUX = 11, 1147 1148 /* 1149 * Indicates that instruction trace has started 1150 * 1151 * struct { 1152 * struct perf_event_header header; 1153 * u32 pid; 1154 * u32 tid; 1155 * struct sample_id sample_id; 1156 * }; 1157 */ 1158 PERF_RECORD_ITRACE_START = 12, 1159 1160 /* 1161 * Records the dropped/lost sample number. 1162 * 1163 * struct { 1164 * struct perf_event_header header; 1165 * 1166 * u64 lost; 1167 * struct sample_id sample_id; 1168 * }; 1169 */ 1170 PERF_RECORD_LOST_SAMPLES = 13, 1171 1172 /* 1173 * Records a context switch in or out (flagged by 1174 * PERF_RECORD_MISC_SWITCH_OUT). See also 1175 * PERF_RECORD_SWITCH_CPU_WIDE. 1176 * 1177 * struct { 1178 * struct perf_event_header header; 1179 * struct sample_id sample_id; 1180 * }; 1181 */ 1182 PERF_RECORD_SWITCH = 14, 1183 1184 /* 1185 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1186 * next_prev_tid that are the next (switching out) or previous 1187 * (switching in) pid/tid. 1188 * 1189 * struct { 1190 * struct perf_event_header header; 1191 * u32 next_prev_pid; 1192 * u32 next_prev_tid; 1193 * struct sample_id sample_id; 1194 * }; 1195 */ 1196 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1197 1198 /* 1199 * struct { 1200 * struct perf_event_header header; 1201 * u32 pid; 1202 * u32 tid; 1203 * u64 nr_namespaces; 1204 * { u64 dev, inode; } [nr_namespaces]; 1205 * struct sample_id sample_id; 1206 * }; 1207 */ 1208 PERF_RECORD_NAMESPACES = 16, 1209 1210 /* 1211 * Record ksymbol register/unregister events: 1212 * 1213 * struct { 1214 * struct perf_event_header header; 1215 * u64 addr; 1216 * u32 len; 1217 * u16 ksym_type; 1218 * u16 flags; 1219 * char name[]; 1220 * struct sample_id sample_id; 1221 * }; 1222 */ 1223 PERF_RECORD_KSYMBOL = 17, 1224 1225 /* 1226 * Record BPF events: 1227 * enum perf_bpf_event_type { 1228 * PERF_BPF_EVENT_UNKNOWN = 0, 1229 * PERF_BPF_EVENT_PROG_LOAD = 1, 1230 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1231 * }; 1232 * 1233 * struct { 1234 * struct perf_event_header header; 1235 * u16 type; 1236 * u16 flags; 1237 * u32 id; 1238 * u8 tag[BPF_TAG_SIZE]; 1239 * struct sample_id sample_id; 1240 * }; 1241 */ 1242 PERF_RECORD_BPF_EVENT = 18, 1243 1244 /* 1245 * struct { 1246 * struct perf_event_header header; 1247 * u64 id; 1248 * char path[]; 1249 * struct sample_id sample_id; 1250 * }; 1251 */ 1252 PERF_RECORD_CGROUP = 19, 1253 1254 /* 1255 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1256 * the number of old bytes, 'new_len' is the number of new bytes. Either 1257 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1258 * addition or removal of a trampoline. 'bytes' contains the old bytes 1259 * followed immediately by the new bytes. 1260 * 1261 * struct { 1262 * struct perf_event_header header; 1263 * u64 addr; 1264 * u16 old_len; 1265 * u16 new_len; 1266 * u8 bytes[]; 1267 * struct sample_id sample_id; 1268 * }; 1269 */ 1270 PERF_RECORD_TEXT_POKE = 20, 1271 1272 /* 1273 * Data written to the AUX area by hardware due to aux_output, may need 1274 * to be matched to the event by an architecture-specific hardware ID. 1275 * This records the hardware ID, but requires sample_id to provide the 1276 * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT 1277 * records from multiple events. 1278 * 1279 * struct { 1280 * struct perf_event_header header; 1281 * u64 hw_id; 1282 * struct sample_id sample_id; 1283 * }; 1284 */ 1285 PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 1286 1287 /* 1288 * This user callchain capture was deferred until shortly before 1289 * returning to user space. Previous samples would have kernel 1290 * callchains only and they need to be stitched with this to make full 1291 * callchains. 1292 * 1293 * struct { 1294 * struct perf_event_header header; 1295 * u64 cookie; 1296 * u64 nr; 1297 * u64 ips[nr]; 1298 * struct sample_id sample_id; 1299 * }; 1300 */ 1301 PERF_RECORD_CALLCHAIN_DEFERRED = 22, 1302 1303 PERF_RECORD_MAX, /* non-ABI */ 1304 }; 1305 1306 enum perf_record_ksymbol_type { 1307 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1308 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1309 /* 1310 * Out of line code such as kprobe-replaced instructions or optimized 1311 * kprobes or ftrace trampolines. 1312 */ 1313 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1314 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1315 }; 1316 1317 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1318 1319 enum perf_bpf_event_type { 1320 PERF_BPF_EVENT_UNKNOWN = 0, 1321 PERF_BPF_EVENT_PROG_LOAD = 1, 1322 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1323 PERF_BPF_EVENT_MAX, /* non-ABI */ 1324 }; 1325 1326 #define PERF_MAX_STACK_DEPTH 127 1327 #define PERF_MAX_CONTEXTS_PER_STACK 8 1328 1329 enum perf_callchain_context { 1330 PERF_CONTEXT_HV = (__u64)-32, 1331 PERF_CONTEXT_KERNEL = (__u64)-128, 1332 PERF_CONTEXT_USER = (__u64)-512, 1333 PERF_CONTEXT_USER_DEFERRED = (__u64)-640, 1334 1335 PERF_CONTEXT_GUEST = (__u64)-2048, 1336 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1337 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1338 1339 PERF_CONTEXT_MAX = (__u64)-4095, 1340 }; 1341 1342 /** 1343 * PERF_RECORD_AUX::flags bits 1344 */ 1345 #define PERF_AUX_FLAG_TRUNCATED 0x0001 /* Record was truncated to fit */ 1346 #define PERF_AUX_FLAG_OVERWRITE 0x0002 /* Snapshot from overwrite mode */ 1347 #define PERF_AUX_FLAG_PARTIAL 0x0004 /* Record contains gaps */ 1348 #define PERF_AUX_FLAG_COLLISION 0x0008 /* Sample collided with another */ 1349 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1350 1351 /* CoreSight PMU AUX buffer formats */ 1352 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1353 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1354 1355 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1356 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1357 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup ID, per-CPU mode only */ 1358 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1359 1360 #if defined(__LITTLE_ENDIAN_BITFIELD) 1361 union perf_mem_data_src { 1362 __u64 val; 1363 struct { 1364 __u64 mem_op : 5, /* Type of opcode */ 1365 mem_lvl : 14, /* Memory hierarchy level */ 1366 mem_snoop : 5, /* Snoop mode */ 1367 mem_lock : 2, /* Lock instr */ 1368 mem_dtlb : 7, /* TLB access */ 1369 mem_lvl_num : 4, /* Memory hierarchy level number */ 1370 mem_remote : 1, /* Remote */ 1371 mem_snoopx : 2, /* Snoop mode, ext */ 1372 mem_blk : 3, /* Access blocked */ 1373 mem_hops : 3, /* Hop level */ 1374 mem_region : 5, /* cache/memory regions */ 1375 mem_rsvd : 13; 1376 }; 1377 }; 1378 #elif defined(__BIG_ENDIAN_BITFIELD) 1379 union perf_mem_data_src { 1380 __u64 val; 1381 struct { 1382 __u64 mem_rsvd : 13, 1383 mem_region : 5, /* cache/memory regions */ 1384 mem_hops : 3, /* Hop level */ 1385 mem_blk : 3, /* Access blocked */ 1386 mem_snoopx : 2, /* Snoop mode, ext */ 1387 mem_remote : 1, /* Remote */ 1388 mem_lvl_num : 4, /* Memory hierarchy level number */ 1389 mem_dtlb : 7, /* TLB access */ 1390 mem_lock : 2, /* Lock instr */ 1391 mem_snoop : 5, /* Snoop mode */ 1392 mem_lvl : 14, /* Memory hierarchy level */ 1393 mem_op : 5; /* Type of opcode */ 1394 }; 1395 }; 1396 #else 1397 # error "Unknown endianness" 1398 #endif 1399 1400 /* Type of memory opcode: */ 1401 #define PERF_MEM_OP_NA 0x0001 /* Not available */ 1402 #define PERF_MEM_OP_LOAD 0x0002 /* Load instruction */ 1403 #define PERF_MEM_OP_STORE 0x0004 /* Store instruction */ 1404 #define PERF_MEM_OP_PFETCH 0x0008 /* Prefetch */ 1405 #define PERF_MEM_OP_EXEC 0x0010 /* Code (execution) */ 1406 #define PERF_MEM_OP_SHIFT 0 1407 1408 /* 1409 * The PERF_MEM_LVL_* namespace is being deprecated to some extent in 1410 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. 1411 * We support this namespace in order to not break defined ABIs. 1412 * 1413 * Memory hierarchy (memory level, hit or miss) 1414 */ 1415 #define PERF_MEM_LVL_NA 0x0001 /* Not available */ 1416 #define PERF_MEM_LVL_HIT 0x0002 /* Hit level */ 1417 #define PERF_MEM_LVL_MISS 0x0004 /* Miss level */ 1418 #define PERF_MEM_LVL_L1 0x0008 /* L1 */ 1419 #define PERF_MEM_LVL_LFB 0x0010 /* Line Fill Buffer */ 1420 #define PERF_MEM_LVL_L2 0x0020 /* L2 */ 1421 #define PERF_MEM_LVL_L3 0x0040 /* L3 */ 1422 #define PERF_MEM_LVL_LOC_RAM 0x0080 /* Local DRAM */ 1423 #define PERF_MEM_LVL_REM_RAM1 0x0100 /* Remote DRAM (1 hop) */ 1424 #define PERF_MEM_LVL_REM_RAM2 0x0200 /* Remote DRAM (2 hops) */ 1425 #define PERF_MEM_LVL_REM_CCE1 0x0400 /* Remote Cache (1 hop) */ 1426 #define PERF_MEM_LVL_REM_CCE2 0x0800 /* Remote Cache (2 hops) */ 1427 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1428 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1429 #define PERF_MEM_LVL_SHIFT 5 1430 1431 #define PERF_MEM_REMOTE_REMOTE 0x0001 /* Remote */ 1432 #define PERF_MEM_REMOTE_SHIFT 37 1433 1434 #define PERF_MEM_LVLNUM_L1 0x0001 /* L1 */ 1435 #define PERF_MEM_LVLNUM_L2 0x0002 /* L2 */ 1436 #define PERF_MEM_LVLNUM_L3 0x0003 /* L3 */ 1437 #define PERF_MEM_LVLNUM_L4 0x0004 /* L4 */ 1438 #define PERF_MEM_LVLNUM_L2_MHB 0x0005 /* L2 Miss Handling Buffer */ 1439 #define PERF_MEM_LVLNUM_MSC 0x0006 /* Memory-side Cache */ 1440 #define PERF_MEM_LVLNUM_L0 0x0007 /* L0 */ 1441 #define PERF_MEM_LVLNUM_UNC 0x0008 /* Uncached */ 1442 #define PERF_MEM_LVLNUM_CXL 0x0009 /* CXL */ 1443 #define PERF_MEM_LVLNUM_IO 0x000a /* I/O */ 1444 #define PERF_MEM_LVLNUM_ANY_CACHE 0x000b /* Any cache */ 1445 #define PERF_MEM_LVLNUM_LFB 0x000c /* LFB / L1 Miss Handling Buffer */ 1446 #define PERF_MEM_LVLNUM_RAM 0x000d /* RAM */ 1447 #define PERF_MEM_LVLNUM_PMEM 0x000e /* PMEM */ 1448 #define PERF_MEM_LVLNUM_NA 0x000f /* N/A */ 1449 1450 #define PERF_MEM_LVLNUM_SHIFT 33 1451 1452 /* Snoop mode */ 1453 #define PERF_MEM_SNOOP_NA 0x0001 /* Not available */ 1454 #define PERF_MEM_SNOOP_NONE 0x0002 /* No snoop */ 1455 #define PERF_MEM_SNOOP_HIT 0x0004 /* Snoop hit */ 1456 #define PERF_MEM_SNOOP_MISS 0x0008 /* Snoop miss */ 1457 #define PERF_MEM_SNOOP_HITM 0x0010 /* Snoop hit modified */ 1458 #define PERF_MEM_SNOOP_SHIFT 19 1459 1460 #define PERF_MEM_SNOOPX_FWD 0x0001 /* Forward */ 1461 #define PERF_MEM_SNOOPX_PEER 0x0002 /* Transfer from peer */ 1462 #define PERF_MEM_SNOOPX_SHIFT 38 1463 1464 /* Locked instruction */ 1465 #define PERF_MEM_LOCK_NA 0x0001 /* Not available */ 1466 #define PERF_MEM_LOCK_LOCKED 0x0002 /* Locked transaction */ 1467 #define PERF_MEM_LOCK_SHIFT 24 1468 1469 /* TLB access */ 1470 #define PERF_MEM_TLB_NA 0x0001 /* Not available */ 1471 #define PERF_MEM_TLB_HIT 0x0002 /* Hit level */ 1472 #define PERF_MEM_TLB_MISS 0x0004 /* Miss level */ 1473 #define PERF_MEM_TLB_L1 0x0008 /* L1 */ 1474 #define PERF_MEM_TLB_L2 0x0010 /* L2 */ 1475 #define PERF_MEM_TLB_WK 0x0020 /* Hardware Walker*/ 1476 #define PERF_MEM_TLB_OS 0x0040 /* OS fault handler */ 1477 #define PERF_MEM_TLB_SHIFT 26 1478 1479 /* Access blocked */ 1480 #define PERF_MEM_BLK_NA 0x0001 /* Not available */ 1481 #define PERF_MEM_BLK_DATA 0x0002 /* Data could not be forwarded */ 1482 #define PERF_MEM_BLK_ADDR 0x0004 /* Address conflict */ 1483 #define PERF_MEM_BLK_SHIFT 40 1484 1485 /* Hop level */ 1486 #define PERF_MEM_HOPS_0 0x0001 /* Remote core, same node */ 1487 #define PERF_MEM_HOPS_1 0x0002 /* Remote node, same socket */ 1488 #define PERF_MEM_HOPS_2 0x0003 /* Remote socket, same board */ 1489 #define PERF_MEM_HOPS_3 0x0004 /* Remote board */ 1490 /* 5-7 available */ 1491 #define PERF_MEM_HOPS_SHIFT 43 1492 1493 /* Cache/Memory region */ 1494 #define PERF_MEM_REGION_NA 0x0 /* Invalid */ 1495 #define PERF_MEM_REGION_RSVD 0x01 /* Reserved */ 1496 #define PERF_MEM_REGION_L_SHARE 0x02 /* Local CA shared cache */ 1497 #define PERF_MEM_REGION_L_NON_SHARE 0x03 /* Local CA non-shared cache */ 1498 #define PERF_MEM_REGION_O_IO 0x04 /* Other CA IO agent */ 1499 #define PERF_MEM_REGION_O_SHARE 0x05 /* Other CA shared cache */ 1500 #define PERF_MEM_REGION_O_NON_SHARE 0x06 /* Other CA non-shared cache */ 1501 #define PERF_MEM_REGION_MMIO 0x07 /* MMIO */ 1502 #define PERF_MEM_REGION_MEM0 0x08 /* Memory region 0 */ 1503 #define PERF_MEM_REGION_MEM1 0x09 /* Memory region 1 */ 1504 #define PERF_MEM_REGION_MEM2 0x0a /* Memory region 2 */ 1505 #define PERF_MEM_REGION_MEM3 0x0b /* Memory region 3 */ 1506 #define PERF_MEM_REGION_MEM4 0x0c /* Memory region 4 */ 1507 #define PERF_MEM_REGION_MEM5 0x0d /* Memory region 5 */ 1508 #define PERF_MEM_REGION_MEM6 0x0e /* Memory region 6 */ 1509 #define PERF_MEM_REGION_MEM7 0x0f /* Memory region 7 */ 1510 #define PERF_MEM_REGION_SHIFT 46 1511 1512 #define PERF_MEM_S(a, s) \ 1513 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1514 1515 /* 1516 * Layout of single taken branch records: 1517 * 1518 * from: source instruction (may not always be a branch insn) 1519 * to: branch target 1520 * mispred: branch target was mispredicted 1521 * predicted: branch target was predicted 1522 * 1523 * support for mispred, predicted is optional. In case it 1524 * is not supported mispred = predicted = 0. 1525 * 1526 * in_tx: running in a hardware transaction 1527 * abort: aborting a hardware transaction 1528 * cycles: cycles from last branch (or 0 if not supported) 1529 * type: branch type 1530 * spec: branch speculation info (or 0 if not supported) 1531 */ 1532 struct perf_branch_entry { 1533 __u64 from; 1534 __u64 to; 1535 __u64 mispred : 1, /* target mispredicted */ 1536 predicted : 1, /* target predicted */ 1537 in_tx : 1, /* in transaction */ 1538 abort : 1, /* transaction abort */ 1539 cycles : 16, /* cycle count to last branch */ 1540 type : 4, /* branch type */ 1541 spec : 2, /* branch speculation info */ 1542 new_type : 4, /* additional branch type */ 1543 priv : 3, /* privilege level */ 1544 reserved : 31; 1545 }; 1546 1547 /* Size of used info bits in struct perf_branch_entry */ 1548 #define PERF_BRANCH_ENTRY_INFO_BITS_MAX 33 1549 1550 union perf_sample_weight { 1551 __u64 full; 1552 #if defined(__LITTLE_ENDIAN_BITFIELD) 1553 struct { 1554 __u32 var1_dw; 1555 __u16 var2_w; 1556 __u16 var3_w; 1557 }; 1558 #elif defined(__BIG_ENDIAN_BITFIELD) 1559 struct { 1560 __u16 var3_w; 1561 __u16 var2_w; 1562 __u32 var1_dw; 1563 }; 1564 #else 1565 # error "Unknown endianness" 1566 #endif 1567 }; 1568 1569 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1570