1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 #ifndef _ASM_X86_PERF_REGS_H 3 #define _ASM_X86_PERF_REGS_H 4 5 #include <linux/bits.h> 6 7 enum perf_event_x86_regs { 8 PERF_REG_X86_AX, 9 PERF_REG_X86_BX, 10 PERF_REG_X86_CX, 11 PERF_REG_X86_DX, 12 PERF_REG_X86_SI, 13 PERF_REG_X86_DI, 14 PERF_REG_X86_BP, 15 PERF_REG_X86_SP, 16 PERF_REG_X86_IP, 17 PERF_REG_X86_FLAGS, 18 PERF_REG_X86_CS, 19 PERF_REG_X86_SS, 20 PERF_REG_X86_DS, 21 PERF_REG_X86_ES, 22 PERF_REG_X86_FS, 23 PERF_REG_X86_GS, 24 PERF_REG_X86_R8, 25 PERF_REG_X86_R9, 26 PERF_REG_X86_R10, 27 PERF_REG_X86_R11, 28 PERF_REG_X86_R12, 29 PERF_REG_X86_R13, 30 PERF_REG_X86_R14, 31 PERF_REG_X86_R15, 32 /* 33 * The eGPRs/SSP and XMM have overlaps. Only one can be used 34 * at a time. The ABI PERF_SAMPLE_REGS_ABI_SIMD is used to 35 * distinguish which one is used. If PERF_SAMPLE_REGS_ABI_SIMD 36 * is set, then eGPRs/SSP is used, otherwise, XMM is used. 37 * 38 * Extended GPRs (eGPRs) 39 */ 40 PERF_REG_X86_R16, 41 PERF_REG_X86_R17, 42 PERF_REG_X86_R18, 43 PERF_REG_X86_R19, 44 PERF_REG_X86_R20, 45 PERF_REG_X86_R21, 46 PERF_REG_X86_R22, 47 PERF_REG_X86_R23, 48 PERF_REG_X86_R24, 49 PERF_REG_X86_R25, 50 PERF_REG_X86_R26, 51 PERF_REG_X86_R27, 52 PERF_REG_X86_R28, 53 PERF_REG_X86_R29, 54 PERF_REG_X86_R30, 55 PERF_REG_X86_R31, 56 PERF_REG_X86_SSP, 57 /* These are the limits for the GPRs. */ 58 PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1, 59 PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1, 60 PERF_REG_MISC_MAX = PERF_REG_X86_SSP + 1, 61 62 /* These all need two bits set because they are 128bit */ 63 PERF_REG_X86_XMM0 = 32, 64 PERF_REG_X86_XMM1 = 34, 65 PERF_REG_X86_XMM2 = 36, 66 PERF_REG_X86_XMM3 = 38, 67 PERF_REG_X86_XMM4 = 40, 68 PERF_REG_X86_XMM5 = 42, 69 PERF_REG_X86_XMM6 = 44, 70 PERF_REG_X86_XMM7 = 46, 71 PERF_REG_X86_XMM8 = 48, 72 PERF_REG_X86_XMM9 = 50, 73 PERF_REG_X86_XMM10 = 52, 74 PERF_REG_X86_XMM11 = 54, 75 PERF_REG_X86_XMM12 = 56, 76 PERF_REG_X86_XMM13 = 58, 77 PERF_REG_X86_XMM14 = 60, 78 PERF_REG_X86_XMM15 = 62, 79 80 /* These include both GPRs and XMMX registers */ 81 PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2, 82 }; 83 84 #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) 85 #define PERF_X86_EGPRS_MASK __GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R16) 86 87 enum { 88 PERF_X86_SIMD_XMM_REGS = 16, 89 PERF_X86_SIMD_YMM_REGS = 16, 90 PERF_X86_SIMD_ZMM_REGS = 32, 91 PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_ZMM_REGS, 92 93 PERF_X86_SIMD_OPMASK_REGS = 8, 94 PERF_X86_SIMD_PRED_REGS_MAX = PERF_X86_SIMD_OPMASK_REGS, 95 }; 96 97 #define PERF_X86_SIMD_PRED_MASK __GENMASK(PERF_X86_SIMD_PRED_REGS_MAX - 1, 0) 98 #define PERF_X86_SIMD_VEC_MASK __GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0) 99 100 #define PERF_X86_H16ZMM_BASE 16 101 102 enum { 103 /* 1 qword = 8 bytes */ 104 PERF_X86_OPMASK_QWORDS = 1, 105 PERF_X86_XMM_QWORDS = 2, 106 PERF_X86_YMM_QWORDS = 4, 107 PERF_X86_ZMM_QWORDS = 8, 108 PERF_X86_SIMD_QWORDS_MAX = PERF_X86_ZMM_QWORDS, 109 }; 110 111 #endif /* _ASM_X86_PERF_REGS_H */ 112