1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * VGICv3 MMIO handling functions 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/irqchip/arm-gic-v3.h> 8 #include <linux/kvm.h> 9 #include <linux/kvm_host.h> 10 #include <linux/interrupt.h> 11 #include <kvm/iodev.h> 12 #include <kvm/arm_vgic.h> 13 14 #include <asm/kvm_emulate.h> 15 #include <asm/kvm_arm.h> 16 #include <asm/kvm_mmu.h> 17 18 #include "vgic.h" 19 #include "vgic-mmio.h" 20 21 /* extract @num bytes at @offset bytes offset in data */ 22 unsigned long extract_bytes(u64 data, unsigned int offset, 23 unsigned int num) 24 { 25 return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0); 26 } 27 28 /* allows updates of any half of a 64-bit register (or the whole thing) */ 29 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, 30 unsigned long val) 31 { 32 int lower = (offset & 4) * 8; 33 int upper = lower + 8 * len - 1; 34 35 reg &= ~GENMASK_ULL(upper, lower); 36 val &= GENMASK_ULL(len * 8 - 1, 0); 37 38 return reg | ((u64)val << lower); 39 } 40 41 bool vgic_has_its(struct kvm *kvm) 42 { 43 struct vgic_dist *dist = &kvm->arch.vgic; 44 45 if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) 46 return false; 47 48 return dist->has_its; 49 } 50 51 bool vgic_supports_direct_msis(struct kvm *kvm) 52 { 53 /* 54 * Deliberately conflate vLPI and vSGI support on GICv4.1 hardware, 55 * indirectly allowing userspace to control whether or not vPEs are 56 * allocated for the VM. 57 */ 58 if (system_supports_direct_sgis() && !vgic_supports_direct_sgis(kvm)) 59 return false; 60 61 return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm); 62 } 63 64 bool system_supports_direct_sgis(void) 65 { 66 return kvm_vgic_global_state.has_gicv4_1 && gic_cpuif_has_vsgi(); 67 } 68 69 bool vgic_supports_direct_sgis(struct kvm *kvm) 70 { 71 return kvm->arch.vgic.nassgicap; 72 } 73 74 /* 75 * The Revision field in the IIDR have the following meanings: 76 * 77 * Revision 2: Interrupt groups are guest-configurable and signaled using 78 * their configured groups. 79 */ 80 81 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, 82 gpa_t addr, unsigned int len) 83 { 84 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 85 u32 value = 0; 86 87 switch (addr & 0x0c) { 88 case GICD_CTLR: 89 if (vgic->enabled) 90 value |= GICD_CTLR_ENABLE_SS_G1; 91 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS; 92 if (vgic->nassgireq) 93 value |= GICD_CTLR_nASSGIreq; 94 break; 95 case GICD_TYPER: 96 value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS; 97 value = (value >> 5) - 1; 98 if (vgic_has_its(vcpu->kvm)) { 99 value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; 100 value |= GICD_TYPER_LPIS; 101 } else { 102 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; 103 } 104 break; 105 case GICD_TYPER2: 106 if (vgic_supports_direct_sgis(vcpu->kvm)) 107 value = GICD_TYPER2_nASSGIcap; 108 break; 109 case GICD_IIDR: 110 value = (PRODUCT_ID_KVM << GICD_IIDR_PRODUCT_ID_SHIFT) | 111 (vgic->implementation_rev << GICD_IIDR_REVISION_SHIFT) | 112 (IMPLEMENTER_ARM << GICD_IIDR_IMPLEMENTER_SHIFT); 113 break; 114 default: 115 return 0; 116 } 117 118 return value; 119 } 120 121 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu, 122 gpa_t addr, unsigned int len, 123 unsigned long val) 124 { 125 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 126 127 switch (addr & 0x0c) { 128 case GICD_CTLR: { 129 bool was_enabled, is_hwsgi; 130 131 mutex_lock(&vcpu->kvm->arch.config_lock); 132 133 was_enabled = dist->enabled; 134 is_hwsgi = dist->nassgireq; 135 136 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 137 138 /* Not a GICv4.1? No HW SGIs */ 139 if (!vgic_supports_direct_sgis(vcpu->kvm)) 140 val &= ~GICD_CTLR_nASSGIreq; 141 142 /* Dist stays enabled? nASSGIreq is RO */ 143 if (was_enabled && dist->enabled) { 144 val &= ~GICD_CTLR_nASSGIreq; 145 val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi); 146 } 147 148 /* Switching HW SGIs? */ 149 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 150 if (is_hwsgi != dist->nassgireq) 151 vgic_v4_configure_vsgis(vcpu->kvm); 152 153 if (vgic_supports_direct_sgis(vcpu->kvm) && 154 was_enabled != dist->enabled) 155 kvm_make_all_cpus_request(vcpu->kvm, KVM_REQ_RELOAD_GICv4); 156 else if (!was_enabled && dist->enabled) 157 vgic_kick_vcpus(vcpu->kvm); 158 159 mutex_unlock(&vcpu->kvm->arch.config_lock); 160 break; 161 } 162 case GICD_TYPER: 163 case GICD_TYPER2: 164 case GICD_IIDR: 165 /* This is at best for documentation purposes... */ 166 return; 167 } 168 } 169 170 static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu, 171 gpa_t addr, unsigned int len, 172 unsigned long val) 173 { 174 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 175 u32 reg; 176 177 switch (addr & 0x0c) { 178 case GICD_TYPER2: 179 reg = vgic_mmio_read_v3_misc(vcpu, addr, len); 180 181 if (reg == val) 182 return 0; 183 if (vgic_initialized(vcpu->kvm)) 184 return -EBUSY; 185 if ((reg ^ val) & ~GICD_TYPER2_nASSGIcap) 186 return -EINVAL; 187 if (!system_supports_direct_sgis() && val) 188 return -EINVAL; 189 190 dist->nassgicap = val & GICD_TYPER2_nASSGIcap; 191 return 0; 192 case GICD_IIDR: 193 reg = vgic_mmio_read_v3_misc(vcpu, addr, len); 194 if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK) 195 return -EINVAL; 196 197 reg = FIELD_GET(GICD_IIDR_REVISION_MASK, val); 198 switch (reg) { 199 case KVM_VGIC_IMP_REV_2: 200 case KVM_VGIC_IMP_REV_3: 201 dist->implementation_rev = reg; 202 return 0; 203 default: 204 return -EINVAL; 205 } 206 case GICD_CTLR: 207 /* Not a GICv4.1? No HW SGIs */ 208 if (!vgic_supports_direct_sgis(vcpu->kvm)) 209 val &= ~GICD_CTLR_nASSGIreq; 210 211 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; 212 dist->nassgireq = val & GICD_CTLR_nASSGIreq; 213 return 0; 214 } 215 216 vgic_mmio_write_v3_misc(vcpu, addr, len, val); 217 return 0; 218 } 219 220 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu, 221 gpa_t addr, unsigned int len) 222 { 223 int intid = VGIC_ADDR_TO_INTID(addr, 64); 224 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, intid); 225 unsigned long ret = 0; 226 227 if (!irq) 228 return 0; 229 230 /* The upper word is RAZ for us. */ 231 if (!(addr & 4)) 232 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len); 233 234 vgic_put_irq(vcpu->kvm, irq); 235 return ret; 236 } 237 238 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu, 239 gpa_t addr, unsigned int len, 240 unsigned long val) 241 { 242 int intid = VGIC_ADDR_TO_INTID(addr, 64); 243 struct vgic_irq *irq; 244 unsigned long flags; 245 246 /* The upper word is WI for us since we don't implement Aff3. */ 247 if (addr & 4) 248 return; 249 250 irq = vgic_get_irq(vcpu->kvm, intid); 251 252 if (!irq) 253 return; 254 255 raw_spin_lock_irqsave(&irq->irq_lock, flags); 256 257 /* We only care about and preserve Aff0, Aff1 and Aff2. */ 258 irq->mpidr = val & GENMASK(23, 0); 259 irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr); 260 261 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 262 vgic_put_irq(vcpu->kvm, irq); 263 } 264 265 bool vgic_lpis_enabled(struct kvm_vcpu *vcpu) 266 { 267 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 268 269 return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS; 270 } 271 272 static unsigned long vgic_mmio_read_v3r_ctlr(struct kvm_vcpu *vcpu, 273 gpa_t addr, unsigned int len) 274 { 275 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 276 unsigned long val; 277 278 val = atomic_read(&vgic_cpu->ctlr); 279 if (vgic_get_implementation_rev(vcpu) >= KVM_VGIC_IMP_REV_3) 280 val |= GICR_CTLR_IR | GICR_CTLR_CES; 281 282 return val; 283 } 284 285 static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu, 286 gpa_t addr, unsigned int len, 287 unsigned long val) 288 { 289 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 290 u32 ctlr; 291 292 if (!vgic_has_its(vcpu->kvm)) 293 return; 294 295 if (!(val & GICR_CTLR_ENABLE_LPIS)) { 296 /* 297 * Don't disable if RWP is set, as there already an 298 * ongoing disable. Funky guest... 299 */ 300 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 301 GICR_CTLR_ENABLE_LPIS, 302 GICR_CTLR_RWP); 303 if (ctlr != GICR_CTLR_ENABLE_LPIS) 304 return; 305 306 vgic_flush_pending_lpis(vcpu); 307 vgic_its_invalidate_all_caches(vcpu->kvm); 308 atomic_set_release(&vgic_cpu->ctlr, 0); 309 } else { 310 ctlr = atomic_cmpxchg_acquire(&vgic_cpu->ctlr, 0, 311 GICR_CTLR_ENABLE_LPIS); 312 if (ctlr != 0) 313 return; 314 315 vgic_enable_lpis(vcpu); 316 } 317 } 318 319 static bool vgic_mmio_vcpu_rdist_is_last(struct kvm_vcpu *vcpu) 320 { 321 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic; 322 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 323 struct vgic_redist_region *iter, *rdreg = vgic_cpu->rdreg; 324 325 if (!rdreg) 326 return false; 327 328 if (vgic_cpu->rdreg_index < rdreg->free_index - 1) { 329 return false; 330 } else if (rdreg->count && vgic_cpu->rdreg_index == (rdreg->count - 1)) { 331 struct list_head *rd_regions = &vgic->rd_regions; 332 gpa_t end = rdreg->base + rdreg->count * KVM_VGIC_V3_REDIST_SIZE; 333 334 /* 335 * the rdist is the last one of the redist region, 336 * check whether there is no other contiguous rdist region 337 */ 338 list_for_each_entry(iter, rd_regions, list) { 339 if (iter->base == end && iter->free_index > 0) 340 return false; 341 } 342 } 343 return true; 344 } 345 346 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu, 347 gpa_t addr, unsigned int len) 348 { 349 unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu); 350 int target_vcpu_id = vcpu->vcpu_id; 351 u64 value; 352 353 value = (u64)(mpidr & GENMASK(23, 0)) << 32; 354 value |= ((target_vcpu_id & 0xffff) << 8); 355 356 if (vgic_has_its(vcpu->kvm)) 357 value |= GICR_TYPER_PLPIS; 358 359 if (vgic_mmio_vcpu_rdist_is_last(vcpu)) 360 value |= GICR_TYPER_LAST; 361 362 return extract_bytes(value, addr & 7, len); 363 } 364 365 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu, 366 gpa_t addr, unsigned int len) 367 { 368 return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); 369 } 370 371 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu, 372 gpa_t addr, unsigned int len) 373 { 374 switch (addr & 0xffff) { 375 case GICD_PIDR2: 376 /* report a GICv3 compliant implementation */ 377 return 0x3b; 378 } 379 380 return 0; 381 } 382 383 static int vgic_v3_uaccess_write_pending(struct kvm_vcpu *vcpu, 384 gpa_t addr, unsigned int len, 385 unsigned long val) 386 { 387 int ret; 388 389 ret = vgic_uaccess_write_spending(vcpu, addr, len, val); 390 if (ret) 391 return ret; 392 393 return vgic_uaccess_write_cpending(vcpu, addr, len, ~val); 394 } 395 396 /* We want to avoid outer shareable. */ 397 u64 vgic_sanitise_shareability(u64 field) 398 { 399 switch (field) { 400 case GIC_BASER_OuterShareable: 401 return GIC_BASER_InnerShareable; 402 default: 403 return field; 404 } 405 } 406 407 /* Avoid any inner non-cacheable mapping. */ 408 u64 vgic_sanitise_inner_cacheability(u64 field) 409 { 410 switch (field) { 411 case GIC_BASER_CACHE_nCnB: 412 case GIC_BASER_CACHE_nC: 413 return GIC_BASER_CACHE_RaWb; 414 default: 415 return field; 416 } 417 } 418 419 /* Non-cacheable or same-as-inner are OK. */ 420 u64 vgic_sanitise_outer_cacheability(u64 field) 421 { 422 switch (field) { 423 case GIC_BASER_CACHE_SameAsInner: 424 case GIC_BASER_CACHE_nC: 425 return field; 426 default: 427 return GIC_BASER_CACHE_SameAsInner; 428 } 429 } 430 431 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, 432 u64 (*sanitise_fn)(u64)) 433 { 434 u64 field = (reg & field_mask) >> field_shift; 435 436 field = sanitise_fn(field) << field_shift; 437 return (reg & ~field_mask) | field; 438 } 439 440 #define PROPBASER_RES0_MASK \ 441 (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5)) 442 #define PENDBASER_RES0_MASK \ 443 (BIT_ULL(63) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \ 444 GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0)) 445 446 static u64 vgic_sanitise_pendbaser(u64 reg) 447 { 448 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK, 449 GICR_PENDBASER_SHAREABILITY_SHIFT, 450 vgic_sanitise_shareability); 451 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK, 452 GICR_PENDBASER_INNER_CACHEABILITY_SHIFT, 453 vgic_sanitise_inner_cacheability); 454 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK, 455 GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT, 456 vgic_sanitise_outer_cacheability); 457 458 reg &= ~PENDBASER_RES0_MASK; 459 460 return reg; 461 } 462 463 static u64 vgic_sanitise_propbaser(u64 reg) 464 { 465 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK, 466 GICR_PROPBASER_SHAREABILITY_SHIFT, 467 vgic_sanitise_shareability); 468 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK, 469 GICR_PROPBASER_INNER_CACHEABILITY_SHIFT, 470 vgic_sanitise_inner_cacheability); 471 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK, 472 GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT, 473 vgic_sanitise_outer_cacheability); 474 475 reg &= ~PROPBASER_RES0_MASK; 476 return reg; 477 } 478 479 static unsigned long vgic_mmio_read_propbase(struct kvm_vcpu *vcpu, 480 gpa_t addr, unsigned int len) 481 { 482 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 483 484 return extract_bytes(dist->propbaser, addr & 7, len); 485 } 486 487 static void vgic_mmio_write_propbase(struct kvm_vcpu *vcpu, 488 gpa_t addr, unsigned int len, 489 unsigned long val) 490 { 491 struct vgic_dist *dist = &vcpu->kvm->arch.vgic; 492 u64 old_propbaser, propbaser; 493 494 /* Storing a value with LPIs already enabled is undefined */ 495 if (vgic_lpis_enabled(vcpu)) 496 return; 497 498 do { 499 old_propbaser = READ_ONCE(dist->propbaser); 500 propbaser = old_propbaser; 501 propbaser = update_64bit_reg(propbaser, addr & 4, len, val); 502 propbaser = vgic_sanitise_propbaser(propbaser); 503 } while (cmpxchg64(&dist->propbaser, old_propbaser, 504 propbaser) != old_propbaser); 505 } 506 507 static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu, 508 gpa_t addr, unsigned int len) 509 { 510 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 511 u64 value = vgic_cpu->pendbaser; 512 513 value &= ~GICR_PENDBASER_PTZ; 514 515 return extract_bytes(value, addr & 7, len); 516 } 517 518 static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu, 519 gpa_t addr, unsigned int len, 520 unsigned long val) 521 { 522 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 523 u64 old_pendbaser, pendbaser; 524 525 /* Storing a value with LPIs already enabled is undefined */ 526 if (vgic_lpis_enabled(vcpu)) 527 return; 528 529 do { 530 old_pendbaser = READ_ONCE(vgic_cpu->pendbaser); 531 pendbaser = old_pendbaser; 532 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val); 533 pendbaser = vgic_sanitise_pendbaser(pendbaser); 534 } while (cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser, 535 pendbaser) != old_pendbaser); 536 } 537 538 static unsigned long vgic_mmio_read_sync(struct kvm_vcpu *vcpu, 539 gpa_t addr, unsigned int len) 540 { 541 return !!atomic_read(&vcpu->arch.vgic_cpu.syncr_busy); 542 } 543 544 static void vgic_set_rdist_busy(struct kvm_vcpu *vcpu, bool busy) 545 { 546 if (busy) { 547 atomic_inc(&vcpu->arch.vgic_cpu.syncr_busy); 548 smp_mb__after_atomic(); 549 } else { 550 smp_mb__before_atomic(); 551 atomic_dec(&vcpu->arch.vgic_cpu.syncr_busy); 552 } 553 } 554 555 static void vgic_mmio_write_invlpi(struct kvm_vcpu *vcpu, 556 gpa_t addr, unsigned int len, 557 unsigned long val) 558 { 559 struct vgic_irq *irq; 560 u32 intid; 561 562 /* 563 * If the guest wrote only to the upper 32bit part of the 564 * register, drop the write on the floor, as it is only for 565 * vPEs (which we don't support for obvious reasons). 566 * 567 * Also discard the access if LPIs are not enabled. 568 */ 569 if ((addr & 4) || !vgic_lpis_enabled(vcpu)) 570 return; 571 572 intid = lower_32_bits(val); 573 if (intid < VGIC_MIN_LPI) 574 return; 575 576 vgic_set_rdist_busy(vcpu, true); 577 578 irq = vgic_get_irq(vcpu->kvm, intid); 579 if (irq) { 580 vgic_its_inv_lpi(vcpu->kvm, irq); 581 vgic_put_irq(vcpu->kvm, irq); 582 } 583 584 vgic_set_rdist_busy(vcpu, false); 585 } 586 587 static void vgic_mmio_write_invall(struct kvm_vcpu *vcpu, 588 gpa_t addr, unsigned int len, 589 unsigned long val) 590 { 591 /* See vgic_mmio_write_invlpi() for the early return rationale */ 592 if ((addr & 4) || !vgic_lpis_enabled(vcpu)) 593 return; 594 595 vgic_set_rdist_busy(vcpu, true); 596 vgic_its_invall(vcpu); 597 vgic_set_rdist_busy(vcpu, false); 598 } 599 600 /* 601 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the 602 * redistributors, while SPIs are covered by registers in the distributor 603 * block. Trying to set private IRQs in this block gets ignored. 604 * We take some special care here to fix the calculation of the register 605 * offset. 606 */ 607 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, ur, uw, bpi, acc) \ 608 { \ 609 .reg_offset = off, \ 610 .bits_per_irq = bpi, \ 611 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 612 .access_flags = acc, \ 613 .read = vgic_mmio_read_raz, \ 614 .write = vgic_mmio_write_wi, \ 615 }, { \ 616 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8, \ 617 .bits_per_irq = bpi, \ 618 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8, \ 619 .access_flags = acc, \ 620 .read = rd, \ 621 .write = wr, \ 622 .uaccess_read = ur, \ 623 .uaccess_write = uw, \ 624 } 625 626 static const struct vgic_register_region vgic_v3_dist_registers[] = { 627 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR, 628 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 629 NULL, vgic_mmio_uaccess_write_v3_misc, 630 16, VGIC_ACCESS_32bit), 631 REGISTER_DESC_WITH_LENGTH(GICD_STATUSR, 632 vgic_mmio_read_rao, vgic_mmio_write_wi, 4, 633 VGIC_ACCESS_32bit), 634 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR, 635 vgic_mmio_read_group, vgic_mmio_write_group, NULL, NULL, 1, 636 VGIC_ACCESS_32bit), 637 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER, 638 vgic_mmio_read_enable, vgic_mmio_write_senable, 639 NULL, vgic_uaccess_write_senable, 1, 640 VGIC_ACCESS_32bit), 641 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER, 642 vgic_mmio_read_enable, vgic_mmio_write_cenable, 643 NULL, vgic_uaccess_write_cenable, 1, 644 VGIC_ACCESS_32bit), 645 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR, 646 vgic_mmio_read_pending, vgic_mmio_write_spending, 647 vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 1, 648 VGIC_ACCESS_32bit), 649 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR, 650 vgic_mmio_read_pending, vgic_mmio_write_cpending, 651 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 1, 652 VGIC_ACCESS_32bit), 653 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER, 654 vgic_mmio_read_active, vgic_mmio_write_sactive, 655 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 1, 656 VGIC_ACCESS_32bit), 657 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER, 658 vgic_mmio_read_active, vgic_mmio_write_cactive, 659 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 660 1, VGIC_ACCESS_32bit), 661 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR, 662 vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, 663 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 664 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR, 665 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, 666 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 667 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR, 668 vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, 669 VGIC_ACCESS_32bit), 670 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR, 671 vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, 672 VGIC_ACCESS_32bit), 673 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER, 674 vgic_mmio_read_irouter, vgic_mmio_write_irouter, NULL, NULL, 64, 675 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 676 REGISTER_DESC_WITH_LENGTH(GICD_IDREGS, 677 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 678 VGIC_ACCESS_32bit), 679 }; 680 681 static const struct vgic_register_region vgic_v3_rd_registers[] = { 682 /* RD_base registers */ 683 REGISTER_DESC_WITH_LENGTH(GICR_CTLR, 684 vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4, 685 VGIC_ACCESS_32bit), 686 REGISTER_DESC_WITH_LENGTH(GICR_STATUSR, 687 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 688 VGIC_ACCESS_32bit), 689 REGISTER_DESC_WITH_LENGTH(GICR_IIDR, 690 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4, 691 VGIC_ACCESS_32bit), 692 REGISTER_DESC_WITH_LENGTH_UACCESS(GICR_TYPER, 693 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 694 NULL, vgic_mmio_uaccess_write_wi, 8, 695 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 696 REGISTER_DESC_WITH_LENGTH(GICR_WAKER, 697 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 698 VGIC_ACCESS_32bit), 699 REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER, 700 vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8, 701 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 702 REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER, 703 vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8, 704 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 705 REGISTER_DESC_WITH_LENGTH(GICR_INVLPIR, 706 vgic_mmio_read_raz, vgic_mmio_write_invlpi, 8, 707 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 708 REGISTER_DESC_WITH_LENGTH(GICR_INVALLR, 709 vgic_mmio_read_raz, vgic_mmio_write_invall, 8, 710 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit), 711 REGISTER_DESC_WITH_LENGTH(GICR_SYNCR, 712 vgic_mmio_read_sync, vgic_mmio_write_wi, 4, 713 VGIC_ACCESS_32bit), 714 REGISTER_DESC_WITH_LENGTH(GICR_IDREGS, 715 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48, 716 VGIC_ACCESS_32bit), 717 /* SGI_base registers */ 718 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0, 719 vgic_mmio_read_group, vgic_mmio_write_group, 4, 720 VGIC_ACCESS_32bit), 721 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISENABLER0, 722 vgic_mmio_read_enable, vgic_mmio_write_senable, 723 NULL, vgic_uaccess_write_senable, 4, 724 VGIC_ACCESS_32bit), 725 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICENABLER0, 726 vgic_mmio_read_enable, vgic_mmio_write_cenable, 727 NULL, vgic_uaccess_write_cenable, 4, 728 VGIC_ACCESS_32bit), 729 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISPENDR0, 730 vgic_mmio_read_pending, vgic_mmio_write_spending, 731 vgic_uaccess_read_pending, vgic_v3_uaccess_write_pending, 4, 732 VGIC_ACCESS_32bit), 733 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICPENDR0, 734 vgic_mmio_read_pending, vgic_mmio_write_cpending, 735 vgic_mmio_read_raz, vgic_mmio_uaccess_write_wi, 4, 736 VGIC_ACCESS_32bit), 737 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ISACTIVER0, 738 vgic_mmio_read_active, vgic_mmio_write_sactive, 739 vgic_uaccess_read_active, vgic_mmio_uaccess_write_sactive, 4, 740 VGIC_ACCESS_32bit), 741 REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_ICACTIVER0, 742 vgic_mmio_read_active, vgic_mmio_write_cactive, 743 vgic_uaccess_read_active, vgic_mmio_uaccess_write_cactive, 4, 744 VGIC_ACCESS_32bit), 745 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0, 746 vgic_mmio_read_priority, vgic_mmio_write_priority, 32, 747 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), 748 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0, 749 vgic_mmio_read_config, vgic_mmio_write_config, 8, 750 VGIC_ACCESS_32bit), 751 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0, 752 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 753 VGIC_ACCESS_32bit), 754 REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR, 755 vgic_mmio_read_raz, vgic_mmio_write_wi, 4, 756 VGIC_ACCESS_32bit), 757 }; 758 759 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev) 760 { 761 dev->regions = vgic_v3_dist_registers; 762 dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 763 764 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops); 765 766 return SZ_64K; 767 } 768 769 /** 770 * vgic_register_redist_iodev - register a single redist iodev 771 * @vcpu: The VCPU to which the redistributor belongs 772 * 773 * Register a KVM iodev for this VCPU's redistributor using the address 774 * provided. 775 * 776 * Return 0 on success, -ERRNO otherwise. 777 */ 778 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu) 779 { 780 struct kvm *kvm = vcpu->kvm; 781 struct vgic_dist *vgic = &kvm->arch.vgic; 782 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; 783 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 784 struct vgic_redist_region *rdreg; 785 gpa_t rd_base; 786 int ret = 0; 787 788 lockdep_assert_held(&kvm->slots_lock); 789 mutex_lock(&kvm->arch.config_lock); 790 791 if (!IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) 792 goto out_unlock; 793 794 /* 795 * We may be creating VCPUs before having set the base address for the 796 * redistributor region, in which case we will come back to this 797 * function for all VCPUs when the base address is set. Just return 798 * without doing any work for now. 799 */ 800 rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions); 801 if (!rdreg) 802 goto out_unlock; 803 804 if (!vgic_v3_check_base(kvm)) { 805 ret = -EINVAL; 806 goto out_unlock; 807 } 808 809 vgic_cpu->rdreg = rdreg; 810 vgic_cpu->rdreg_index = rdreg->free_index; 811 812 rd_base = rdreg->base + rdreg->free_index * KVM_VGIC_V3_REDIST_SIZE; 813 814 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops); 815 rd_dev->base_addr = rd_base; 816 rd_dev->iodev_type = IODEV_REDIST; 817 rd_dev->regions = vgic_v3_rd_registers; 818 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 819 rd_dev->redist_vcpu = vcpu; 820 821 /* Protected by slots_lock */ 822 rdreg->free_index++; 823 824 mutex_unlock(&kvm->arch.config_lock); 825 826 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base, 827 2 * SZ_64K, &rd_dev->dev); 828 if (ret) { 829 guard(mutex)(&vcpu->kvm->arch.config_lock); 830 vgic_cpu->rdreg->free_index--; 831 vgic_cpu->rdreg = NULL; 832 vgic_cpu->rd_iodev.base_addr = VGIC_ADDR_UNDEF; 833 } 834 835 return ret; 836 837 out_unlock: 838 mutex_unlock(&kvm->arch.config_lock); 839 return ret; 840 } 841 842 void vgic_unregister_redist_iodev(struct kvm_vcpu *vcpu) 843 { 844 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev; 845 846 kvm_io_bus_unregister_dev(vcpu->kvm, KVM_MMIO_BUS, &rd_dev->dev); 847 } 848 849 static int vgic_register_all_redist_iodevs(struct kvm *kvm, 850 struct vgic_redist_region *rdreg) 851 { 852 struct kvm_vcpu *vcpu; 853 unsigned long c; 854 int ret = 0; 855 856 lockdep_assert_held(&kvm->slots_lock); 857 858 kvm_for_each_vcpu(c, vcpu, kvm) { 859 ret = vgic_register_redist_iodev(vcpu); 860 if (ret) 861 break; 862 } 863 864 if (ret) { 865 /* The current c failed, so iterate over the previous ones. */ 866 int i; 867 868 for (i = 0; i < c; i++) { 869 vcpu = kvm_get_vcpu(kvm, i); 870 if (vcpu->arch.vgic_cpu.rdreg != rdreg) 871 continue; 872 873 vgic_unregister_redist_iodev(vcpu); 874 875 guard(mutex)(&vcpu->kvm->arch.config_lock); 876 vcpu->arch.vgic_cpu.rdreg = NULL; 877 vcpu->arch.vgic_cpu.rd_iodev.base_addr = VGIC_ADDR_UNDEF; 878 } 879 } 880 881 return ret; 882 } 883 884 /** 885 * vgic_v3_alloc_redist_region - Allocate a new redistributor region 886 * 887 * Performs various checks before inserting the rdist region in the list. 888 * Those tests depend on whether the size of the rdist region is known 889 * (ie. count != 0). The list is sorted by rdist region index. 890 * 891 * @kvm: kvm handle 892 * @index: redist region index 893 * @base: base of the new rdist region 894 * @count: number of redistributors the region is made of (0 in the old style 895 * single region, whose size is induced from the number of vcpus) 896 * 897 * Return 0 on success, < 0 otherwise 898 */ 899 static int vgic_v3_alloc_redist_region(struct kvm *kvm, uint32_t index, 900 gpa_t base, uint32_t count) 901 { 902 struct vgic_dist *d = &kvm->arch.vgic; 903 struct vgic_redist_region *rdreg; 904 struct list_head *rd_regions = &d->rd_regions; 905 int nr_vcpus = atomic_read(&kvm->online_vcpus); 906 size_t size = count ? count * KVM_VGIC_V3_REDIST_SIZE 907 : nr_vcpus * KVM_VGIC_V3_REDIST_SIZE; 908 int ret; 909 910 /* cross the end of memory ? */ 911 if (base + size < base) 912 return -EINVAL; 913 914 if (list_empty(rd_regions)) { 915 if (index != 0) 916 return -EINVAL; 917 } else { 918 rdreg = list_last_entry(rd_regions, 919 struct vgic_redist_region, list); 920 921 /* Don't mix single region and discrete redist regions */ 922 if (!count && rdreg->count) 923 return -EINVAL; 924 925 if (!count) 926 return -EEXIST; 927 928 if (index != rdreg->index + 1) 929 return -EINVAL; 930 } 931 932 /* 933 * For legacy single-region redistributor regions (!count), 934 * check that the redistributor region does not overlap with the 935 * distributor's address space. 936 */ 937 if (!count && !IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && 938 vgic_dist_overlap(kvm, base, size)) 939 return -EINVAL; 940 941 /* collision with any other rdist region? */ 942 if (vgic_v3_rdist_overlap(kvm, base, size)) 943 return -EINVAL; 944 945 rdreg = kzalloc_obj(*rdreg, GFP_KERNEL_ACCOUNT); 946 if (!rdreg) 947 return -ENOMEM; 948 949 rdreg->base = VGIC_ADDR_UNDEF; 950 951 ret = vgic_check_iorange(kvm, rdreg->base, base, SZ_64K, size); 952 if (ret) 953 goto free; 954 955 rdreg->base = base; 956 rdreg->count = count; 957 rdreg->free_index = 0; 958 rdreg->index = index; 959 960 list_add_tail(&rdreg->list, rd_regions); 961 return 0; 962 free: 963 kfree(rdreg); 964 return ret; 965 } 966 967 void vgic_v3_free_redist_region(struct kvm *kvm, struct vgic_redist_region *rdreg) 968 { 969 struct kvm_vcpu *vcpu; 970 unsigned long c; 971 972 lockdep_assert_held(&kvm->arch.config_lock); 973 974 /* Garbage collect the region */ 975 kvm_for_each_vcpu(c, vcpu, kvm) { 976 if (vcpu->arch.vgic_cpu.rdreg == rdreg) 977 vcpu->arch.vgic_cpu.rdreg = NULL; 978 } 979 980 list_del(&rdreg->list); 981 kfree(rdreg); 982 } 983 984 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count) 985 { 986 struct vgic_redist_region *rdreg; 987 int ret; 988 989 mutex_lock(&kvm->arch.config_lock); 990 ret = vgic_v3_alloc_redist_region(kvm, index, addr, count); 991 if (!ret) 992 rdreg = vgic_v3_rdist_region_from_index(kvm, index); 993 mutex_unlock(&kvm->arch.config_lock); 994 if (ret) 995 return ret; 996 997 /* 998 * Register iodevs for each existing VCPU. Adding more VCPUs 999 * afterwards will register the iodevs when needed. 1000 */ 1001 ret = vgic_register_all_redist_iodevs(kvm, rdreg); 1002 if (ret) { 1003 mutex_lock(&kvm->arch.config_lock); 1004 vgic_v3_free_redist_region(kvm, rdreg); 1005 mutex_unlock(&kvm->arch.config_lock); 1006 return ret; 1007 } 1008 1009 return 0; 1010 } 1011 1012 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr) 1013 { 1014 const struct vgic_register_region *region; 1015 struct vgic_io_device iodev; 1016 struct vgic_reg_attr reg_attr; 1017 struct kvm_vcpu *vcpu; 1018 gpa_t addr; 1019 int ret; 1020 1021 ret = vgic_v3_parse_attr(dev, attr, ®_attr); 1022 if (ret) 1023 return ret; 1024 1025 vcpu = reg_attr.vcpu; 1026 addr = reg_attr.addr; 1027 1028 switch (attr->group) { 1029 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: 1030 iodev.regions = vgic_v3_dist_registers; 1031 iodev.nr_regions = ARRAY_SIZE(vgic_v3_dist_registers); 1032 iodev.base_addr = 0; 1033 break; 1034 case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS:{ 1035 iodev.regions = vgic_v3_rd_registers; 1036 iodev.nr_regions = ARRAY_SIZE(vgic_v3_rd_registers); 1037 iodev.base_addr = 0; 1038 break; 1039 } 1040 case KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS: 1041 return vgic_v3_has_cpu_sysregs_attr(vcpu, attr); 1042 default: 1043 return -ENXIO; 1044 } 1045 1046 /* We only support aligned 32-bit accesses. */ 1047 if (addr & 3) 1048 return -ENXIO; 1049 1050 region = vgic_get_mmio_region(vcpu, &iodev, addr, sizeof(u32)); 1051 if (!region) 1052 return -ENXIO; 1053 1054 return 0; 1055 } 1056 1057 /* 1058 * The ICC_SGI* registers encode the affinity differently from the MPIDR, 1059 * so provide a wrapper to use the existing defines to isolate a certain 1060 * affinity level. 1061 */ 1062 #define SGI_AFFINITY_LEVEL(reg, level) \ 1063 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ 1064 >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level)) 1065 1066 static void vgic_v3_queue_sgi(struct kvm_vcpu *vcpu, u32 sgi, bool allow_group1) 1067 { 1068 struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, sgi); 1069 unsigned long flags; 1070 1071 raw_spin_lock_irqsave(&irq->irq_lock, flags); 1072 1073 /* 1074 * An access targeting Group0 SGIs can only generate 1075 * those, while an access targeting Group1 SGIs can 1076 * generate interrupts of either group. 1077 */ 1078 if (!irq->group || allow_group1) { 1079 if (!irq->hw) { 1080 irq->pending_latch = true; 1081 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); 1082 } else { 1083 /* HW SGI? Ask the GIC to inject it */ 1084 int err; 1085 err = irq_set_irqchip_state(irq->host_irq, 1086 IRQCHIP_STATE_PENDING, 1087 true); 1088 WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); 1089 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1090 } 1091 } else { 1092 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); 1093 } 1094 1095 vgic_put_irq(vcpu->kvm, irq); 1096 } 1097 1098 /** 1099 * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs 1100 * @vcpu: The VCPU requesting a SGI 1101 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU 1102 * @allow_group1: Does the sysreg access allow generation of G1 SGIs 1103 * 1104 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register. 1105 * This will trap in sys_regs.c and call this function. 1106 * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the 1107 * target processors as well as a bitmask of 16 Aff0 CPUs. 1108 * 1109 * If the interrupt routing mode bit is not set, we iterate over the Aff0 1110 * bits and signal the VCPUs matching the provided Aff{3,2,1}. 1111 * 1112 * If this bit is set, we signal all, but not the calling VCPU. 1113 */ 1114 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1) 1115 { 1116 struct kvm *kvm = vcpu->kvm; 1117 struct kvm_vcpu *c_vcpu; 1118 unsigned long target_cpus; 1119 u64 mpidr; 1120 u32 sgi, aff0; 1121 unsigned long c; 1122 1123 sgi = FIELD_GET(ICC_SGI1R_SGI_ID_MASK, reg); 1124 1125 /* Broadcast */ 1126 if (unlikely(reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT))) { 1127 kvm_for_each_vcpu(c, c_vcpu, kvm) { 1128 /* Don't signal the calling VCPU */ 1129 if (c_vcpu == vcpu) 1130 continue; 1131 1132 vgic_v3_queue_sgi(c_vcpu, sgi, allow_group1); 1133 } 1134 1135 return; 1136 } 1137 1138 /* We iterate over affinities to find the corresponding vcpus */ 1139 mpidr = SGI_AFFINITY_LEVEL(reg, 3); 1140 mpidr |= SGI_AFFINITY_LEVEL(reg, 2); 1141 mpidr |= SGI_AFFINITY_LEVEL(reg, 1); 1142 target_cpus = FIELD_GET(ICC_SGI1R_TARGET_LIST_MASK, reg); 1143 1144 for_each_set_bit(aff0, &target_cpus, hweight_long(ICC_SGI1R_TARGET_LIST_MASK)) { 1145 c_vcpu = kvm_mpidr_to_vcpu(kvm, mpidr | aff0); 1146 if (c_vcpu) 1147 vgic_v3_queue_sgi(c_vcpu, sgi, allow_group1); 1148 } 1149 } 1150 1151 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1152 int offset, u32 *val) 1153 { 1154 struct vgic_io_device dev = { 1155 .regions = vgic_v3_dist_registers, 1156 .nr_regions = ARRAY_SIZE(vgic_v3_dist_registers), 1157 }; 1158 1159 return vgic_uaccess(vcpu, &dev, is_write, offset, val); 1160 } 1161 1162 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1163 int offset, u32 *val) 1164 { 1165 struct vgic_io_device rd_dev = { 1166 .regions = vgic_v3_rd_registers, 1167 .nr_regions = ARRAY_SIZE(vgic_v3_rd_registers), 1168 }; 1169 1170 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val); 1171 } 1172 1173 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write, 1174 u32 intid, u32 *val) 1175 { 1176 if (intid % 32) 1177 return -EINVAL; 1178 1179 if (is_write) 1180 vgic_write_irq_line_level_info(vcpu, intid, *val); 1181 else 1182 *val = vgic_read_irq_line_level_info(vcpu, intid); 1183 1184 return 0; 1185 } 1186