1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PEF2256 registers definition 4 * 5 * Copyright 2023 CS GROUP France 6 * 7 * Author: Herve Codina <herve.codina@bootlin.com> 8 */ 9 #ifndef __PEF2256_REGS_H__ 10 #define __PEF2256_REGS_H__ 11 12 #include "linux/bitfield.h" 13 14 /* Command Register */ 15 #define PEF2256_CMDR 0x02 16 #define PEF2256_CMDR_RRES BIT(6) 17 #define PEF2256_CMDR_XRES BIT(4) 18 #define PEF2256_CMDR_SRES BIT(0) 19 20 /* Interrupt Mask Register 0..5 */ 21 #define PEF2256_IMR0 0x14 22 #define PEF2256_IMR1 0x15 23 #define PEF2256_IMR2 0x16 24 #define PEF2256_IMR3 0x17 25 #define PEF2256_IMR4 0x18 26 #define PEF2256_IMR5 0x19 27 28 /* Framer Mode Register 0 */ 29 #define PEF2256_FMR0 0x1C 30 #define PEF2256_FMR0_XC_MASK GENMASK(7, 6) 31 #define PEF2256_FMR0_XC_NRZ FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x0) 32 #define PEF2256_FMR0_XC_CMI FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x1) 33 #define PEF2256_FMR0_XC_AMI FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x2) 34 #define PEF2256_FMR0_XC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3) 35 #define PEF2256_FMR0_RC_MASK GENMASK(5, 4) 36 #define PEF2256_FMR0_RC_NRZ FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x0) 37 #define PEF2256_FMR0_RC_CMI FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x1) 38 #define PEF2256_FMR0_RC_AMI FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x2) 39 #define PEF2256_FMR0_RC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3) 40 41 /* Framer Mode Register 1 */ 42 #define PEF2256_FMR1 0x1D 43 #define PEF2256_FMR1_XFS BIT(3) 44 #define PEF2256_FMR1_ECM BIT(2) 45 /* SSD is defined on 2 bits. The other bit is on SIC1 register */ 46 #define PEF2256_FMR1_SSD_MASK GENMASK(1, 1) 47 #define PEF2256_FMR1_SSD_2048 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0) 48 #define PEF2256_FMR1_SSD_4096 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1) 49 #define PEF2256_FMR1_SSD_8192 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0) 50 #define PEF2256_FMR1_SSD_16384 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1) 51 52 /* Framer Mode Register 2 */ 53 #define PEF2256_FMR2 0x1E 54 #define PEF2256_FMR2_RFS_MASK GENMASK(7, 6) 55 #define PEF2256_FMR2_RFS_DOUBLEFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x0) 56 #define PEF2256_FMR2_RFS_CRC4_MULTIFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x2) 57 #define PEF2256_FMR2_RFS_AUTO_MULTIFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x3) 58 #define PEF2256_FMR2_AXRA BIT(1) 59 60 /* Transmit Service Word */ 61 #define PEF2256_XSW 0x20 62 #define PEF2256_XSW_XSIS BIT(7) 63 #define PEF2256_XSW_XTM BIT(6) 64 #define PEF2256_XSW_XY_MASK GENMASK(5, 0) 65 #define PEF2256_XSW_XY(_v) FIELD_PREP(PEF2256_XSW_XY_MASK, _v) 66 67 /* Transmit Spare Bits */ 68 #define PEF2256_XSP 0x21 69 #define PEF2256_XSP_XSIF BIT(2) 70 71 /* Transmit Control 0..1 */ 72 #define PEF2256_XC0 0x22 73 #define PEF2256_XC1 0x23 74 75 /* Receive Control 0 */ 76 #define PEF2256_RC0 0x24 77 #define PEF2256_RC0_SWD BIT(7) 78 #define PEF2256_RC0_ASY4 BIT(6) 79 80 /* Receive Control 1 */ 81 #define PEF2256_RC1 0x25 82 83 /* Transmit Pulse Mask 0..1 */ 84 #define PEF2256_XPM0 0x26 85 #define PEF2256_XPM1 0x27 86 87 /* Transmit Pulse Mask 2 */ 88 #define PEF2256_XPM2 0x28 89 #define PEF2256_XPM2_XLT BIT(6) 90 91 /* Transparent Service Word Mask */ 92 #define PEF2256_TSWM 0x29 93 94 /* Line Interface Mode 0 */ 95 #define PEF2256_LIM0 0x36 96 #define PEF2256_2X_LIM0_BIT3 BIT(3) /* v2.x, described as a forced '1' bit */ 97 #define PEF2256_LIM0_MAS BIT(0) 98 99 /* Line Interface Mode 1 */ 100 #define PEF2256_LIM1 0x37 101 #define PEF2256_12_LIM1_RIL_MASK GENMASK(6, 4) 102 #define PEF2256_12_LIM1_RIL_910 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x0) 103 #define PEF2256_12_LIM1_RIL_740 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x1) 104 #define PEF2256_12_LIM1_RIL_590 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x2) 105 #define PEF2256_12_LIM1_RIL_420 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x3) 106 #define PEF2256_12_LIM1_RIL_320 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x4) 107 #define PEF2256_12_LIM1_RIL_210 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x5) 108 #define PEF2256_12_LIM1_RIL_160 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x6) 109 #define PEF2256_12_LIM1_RIL_100 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x7) 110 #define PEF2256_2X_LIM1_RIL_MASK GENMASK(6, 4) 111 #define PEF2256_2X_LIM1_RIL_2250 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x0) 112 #define PEF2256_2X_LIM1_RIL_1100 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x1) 113 #define PEF2256_2X_LIM1_RIL_600 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x2) 114 #define PEF2256_2X_LIM1_RIL_350 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x3) 115 #define PEF2256_2X_LIM1_RIL_210 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x4) 116 #define PEF2256_2X_LIM1_RIL_140 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x5) 117 #define PEF2256_2X_LIM1_RIL_100 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x6) 118 #define PEF2256_2X_LIM1_RIL_50 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x7) 119 120 /* Pulse Count Detection */ 121 #define PEF2256_PCD 0x38 122 123 /* Pulse Count Recovery */ 124 #define PEF2256_PCR 0x39 125 126 /* Line Interface Mode 2 */ 127 #define PEF2256_LIM2 0x3A 128 #define PEF2256_LIM2_SLT_MASK GENMASK(5, 4) 129 #define PEF2256_LIM2_SLT_THR55 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x0) 130 #define PEF2256_LIM2_SLT_THR67 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x1) 131 #define PEF2256_LIM2_SLT_THR50 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x2) 132 #define PEF2256_LIM2_SLT_THR45 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x3) 133 #define PEF2256_LIM2_ELT BIT(2) 134 135 /* System Interface Control 1 */ 136 #define PEF2256_SIC1 0x3E 137 #define PEF2256_SIC1_SSC_MASK (BIT(7) | BIT(3)) 138 #define PEF2256_SIC1_SSC_2048 (0) 139 #define PEF2256_SIC1_SSC_4096 BIT(3) 140 #define PEF2256_SIC1_SSC_8192 BIT(7) 141 #define PEF2256_SIC1_SSC_16384 (BIT(7) | BIT(3)) 142 /* SSD is defined on 2 bits. The other bit is on FMR1 register */ 143 #define PEF2256_SIC1_SSD_MASK GENMASK(6, 6) 144 #define PEF2256_SIC1_SSD_2048 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0) 145 #define PEF2256_SIC1_SSD_4096 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0) 146 #define PEF2256_SIC1_SSD_8192 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1) 147 #define PEF2256_SIC1_SSD_16384 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1) 148 #define PEF2256_SIC1_RBS_MASK GENMASK(5, 4) 149 #define PEF2256_SIC1_RBS_2FRAMES FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x0) 150 #define PEF2256_SIC1_RBS_1FRAME FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x1) 151 #define PEF2256_SIC1_RBS_96BITS FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x2) 152 #define PEF2256_SIC1_RBS_BYPASS FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x3) 153 #define PEF2256_SIC1_XBS_MASK GENMASK(1, 0) 154 #define PEF2256_SIC1_XBS_BYPASS FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x0) 155 #define PEF2256_SIC1_XBS_1FRAME FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x1) 156 #define PEF2256_SIC1_XBS_2FRAMES FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x2) 157 #define PEF2256_SIC1_XBS_96BITS FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x3) 158 159 /* System Interface Control 2 */ 160 #define PEF2256_SIC2 0x3F 161 #define PEF2256_SIC2_SICS_MASK GENMASK(3, 1) 162 #define PEF2256_SIC2_SICS(_v) FIELD_PREP(PEF2256_SIC2_SICS_MASK, _v) 163 164 /* System Interface Control 3 */ 165 #define PEF2256_SIC3 0x40 166 #define PEF2256_SIC3_RTRI BIT(5) 167 #define PEF2256_SIC3_RESX BIT(3) 168 #define PEF2256_SIC3_RESR BIT(2) 169 170 /* Clock Mode Register 1 */ 171 #define PEF2256_CMR1 0x44 172 #define PEF2256_CMR1_RS_MASK GENMASK(5, 4) 173 #define PEF2256_CMR1_RS_DPLL FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x0) 174 #define PEF2256_CMR1_RS_DPLL_LOS_HIGH FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x1) 175 #define PEF2256_CMR1_RS_DCOR_2048 FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x2) 176 #define PEF2256_CMR1_RS_DCOR_8192 FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x3) 177 #define PEF2256_CMR1_DCS BIT(3) 178 179 /* Clock Mode Register 2 */ 180 #define PEF2256_CMR2 0x45 181 #define PEF2256_CMR2_DCOXC BIT(5) 182 183 /* Global Configuration Register */ 184 #define PEF2256_GCR 0x46 185 #define PEF2256_GCR_SCI BIT(6) 186 #define PEF2256_GCR_ECMC BIT(4) 187 188 /* Port Configuration 5 */ 189 #define PEF2256_PC5 0x84 190 #define PEF2256_PC5_CRP BIT(0) 191 192 /* Global Port Configuration 1 */ 193 #define PEF2256_GPC1 0x85 194 #define PEF2256_GPC1_CSFP_MASK GENMASK(7, 5) 195 #define PEF2256_GPC1_CSFP_SEC_IN_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x0) 196 #define PEF2256_GPC1_CSFP_SEC_OUT_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x1) 197 #define PEF2256_GPC1_CSFP_FSC_OUT_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x2) 198 #define PEF2256_GPC1_CSFP_FSC_OUT_LOW FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x3) 199 200 /* Port Configuration 6 */ 201 #define PEF2256_PC6 0x86 202 203 /* Global Counter Mode n=1..8 */ 204 #define PEF2256_GCM(_n) (0x92 + (_n) - 1) 205 #define PEF2256_GCM1 0x92 206 #define PEF2256_GCM2 0x93 207 #define PEF2256_GCM3 0x94 208 #define PEF2256_GCM4 0x95 209 #define PEF2256_GCM5 0x96 210 #define PEF2256_GCM6 0x97 211 #define PEF2256_GCM7 0x98 212 #define PEF2256_GCM8 0x99 213 214 /* Version Status Register */ 215 #define PEF2256_VSTR 0x4A 216 #define PEF2256_VSTR_VERSION_12 0x00 217 #define PEF2256_VSTR_VERSION_21 0x10 218 #define PEF2256_VSTR_VERSION_2x 0x05 219 220 /* Framer Receive Status 0 */ 221 #define PEF2256_FRS0 0x4C 222 #define PEF2256_FRS0_LOS BIT(7) 223 #define PEF2256_FRS0_AIS BIT(6) 224 225 /* Interrupt Status Register 0..5 */ 226 #define PEF2256_ISR(_n) (0x68 + (_n)) 227 #define PEF2256_ISR0 0x68 228 #define PEF2256_ISR1 0x69 229 #define PEF2256_ISR2 0x6A 230 #define PEF2256_ISR3 0x6B 231 #define PEF2256_ISR4 0x6C 232 #define PEF2256_ISR5 0x6D 233 234 /* Global Interrupt Status */ 235 #define PEF2256_GIS 0x6E 236 #define PEF2256_GIS_ISR(_n) BIT(_n) 237 238 /* Wafer Identification Register */ 239 #define PEF2256_WID 0xEC 240 #define PEF2256_12_WID_MASK GENMASK(1, 0) 241 #define PEF2256_12_WID_VERSION_12 FIELD_PREP_CONST(PEF2256_12_WID_MASK, 0x3) 242 #define PEF2256_2X_WID_MASK GENMASK(7, 6) 243 #define PEF2256_2X_WID_VERSION_21 FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x0) 244 #define PEF2256_2X_WID_VERSION_22 FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x1) 245 246 /* IMR2/ISR2 Interrupts common bits */ 247 #define PEF2256_INT2_AIS BIT(3) 248 #define PEF2256_INT2_LOS BIT(2) 249 250 #endif /* __PEF2256_REGS_H__ */ 251