1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2017-2018 NXP.
4 */
5
6 #define pr_fmt(fmt) "pll14xx: " fmt
7
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/clk-provider.h>
11 #include <linux/debugfs.h>
12 #include <linux/err.h>
13 #include <linux/export.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/slab.h>
17 #include <linux/spinlock.h>
18 #include <linux/jiffies.h>
19
20 #include "clk.h"
21
22 #define GNRL_CTL 0x0
23 #define DIV_CTL0 0x4
24 #define DIV_CTL1 0x8
25 #define LOCK_STATUS BIT(31)
26 #define LOCK_SEL_MASK BIT(29)
27 #define CLKE_MASK BIT(11)
28 #define RST_MASK BIT(9)
29 #define BYPASS_MASK BIT(4)
30 #define MDIV_MASK GENMASK(21, 12)
31 #define PDIV_MASK GENMASK(9, 4)
32 #define SDIV_MASK GENMASK(2, 0)
33 #define KDIV_MASK GENMASK(15, 0)
34 #define KDIV_MIN SHRT_MIN
35 #define KDIV_MAX SHRT_MAX
36
37 #define LOCK_TIMEOUT_US 10000
38
39 struct clk_pll14xx {
40 struct clk_hw hw;
41 void __iomem *base;
42 enum imx_pll14xx_type type;
43 const struct imx_pll14xx_rate_table *rate_table;
44 int rate_count;
45 s16 delta_k;
46 spinlock_t lock;
47 };
48
49 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
50
51 static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
52 PLL_1416X_RATE(1800000000U, 225, 3, 0),
53 PLL_1416X_RATE(1600000000U, 200, 3, 0),
54 PLL_1416X_RATE(1500000000U, 375, 3, 1),
55 PLL_1416X_RATE(1400000000U, 350, 3, 1),
56 PLL_1416X_RATE(1200000000U, 300, 3, 1),
57 PLL_1416X_RATE(1000000000U, 250, 3, 1),
58 PLL_1416X_RATE(800000000U, 200, 3, 1),
59 PLL_1416X_RATE(750000000U, 250, 2, 2),
60 PLL_1416X_RATE(700000000U, 350, 3, 2),
61 PLL_1416X_RATE(640000000U, 320, 3, 2),
62 PLL_1416X_RATE(600000000U, 300, 3, 2),
63 PLL_1416X_RATE(416000000U, 208, 3, 2),
64 PLL_1416X_RATE(320000000U, 160, 3, 2),
65 PLL_1416X_RATE(208000000U, 208, 3, 3),
66 };
67
68 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
69 PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
70 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
71 PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
72 PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
73 };
74
75 struct imx_pll14xx_clk imx_1443x_pll = {
76 .type = PLL_1443X,
77 .rate_table = imx_pll1443x_tbl,
78 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
79 };
80 EXPORT_SYMBOL_GPL(imx_1443x_pll);
81
82 struct imx_pll14xx_clk imx_1443x_dram_pll = {
83 .type = PLL_1443X,
84 .rate_table = imx_pll1443x_tbl,
85 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
86 .flags = CLK_GET_RATE_NOCACHE,
87 };
88 EXPORT_SYMBOL_GPL(imx_1443x_dram_pll);
89
90 struct imx_pll14xx_clk imx_1416x_pll = {
91 .type = PLL_1416X,
92 .rate_table = imx_pll1416x_tbl,
93 .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
94 };
95 EXPORT_SYMBOL_GPL(imx_1416x_pll);
96
imx_get_pll_settings(struct clk_pll14xx * pll,unsigned long rate)97 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
98 struct clk_pll14xx *pll, unsigned long rate)
99 {
100 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
101 int i;
102
103 for (i = 0; i < pll->rate_count; i++)
104 if (rate == rate_table[i].rate)
105 return &rate_table[i];
106
107 return NULL;
108 }
109
pll14xx_calc_rate(struct clk_pll14xx * pll,int mdiv,int pdiv,int sdiv,int kdiv,unsigned long prate)110 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv,
111 int sdiv, int kdiv, unsigned long prate)
112 {
113 u64 fout = prate;
114
115 /* fout = (m * 65536 + k) * Fin / (p * 65536) / (1 << sdiv) */
116 fout *= (mdiv * 65536 + kdiv);
117 pdiv *= 65536;
118
119 do_div(fout, pdiv << sdiv);
120
121 return fout;
122 }
123
pll1443x_calc_kdiv(int mdiv,int pdiv,int sdiv,unsigned long rate,unsigned long prate)124 static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv,
125 unsigned long rate, unsigned long prate)
126 {
127 long kdiv;
128
129 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */
130 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536);
131
132 return clamp_t(short, kdiv, KDIV_MIN, KDIV_MAX);
133 }
134
imx_pll14xx_calc_settings(struct clk_pll14xx * pll,unsigned long rate,unsigned long prate,struct imx_pll14xx_rate_table * t)135 static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate,
136 unsigned long prate, struct imx_pll14xx_rate_table *t)
137 {
138 u32 pll_div_ctl0, pll_div_ctl1;
139 int mdiv, pdiv, sdiv, kdiv;
140 long fout, rate_min, rate_max, dist, best = LONG_MAX;
141 unsigned long flags;
142 const struct imx_pll14xx_rate_table *tt;
143
144 /*
145 * Fractional PLL constrains:
146 *
147 * a) 1 <= p <= 63
148 * b) 64 <= m <= 1023
149 * c) 0 <= s <= 6
150 * d) -32768 <= k <= 32767
151 *
152 * fvco = (m * 65536 + k) * prate / (p * 65536)
153 * fout = (m * 65536 + k) * prate / (p * 65536) / (1 << sdiv)
154 */
155
156 /* First try if we can get the desired rate from one of the static entries */
157 tt = imx_get_pll_settings(pll, rate);
158 if (tt) {
159 pr_debug("%s: in=%lu, want=%lu, Using PLL setting from table\n",
160 clk_hw_get_name(&pll->hw), prate, rate);
161 t->rate = tt->rate;
162 t->mdiv = tt->mdiv;
163 t->pdiv = tt->pdiv;
164 t->sdiv = tt->sdiv;
165 t->kdiv = tt->kdiv;
166 return;
167 }
168
169 spin_lock_irqsave(&pll->lock, flags);
170
171 pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);
172 pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);
173
174 spin_unlock_irqrestore(&pll->lock, flags);
175
176 mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0);
177 pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0);
178 sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0);
179
180 /* Then see if we can get the desired rate by only adjusting kdiv (glitch free) */
181 rate_min = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MIN, prate);
182 rate_max = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, KDIV_MAX, prate);
183
184 if (rate >= rate_min && rate <= rate_max) {
185 kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
186 pr_debug("%s: in=%lu, want=%lu Only adjust kdiv %ld -> %d\n",
187 clk_hw_get_name(&pll->hw), prate, rate,
188 FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv);
189 fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
190 t->rate = (unsigned int)fout;
191 t->mdiv = mdiv;
192 t->pdiv = pdiv;
193 t->sdiv = sdiv;
194 t->kdiv = kdiv;
195 return;
196 }
197
198 /* Finally calculate best values */
199 for (pdiv = 1; pdiv <= 63; pdiv++) {
200 for (sdiv = 0; sdiv <= 6; sdiv++) {
201 /* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */
202 mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate);
203 mdiv = clamp(mdiv, 64, 1023);
204
205 kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
206 fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
207
208 /* best match */
209 dist = abs((long)rate - (long)fout);
210 if (dist < best) {
211 best = dist;
212 t->rate = (unsigned int)fout;
213 t->mdiv = mdiv;
214 t->pdiv = pdiv;
215 t->sdiv = sdiv;
216 t->kdiv = kdiv;
217
218 if (!dist)
219 goto found;
220 }
221 }
222 }
223 found:
224 pr_debug("%s: in=%lu, want=%lu got=%u (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
225 clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,
226 t->mdiv, t->kdiv);
227 }
228
clk_pll1416x_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)229 static int clk_pll1416x_determine_rate(struct clk_hw *hw,
230 struct clk_rate_request *req)
231 {
232 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
233 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
234 int i;
235
236 /* Assuming rate_table is in descending order */
237 for (i = 0; i < pll->rate_count; i++)
238 if (req->rate >= rate_table[i].rate) {
239 req->rate = rate_table[i].rate;
240
241 return 0;
242 }
243
244 /* return minimum supported value */
245 req->rate = rate_table[pll->rate_count - 1].rate;
246
247 return 0;
248 }
249
clk_pll1443x_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)250 static int clk_pll1443x_determine_rate(struct clk_hw *hw,
251 struct clk_rate_request *req)
252 {
253 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
254 struct imx_pll14xx_rate_table t;
255
256 imx_pll14xx_calc_settings(pll, req->rate, req->best_parent_rate, &t);
257
258 req->rate = t.rate;
259
260 return 0;
261 }
262
clk_pll14xx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)263 static unsigned long clk_pll14xx_recalc_rate(struct clk_hw *hw,
264 unsigned long parent_rate)
265 {
266 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
267 u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1;
268
269 pll_div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);
270 mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0);
271 pdiv = FIELD_GET(PDIV_MASK, pll_div_ctl0);
272 sdiv = FIELD_GET(SDIV_MASK, pll_div_ctl0);
273
274 if (pll->type == PLL_1443X) {
275 pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);
276 kdiv = (s16)FIELD_GET(KDIV_MASK, pll_div_ctl1);
277 } else {
278 kdiv = 0;
279 }
280
281 return pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, parent_rate);
282 }
283
clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table * rate,u32 pll_div)284 static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
285 u32 pll_div)
286 {
287 u32 old_mdiv, old_pdiv;
288
289 old_mdiv = FIELD_GET(MDIV_MASK, pll_div);
290 old_pdiv = FIELD_GET(PDIV_MASK, pll_div);
291
292 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
293 }
294
clk_pll14xx_wait_lock(struct clk_pll14xx * pll)295 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
296 {
297 u32 val;
298
299 return readl_poll_timeout(pll->base + GNRL_CTL, val, val & LOCK_STATUS, 0,
300 LOCK_TIMEOUT_US);
301 }
302
clk_pll1416x_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)303 static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
304 unsigned long prate)
305 {
306 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
307 const struct imx_pll14xx_rate_table *rate;
308 u32 tmp, div_val;
309 int ret;
310
311 rate = imx_get_pll_settings(pll, drate);
312 if (!rate) {
313 pr_err("Invalid rate %lu for pll clk %s\n", drate,
314 clk_hw_get_name(hw));
315 return -EINVAL;
316 }
317
318 tmp = readl_relaxed(pll->base + DIV_CTL0);
319
320 if (!clk_pll14xx_mp_change(rate, tmp)) {
321 tmp &= ~SDIV_MASK;
322 tmp |= FIELD_PREP(SDIV_MASK, rate->sdiv);
323 writel_relaxed(tmp, pll->base + DIV_CTL0);
324
325 return 0;
326 }
327
328 /* Bypass clock and set lock to pll output lock */
329 tmp = readl_relaxed(pll->base + GNRL_CTL);
330 tmp |= LOCK_SEL_MASK;
331 writel_relaxed(tmp, pll->base + GNRL_CTL);
332
333 /* Enable RST */
334 tmp &= ~RST_MASK;
335 writel_relaxed(tmp, pll->base + GNRL_CTL);
336
337 /* Enable BYPASS */
338 tmp |= BYPASS_MASK;
339 writel(tmp, pll->base + GNRL_CTL);
340
341 div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) |
342 FIELD_PREP(SDIV_MASK, rate->sdiv);
343 writel_relaxed(div_val, pll->base + DIV_CTL0);
344
345 /*
346 * According to SPEC, t3 - t2 need to be greater than
347 * 1us and 1/FREF, respectively.
348 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
349 * 3us.
350 */
351 udelay(3);
352
353 /* Disable RST */
354 tmp |= RST_MASK;
355 writel_relaxed(tmp, pll->base + GNRL_CTL);
356
357 /* Wait Lock */
358 ret = clk_pll14xx_wait_lock(pll);
359 if (ret)
360 return ret;
361
362 /* Bypass */
363 tmp &= ~BYPASS_MASK;
364 writel_relaxed(tmp, pll->base + GNRL_CTL);
365
366 return 0;
367 }
368
clk_pll1443x_set_rate(struct clk_hw * hw,unsigned long drate,unsigned long prate)369 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
370 unsigned long prate)
371 {
372 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
373 struct imx_pll14xx_rate_table rate;
374 unsigned long flags;
375 u32 gnrl_ctl, div_ctl0;
376 int ret;
377
378 imx_pll14xx_calc_settings(pll, drate, prate, &rate);
379
380 spin_lock_irqsave(&pll->lock, flags);
381
382 div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);
383
384 if (!clk_pll14xx_mp_change(&rate, div_ctl0)) {
385 /* only sdiv and/or kdiv changed - no need to RESET PLL */
386 div_ctl0 &= ~SDIV_MASK;
387 div_ctl0 |= FIELD_PREP(SDIV_MASK, rate.sdiv);
388 writel_relaxed(div_ctl0, pll->base + DIV_CTL0);
389
390 writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv),
391 pll->base + DIV_CTL1);
392
393 spin_unlock_irqrestore(&pll->lock, flags);
394
395 return 0;
396 }
397
398 /* Enable RST */
399 gnrl_ctl = readl_relaxed(pll->base + GNRL_CTL);
400 gnrl_ctl &= ~RST_MASK;
401 writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
402
403 /* Enable BYPASS */
404 gnrl_ctl |= BYPASS_MASK;
405 writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
406
407 div_ctl0 = FIELD_PREP(MDIV_MASK, rate.mdiv) |
408 FIELD_PREP(PDIV_MASK, rate.pdiv) |
409 FIELD_PREP(SDIV_MASK, rate.sdiv);
410 writel_relaxed(div_ctl0, pll->base + DIV_CTL0);
411
412 writel_relaxed(FIELD_PREP(KDIV_MASK, rate.kdiv), pll->base + DIV_CTL1);
413
414 spin_unlock_irqrestore(&pll->lock, flags);
415
416 /*
417 * According to SPEC, t3 - t2 need to be greater than
418 * 1us and 1/FREF, respectively.
419 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
420 * 3us.
421 */
422 udelay(3);
423
424 /* Disable RST */
425 gnrl_ctl |= RST_MASK;
426 writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
427
428 /* Wait Lock*/
429 ret = clk_pll14xx_wait_lock(pll);
430 if (ret)
431 return ret;
432
433 /* Bypass */
434 gnrl_ctl &= ~BYPASS_MASK;
435 writel_relaxed(gnrl_ctl, pll->base + GNRL_CTL);
436
437 return 0;
438 }
439
clk_pll14xx_prepare(struct clk_hw * hw)440 static int clk_pll14xx_prepare(struct clk_hw *hw)
441 {
442 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
443 u32 val;
444 int ret;
445
446 /*
447 * RESETB = 1 from 0, PLL starts its normal
448 * operation after lock time
449 */
450 val = readl_relaxed(pll->base + GNRL_CTL);
451 if (val & RST_MASK)
452 return 0;
453 val |= BYPASS_MASK;
454 writel_relaxed(val, pll->base + GNRL_CTL);
455 val |= RST_MASK;
456 writel_relaxed(val, pll->base + GNRL_CTL);
457
458 ret = clk_pll14xx_wait_lock(pll);
459 if (ret)
460 return ret;
461
462 val &= ~BYPASS_MASK;
463 writel_relaxed(val, pll->base + GNRL_CTL);
464
465 return 0;
466 }
467
clk_pll14xx_is_prepared(struct clk_hw * hw)468 static int clk_pll14xx_is_prepared(struct clk_hw *hw)
469 {
470 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
471 u32 val;
472
473 val = readl_relaxed(pll->base + GNRL_CTL);
474
475 return (val & RST_MASK) ? 1 : 0;
476 }
477
clk_pll14xx_unprepare(struct clk_hw * hw)478 static void clk_pll14xx_unprepare(struct clk_hw *hw)
479 {
480 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
481 u32 val;
482
483 /*
484 * Set RST to 0, power down mode is enabled and
485 * every digital block is reset
486 */
487 val = readl_relaxed(pll->base + GNRL_CTL);
488 val &= ~RST_MASK;
489 writel_relaxed(val, pll->base + GNRL_CTL);
490 }
491
492 static const struct clk_ops clk_pll1416x_ops = {
493 .prepare = clk_pll14xx_prepare,
494 .unprepare = clk_pll14xx_unprepare,
495 .is_prepared = clk_pll14xx_is_prepared,
496 .recalc_rate = clk_pll14xx_recalc_rate,
497 .determine_rate = clk_pll1416x_determine_rate,
498 .set_rate = clk_pll1416x_set_rate,
499 };
500
501 static const struct clk_ops clk_pll1416x_min_ops = {
502 .recalc_rate = clk_pll14xx_recalc_rate,
503 };
504
505 static const struct clk_ops clk_pll1443x_ops = {
506 .prepare = clk_pll14xx_prepare,
507 .unprepare = clk_pll14xx_unprepare,
508 .is_prepared = clk_pll14xx_is_prepared,
509 .recalc_rate = clk_pll14xx_recalc_rate,
510 .determine_rate = clk_pll1443x_determine_rate,
511 .set_rate = clk_pll1443x_set_rate,
512 };
513
imx_dev_clk_hw_pll14xx(struct device * dev,const char * name,const char * parent_name,void __iomem * base,const struct imx_pll14xx_clk * pll_clk)514 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
515 const char *parent_name, void __iomem *base,
516 const struct imx_pll14xx_clk *pll_clk)
517 {
518 struct clk_pll14xx *pll;
519 struct clk_hw *hw;
520 struct clk_init_data init;
521 int ret;
522 u32 val;
523
524 pll = kzalloc_obj(*pll);
525 if (!pll)
526 return ERR_PTR(-ENOMEM);
527
528 spin_lock_init(&pll->lock);
529
530 init.name = name;
531 init.flags = pll_clk->flags;
532 init.parent_names = &parent_name;
533 init.num_parents = 1;
534
535 switch (pll_clk->type) {
536 case PLL_1416X:
537 if (!pll_clk->rate_table)
538 init.ops = &clk_pll1416x_min_ops;
539 else
540 init.ops = &clk_pll1416x_ops;
541 break;
542 case PLL_1443X:
543 init.ops = &clk_pll1443x_ops;
544 break;
545 default:
546 pr_err("Unknown pll type for pll clk %s\n", name);
547 kfree(pll);
548 return ERR_PTR(-EINVAL);
549 }
550
551 pll->base = base;
552 pll->hw.init = &init;
553 pll->type = pll_clk->type;
554 pll->rate_table = pll_clk->rate_table;
555 pll->rate_count = pll_clk->rate_count;
556
557 val = readl_relaxed(pll->base + GNRL_CTL);
558 val &= ~BYPASS_MASK;
559 writel_relaxed(val, pll->base + GNRL_CTL);
560
561 hw = &pll->hw;
562
563 ret = clk_hw_register(dev, hw);
564 if (ret) {
565 pr_err("failed to register pll %s %d\n", name, ret);
566 kfree(pll);
567 return ERR_PTR(ret);
568 }
569
570 return hw;
571 }
572 EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx);
573
574 /*
575 * Debugfs interface for Audio PLL runtime monitoring and control
576 *
577 * This interface allows dynamic adjustment of the Audio PLL
578 * K-divider for precise frequency tuning, particularly useful
579 * for audio applications.
580 *
581 * examples for the usage of the two interfaces:
582 * 1): Get the current PLL setting of dividers
583 * cat /sys/kernel/debug/audio_pll_monitor/audio_pll1/pll_parameter
584 *
585 * 2): Adjust the K-divider by a small delta_k
586 * echo 1 > /sys/kernel/debug/audio_pll_monitor/audio_pll1/delta_k;
587 */
588 #ifdef CONFIG_DEBUG_FS
pll_delta_k_get(void * data,u64 * val)589 static int pll_delta_k_get(void *data, u64 *val)
590 {
591 struct clk_pll14xx *pll = to_clk_pll14xx(data);
592 *val = pll->delta_k;
593 return 0;
594 }
595
pll_delta_k_set(void * data,u64 val)596 static int pll_delta_k_set(void *data, u64 val)
597 {
598 struct clk_pll14xx *pll = to_clk_pll14xx(data);
599 unsigned long flags;
600 u32 div_ctl1;
601 s16 kdiv, delta_k;
602
603 delta_k = (s16)clamp_t(s64, val, KDIV_MIN, KDIV_MAX);
604
605 spin_lock_irqsave(&pll->lock, flags);
606
607 pll->delta_k = delta_k;
608
609 div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);
610 kdiv = (s16)FIELD_GET(KDIV_MASK, div_ctl1);
611 kdiv = (s16)clamp_t(s32, (s32)kdiv + delta_k, KDIV_MIN, KDIV_MAX);
612 writel_relaxed(FIELD_PREP(KDIV_MASK, kdiv), pll->base + DIV_CTL1);
613
614 spin_unlock_irqrestore(&pll->lock, flags);
615
616 return 0;
617 }
618 DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(delta_k_fops, pll_delta_k_get, pll_delta_k_set, "%lld\n");
619
pll_setting_show(struct seq_file * s,void * data)620 static int pll_setting_show(struct seq_file *s, void *data)
621 {
622 struct clk_pll14xx *pll = to_clk_pll14xx(s->private);
623 unsigned long flags;
624 u32 div_ctl0, div_ctl1;
625 u32 mdiv, pdiv, sdiv, kdiv;
626
627 spin_lock_irqsave(&pll->lock, flags);
628
629 div_ctl0 = readl_relaxed(pll->base + DIV_CTL0);
630 div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);
631
632 spin_unlock_irqrestore(&pll->lock, flags);
633
634 mdiv = FIELD_GET(MDIV_MASK, div_ctl0);
635 pdiv = FIELD_GET(PDIV_MASK, div_ctl0);
636 sdiv = FIELD_GET(SDIV_MASK, div_ctl0);
637 kdiv = FIELD_GET(KDIV_MASK, div_ctl1);
638
639 seq_printf(s, "Mdiv: 0x%x; Pdiv: 0x%x; Sdiv: 0x%x; Kdiv: 0x%x\n",
640 mdiv, pdiv, sdiv, kdiv);
641
642 return 0;
643 }
644 DEFINE_SHOW_ATTRIBUTE(pll_setting);
645
imx_audio_pll_debug_init(struct clk_hw * hws[],unsigned int num_plls)646 void imx_audio_pll_debug_init(struct clk_hw *hws[], unsigned int num_plls)
647 {
648 struct dentry *rootdir, *audio_pll_dir;
649 const char *pll_name;
650 int i;
651
652 rootdir = debugfs_create_dir("audio_pll_monitor", NULL);
653
654 for (i = 0; i < num_plls; i++) {
655 if (!IS_ERR_OR_NULL(hws[i])) {
656 pll_name = clk_hw_get_name(hws[i]);
657 audio_pll_dir = debugfs_create_dir(pll_name, rootdir);
658 debugfs_create_file_unsafe("delta_k", 0600, audio_pll_dir,
659 hws[i], &delta_k_fops);
660 debugfs_create_file("pll_parameter", 0444, audio_pll_dir,
661 hws[i], &pll_setting_fops);
662 }
663 }
664 }
665 #else /* !CONFIG_DEBUG_FS */
imx_audio_pll_debug_init(struct clk_hw * hws[],unsigned int num_plls)666 void imx_audio_pll_debug_init(struct clk_hw *hws[], unsigned int num_plls)
667 {
668 }
669 #endif /* CONFIG_DEBUG_FS */
670 EXPORT_SYMBOL_GPL(imx_audio_pll_debug_init);
671