1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21
22 #include <ufs/unipro.h>
23
24 #include "phy-qcom-qmp-common.h"
25
26 #include "phy-qcom-qmp.h"
27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
32 #include "phy-qcom-qmp-pcs-ufs-v7.h"
33
34 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
35 #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h"
36 #include "phy-qcom-qmp-qserdes-txrx-ufs-v8.h"
37
38 /* QPHY_PCS_READY_STATUS bit */
39 #define PCS_READY BIT(0)
40
41 #define PHY_INIT_COMPLETE_TIMEOUT 10000
42
43 #define NUM_OVERLAY 2
44
45 /* set of registers with offsets different per-PHY */
46 enum qphy_reg_layout {
47 /* PCS registers */
48 QPHY_SW_RESET,
49 QPHY_START_CTRL,
50 QPHY_PCS_READY_STATUS,
51 QPHY_PCS_POWER_DOWN_CONTROL,
52 /* Keep last to ensure regs_layout arrays are properly initialized */
53 QPHY_LAYOUT_SIZE
54 };
55
56 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
57 [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START,
58 [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS,
59 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
60 };
61
62 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
63 [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START,
64 [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS,
65 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
66 };
67
68 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
69 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
70 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
71 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
72 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
73 };
74
75 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
76 [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
77 [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
78 [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
79 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
80 };
81
82 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
83 [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START,
84 [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,
85 [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET,
86 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
87 };
88
89 static const unsigned int ufsphy_v7_regs_layout[QPHY_LAYOUT_SIZE] = {
90 [QPHY_START_CTRL] = QPHY_V7_PCS_UFS_PHY_START,
91 [QPHY_PCS_READY_STATUS] = QPHY_V7_PCS_UFS_READY_STATUS,
92 [QPHY_SW_RESET] = QPHY_V7_PCS_UFS_SW_RESET,
93 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL,
94 };
95
96 static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] = {
97 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
98 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
99 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
100 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
101 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
102 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
103 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),
104 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),
105 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
106 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
107 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
108 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
109 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14),
110 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
111 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18),
112 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
113 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c),
114 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98),
115 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14),
116 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
117 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18),
118 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32),
119 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f),
120 };
121
122 static const struct qmp_phy_init_tbl milos_ufsphy_tx[] = {
123 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
124 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
125 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
126 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0xcc),
127 };
128
129 static const struct qmp_phy_init_tbl milos_ufsphy_rx[] = {
130 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
131 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),
132 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
133 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),
134 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),
135 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),
136 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
137 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),
138 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
139 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
140 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
141 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
142 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
143 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
144 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
145 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
146 };
147
148 static const struct qmp_phy_init_tbl milos_ufsphy_pcs[] = {
149 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
150 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
151 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b),
152 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
153 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
154 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
155 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
156 };
157
158 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
159 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x0e),
160 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0xd7),
161 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30),
162 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x06),
163 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
164 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a),
165 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x05),
166 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x0a),
167 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV_MODE1, 0x0a),
168 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x01),
169 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x10),
170 QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20),
171 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00),
172 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00),
173 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff),
174 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x3f),
175 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x54),
176 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x05),
177 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82),
178 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00),
179 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x00),
180 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x00),
181 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b),
182 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16),
183 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28),
184 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
185 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
186 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE0, 0x28),
187 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE0, 0x02),
188 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xff),
189 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x0c),
190 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00),
191 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE1, 0x98),
192 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE1, 0x00),
193 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE1, 0x00),
194 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE1, 0x00),
195 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE1, 0x0b),
196 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE1, 0x16),
197 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE1, 0x28),
198 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
199 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
200 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE1, 0xd6),
201 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE1, 0x00),
202 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE1, 0x32),
203 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE1, 0x0f),
204 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE1, 0x00),
205 };
206
207 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
208 QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
209 QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x02),
210 };
211
212 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
213 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_LVL, 0x24),
214 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x02),
215 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_INTERFACE_MODE, 0x00),
216 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
217 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
218 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_TERM_BW, 0x5b),
219 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN1_LSB, 0xff),
220 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN1_MSB, 0x3f),
221 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN2_LSB, 0xff),
222 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN2_MSB, 0x0f),
223 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
224 };
225
226 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = {
227 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
228 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
229 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
230 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
231 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
232 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
233 };
234
235 static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = {
236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
271 };
272
273 static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = {
274 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
275 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
276 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
279 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
280 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
281 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
282 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
288 };
289
290 static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
291 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
292 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
293 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
294 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
295 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
296 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
297 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
298 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
299 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
300 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
301 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
302 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
303 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
304 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
305 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
306 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
307 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
308 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
309 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
310 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
311 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
312 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
313 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
314 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
315 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
316 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
317 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
318 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
319 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
320 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
321 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
322 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
323 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
324 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
325 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
326 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
327 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
328 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
329 };
330
331 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
332 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CMN_CONFIG, 0x0e),
333 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYSCLK_EN_SEL, 0x14),
334 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_SELECT, 0x30),
335 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SYS_CLK_CTRL, 0x02),
336 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
337 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TIMER, 0x0a),
338 QMP_PHY_INIT_CFG(QSERDES_V2_COM_HSCLK_SEL, 0x00),
339 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV, 0x0a),
340 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORECLK_DIV_MODE1, 0x0a),
341 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_EN, 0x01),
342 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_CTRL, 0x00),
343 QMP_PHY_INIT_CFG(QSERDES_V2_COM_RESETSM_CNTRL, 0x20),
344 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CORE_CLK_EN, 0x00),
345 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP_CFG, 0x00),
346 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER1, 0xff),
347 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_TIMER2, 0x3f),
348 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x04),
349 QMP_PHY_INIT_CFG(QSERDES_V2_COM_SVS_MODE_CLK_SEL, 0x05),
350 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE0, 0x82),
351 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE0, 0x00),
352 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE0, 0x00),
353 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE0, 0x00),
354 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE0, 0x0b),
355 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE0, 0x16),
356 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE0, 0x28),
357 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
358 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
359 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE0, 0x28),
360 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE0, 0x02),
361 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE0, 0xff),
362 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE0, 0x0c),
363 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE0, 0x00),
364 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DEC_START_MODE1, 0x98),
365 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START1_MODE1, 0x00),
366 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START2_MODE1, 0x00),
367 QMP_PHY_INIT_CFG(QSERDES_V2_COM_DIV_FRAC_START3_MODE1, 0x00),
368 QMP_PHY_INIT_CFG(QSERDES_V2_COM_CP_CTRL_MODE1, 0x0b),
369 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_RCTRL_MODE1, 0x16),
370 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_CCTRL_MODE1, 0x28),
371 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
372 QMP_PHY_INIT_CFG(QSERDES_V2_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
373 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE1_MODE1, 0xd6),
374 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE2_MODE1, 0x00),
375 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP1_MODE1, 0x32),
376 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP2_MODE1, 0x0f),
377 QMP_PHY_INIT_CFG(QSERDES_V2_COM_LOCK_CMP3_MODE1, 0x00),
378 QMP_PHY_INIT_CFG(QSERDES_V2_COM_PLL_IVCO, 0x0f),
379 QMP_PHY_INIT_CFG(QSERDES_V2_COM_BG_TRIM, 0x0f),
380 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_INITVAL1, 0xff),
381 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_INITVAL2, 0x00),
382 };
383
384 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
385 QMP_PHY_INIT_CFG(QSERDES_V2_COM_VCO_TUNE_MAP, 0x44),
386 };
387
388 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
389 QMP_PHY_INIT_CFG(QSERDES_V2_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
390 QMP_PHY_INIT_CFG(QSERDES_V2_TX_LANE_MODE, 0x06),
391 };
392
393 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
394 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_LVL, 0x24),
395 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_CNTRL, 0x0F),
396 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_INTERFACE_MODE, 0x40),
397 QMP_PHY_INIT_CFG(QSERDES_V2_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
398 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
399 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_TERM_BW, 0x5B),
400 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN1_LSB, 0xFF),
401 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN1_MSB, 0x3F),
402 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN2_LSB, 0xFF),
403 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQ_GAIN2_MSB, 0x3F),
404 QMP_PHY_INIT_CFG(QSERDES_V2_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
405 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
406 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
407 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SVS_SO_GAIN, 0x04),
408 QMP_PHY_INIT_CFG(QSERDES_V2_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
409 };
410
411 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
412 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
413 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
414 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
415 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
416 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
417 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
418 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
419 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
420 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
421 };
422
423 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
443 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
444 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
445 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
446 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
447 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
448 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
449 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
450 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
451 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
452 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
453 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
454 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
455 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
456 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
457 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
458 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
459 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
460 };
461
462 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
463 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
464 };
465
466 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
467 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
468 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
469 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
470 };
471
472 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
473 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
474 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
475 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
476 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
477 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
478 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
479 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
480 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
481 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
482 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
483 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
484 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
485 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
486 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
487 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
488 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
489 };
490
491 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
500 };
501
502 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
503 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
504 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
505 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
506 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
507 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
508 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
509 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
510 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
511 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
512 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
513 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
514 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
515 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
516 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
517 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
518 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
519 };
520
521 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
522 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
523 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
524 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
525 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
526 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
527 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
528 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
529 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
530 };
531
532 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
533 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
534 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
535 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
536 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
537 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
538 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
539 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
540 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
541 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
542 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
543 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
544 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
545 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
546 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
547 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
548 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
549 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
550 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
551 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
552 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
553 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
554 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
557 };
558
559 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
560 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
561 };
562
563 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
564 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
565 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
566 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
567 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
568 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
569 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
570 };
571
572 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
573 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
574 };
575
576 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
611 };
612
613 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
630 };
631
632 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
633 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
634 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
635 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
638 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
639 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
640 };
641
642 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
645 };
646
647 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
648 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
649 };
650
651 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
673 };
674
675 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
676 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
677 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
678 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
679 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
680 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
681 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
682 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
683 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
684 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
685 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
686 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
687 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
688 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
689 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
690 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
691 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
692 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
693 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
694 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
695 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
696 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
697 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
698 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
699 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
700 };
701
702 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
703 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
704 };
705
706 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
707 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
708 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
709 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
710 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
711 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
712 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
713 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
714 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
715 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
716 };
717
718 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
720 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
721 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
722 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
723 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
724 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
725 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
726 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
727 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
728 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
729 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
730 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
731 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
732 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
733 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
734 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
735 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
736 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
737 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
738 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
739 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
740 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
743 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
744 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
745 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
746 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
747 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
748 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
749 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
750 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
751 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
752 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
753 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
754 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
755 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
756 };
757
758 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
759 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
760 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
761 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
762 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
763 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
764 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
765 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
766 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
767 };
768
769 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
770 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
771 };
772
773 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
774 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
775 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
776 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
777 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
778 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
779 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
780 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
781 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
782 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
783 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
784 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
785 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
786 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
787 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
788 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
789 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
790 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
791 };
792
793 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
794 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
795 };
796
797 static const struct qmp_phy_init_tbl sm8475_ufsphy_serdes[] = {
798 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
799 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
800 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
801 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
802 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
803 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
804 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
805 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18),
807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),
808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c),
809 };
810
811 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_serdes[] = {
812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14),
815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98),
816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14),
817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18),
819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32),
820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f),
821 };
822
823 static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_pcs[] = {
824 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b),
825 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
826 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
827 };
828
829 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
832 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
833 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
834 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
836 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
837 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
838 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
841 };
842
843 static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
844 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
845 };
846
847 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
848 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
849 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
850 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
851 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
852 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
854 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
855 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
856 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
857 };
858
859 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
860 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
861 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
862 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
863 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
864 };
865
866 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
867 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
868 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
869 };
870
871 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
872 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
873 };
874
875 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
876 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
877
878 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
879 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
880 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
881 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
882
883 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
884 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
885
886 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
887 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
888 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
889 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
890 };
891
892 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
893 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
894 };
895
896 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
897 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
898 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
899 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
900 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
901 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
902 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
903 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
904 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
905 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
906 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
907 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
908 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
909 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
910 };
911
912 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
913 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
914 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
915 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
916 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
917 };
918
919 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
920 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
921 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
922 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
923 };
924
925 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
926 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
927 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
928 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
929 };
930
931 static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {
932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
933 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
934 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
935 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
936 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
937 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
938 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f),
939 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a),
940 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17),
941 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
942 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
943 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
944 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
945 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
946 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
947 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
948 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
949 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
950 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
951 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
952 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
953 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
954 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
955 };
956
957 static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = {
958 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01),
959 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
960 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
961 };
962
963 static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = {
964 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
965 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
966 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
967 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
968 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
969 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
970 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
971 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
972 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
973 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e),
974 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
975 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce),
976 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce),
977 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18),
978 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
979 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f),
980 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
981 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
982 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
983 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
984 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
985 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
986 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
987 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24),
988 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24),
989 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20),
990 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
991 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
992 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f),
993 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
994 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa),
995 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
996 };
997
998 static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = {
999 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1000 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1001 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1),
1002 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
1003 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
1004 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
1005 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e),
1006 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
1007 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
1008 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
1009 };
1010
1011 static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = {
1012 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
1013 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
1014 };
1015
1016 static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {
1017 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
1018 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
1019 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d),
1020 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
1021 };
1022
1023 static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {
1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1028 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
1029 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60),
1030 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
1031 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f),
1032 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07),
1033 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20),
1034 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
1035 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40),
1036 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
1037 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1038 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1039 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
1040 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
1041 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
1042 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
1043 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
1044 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
1049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
1054 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
1055 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
1056 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe),
1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1059 };
1060
1061 static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {
1062 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00),
1063 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
1064 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
1065 };
1066
1067 static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {
1068 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1069 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c),
1070 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
1071 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
1072 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
1073 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
1074 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
1075 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
1076 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
1077 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8e),
1078 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1079 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce),
1080 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce),
1081 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
1082 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a),
1083 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f),
1084 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
1085 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
1086 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a),
1087 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2),
1088 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
1089 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b),
1090 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b),
1091 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
1092 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b),
1093 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a),
1094 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
1095 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
1096 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
1097 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
1098 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
1099 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
1100 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
1101 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f),
1102 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
1103 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3),
1104 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
1105 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9b),
1106 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9b),
1107 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60),
1108 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
1109 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f),
1110 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
1111 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb),
1112 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
1113 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f),
1114 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
1115 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa),
1116 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
1117 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
1118 };
1119
1120 static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {
1121 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1122 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1123 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40),
1124 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
1125 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
1126 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
1127 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e),
1128 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12),
1129 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15),
1130 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19),
1131 };
1132
1133 static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {
1134 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
1135 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
1136 };
1137
1138 static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {
1139 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41),
1140 };
1141
1142 struct qmp_ufs_offsets {
1143 u16 serdes;
1144 u16 pcs;
1145 u16 tx;
1146 u16 rx;
1147 u16 tx2;
1148 u16 rx2;
1149 };
1150
1151 struct qmp_phy_cfg_tbls {
1152 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1153 const struct qmp_phy_init_tbl *serdes;
1154 int serdes_num;
1155 const struct qmp_phy_init_tbl *tx;
1156 int tx_num;
1157 const struct qmp_phy_init_tbl *rx;
1158 int rx_num;
1159 const struct qmp_phy_init_tbl *pcs;
1160 int pcs_num;
1161 /* Maximum supported Gear of this tbls */
1162 u32 max_gear;
1163 };
1164
1165 /* struct qmp_phy_cfg - per-PHY initialization config */
1166 struct qmp_phy_cfg {
1167 int lanes;
1168
1169 const struct qmp_ufs_offsets *offsets;
1170 /* Maximum supported Gear of this config */
1171 u32 max_supported_gear;
1172
1173 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
1174 const struct qmp_phy_cfg_tbls tbls;
1175 /* Additional sequence for HS Series B */
1176 const struct qmp_phy_cfg_tbls tbls_hs_b;
1177 /* Additional sequence for different HS Gears */
1178 const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
1179
1180 /* regulators to be requested */
1181 const struct regulator_bulk_data *vreg_list;
1182 int num_vregs;
1183
1184 /* array of registers with different offsets */
1185 const unsigned int *regs;
1186
1187 /* true, if PCS block has no separate SW_RESET register */
1188 bool no_pcs_sw_reset;
1189 };
1190
1191 struct qmp_ufs {
1192 struct device *dev;
1193
1194 const struct qmp_phy_cfg *cfg;
1195
1196 void __iomem *serdes;
1197 void __iomem *pcs;
1198 void __iomem *pcs_misc;
1199 void __iomem *tx;
1200 void __iomem *rx;
1201 void __iomem *tx2;
1202 void __iomem *rx2;
1203
1204 struct clk_bulk_data *clks;
1205 int num_clks;
1206 struct regulator_bulk_data *vregs;
1207 struct reset_control *ufs_reset;
1208
1209 struct phy *phy;
1210 u32 mode;
1211 u32 submode;
1212 };
1213
qphy_setbits(void __iomem * base,u32 offset,u32 val)1214 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1215 {
1216 u32 reg;
1217
1218 reg = readl(base + offset);
1219 reg |= val;
1220 writel(reg, base + offset);
1221
1222 /* ensure that above write is through */
1223 readl(base + offset);
1224 }
1225
qphy_clrbits(void __iomem * base,u32 offset,u32 val)1226 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1227 {
1228 u32 reg;
1229
1230 reg = readl(base + offset);
1231 reg &= ~val;
1232 writel(reg, base + offset);
1233
1234 /* ensure that above write is through */
1235 readl(base + offset);
1236 }
1237
1238 /* Regulator bulk data with load values for specific configurations */
1239 static const struct regulator_bulk_data milos_ufsphy_vreg_l[] = {
1240 { .supply = "vdda-phy", .init_load_uA = 140120 },
1241 { .supply = "vdda-pll", .init_load_uA = 18340 },
1242 };
1243
1244 static const struct regulator_bulk_data msm8996_ufsphy_vreg_l[] = {
1245 { .supply = "vdda-phy", .init_load_uA = 51400 },
1246 { .supply = "vdda-pll", .init_load_uA = 14600 },
1247 };
1248
1249 static const struct regulator_bulk_data sa8775p_ufsphy_vreg_l[] = {
1250 { .supply = "vdda-phy", .init_load_uA = 137000 },
1251 { .supply = "vdda-pll", .init_load_uA = 18300 },
1252 };
1253
1254 static const struct regulator_bulk_data sc7280_ufsphy_vreg_l[] = {
1255 { .supply = "vdda-phy", .init_load_uA = 97500 },
1256 { .supply = "vdda-pll", .init_load_uA = 18400 },
1257 };
1258
1259 static const struct regulator_bulk_data sc8280xp_ufsphy_vreg_l[] = {
1260 { .supply = "vdda-phy", .init_load_uA = 85700 },
1261 { .supply = "vdda-pll", .init_load_uA = 18300 },
1262 };
1263
1264 static const struct regulator_bulk_data sdm845_ufsphy_vreg_l[] = {
1265 { .supply = "vdda-phy", .init_load_uA = 51400 },
1266 { .supply = "vdda-pll", .init_load_uA = 14600 },
1267 };
1268
1269 static const struct regulator_bulk_data sm6115_ufsphy_vreg_l[] = {
1270 { .supply = "vdda-phy", .init_load_uA = 51400 },
1271 { .supply = "vdda-pll", .init_load_uA = 14200 },
1272 };
1273
1274 static const struct regulator_bulk_data sm7150_ufsphy_vreg_l[] = {
1275 { .supply = "vdda-phy", .init_load_uA = 62900 },
1276 { .supply = "vdda-pll", .init_load_uA = 18300 },
1277 };
1278
1279 static const struct regulator_bulk_data sm8150_ufsphy_vreg_l[] = {
1280 { .supply = "vdda-phy", .init_load_uA = 90200 },
1281 { .supply = "vdda-pll", .init_load_uA = 19000 },
1282 };
1283
1284 static const struct regulator_bulk_data sm8250_ufsphy_vreg_l[] = {
1285 { .supply = "vdda-phy", .init_load_uA = 89900 },
1286 { .supply = "vdda-pll", .init_load_uA = 18800 },
1287 };
1288
1289 static const struct regulator_bulk_data sm8350_ufsphy_vreg_l[] = {
1290 { .supply = "vdda-phy", .init_load_uA = 91600 },
1291 { .supply = "vdda-pll", .init_load_uA = 19000 },
1292 };
1293
1294 static const struct regulator_bulk_data sm8450_ufsphy_vreg_l[] = {
1295 { .supply = "vdda-phy", .init_load_uA = 173000 },
1296 { .supply = "vdda-pll", .init_load_uA = 24900 },
1297 };
1298
1299 static const struct regulator_bulk_data sm8475_ufsphy_vreg_l[] = {
1300 { .supply = "vdda-phy", .init_load_uA = 213030 },
1301 { .supply = "vdda-pll", .init_load_uA = 18340 },
1302 };
1303
1304 static const struct regulator_bulk_data sm8550_ufsphy_vreg_l[] = {
1305 { .supply = "vdda-phy", .init_load_uA = 188000 },
1306 { .supply = "vdda-pll", .init_load_uA = 18300 },
1307 };
1308
1309 static const struct regulator_bulk_data sm8650_ufsphy_vreg_l[] = {
1310 { .supply = "vdda-phy", .init_load_uA = 205000 },
1311 { .supply = "vdda-pll", .init_load_uA = 17500 },
1312 };
1313
1314 static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] = {
1315 { .supply = "vdda-phy", .init_load_uA = 213000 },
1316 { .supply = "vdda-pll", .init_load_uA = 18300 },
1317 };
1318
1319 static const struct regulator_bulk_data hawi_ufsphy_vreg_l[] = {
1320 { .supply = "vdda-phy", .init_load_uA = 324000 },
1321 { .supply = "vdda-pll", .init_load_uA = 27000 },
1322 };
1323
1324 static const struct qmp_ufs_offsets qmp_ufs_offsets = {
1325 .serdes = 0,
1326 .pcs = 0xc00,
1327 .tx = 0x400,
1328 .rx = 0x600,
1329 .tx2 = 0x800,
1330 .rx2 = 0xa00,
1331 };
1332
1333 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
1334 .serdes = 0,
1335 .pcs = 0x0400,
1336 .tx = 0x1000,
1337 .rx = 0x1200,
1338 .tx2 = 0x1800,
1339 .rx2 = 0x1a00,
1340 };
1341
1342 static const struct qmp_ufs_offsets qmp_ufs_offsets_v7 = {
1343 .serdes = 0,
1344 .pcs = 0x0400,
1345 .tx = 0x2000,
1346 .rx = 0x2000,
1347 .tx2 = 0x3000,
1348 .rx2 = 0x3000,
1349 };
1350
1351 static const struct qmp_phy_cfg milos_ufsphy_cfg = {
1352 .lanes = 2,
1353
1354 .offsets = &qmp_ufs_offsets_v6,
1355 .max_supported_gear = UFS_HS_G4,
1356
1357 .tbls = {
1358 .serdes = milos_ufsphy_serdes,
1359 .serdes_num = ARRAY_SIZE(milos_ufsphy_serdes),
1360 .tx = milos_ufsphy_tx,
1361 .tx_num = ARRAY_SIZE(milos_ufsphy_tx),
1362 .rx = milos_ufsphy_rx,
1363 .rx_num = ARRAY_SIZE(milos_ufsphy_rx),
1364 .pcs = milos_ufsphy_pcs,
1365 .pcs_num = ARRAY_SIZE(milos_ufsphy_pcs),
1366 },
1367 .tbls_hs_b = {
1368 .serdes = sm8550_ufsphy_hs_b_serdes,
1369 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1370 },
1371
1372 .vreg_list = milos_ufsphy_vreg_l,
1373 .num_vregs = ARRAY_SIZE(milos_ufsphy_vreg_l),
1374 .regs = ufsphy_v6_regs_layout,
1375 };
1376
1377 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
1378 .lanes = 1,
1379
1380 .offsets = &qmp_ufs_offsets,
1381 .max_supported_gear = UFS_HS_G3,
1382
1383 .tbls = {
1384 .serdes = msm8996_ufsphy_serdes,
1385 .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
1386 .tx = msm8996_ufsphy_tx,
1387 .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx),
1388 .rx = msm8996_ufsphy_rx,
1389 .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx),
1390 },
1391
1392 .vreg_list = msm8996_ufsphy_vreg_l,
1393 .num_vregs = ARRAY_SIZE(msm8996_ufsphy_vreg_l),
1394
1395 .regs = ufsphy_v2_regs_layout,
1396
1397 .no_pcs_sw_reset = true,
1398 };
1399
1400 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
1401 .lanes = 2,
1402
1403 .offsets = &qmp_ufs_offsets,
1404 .max_supported_gear = UFS_HS_G4,
1405
1406 .tbls = {
1407 .serdes = sm8350_ufsphy_serdes,
1408 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1409 .tx = sm8350_ufsphy_tx,
1410 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1411 .rx = sm8350_ufsphy_rx,
1412 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1413 .pcs = sm8350_ufsphy_pcs,
1414 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1415 },
1416 .tbls_hs_b = {
1417 .serdes = sm8350_ufsphy_hs_b_serdes,
1418 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1419 },
1420 .tbls_hs_overlay[0] = {
1421 .tx = sm8350_ufsphy_g4_tx,
1422 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1423 .rx = sm8350_ufsphy_g4_rx,
1424 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1425 .pcs = sm8350_ufsphy_g4_pcs,
1426 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1427 .max_gear = UFS_HS_G4,
1428 },
1429 .vreg_list = sa8775p_ufsphy_vreg_l,
1430 .num_vregs = ARRAY_SIZE(sa8775p_ufsphy_vreg_l),
1431 .regs = ufsphy_v5_regs_layout,
1432 };
1433
1434 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
1435 .lanes = 2,
1436
1437 .offsets = &qmp_ufs_offsets,
1438 .max_supported_gear = UFS_HS_G4,
1439
1440 .tbls = {
1441 .serdes = sm8150_ufsphy_serdes,
1442 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
1443 .tx = sc7280_ufsphy_tx,
1444 .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
1445 .rx = sc7280_ufsphy_rx,
1446 .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
1447 .pcs = sc7280_ufsphy_pcs,
1448 .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
1449 },
1450 .tbls_hs_b = {
1451 .serdes = sm8150_ufsphy_hs_b_serdes,
1452 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1453 },
1454 .tbls_hs_overlay[0] = {
1455 .tx = sm8250_ufsphy_hs_g4_tx,
1456 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1457 .rx = sc7280_ufsphy_hs_g4_rx,
1458 .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
1459 .pcs = sm8150_ufsphy_hs_g4_pcs,
1460 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1461 .max_gear = UFS_HS_G4,
1462 },
1463 .vreg_list = sc7280_ufsphy_vreg_l,
1464 .num_vregs = ARRAY_SIZE(sc7280_ufsphy_vreg_l),
1465 .regs = ufsphy_v4_regs_layout,
1466 };
1467
1468 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
1469 .lanes = 2,
1470
1471 .offsets = &qmp_ufs_offsets,
1472 .max_supported_gear = UFS_HS_G4,
1473
1474 .tbls = {
1475 .serdes = sm8350_ufsphy_serdes,
1476 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1477 .tx = sm8350_ufsphy_tx,
1478 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1479 .rx = sm8350_ufsphy_rx,
1480 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1481 .pcs = sm8350_ufsphy_pcs,
1482 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1483 },
1484 .tbls_hs_b = {
1485 .serdes = sm8350_ufsphy_hs_b_serdes,
1486 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1487 },
1488 .tbls_hs_overlay[0] = {
1489 .tx = sm8350_ufsphy_g4_tx,
1490 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1491 .rx = sm8350_ufsphy_g4_rx,
1492 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1493 .pcs = sm8350_ufsphy_g4_pcs,
1494 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1495 .max_gear = UFS_HS_G4,
1496 },
1497 .vreg_list = sc8280xp_ufsphy_vreg_l,
1498 .num_vregs = ARRAY_SIZE(sc8280xp_ufsphy_vreg_l),
1499 .regs = ufsphy_v5_regs_layout,
1500 };
1501
1502 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1503 .lanes = 2,
1504
1505 .offsets = &qmp_ufs_offsets,
1506 .max_supported_gear = UFS_HS_G3,
1507
1508 .tbls = {
1509 .serdes = sdm845_ufsphy_serdes,
1510 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
1511 .tx = sdm845_ufsphy_tx,
1512 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
1513 .rx = sdm845_ufsphy_rx,
1514 .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx),
1515 .pcs = sdm845_ufsphy_pcs,
1516 .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
1517 },
1518 .tbls_hs_b = {
1519 .serdes = sdm845_ufsphy_hs_b_serdes,
1520 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1521 },
1522 .vreg_list = sdm845_ufsphy_vreg_l,
1523 .num_vregs = ARRAY_SIZE(sdm845_ufsphy_vreg_l),
1524 .regs = ufsphy_v3_regs_layout,
1525
1526 .no_pcs_sw_reset = true,
1527 };
1528
1529 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
1530 .lanes = 1,
1531
1532 .offsets = &qmp_ufs_offsets,
1533 .max_supported_gear = UFS_HS_G3,
1534
1535 .tbls = {
1536 .serdes = sm6115_ufsphy_serdes,
1537 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
1538 .tx = sm6115_ufsphy_tx,
1539 .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx),
1540 .rx = sm6115_ufsphy_rx,
1541 .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx),
1542 .pcs = sm6115_ufsphy_pcs,
1543 .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
1544 },
1545 .tbls_hs_b = {
1546 .serdes = sm6115_ufsphy_hs_b_serdes,
1547 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
1548 },
1549 .vreg_list = sm6115_ufsphy_vreg_l,
1550 .num_vregs = ARRAY_SIZE(sm6115_ufsphy_vreg_l),
1551 .regs = ufsphy_v2_regs_layout,
1552
1553 .no_pcs_sw_reset = true,
1554 };
1555
1556 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
1557 .lanes = 1,
1558
1559 .offsets = &qmp_ufs_offsets,
1560 .max_supported_gear = UFS_HS_G3,
1561
1562 .tbls = {
1563 .serdes = sdm845_ufsphy_serdes,
1564 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
1565 .tx = sdm845_ufsphy_tx,
1566 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx),
1567 .rx = sm7150_ufsphy_rx,
1568 .rx_num = ARRAY_SIZE(sm7150_ufsphy_rx),
1569 .pcs = sm7150_ufsphy_pcs,
1570 .pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs),
1571 },
1572 .tbls_hs_b = {
1573 .serdes = sdm845_ufsphy_hs_b_serdes,
1574 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1575 },
1576 .vreg_list = sm7150_ufsphy_vreg_l,
1577 .num_vregs = ARRAY_SIZE(sm7150_ufsphy_vreg_l),
1578 .regs = ufsphy_v3_regs_layout,
1579
1580 .no_pcs_sw_reset = true,
1581 };
1582
1583 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1584 .lanes = 2,
1585
1586 .offsets = &qmp_ufs_offsets,
1587 .max_supported_gear = UFS_HS_G4,
1588
1589 .tbls = {
1590 .serdes = sm8150_ufsphy_serdes,
1591 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
1592 .tx = sm8150_ufsphy_tx,
1593 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
1594 .rx = sm8150_ufsphy_rx,
1595 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
1596 .pcs = sm8150_ufsphy_pcs,
1597 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
1598 },
1599 .tbls_hs_b = {
1600 .serdes = sm8150_ufsphy_hs_b_serdes,
1601 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1602 },
1603 .tbls_hs_overlay[0] = {
1604 .tx = sm8150_ufsphy_hs_g4_tx,
1605 .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
1606 .rx = sm8150_ufsphy_hs_g4_rx,
1607 .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
1608 .pcs = sm8150_ufsphy_hs_g4_pcs,
1609 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1610 .max_gear = UFS_HS_G4,
1611 },
1612 .vreg_list = sm8150_ufsphy_vreg_l,
1613 .num_vregs = ARRAY_SIZE(sm8150_ufsphy_vreg_l),
1614 .regs = ufsphy_v4_regs_layout,
1615 };
1616
1617 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
1618 .lanes = 2,
1619
1620 .offsets = &qmp_ufs_offsets,
1621 .max_supported_gear = UFS_HS_G4,
1622
1623 .tbls = {
1624 .serdes = sm8150_ufsphy_serdes,
1625 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
1626 .tx = sm8150_ufsphy_tx,
1627 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
1628 .rx = sm8150_ufsphy_rx,
1629 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
1630 .pcs = sm8150_ufsphy_pcs,
1631 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
1632 },
1633 .tbls_hs_b = {
1634 .serdes = sm8150_ufsphy_hs_b_serdes,
1635 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1636 },
1637 .tbls_hs_overlay[0] = {
1638 .tx = sm8250_ufsphy_hs_g4_tx,
1639 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1640 .rx = sm8250_ufsphy_hs_g4_rx,
1641 .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
1642 .pcs = sm8150_ufsphy_hs_g4_pcs,
1643 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1644 .max_gear = UFS_HS_G4,
1645 },
1646 .vreg_list = sm8250_ufsphy_vreg_l,
1647 .num_vregs = ARRAY_SIZE(sm8250_ufsphy_vreg_l),
1648 .regs = ufsphy_v4_regs_layout,
1649 };
1650
1651 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
1652 .lanes = 2,
1653
1654 .offsets = &qmp_ufs_offsets,
1655 .max_supported_gear = UFS_HS_G4,
1656
1657 .tbls = {
1658 .serdes = sm8350_ufsphy_serdes,
1659 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1660 .tx = sm8350_ufsphy_tx,
1661 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1662 .rx = sm8350_ufsphy_rx,
1663 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1664 .pcs = sm8350_ufsphy_pcs,
1665 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1666 },
1667 .tbls_hs_b = {
1668 .serdes = sm8350_ufsphy_hs_b_serdes,
1669 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1670 },
1671 .tbls_hs_overlay[0] = {
1672 .tx = sm8350_ufsphy_g4_tx,
1673 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1674 .rx = sm8350_ufsphy_g4_rx,
1675 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1676 .pcs = sm8350_ufsphy_g4_pcs,
1677 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1678 .max_gear = UFS_HS_G4,
1679 },
1680 .vreg_list = sm8350_ufsphy_vreg_l,
1681 .num_vregs = ARRAY_SIZE(sm8350_ufsphy_vreg_l),
1682 .regs = ufsphy_v5_regs_layout,
1683 };
1684
1685 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
1686 .lanes = 2,
1687
1688 .offsets = &qmp_ufs_offsets,
1689 .max_supported_gear = UFS_HS_G4,
1690
1691 .tbls = {
1692 .serdes = sm8350_ufsphy_serdes,
1693 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
1694 .tx = sm8350_ufsphy_tx,
1695 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx),
1696 .rx = sm8350_ufsphy_rx,
1697 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx),
1698 .pcs = sm8350_ufsphy_pcs,
1699 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
1700 },
1701 .tbls_hs_b = {
1702 .serdes = sm8350_ufsphy_hs_b_serdes,
1703 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1704 },
1705 .tbls_hs_overlay[0] = {
1706 .tx = sm8350_ufsphy_g4_tx,
1707 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1708 .rx = sm8350_ufsphy_g4_rx,
1709 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1710 .pcs = sm8350_ufsphy_g4_pcs,
1711 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1712 .max_gear = UFS_HS_G4,
1713 },
1714 .vreg_list = sm8450_ufsphy_vreg_l,
1715 .num_vregs = ARRAY_SIZE(sm8450_ufsphy_vreg_l),
1716 .regs = ufsphy_v5_regs_layout,
1717 };
1718
1719 static const struct qmp_phy_cfg sm8475_ufsphy_cfg = {
1720 .lanes = 2,
1721
1722 .offsets = &qmp_ufs_offsets_v6,
1723 .max_supported_gear = UFS_HS_G4,
1724
1725 .tbls = {
1726 .serdes = sm8475_ufsphy_serdes,
1727 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_serdes),
1728 .tx = sm8550_ufsphy_tx,
1729 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx),
1730 .rx = sm8550_ufsphy_rx,
1731 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx),
1732 .pcs = sm8550_ufsphy_pcs,
1733 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
1734 },
1735 .tbls_hs_b = {
1736 .serdes = sm8550_ufsphy_hs_b_serdes,
1737 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1738 },
1739 .tbls_hs_overlay[0] = {
1740 .serdes = sm8475_ufsphy_g4_serdes,
1741 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_g4_serdes),
1742 .tx = sm8550_ufsphy_g4_tx,
1743 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
1744 .rx = sm8550_ufsphy_g4_rx,
1745 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
1746 .pcs = sm8475_ufsphy_g4_pcs,
1747 .pcs_num = ARRAY_SIZE(sm8475_ufsphy_g4_pcs),
1748 .max_gear = UFS_HS_G4,
1749 },
1750 .vreg_list = sm8475_ufsphy_vreg_l,
1751 .num_vregs = ARRAY_SIZE(sm8475_ufsphy_vreg_l),
1752 .regs = ufsphy_v6_regs_layout,
1753 };
1754
1755 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
1756 .lanes = 2,
1757
1758 .offsets = &qmp_ufs_offsets_v6,
1759 .max_supported_gear = UFS_HS_G5,
1760
1761 .tbls = {
1762 .serdes = sm8550_ufsphy_serdes,
1763 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
1764 .tx = sm8550_ufsphy_tx,
1765 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx),
1766 .rx = sm8550_ufsphy_rx,
1767 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx),
1768 .pcs = sm8550_ufsphy_pcs,
1769 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
1770 },
1771 .tbls_hs_b = {
1772 .serdes = sm8550_ufsphy_hs_b_serdes,
1773 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1774 },
1775 .tbls_hs_overlay[0] = {
1776 .serdes = sm8550_ufsphy_g4_serdes,
1777 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
1778 .tx = sm8550_ufsphy_g4_tx,
1779 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
1780 .rx = sm8550_ufsphy_g4_rx,
1781 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
1782 .pcs = sm8550_ufsphy_g4_pcs,
1783 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
1784 .max_gear = UFS_HS_G4,
1785 },
1786 .tbls_hs_overlay[1] = {
1787 .serdes = sm8550_ufsphy_g5_serdes,
1788 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
1789 .rx = sm8550_ufsphy_g5_rx,
1790 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
1791 .pcs = sm8550_ufsphy_g5_pcs,
1792 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
1793 .max_gear = UFS_HS_G5,
1794 },
1795 .vreg_list = sm8550_ufsphy_vreg_l,
1796 .num_vregs = ARRAY_SIZE(sm8550_ufsphy_vreg_l),
1797 .regs = ufsphy_v6_regs_layout,
1798 };
1799
1800 static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
1801 .lanes = 2,
1802
1803 .offsets = &qmp_ufs_offsets_v6,
1804 .max_supported_gear = UFS_HS_G5,
1805
1806 .tbls = {
1807 .serdes = sm8650_ufsphy_serdes,
1808 .serdes_num = ARRAY_SIZE(sm8650_ufsphy_serdes),
1809 .tx = sm8650_ufsphy_tx,
1810 .tx_num = ARRAY_SIZE(sm8650_ufsphy_tx),
1811 .rx = sm8650_ufsphy_rx,
1812 .rx_num = ARRAY_SIZE(sm8650_ufsphy_rx),
1813 .pcs = sm8650_ufsphy_pcs,
1814 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs),
1815 },
1816 .tbls_hs_overlay[0] = {
1817 .pcs = sm8650_ufsphy_g4_pcs,
1818 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g4_pcs),
1819 .max_gear = UFS_HS_G4,
1820 },
1821 .tbls_hs_overlay[1] = {
1822 .pcs = sm8650_ufsphy_g5_pcs,
1823 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs),
1824 .max_gear = UFS_HS_G5,
1825 },
1826
1827 .vreg_list = sm8650_ufsphy_vreg_l,
1828 .num_vregs = ARRAY_SIZE(sm8650_ufsphy_vreg_l),
1829 .regs = ufsphy_v6_regs_layout,
1830 };
1831
1832 static const struct qmp_phy_cfg sm8750_ufsphy_cfg = {
1833 .lanes = 2,
1834
1835 .offsets = &qmp_ufs_offsets_v6,
1836 .max_supported_gear = UFS_HS_G5,
1837
1838 .tbls = {
1839 .serdes = sm8750_ufsphy_serdes,
1840 .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
1841 .tx = sm8750_ufsphy_tx,
1842 .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
1843 .rx = sm8750_ufsphy_rx,
1844 .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx),
1845 .pcs = sm8750_ufsphy_pcs,
1846 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
1847 },
1848
1849 .tbls_hs_b = {
1850 .pcs = sm8750_ufsphy_hs_b_pcs,
1851 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
1852 },
1853
1854 .tbls_hs_overlay[0] = {
1855 .pcs = sm8750_ufsphy_g4_pcs,
1856 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
1857 .max_gear = UFS_HS_G4,
1858 },
1859 .tbls_hs_overlay[1] = {
1860 .pcs = sm8650_ufsphy_g5_pcs,
1861 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs),
1862 .max_gear = UFS_HS_G5,
1863 },
1864
1865 .vreg_list = sm8750_ufsphy_vreg_l,
1866 .num_vregs = ARRAY_SIZE(sm8750_ufsphy_vreg_l),
1867 .regs = ufsphy_v6_regs_layout,
1868
1869 };
1870
1871 static const struct qmp_phy_init_tbl hawi_ufsphy_serdes[] = {
1872 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0xd9),
1873 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16),
1874 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x11),
1875 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1876 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_EN, 0x01),
1877 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x60),
1878 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO, 0x1f),
1879 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_IVCO_MODE1, 0x1f),
1880 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IETRIM, 0x07),
1881 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_IPTRIM, 0x20),
1882 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04),
1883 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_CTRL, 0x40),
1884 QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADAPTIVE_ANALOG_CONFIG, 0x06),
1885 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41),
1886 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x06),
1887 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x18),
1888 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x14),
1889 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06),
1890 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18),
1891 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14),
1892 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x7f),
1893 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x06),
1894 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92),
1895 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1896 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x4c),
1897 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x06),
1898 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x18),
1899 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x14),
1900 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06),
1901 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18),
1902 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14),
1903 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x99),
1904 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x07),
1905 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe),
1906 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1907 };
1908
1909 static const struct qmp_phy_init_tbl hawi_ufsphy_tx[] = {
1910 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_LANE_MODE_1, 0x0c),
1911 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
1912 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x17),
1913 };
1914
1915 static const struct qmp_phy_init_tbl hawi_ufsphy_rx[] = {
1916 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1917 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4, 0x0c),
1918 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4, 0x04),
1919 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
1920 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS, 0x07),
1921 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
1922 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
1923 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
1924 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
1925 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL, 0x8e),
1926 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1927 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4, 0xb8),
1928 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7, 0x66),
1929 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9, 0x1f),
1930 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7, 0x66),
1931 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9, 0x1f),
1932 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7, 0x66),
1933 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9, 0x1f),
1934 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7, 0x66),
1935 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9, 0x1f),
1936 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_UCDR_SO_SATURATION, 0x1f),
1937 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_TERM_BW_CTRL0, 0xfa),
1938 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL, 0x30),
1939 QMP_PHY_INIT_CFG(QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM, 0x77),
1940 };
1941
1942 static const struct qmp_phy_init_tbl hawi_ufsphy_pcs[] = {
1943 QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1944 QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PCS_CTRL1, 0x42),
1945 QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
1946 QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2, 0x68),
1947 QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1948 };
1949
1950 static const struct qmp_phy_init_tbl hawi_ufsphy_g5_pcs[] = {
1951 QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_PLL_CNTL, 0x3b),
1952 QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05),
1953 QMP_PHY_INIT_CFG(QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05),
1954 };
1955
1956 static const struct qmp_phy_cfg hawi_ufsphy_cfg = {
1957 .lanes = 2,
1958
1959 .offsets = &qmp_ufs_offsets_v7,
1960 .max_supported_gear = UFS_HS_G5,
1961
1962 .tbls = {
1963 .serdes = hawi_ufsphy_serdes,
1964 .serdes_num = ARRAY_SIZE(hawi_ufsphy_serdes),
1965 .tx = hawi_ufsphy_tx,
1966 .tx_num = ARRAY_SIZE(hawi_ufsphy_tx),
1967 .rx = hawi_ufsphy_rx,
1968 .rx_num = ARRAY_SIZE(hawi_ufsphy_rx),
1969 .pcs = hawi_ufsphy_pcs,
1970 .pcs_num = ARRAY_SIZE(hawi_ufsphy_pcs),
1971 },
1972
1973 .tbls_hs_overlay[0] = {
1974 .pcs = hawi_ufsphy_g5_pcs,
1975 .pcs_num = ARRAY_SIZE(hawi_ufsphy_g5_pcs),
1976 .max_gear = UFS_HS_G5,
1977 },
1978
1979 .vreg_list = hawi_ufsphy_vreg_l,
1980 .num_vregs = ARRAY_SIZE(hawi_ufsphy_vreg_l),
1981 .regs = ufsphy_v7_regs_layout,
1982 };
1983
qmp_ufs_serdes_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1984 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1985 {
1986 void __iomem *serdes = qmp->serdes;
1987
1988 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);
1989 }
1990
qmp_ufs_lanes_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)1991 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1992 {
1993 const struct qmp_phy_cfg *cfg = qmp->cfg;
1994 void __iomem *tx = qmp->tx;
1995 void __iomem *rx = qmp->rx;
1996
1997 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);
1998 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);
1999
2000 if (cfg->lanes >= 2) {
2001 qmp_configure_lane(qmp->dev, qmp->tx2, tbls->tx, tbls->tx_num, 2);
2002 qmp_configure_lane(qmp->dev, qmp->rx2, tbls->rx, tbls->rx_num, 2);
2003 }
2004 }
2005
qmp_ufs_pcs_init(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)2006 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
2007 {
2008 void __iomem *pcs = qmp->pcs;
2009
2010 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);
2011 }
2012
qmp_ufs_get_gear_overlay(struct qmp_ufs * qmp,const struct qmp_phy_cfg * cfg)2013 static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
2014 {
2015 u32 max_gear, floor_max_gear = cfg->max_supported_gear;
2016 int idx, ret = -EINVAL;
2017
2018 for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) {
2019 max_gear = cfg->tbls_hs_overlay[idx].max_gear;
2020
2021 /* Skip if the table is not available */
2022 if (max_gear == 0)
2023 continue;
2024
2025 /* Direct matching, bail */
2026 if (qmp->submode == max_gear)
2027 return idx;
2028
2029 /* If no direct matching, the lowest gear is the best matching */
2030 if (max_gear < floor_max_gear) {
2031 ret = idx;
2032 floor_max_gear = max_gear;
2033 }
2034 }
2035
2036 return ret;
2037 }
2038
qmp_ufs_init_all(struct qmp_ufs * qmp,const struct qmp_phy_cfg_tbls * tbls)2039 static void qmp_ufs_init_all(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
2040 {
2041 qmp_ufs_serdes_init(qmp, tbls);
2042 qmp_ufs_lanes_init(qmp, tbls);
2043 qmp_ufs_pcs_init(qmp, tbls);
2044 }
2045
qmp_ufs_init_registers(struct qmp_ufs * qmp,const struct qmp_phy_cfg * cfg)2046 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
2047 {
2048 int i;
2049
2050 qmp_ufs_init_all(qmp, &cfg->tbls);
2051
2052 i = qmp_ufs_get_gear_overlay(qmp, cfg);
2053 if (i >= 0) {
2054 qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]);
2055 }
2056
2057 if (qmp->mode == PHY_MODE_UFS_HS_B)
2058 qmp_ufs_init_all(qmp, &cfg->tbls_hs_b);
2059 }
2060
qmp_ufs_power_on(struct phy * phy)2061 static int qmp_ufs_power_on(struct phy *phy)
2062 {
2063 struct qmp_ufs *qmp = phy_get_drvdata(phy);
2064 const struct qmp_phy_cfg *cfg = qmp->cfg;
2065 void __iomem *pcs = qmp->pcs;
2066 int ret;
2067
2068 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2069 if (ret) {
2070 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2071 return ret;
2072 }
2073
2074 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
2075 if (ret)
2076 goto err_disable_regulators;
2077
2078 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
2079 return 0;
2080
2081 err_disable_regulators:
2082 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2083 return ret;
2084 }
2085
qmp_ufs_phy_calibrate(struct phy * phy)2086 static int qmp_ufs_phy_calibrate(struct phy *phy)
2087 {
2088 struct qmp_ufs *qmp = phy_get_drvdata(phy);
2089 const struct qmp_phy_cfg *cfg = qmp->cfg;
2090 void __iomem *pcs = qmp->pcs;
2091 void __iomem *status;
2092 unsigned int val;
2093 int ret;
2094
2095 ret = reset_control_assert(qmp->ufs_reset);
2096 if (ret)
2097 return ret;
2098
2099 qmp_ufs_init_registers(qmp, cfg);
2100
2101 ret = reset_control_deassert(qmp->ufs_reset);
2102 if (ret)
2103 return ret;
2104
2105 /* Pull PHY out of reset state */
2106 if (!cfg->no_pcs_sw_reset)
2107 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2108
2109 /* start SerDes */
2110 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
2111
2112 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
2113 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200,
2114 PHY_INIT_COMPLETE_TIMEOUT);
2115 if (ret) {
2116 dev_err(qmp->dev, "phy initialization timed-out\n");
2117 return ret;
2118 }
2119
2120 return 0;
2121 }
2122
qmp_ufs_power_off(struct phy * phy)2123 static int qmp_ufs_power_off(struct phy *phy)
2124 {
2125 struct qmp_ufs *qmp = phy_get_drvdata(phy);
2126 const struct qmp_phy_cfg *cfg = qmp->cfg;
2127
2128 /* Put PHY into POWER DOWN state: active low */
2129 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2130 SW_PWRDN);
2131
2132 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2133
2134 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2135
2136 return 0;
2137 }
2138
qmp_ufs_set_mode(struct phy * phy,enum phy_mode mode,int submode)2139 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2140 {
2141 struct qmp_ufs *qmp = phy_get_drvdata(phy);
2142 const struct qmp_phy_cfg *cfg = qmp->cfg;
2143
2144 if (submode > cfg->max_supported_gear || submode == 0) {
2145 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode);
2146 return -EINVAL;
2147 }
2148
2149 qmp->mode = mode;
2150 qmp->submode = submode;
2151
2152 return 0;
2153 }
2154
qmp_ufs_phy_init(struct phy * phy)2155 static int qmp_ufs_phy_init(struct phy *phy)
2156 {
2157 struct qmp_ufs *qmp = phy_get_drvdata(phy);
2158 const struct qmp_phy_cfg *cfg = qmp->cfg;
2159 int ret;
2160
2161 if (!cfg->no_pcs_sw_reset)
2162 return 0;
2163
2164 /*
2165 * Get UFS reset, which is delayed until now to avoid a
2166 * circular dependency where UFS needs its PHY, but the PHY
2167 * needs this UFS reset.
2168 */
2169 if (!qmp->ufs_reset) {
2170 qmp->ufs_reset =
2171 devm_reset_control_get_exclusive(qmp->dev, "ufsphy");
2172
2173 if (IS_ERR(qmp->ufs_reset)) {
2174 ret = PTR_ERR(qmp->ufs_reset);
2175 dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret);
2176 qmp->ufs_reset = NULL;
2177 return ret;
2178 }
2179 }
2180
2181 return 0;
2182 }
2183
2184 static const struct phy_ops qcom_qmp_ufs_phy_ops = {
2185 .init = qmp_ufs_phy_init,
2186 .power_on = qmp_ufs_power_on,
2187 .power_off = qmp_ufs_power_off,
2188 .calibrate = qmp_ufs_phy_calibrate,
2189 .set_mode = qmp_ufs_set_mode,
2190 .owner = THIS_MODULE,
2191 };
2192
2193
qmp_ufs_clk_init(struct qmp_ufs * qmp)2194 static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
2195 {
2196 struct device *dev = qmp->dev;
2197
2198 qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks);
2199 if (qmp->num_clks < 0)
2200 return qmp->num_clks;
2201
2202 return 0;
2203 }
2204
qmp_ufs_clk_release_provider(void * res)2205 static void qmp_ufs_clk_release_provider(void *res)
2206 {
2207 of_clk_del_provider(res);
2208 }
2209
2210 #define UFS_SYMBOL_CLOCKS 3
2211
qmp_ufs_register_clocks(struct qmp_ufs * qmp,struct device_node * np)2212 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np)
2213 {
2214 struct clk_hw_onecell_data *clk_data;
2215 struct clk_hw *hw;
2216 char name[64];
2217 int ret;
2218
2219 clk_data = devm_kzalloc(qmp->dev,
2220 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
2221 GFP_KERNEL);
2222 if (!clk_data)
2223 return -ENOMEM;
2224
2225 clk_data->num = UFS_SYMBOL_CLOCKS;
2226
2227 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
2228 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2229 if (IS_ERR(hw))
2230 return PTR_ERR(hw);
2231
2232 clk_data->hws[0] = hw;
2233
2234 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
2235 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2236 if (IS_ERR(hw))
2237 return PTR_ERR(hw);
2238
2239 clk_data->hws[1] = hw;
2240
2241 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
2242 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
2243 if (IS_ERR(hw))
2244 return PTR_ERR(hw);
2245
2246 clk_data->hws[2] = hw;
2247
2248 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
2249 if (ret)
2250 return ret;
2251
2252 /*
2253 * Roll a devm action because the clock provider can be a child node.
2254 */
2255 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
2256 }
2257
qmp_ufs_parse_dt_legacy(struct qmp_ufs * qmp,struct device_node * np)2258 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
2259 {
2260 struct platform_device *pdev = to_platform_device(qmp->dev);
2261 const struct qmp_phy_cfg *cfg = qmp->cfg;
2262 struct device *dev = qmp->dev;
2263
2264 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2265 if (IS_ERR(qmp->serdes))
2266 return PTR_ERR(qmp->serdes);
2267
2268 /*
2269 * Get memory resources for the PHY:
2270 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2271 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2272 * For single lane PHYs: pcs_misc (optional) -> 3.
2273 */
2274 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2275 if (IS_ERR(qmp->tx))
2276 return PTR_ERR(qmp->tx);
2277
2278 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2279 if (IS_ERR(qmp->rx))
2280 return PTR_ERR(qmp->rx);
2281
2282 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
2283 if (IS_ERR(qmp->pcs))
2284 return PTR_ERR(qmp->pcs);
2285
2286 if (cfg->lanes >= 2) {
2287 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2288 if (IS_ERR(qmp->tx2))
2289 return PTR_ERR(qmp->tx2);
2290
2291 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2292 if (IS_ERR(qmp->rx2))
2293 return PTR_ERR(qmp->rx2);
2294
2295 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2296 } else {
2297 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2298 }
2299
2300 if (IS_ERR(qmp->pcs_misc))
2301 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2302
2303 return 0;
2304 }
2305
qmp_ufs_parse_dt(struct qmp_ufs * qmp)2306 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp)
2307 {
2308 struct platform_device *pdev = to_platform_device(qmp->dev);
2309 const struct qmp_phy_cfg *cfg = qmp->cfg;
2310 const struct qmp_ufs_offsets *offs = cfg->offsets;
2311 void __iomem *base;
2312
2313 if (!offs)
2314 return -EINVAL;
2315
2316 base = devm_platform_ioremap_resource(pdev, 0);
2317 if (IS_ERR(base))
2318 return PTR_ERR(base);
2319
2320 qmp->serdes = base + offs->serdes;
2321 qmp->pcs = base + offs->pcs;
2322 qmp->tx = base + offs->tx;
2323 qmp->rx = base + offs->rx;
2324
2325 if (cfg->lanes >= 2) {
2326 qmp->tx2 = base + offs->tx2;
2327 qmp->rx2 = base + offs->rx2;
2328 }
2329
2330 return 0;
2331 }
2332
qmp_ufs_probe(struct platform_device * pdev)2333 static int qmp_ufs_probe(struct platform_device *pdev)
2334 {
2335 struct device *dev = &pdev->dev;
2336 struct phy_provider *phy_provider;
2337 struct device_node *np;
2338 struct qmp_ufs *qmp;
2339 int ret;
2340
2341 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2342 if (!qmp)
2343 return -ENOMEM;
2344
2345 qmp->dev = dev;
2346
2347 qmp->cfg = of_device_get_match_data(dev);
2348 if (!qmp->cfg)
2349 return -EINVAL;
2350
2351 ret = qmp_ufs_clk_init(qmp);
2352 if (ret)
2353 return ret;
2354
2355 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs,
2356 qmp->cfg->vreg_list,
2357 &qmp->vregs);
2358 if (ret)
2359 return ret;
2360
2361 /* Check for legacy binding with child node. */
2362 np = of_get_next_available_child(dev->of_node, NULL);
2363 if (np) {
2364 ret = qmp_ufs_parse_dt_legacy(qmp, np);
2365 } else {
2366 np = of_node_get(dev->of_node);
2367 ret = qmp_ufs_parse_dt(qmp);
2368 }
2369 if (ret)
2370 goto err_node_put;
2371
2372 ret = qmp_ufs_register_clocks(qmp, np);
2373 if (ret)
2374 goto err_node_put;
2375
2376 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
2377 if (IS_ERR(qmp->phy)) {
2378 ret = PTR_ERR(qmp->phy);
2379 dev_err(dev, "failed to create PHY: %d\n", ret);
2380 goto err_node_put;
2381 }
2382
2383 phy_set_drvdata(qmp->phy, qmp);
2384
2385 of_node_put(np);
2386
2387 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2388
2389 return PTR_ERR_OR_ZERO(phy_provider);
2390
2391 err_node_put:
2392 of_node_put(np);
2393 return ret;
2394 }
2395
2396 static const struct of_device_id qmp_ufs_of_match_table[] = {
2397 {
2398 .compatible = "qcom,hawi-qmp-ufs-phy",
2399 .data = &hawi_ufsphy_cfg,
2400 }, {
2401 .compatible = "qcom,milos-qmp-ufs-phy",
2402 .data = &milos_ufsphy_cfg,
2403 }, {
2404 .compatible = "qcom,msm8996-qmp-ufs-phy",
2405 .data = &msm8996_ufsphy_cfg,
2406 }, {
2407 .compatible = "qcom,msm8998-qmp-ufs-phy",
2408 .data = &sdm845_ufsphy_cfg,
2409 }, {
2410 .compatible = "qcom,sa8775p-qmp-ufs-phy",
2411 .data = &sa8775p_ufsphy_cfg,
2412 }, {
2413 .compatible = "qcom,sc7180-qmp-ufs-phy",
2414 .data = &sm7150_ufsphy_cfg,
2415 }, {
2416 .compatible = "qcom,sc7280-qmp-ufs-phy",
2417 .data = &sc7280_ufsphy_cfg,
2418 }, {
2419 .compatible = "qcom,sc8180x-qmp-ufs-phy",
2420 .data = &sm8150_ufsphy_cfg,
2421 }, {
2422 .compatible = "qcom,sc8280xp-qmp-ufs-phy",
2423 .data = &sc8280xp_ufsphy_cfg,
2424 }, {
2425 .compatible = "qcom,sdm845-qmp-ufs-phy",
2426 .data = &sdm845_ufsphy_cfg,
2427 }, {
2428 .compatible = "qcom,sm6115-qmp-ufs-phy",
2429 .data = &sm6115_ufsphy_cfg,
2430 }, {
2431 .compatible = "qcom,sm6125-qmp-ufs-phy",
2432 .data = &sm6115_ufsphy_cfg,
2433 }, {
2434 .compatible = "qcom,sm6350-qmp-ufs-phy",
2435 .data = &sdm845_ufsphy_cfg,
2436 }, {
2437 .compatible = "qcom,sm7150-qmp-ufs-phy",
2438 .data = &sm7150_ufsphy_cfg,
2439 }, {
2440 .compatible = "qcom,sm8150-qmp-ufs-phy",
2441 .data = &sm8150_ufsphy_cfg,
2442 }, {
2443 .compatible = "qcom,sm8250-qmp-ufs-phy",
2444 .data = &sm8250_ufsphy_cfg,
2445 }, {
2446 .compatible = "qcom,sm8350-qmp-ufs-phy",
2447 .data = &sm8350_ufsphy_cfg,
2448 }, {
2449 .compatible = "qcom,sm8450-qmp-ufs-phy",
2450 .data = &sm8450_ufsphy_cfg,
2451 }, {
2452 .compatible = "qcom,sm8475-qmp-ufs-phy",
2453 .data = &sm8475_ufsphy_cfg,
2454 }, {
2455 .compatible = "qcom,sm8550-qmp-ufs-phy",
2456 .data = &sm8550_ufsphy_cfg,
2457 }, {
2458 .compatible = "qcom,sm8650-qmp-ufs-phy",
2459 .data = &sm8650_ufsphy_cfg,
2460 }, {
2461 .compatible = "qcom,sm8750-qmp-ufs-phy",
2462 .data = &sm8750_ufsphy_cfg,
2463 },
2464
2465 { },
2466 };
2467 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
2468
2469 static struct platform_driver qmp_ufs_driver = {
2470 .probe = qmp_ufs_probe,
2471 .driver = {
2472 .name = "qcom-qmp-ufs-phy",
2473 .of_match_table = qmp_ufs_of_match_table,
2474 },
2475 };
2476
2477 module_platform_driver(qmp_ufs_driver);
2478
2479 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2480 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver");
2481 MODULE_LICENSE("GPL v2");
2482