1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #include <linux/bitfield.h> 10 11 #define MT7530_NUM_PORTS 7 12 #define MT7530_NUM_PHYS 5 13 #define MT7530_NUM_FDB_RECORDS 2048 14 #define MT7530_ALL_MEMBERS 0xff 15 16 #define MTK_HDR_LEN 4 17 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 18 19 enum mt753x_id { 20 ID_MT7530 = 0, 21 ID_MT7621 = 1, 22 ID_MT7531 = 2, 23 ID_MT7988 = 3, 24 ID_EN7581 = 4, 25 ID_AN7583 = 5, 26 ID_EN7528 = 6, 27 }; 28 29 #define NUM_TRGMII_CTRL 5 30 31 #define TRGMII_BASE(x) (0x10000 + (x)) 32 33 /* Registers to ethsys access */ 34 #define ETHSYS_CLKCFG0 0x2c 35 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 36 37 #define SYSC_REG_RSTCTRL 0x34 38 #define RESET_MCM BIT(2) 39 40 /* Register for ARL global control */ 41 #define MT753X_AGC 0xc 42 #define LOCAL_EN BIT(7) 43 44 /* Register for MAC forward control */ 45 #define MT753X_MFC 0x10 46 #define BC_FFP_MASK GENMASK(31, 24) 47 #define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x) 48 #define UNM_FFP_MASK GENMASK(23, 16) 49 #define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x) 50 #define UNU_FFP_MASK GENMASK(15, 8) 51 #define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x) 52 #define MT7530_CPU_EN BIT(7) 53 #define MT7530_CPU_PORT_MASK GENMASK(6, 4) 54 #define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x) 55 #define MT7530_MIRROR_EN BIT(3) 56 #define MT7530_MIRROR_PORT_MASK GENMASK(2, 0) 57 #define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x) 58 #define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x) 59 #define MT7531_QRY_FFP_MASK GENMASK(7, 0) 60 #define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x) 61 62 /* Register for CPU forward control */ 63 #define MT7531_CFC 0x4 64 #define MT7531_MIRROR_EN BIT(19) 65 #define MT7531_MIRROR_PORT_MASK GENMASK(18, 16) 66 #define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x) 67 #define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x) 68 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 69 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x) 70 71 #define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \ 72 id == ID_MT7988 || \ 73 id == ID_EN7581 || \ 74 id == ID_AN7583) ? \ 75 MT7531_CFC : MT753X_MFC) 76 77 #define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \ 78 id == ID_MT7988 || \ 79 id == ID_EN7581) ? \ 80 MT7531_MIRROR_EN : MT7530_MIRROR_EN) 81 82 #define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \ 83 id == ID_MT7988 || \ 84 id == ID_EN7581 || \ 85 id == ID_AN7583) ? \ 86 MT7531_MIRROR_PORT_MASK : \ 87 MT7530_MIRROR_PORT_MASK) 88 89 #define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \ 90 id == ID_MT7988 || \ 91 id == ID_EN7581 || \ 92 id == ID_AN7583) ? \ 93 MT7531_MIRROR_PORT_GET(val) : \ 94 MT7530_MIRROR_PORT_GET(val)) 95 96 #define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \ 97 id == ID_MT7988 || \ 98 id == ID_EN7581 || \ 99 id == ID_AN7583) ? \ 100 MT7531_MIRROR_PORT_SET(val) : \ 101 MT7530_MIRROR_PORT_SET(val)) 102 103 /* Register for BPDU and PAE frame control */ 104 #define MT753X_BPC 0x24 105 #define PAE_BPDU_FR BIT(25) 106 #define PAE_EG_TAG_MASK GENMASK(24, 22) 107 #define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x) 108 #define PAE_PORT_FW_MASK GENMASK(18, 16) 109 #define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x) 110 #define BPDU_EG_TAG_MASK GENMASK(8, 6) 111 #define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x) 112 #define BPDU_PORT_FW_MASK GENMASK(2, 0) 113 114 /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */ 115 #define MT753X_RGAC1 0x28 116 #define R02_BPDU_FR BIT(25) 117 #define R02_EG_TAG_MASK GENMASK(24, 22) 118 #define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x) 119 #define R02_PORT_FW_MASK GENMASK(18, 16) 120 #define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x) 121 #define R01_BPDU_FR BIT(9) 122 #define R01_EG_TAG_MASK GENMASK(8, 6) 123 #define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x) 124 #define R01_PORT_FW_MASK GENMASK(2, 0) 125 126 /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */ 127 #define MT753X_RGAC2 0x2c 128 #define R0E_BPDU_FR BIT(25) 129 #define R0E_EG_TAG_MASK GENMASK(24, 22) 130 #define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x) 131 #define R0E_PORT_FW_MASK GENMASK(18, 16) 132 #define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x) 133 #define R03_BPDU_FR BIT(9) 134 #define R03_EG_TAG_MASK GENMASK(8, 6) 135 #define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x) 136 #define R03_PORT_FW_MASK GENMASK(2, 0) 137 138 enum mt753x_to_cpu_fw { 139 TO_CPU_FW_SYSTEM_DEFAULT, 140 TO_CPU_FW_CPU_EXCLUDE = 4, 141 TO_CPU_FW_CPU_INCLUDE = 5, 142 TO_CPU_FW_CPU_ONLY = 6, 143 TO_CPU_FW_DROP = 7, 144 }; 145 146 /* Registers for address table access */ 147 #define MT7530_ATA1 0x74 148 #define STATIC_EMP 0 149 #define STATIC_ENT 3 150 #define MT7530_ATA2 0x78 151 #define ATA2_IVL BIT(15) 152 #define ATA2_FID_MASK GENMASK(14, 12) 153 #define ATA2_FID(x) FIELD_PREP(ATA2_FID_MASK, x) 154 155 /* Register for address table write data */ 156 #define MT7530_ATWD 0x7c 157 158 /* Register for address table control */ 159 #define MT7530_ATC 0x80 160 #define ATC_HASH_MASK GENMASK(27, 16) 161 #define ATC_HASH(x) FIELD_PREP(ATC_HASH_MASK, x) 162 #define ATC_BUSY BIT(15) 163 #define ATC_SRCH_END BIT(14) 164 #define ATC_SRCH_HIT BIT(13) 165 #define ATC_INVALID BIT(12) 166 #define ATC_MAT_MASK GENMASK(11, 8) 167 #define ATC_MAT(x) FIELD_PREP(ATC_MAT_MASK, x) 168 #define ATC_MAT_MACTAB ATC_MAT(0) 169 #define ATC_MAT_NON_STATIC_MAC ATC_MAT(4) 170 171 enum mt7530_fdb_cmd { 172 MT7530_FDB_READ = 0, 173 MT7530_FDB_WRITE = 1, 174 MT7530_FDB_FLUSH = 2, 175 MT7530_FDB_START = 4, 176 MT7530_FDB_NEXT = 5, 177 }; 178 179 /* Registers for table search read address */ 180 #define MT7530_TSRA1 0x84 181 #define MAC_BYTE_0_MASK GENMASK(31, 24) 182 #define MAC_BYTE_1_MASK GENMASK(23, 16) 183 #define MAC_BYTE_2_MASK GENMASK(15, 8) 184 #define MAC_BYTE_3_MASK GENMASK(7, 0) 185 186 #define MT7530_TSRA2 0x88 187 #define MAC_BYTE_4_MASK GENMASK(31, 24) 188 #define MAC_BYTE_5_MASK GENMASK(23, 16) 189 #define CVID_MASK GENMASK(11, 0) 190 191 #define MT7530_ATRD 0x8C 192 #define AGE_TIMER_MASK GENMASK(31, 24) 193 #define PORT_MAP_MASK GENMASK(11, 4) 194 #define ENT_STATUS_MASK GENMASK(3, 2) 195 196 /* Register for vlan table control */ 197 #define MT7530_VTCR 0x90 198 #define VTCR_BUSY BIT(31) 199 #define VTCR_INVALID BIT(16) 200 #define VTCR_FUNC_MASK GENMASK(15, 12) 201 #define VTCR_FUNC(x) FIELD_PREP(VTCR_FUNC_MASK, x) 202 #define VTCR_VID_MASK GENMASK(11, 0) 203 #define VTCR_VID(x) FIELD_PREP(VTCR_VID_MASK, x) 204 205 enum mt7530_vlan_cmd { 206 /* Read/Write the specified VID entry from VAWD register based 207 * on VID. 208 */ 209 MT7530_VTCR_RD_VID = 0, 210 MT7530_VTCR_WR_VID = 1, 211 }; 212 213 /* Register for setup vlan and acl write data */ 214 #define MT7530_VAWD1 0x94 215 #define PORT_STAG BIT(31) 216 /* Independent VLAN Learning */ 217 #define IVL_MAC BIT(30) 218 /* Egress Tag Consistent */ 219 #define EG_CON BIT(29) 220 /* Per VLAN Egress Tag Control */ 221 #define VTAG_EN BIT(28) 222 /* VLAN Member Control */ 223 #define PORT_MEM_MASK GENMASK(23, 16) 224 #define PORT_MEM(x) FIELD_PREP(PORT_MEM_MASK, x) 225 /* Filter ID */ 226 #define FID_MASK GENMASK(3, 1) 227 #define FID(x) FIELD_PREP(FID_MASK, x) 228 /* VLAN Entry Valid */ 229 #define VLAN_VALID BIT(0) 230 231 enum mt7530_fid { 232 FID_STANDALONE = 0, 233 FID_BRIDGED = 1, 234 }; 235 236 #define MT7530_VAWD2 0x98 237 /* Egress Tag Control */ 238 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 239 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 240 241 enum mt7530_vlan_egress_attr { 242 MT7530_VLAN_EGRESS_UNTAG = 0, 243 MT7530_VLAN_EGRESS_TAG = 2, 244 MT7530_VLAN_EGRESS_STACK = 3, 245 }; 246 247 /* Register for address age control */ 248 #define MT7530_AAC 0xa0 249 /* Disable ageing */ 250 #define AGE_DIS BIT(20) 251 /* Age count */ 252 #define AGE_CNT_MASK GENMASK(19, 12) 253 #define AGE_CNT_MAX 0xff 254 #define AGE_CNT(x) FIELD_PREP(AGE_CNT_MASK, x) 255 /* Age unit */ 256 #define AGE_UNIT_MASK GENMASK(11, 0) 257 #define AGE_UNIT_MAX 0xfff 258 #define AGE_UNIT(x) FIELD_PREP(AGE_UNIT_MASK, x) 259 260 #define MT753X_ERLCR_P(x) (0x1040 + ((x) * 0x100)) 261 #define ERLCR_CIR_MASK GENMASK(31, 16) 262 #define ERLCR_EN_MASK BIT(15) 263 #define ERLCR_EXP_MASK GENMASK(11, 8) 264 #define ERLCR_TBF_MODE_MASK BIT(7) 265 #define ERLCR_MANT_MASK GENMASK(6, 0) 266 267 #define MT753X_GERLCR 0x10e0 268 #define EGR_BC_MASK GENMASK(7, 0) 269 #define EGR_BC_CRC 0x4 /* crc */ 270 #define EGR_BC_CRC_IPG_PREAMBLE 0x18 /* crc + ipg + preamble */ 271 272 /* Register for port STP state control */ 273 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 274 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) 275 #define FID_PST_MASK(fid) FID_PST(fid, 0x3) 276 277 enum mt7530_stp_state { 278 MT7530_STP_DISABLED = 0, 279 MT7530_STP_BLOCKING = 1, 280 MT7530_STP_LISTENING = 1, 281 MT7530_STP_LEARNING = 2, 282 MT7530_STP_FORWARDING = 3 283 }; 284 285 /* Register for port control */ 286 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 287 #define PORT_TX_MIR BIT(9) 288 #define PORT_RX_MIR BIT(8) 289 #define PCR_PORT_VLAN_MASK GENMASK(1, 0) 290 291 enum mt7530_port_mode { 292 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 293 MT7530_PORT_MATRIX_MODE = 0, 294 295 /* Fallback Mode: Forward received frames with ingress ports that do 296 * not belong to the VLAN member. Frames whose VID is not listed on 297 * the VLAN table are forwarded by the PCR_MATRIX members. 298 */ 299 MT7530_PORT_FALLBACK_MODE = 1, 300 301 /* Security Mode: Discard any frame due to ingress membership 302 * violation or VID missed on the VLAN table. 303 */ 304 MT7530_PORT_SECURITY_MODE = 3, 305 }; 306 307 #define PCR_MATRIX_MASK GENMASK(23, 16) 308 #define PCR_MATRIX(x) FIELD_PREP(PCR_MATRIX_MASK, x) 309 #define PORT_PRI_MASK GENMASK(26, 24) 310 #define PORT_PRI(x) FIELD_PREP(PORT_PRI_MASK, x) 311 #define EG_TAG_MASK GENMASK(29, 28) 312 #define EG_TAG(x) FIELD_PREP(EG_TAG_MASK, x) 313 #define PCR_MATRIX_CLR PCR_MATRIX(0) 314 315 /* Register for port security control */ 316 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 317 #define SA_DIS BIT(4) 318 319 /* Register for port vlan control */ 320 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 321 #define PORT_SPEC_TAG BIT(5) 322 #define PVC_EG_TAG_MASK GENMASK(10, 8) 323 #define PVC_EG_TAG(x) FIELD_PREP(PVC_EG_TAG_MASK, x) 324 #define VLAN_ATTR_MASK GENMASK(7, 6) 325 #define VLAN_ATTR(x) FIELD_PREP(VLAN_ATTR_MASK, x) 326 #define ACC_FRM_MASK GENMASK(1, 0) 327 328 enum mt7530_vlan_port_eg_tag { 329 MT7530_VLAN_EG_DISABLED = 0, 330 MT7530_VLAN_EG_CONSISTENT = 1, 331 MT7530_VLAN_EG_UNTAGGED = 4, 332 }; 333 334 enum mt7530_vlan_port_attr { 335 MT7530_VLAN_USER = 0, 336 MT7530_VLAN_TRANSPARENT = 3, 337 }; 338 339 enum mt7530_vlan_port_acc_frm { 340 MT7530_VLAN_ACC_ALL = 0, 341 MT7530_VLAN_ACC_TAGGED = 1, 342 MT7530_VLAN_ACC_UNTAGGED = 2, 343 }; 344 345 #define STAG_VPID_MASK GENMASK(31, 16) 346 #define STAG_VPID(x) FIELD_PREP(STAG_VPID_MASK, x) 347 348 /* Register for port port-and-protocol based vlan 1 control */ 349 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 350 #define G0_PORT_VID_MASK GENMASK(11, 0) 351 #define G0_PORT_VID(x) FIELD_PREP(G0_PORT_VID_MASK, x) 352 #define G0_PORT_VID_DEF G0_PORT_VID(0) 353 354 /* Register for port MAC control register */ 355 #define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100)) 356 #define PMCR_IFG_XMIT_MASK GENMASK(19, 18) 357 #define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x) 358 #define PMCR_EXT_PHY BIT(17) 359 #define PMCR_MAC_MODE BIT(16) 360 #define MT7530_FORCE_MODE BIT(15) 361 #define PMCR_MAC_TX_EN BIT(14) 362 #define PMCR_MAC_RX_EN BIT(13) 363 #define PMCR_BACKOFF_EN BIT(9) 364 #define PMCR_BACKPR_EN BIT(8) 365 #define PMCR_FORCE_EEE1G BIT(7) 366 #define PMCR_FORCE_EEE100 BIT(6) 367 #define PMCR_FORCE_RX_FC_EN BIT(5) 368 #define PMCR_FORCE_TX_FC_EN BIT(4) 369 #define PMCR_FORCE_SPEED_1000 BIT(3) 370 #define PMCR_FORCE_SPEED_100 BIT(2) 371 #define PMCR_FORCE_FDX BIT(1) 372 #define PMCR_FORCE_LNK BIT(0) 373 #define MT7531_FORCE_MODE_LNK BIT(31) 374 #define MT7531_FORCE_MODE_SPD BIT(30) 375 #define MT7531_FORCE_MODE_DPX BIT(29) 376 #define MT7531_FORCE_MODE_RX_FC BIT(28) 377 #define MT7531_FORCE_MODE_TX_FC BIT(27) 378 #define MT7531_FORCE_MODE_EEE100 BIT(26) 379 #define MT7531_FORCE_MODE_EEE1G BIT(25) 380 #define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \ 381 MT7531_FORCE_MODE_SPD | \ 382 MT7531_FORCE_MODE_DPX | \ 383 MT7531_FORCE_MODE_RX_FC | \ 384 MT7531_FORCE_MODE_TX_FC | \ 385 MT7531_FORCE_MODE_EEE100 | \ 386 MT7531_FORCE_MODE_EEE1G) 387 #define MT753X_FORCE_MODE(id) ((id == ID_MT7531 || \ 388 id == ID_MT7988) ? \ 389 MT7531_FORCE_MODE_MASK : \ 390 MT7530_FORCE_MODE) 391 #define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \ 392 PMCR_FORCE_EEE1G | \ 393 PMCR_FORCE_EEE100 | \ 394 PMCR_FORCE_RX_FC_EN | \ 395 PMCR_FORCE_TX_FC_EN | \ 396 PMCR_FORCE_SPEED_1000 | \ 397 PMCR_FORCE_SPEED_100 | \ 398 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 399 400 #define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100) 401 #define WAKEUP_TIME_1000_MASK GENMASK(31, 24) 402 #define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x) 403 #define WAKEUP_TIME_100_MASK GENMASK(23, 16) 404 #define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x) 405 #define LPI_THRESH_MASK GENMASK(15, 4) 406 #define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x) 407 #define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x) 408 #define LPI_MODE_EN BIT(0) 409 410 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 411 #define PMSR_EEE1G BIT(7) 412 #define PMSR_EEE100M BIT(6) 413 #define PMSR_RX_FC BIT(5) 414 #define PMSR_TX_FC BIT(4) 415 #define PMSR_SPEED_1000 BIT(3) 416 #define PMSR_SPEED_100 BIT(2) 417 #define PMSR_SPEED_10 0x00 418 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 419 #define PMSR_DPX BIT(1) 420 #define PMSR_LINK BIT(0) 421 422 /* Register for port debug count */ 423 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 424 #define MT7531_DIS_CLR BIT(31) 425 426 #define MT7530_GMACCR 0x30e0 427 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 428 #define MAX_RX_JUMBO(x) FIELD_PREP(MAX_RX_JUMBO_MASK, x) 429 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 430 #define MAX_RX_PKT_LEN_1522 0x0 431 #define MAX_RX_PKT_LEN_1536 0x1 432 #define MAX_RX_PKT_LEN_1552 0x2 433 #define MAX_RX_PKT_LEN_JUMBO 0x3 434 435 /* Register for MIB */ 436 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 437 /* Each define is an offset of MT7530_PORT_MIB_COUNTER */ 438 #define MT7530_PORT_MIB_TX_DROP 0x00 439 #define MT7530_PORT_MIB_TX_CRC_ERR 0x04 440 #define MT7530_PORT_MIB_TX_UNICAST 0x08 441 #define MT7530_PORT_MIB_TX_MULTICAST 0x0c 442 #define MT7530_PORT_MIB_TX_BROADCAST 0x10 443 #define MT7530_PORT_MIB_TX_COLLISION 0x14 444 #define MT7530_PORT_MIB_TX_SINGLE_COLLISION 0x18 445 #define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c 446 #define MT7530_PORT_MIB_TX_DEFERRED 0x20 447 #define MT7530_PORT_MIB_TX_LATE_COLLISION 0x24 448 #define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28 449 #define MT7530_PORT_MIB_TX_PAUSE 0x2c 450 #define MT7530_PORT_MIB_TX_PKT_SZ_64 0x30 451 #define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34 452 #define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38 453 #define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3c 454 #define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40 455 #define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX 0x44 456 #define MT7530_PORT_MIB_TX_BYTES 0x48 /* 64 bytes */ 457 #define MT7530_PORT_MIB_RX_DROP 0x60 458 #define MT7530_PORT_MIB_RX_FILTERING 0x64 459 #define MT7530_PORT_MIB_RX_UNICAST 0x68 460 #define MT7530_PORT_MIB_RX_MULTICAST 0x6c 461 #define MT7530_PORT_MIB_RX_BROADCAST 0x70 462 #define MT7530_PORT_MIB_RX_ALIGN_ERR 0x74 463 #define MT7530_PORT_MIB_RX_CRC_ERR 0x78 464 #define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR 0x7c 465 #define MT7530_PORT_MIB_RX_FRAG_ERR 0x80 466 #define MT7530_PORT_MIB_RX_OVER_SZ_ERR 0x84 467 #define MT7530_PORT_MIB_RX_JABBER_ERR 0x88 468 #define MT7530_PORT_MIB_RX_PAUSE 0x8c 469 #define MT7530_PORT_MIB_RX_PKT_SZ_64 0x90 470 #define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 0x94 471 #define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 0x98 472 #define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 0x9c 473 #define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xa0 474 #define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX 0xa4 475 #define MT7530_PORT_MIB_RX_BYTES 0xa8 /* 64 bytes */ 476 #define MT7530_PORT_MIB_RX_CTRL_DROP 0xb0 477 #define MT7530_PORT_MIB_RX_INGRESS_DROP 0xb4 478 #define MT7530_PORT_MIB_RX_ARL_DROP 0xb8 479 #define MT7530_MIB_CCR 0x4fe0 480 #define CCR_MIB_ENABLE BIT(31) 481 #define CCR_RX_OCT_CNT_GOOD BIT(7) 482 #define CCR_RX_OCT_CNT_BAD BIT(6) 483 #define CCR_TX_OCT_CNT_GOOD BIT(5) 484 #define CCR_TX_OCT_CNT_BAD BIT(4) 485 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 486 CCR_RX_OCT_CNT_BAD | \ 487 CCR_TX_OCT_CNT_GOOD | \ 488 CCR_TX_OCT_CNT_BAD) 489 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 490 CCR_RX_OCT_CNT_GOOD | \ 491 CCR_RX_OCT_CNT_BAD | \ 492 CCR_TX_OCT_CNT_GOOD | \ 493 CCR_TX_OCT_CNT_BAD) 494 495 /* MT7531 SGMII register group */ 496 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000) 497 #define MT7531_PHYA_CTRL_SIGNAL3 0x128 498 499 /* Register for system reset */ 500 #define MT7530_SYS_CTRL 0x7000 501 #define SYS_CTRL_PHY_RST BIT(2) 502 #define SYS_CTRL_SW_RST BIT(1) 503 #define SYS_CTRL_REG_RST BIT(0) 504 505 /* Register for system interrupt */ 506 #define MT7530_SYS_INT_EN 0x7008 507 508 /* Register for system interrupt status */ 509 #define MT7530_SYS_INT_STS 0x700c 510 511 /* Register for PHY Indirect Access Control */ 512 #define MT7531_PHY_IAC 0x701C 513 #define MT7531_PHY_ACS_ST BIT(31) 514 #define MT7531_MDIO_REG_ADDR_MASK GENMASK(29, 25) 515 #define MT7531_MDIO_PHY_ADDR_MASK GENMASK(24, 20) 516 #define MT7531_MDIO_CMD_MASK GENMASK(19, 18) 517 #define MT7531_MDIO_ST_MASK GENMASK(17, 16) 518 #define MT7531_MDIO_RW_DATA_MASK GENMASK(15, 0) 519 #define MT7531_MDIO_REG_ADDR(x) FIELD_PREP(MT7531_MDIO_REG_ADDR_MASK, x) 520 #define MT7531_MDIO_DEV_ADDR(x) FIELD_PREP(MT7531_MDIO_REG_ADDR_MASK, x) 521 #define MT7531_MDIO_PHY_ADDR(x) FIELD_PREP(MT7531_MDIO_PHY_ADDR_MASK, x) 522 #define MT7531_MDIO_CMD(x) FIELD_PREP(MT7531_MDIO_CMD_MASK, x) 523 #define MT7531_MDIO_ST(x) FIELD_PREP(MT7531_MDIO_ST_MASK, x) 524 525 enum mt7531_phy_iac_cmd { 526 MT7531_MDIO_ADDR = 0, 527 MT7531_MDIO_WRITE = 1, 528 MT7531_MDIO_READ = 2, 529 MT7531_MDIO_READ_CL45 = 3, 530 }; 531 532 /* MDIO_ST: MDIO start field */ 533 enum mt7531_mdio_st { 534 MT7531_MDIO_ST_CL45 = 0, 535 MT7531_MDIO_ST_CL22 = 1, 536 }; 537 538 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 539 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 540 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 541 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 542 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 543 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 544 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 545 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 546 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 547 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 548 549 /* Register for RGMII clock phase */ 550 #define MT7531_CLKGEN_CTRL 0x7500 551 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 552 #define CLK_SKEW_OUT(x) FIELD_PREP(CLK_SKEW_OUT_MASK, x) 553 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 554 #define CLK_SKEW_IN(x) FIELD_PREP(CLK_SKEW_IN_MASK, x) 555 #define RXCLK_NO_DELAY BIT(5) 556 #define TXCLK_NO_REVERSE BIT(4) 557 #define GP_MODE_MASK GENMASK(2, 1) 558 #define GP_MODE(x) FIELD_PREP(GP_MODE_MASK, x) 559 #define GP_CLK_EN BIT(0) 560 561 enum mt7531_gp_mode { 562 MT7531_GP_MODE_RGMII = 0, 563 MT7531_GP_MODE_MII = 1, 564 MT7531_GP_MODE_REV_MII = 2 565 }; 566 567 enum mt7531_clk_skew { 568 MT7531_CLK_SKEW_NO_CHG = 0, 569 MT7531_CLK_SKEW_DLY_100PPS = 1, 570 MT7531_CLK_SKEW_DLY_200PPS = 2, 571 MT7531_CLK_SKEW_REVERSE = 3, 572 }; 573 574 /* Register for trap status */ 575 #define MT753X_TRAP 0x7800 576 #define MT7530_XTAL_MASK (BIT(10) | BIT(9)) 577 #define MT7530_XTAL_25MHZ (BIT(10) | BIT(9)) 578 #define MT7530_XTAL_40MHZ BIT(10) 579 #define MT7530_XTAL_20MHZ BIT(9) 580 #define MT7531_XTAL25 BIT(7) 581 582 /* Register for trap modification */ 583 #define MT753X_MTRAP 0x7804 584 #define MT7530_P5_PHY0_SEL BIT(20) 585 #define MT7530_CHG_TRAP BIT(16) 586 #define MT7530_P5_MAC_SEL BIT(13) 587 #define MT7530_P6_DIS BIT(8) 588 #define MT7530_P5_RGMII_MODE BIT(7) 589 #define MT7530_P5_DIS BIT(6) 590 #define MT7530_PHY_INDIRECT_ACCESS BIT(5) 591 #define MT7531_CHG_STRAP BIT(8) 592 #define MT7531_PHY_EN BIT(6) 593 594 enum mt7531_xtal_fsel { 595 MT7531_XTAL_FSEL_25MHZ, 596 MT7531_XTAL_FSEL_40MHZ, 597 }; 598 599 /* Register for TOP signal control */ 600 #define MT7530_TOP_SIG_CTRL 0x7808 601 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 602 603 #define MT7531_TOP_SIG_SR 0x780c 604 #define PAD_DUAL_SGMII_EN BIT(1) 605 #define PAD_MCM_SMI_EN BIT(0) 606 607 #define MT7530_IO_DRV_CR 0x7810 608 #define P5_IO_CLK_DRV_MASK GENMASK(1, 0) 609 #define P5_IO_CLK_DRV(x) FIELD_PREP(P5_IO_CLK_DRV_MASK, x) 610 #define P5_IO_DATA_DRV_MASK GENMASK(5, 4) 611 #define P5_IO_DATA_DRV(x) FIELD_PREP(P5_IO_DATA_DRV_MASK, x) 612 613 #define MT7531_CHIP_REV 0x781C 614 615 #define MT7531_PLLGP_EN 0x7820 616 #define EN_COREPLL BIT(2) 617 #define SW_CLKSW BIT(1) 618 #define SW_PLLGP BIT(0) 619 620 #define MT7530_P6ECR 0x7830 621 #define P6_INTF_MODE_MASK GENMASK(1, 0) 622 #define P6_INTF_MODE(x) FIELD_PREP(P6_INTF_MODE_MASK, x) 623 624 #define MT7531_PLLGP_CR0 0x78a8 625 #define RG_COREPLL_EN BIT(22) 626 #define RG_COREPLL_POSDIV_MASK GENMASK(25, 23) 627 #define RG_COREPLL_POSDIV(x) FIELD_PREP(RG_COREPLL_POSDIV_MASK, x) 628 #define RG_COREPLL_SDM_PCW_MASK GENMASK(21, 1) 629 #define RG_COREPLL_SDM_PCW(x) FIELD_PREP(RG_COREPLL_SDM_PCW_MASK, x) 630 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 631 632 /* Registers for RGMII and SGMII PLL clock */ 633 #define MT7531_ANA_PLLGP_CR2 0x78b0 634 #define MT7531_ANA_PLLGP_CR5 0x78bc 635 636 /* Registers for TRGMII on the both side */ 637 #define MT7530_TRGMII_RCK_CTRL 0x7a00 638 #define RX_RST BIT(31) 639 #define RXC_DQSISEL BIT(30) 640 #define DQSI1_TAP_MASK GENMASK(14, 8) 641 #define DQSI0_TAP_MASK GENMASK(6, 0) 642 #define DQSI1_TAP(x) FIELD_PREP(DQSI1_TAP_MASK, x) 643 #define DQSI0_TAP(x) FIELD_PREP(DQSI0_TAP_MASK, x) 644 645 #define MT7530_TRGMII_RCK_RTT 0x7a04 646 #define DQS1_GATE BIT(31) 647 #define DQS0_GATE BIT(30) 648 649 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 650 #define BSLIP_EN BIT(31) 651 #define EDGE_CHK BIT(30) 652 #define RD_TAP_MASK GENMASK(6, 0) 653 #define RD_TAP(x) FIELD_PREP(RD_TAP_MASK, x) 654 655 #define MT7530_TRGMII_TXCTRL 0x7a40 656 #define TRAIN_TXEN BIT(31) 657 #define TXC_INV BIT(30) 658 #define TX_RST BIT(28) 659 660 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 661 #define TD_DM_DRVP_MASK GENMASK(3, 0) 662 #define TD_DM_DRVP(x) FIELD_PREP(TD_DM_DRVP_MASK, x) 663 #define TD_DM_DRVN_MASK GENMASK(7, 4) 664 #define TD_DM_DRVN(x) FIELD_PREP(TD_DM_DRVN_MASK, x) 665 666 #define MT7530_TRGMII_TCK_CTRL 0x7a78 667 #define TCK_TAP_MASK GENMASK(11, 8) 668 #define TCK_TAP(x) FIELD_PREP(TCK_TAP_MASK, x) 669 670 #define MT7530_P5RGMIIRXCR 0x7b00 671 #define CSR_RGMII_EDGE_ALIGN BIT(8) 672 #define CSR_RGMII_RXC_0DEG_CFG_MASK GENMASK(3, 0) 673 #define CSR_RGMII_RXC_0DEG_CFG(x) FIELD_PREP(CSR_RGMII_RXC_0DEG_CFG_MASK, x) 674 675 #define MT7530_P5RGMIITXCR 0x7b04 676 #define CSR_RGMII_TXC_CFG_MASK GENMASK(4, 0) 677 #define CSR_RGMII_TXC_CFG(x) FIELD_PREP(CSR_RGMII_TXC_CFG_MASK, x) 678 679 /* Registers for GPIO mode */ 680 #define MT7531_GPIO_MODE0 0x7c0c 681 #define MT7531_GPIO0_MASK GENMASK(3, 0) 682 #define MT7531_GPIO0_INTERRUPT 1 683 684 #define MT7531_GPIO_MODE1 0x7c10 685 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 686 #define MT7531_EXT_P_MDC_11 FIELD_PREP(MT7531_GPIO11_RG_RXD2_MASK, 2) 687 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 688 #define MT7531_EXT_P_MDIO_12 FIELD_PREP(MT7531_GPIO12_RG_RXD3_MASK, 2) 689 690 #define MT753X_CPORT_SPTAG_CFG 0x7c10 691 #define CPORT_SW2FE_STAG_EN BIT(1) 692 #define CPORT_FE2SW_STAG_EN BIT(0) 693 694 #define AN7583_GEPHY_CONN_CFG 0x7c14 695 #define AN7583_CSR_DPHY_CKIN_SEL BIT(31) 696 #define AN7583_CSR_PHY_CORE_REG_CLK_SEL BIT(30) 697 #define AN7583_CSR_ETHER_AFE_PWD GENMASK(28, 24) 698 699 /* Registers for LED GPIO control (MT7530 only) 700 * All registers follow this pattern: 701 * [ 2: 0] port 0 702 * [ 6: 4] port 1 703 * [10: 8] port 2 704 * [14:12] port 3 705 * [18:16] port 4 706 */ 707 708 /* LED enable, 0: Disable, 1: Enable (Default) */ 709 #define MT7530_LED_EN 0x7d00 710 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 711 #define MT7530_LED_IO_MODE 0x7d04 712 /* GPIO direction, 0: Input, 1: Output */ 713 #define MT7530_LED_GPIO_DIR 0x7d10 714 /* GPIO output enable, 0: Disable, 1: Enable */ 715 #define MT7530_LED_GPIO_OE 0x7d14 716 /* GPIO value, 0: Low, 1: High */ 717 #define MT7530_LED_GPIO_DATA 0x7d18 718 719 #define MT7530_CREV 0x7ffc 720 #define CHIP_NAME_MASK GENMASK(31, 16) 721 #define MT7530_ID 0x7530 722 723 #define MT7531_CREV 0x781C 724 #define CHIP_REV_M 0x0f 725 #define MT7531_ID 0x7531 726 727 /* Registers for core PLL access through mmd indirect */ 728 #define CORE_PLL_GROUP2 0x401 729 #define RG_SYSPLL_EN_NORMAL BIT(15) 730 #define RG_SYSPLL_VODEN BIT(14) 731 #define RG_SYSPLL_LF BIT(13) 732 #define RG_SYSPLL_RST_DLY_MASK GENMASK(13, 12) 733 #define RG_SYSPLL_RST_DLY(x) FIELD_PREP(RG_SYSPLL_RST_DLY_MASK, x) 734 #define RG_SYSPLL_LVROD_EN BIT(10) 735 #define RG_SYSPLL_PREDIV_MASK GENMASK(9, 8) 736 #define RG_SYSPLL_PREDIV(x) FIELD_PREP(RG_SYSPLL_PREDIV_MASK, x) 737 #define RG_SYSPLL_POSDIV_MASK GENMASK(6, 5) 738 #define RG_SYSPLL_POSDIV(x) FIELD_PREP(RG_SYSPLL_POSDIV_MASK, x) 739 #define RG_SYSPLL_FBKSEL BIT(4) 740 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 741 742 #define CORE_PLL_GROUP4 0x403 743 #define RG_SYSPLL_DDSFBK_EN BIT(12) 744 #define RG_SYSPLL_BIAS_EN BIT(11) 745 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 746 #define MT7531_RG_SYSPLL_DMY2 BIT(6) 747 #define MT7531_PHY_PLL_OFF BIT(5) 748 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 749 750 #define MT753X_CTRL_PHY_ADDR(addr) (((addr) + 1) & (PHY_MAX_ADDR - 1)) 751 752 #define CORE_PLL_GROUP5 0x404 753 #define RG_LCDDS_PCW_NCPO1_MASK GENMASK(15, 0) 754 #define RG_LCDDS_PCW_NCPO1(x) FIELD_PREP(RG_LCDDS_PCW_NCPO1_MASK, x) 755 756 #define CORE_PLL_GROUP6 0x405 757 #define RG_LCDDS_PCW_NCPO0_MASK GENMASK(15, 0) 758 #define RG_LCDDS_PCW_NCPO0(x) FIELD_PREP(RG_LCDDS_PCW_NCPO0_MASK, x) 759 760 #define CORE_PLL_GROUP7 0x406 761 #define RG_LCDDS_PWDB BIT(15) 762 #define RG_LCDDS_ISO_EN BIT(13) 763 #define RG_LCCDS_C_MASK GENMASK(6, 4) 764 #define RG_LCCDS_C(x) FIELD_PREP(RG_LCCDS_C_MASK, x) 765 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 766 767 #define CORE_PLL_GROUP10 0x409 768 #define RG_LCDDS_SSC_DELTA_MASK GENMASK(11, 0) 769 #define RG_LCDDS_SSC_DELTA(x) FIELD_PREP(RG_LCDDS_SSC_DELTA_MASK, x) 770 771 #define CORE_PLL_GROUP11 0x40a 772 #define RG_LCDDS_SSC_DELTA1_MASK GENMASK(11, 0) 773 #define RG_LCDDS_SSC_DELTA1(x) FIELD_PREP(RG_LCDDS_SSC_DELTA1_MASK, x) 774 775 #define CORE_GSWPLL_GRP1 0x40d 776 #define RG_GSWPLL_PREDIV_MASK GENMASK(15, 14) 777 #define RG_GSWPLL_PREDIV(x) FIELD_PREP(RG_GSWPLL_PREDIV_MASK, x) 778 #define RG_GSWPLL_POSDIV_200M_MASK GENMASK(13, 12) 779 #define RG_GSWPLL_POSDIV_200M(x) FIELD_PREP(RG_GSWPLL_POSDIV_200M_MASK, x) 780 #define RG_GSWPLL_EN_PRE BIT(11) 781 #define RG_GSWPLL_FBKSEL BIT(10) 782 #define RG_GSWPLL_BP BIT(9) 783 #define RG_GSWPLL_BR BIT(8) 784 #define RG_GSWPLL_FBKDIV_200M_MASK GENMASK(7, 0) 785 #define RG_GSWPLL_FBKDIV_200M(x) FIELD_PREP(RG_GSWPLL_FBKDIV_200M_MASK, x) 786 787 #define CORE_GSWPLL_GRP2 0x40e 788 #define RG_GSWPLL_POSDIV_500M_MASK GENMASK(9, 8) 789 #define RG_GSWPLL_POSDIV_500M(x) FIELD_PREP(RG_GSWPLL_POSDIV_500M_MASK, x) 790 #define RG_GSWPLL_FBKDIV_500M_MASK GENMASK(7, 0) 791 #define RG_GSWPLL_FBKDIV_500M(x) FIELD_PREP(RG_GSWPLL_FBKDIV_500M_MASK, x) 792 793 #define CORE_TRGMII_GSW_CLK_CG 0x410 794 #define REG_GSWCK_EN BIT(0) 795 #define REG_TRGMIICK_EN BIT(1) 796 797 #define MIB_DESC(_s, _o, _n) \ 798 { \ 799 .size = (_s), \ 800 .offset = (_o), \ 801 .name = (_n), \ 802 } 803 804 struct mt7530_mib_desc { 805 unsigned int size; 806 unsigned int offset; 807 const char *name; 808 }; 809 810 struct mt7530_fdb { 811 u16 vid; 812 u8 port_mask; 813 u8 aging; 814 u8 mac[6]; 815 bool noarp; 816 }; 817 818 /* struct mt7530_port - This is the main data structure for holding the state 819 * of the port. 820 * @enable: The status used for show port is enabled or not. 821 * @pm: The matrix used to show all connections with the port. 822 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 823 * untagged frames will be assigned to the related VLAN. 824 * @sgmii_pcs: Pointer to PCS instance for SerDes ports 825 * @stats: Cached port statistics for MDIO-connected switches 826 */ 827 struct mt7530_port { 828 bool enable; 829 bool isolated; 830 u32 pm; 831 u16 pvid; 832 struct phylink_pcs *sgmii_pcs; 833 struct rtnl_link_stats64 stats; 834 }; 835 836 /* Port 5 mode definitions of the MT7530 switch */ 837 enum mt7530_p5_mode { 838 GMAC5, 839 MUX_PHY_P0, 840 MUX_PHY_P4, 841 }; 842 843 struct mt7530_priv; 844 845 struct mt753x_pcs { 846 struct phylink_pcs pcs; 847 struct mt7530_priv *priv; 848 int port; 849 }; 850 851 /* struct mt753x_info - This is the main data structure for holding the specific 852 * part for each supported device 853 * @id: Holding the identifier to a switch model 854 * @pcs_ops: Holding the pointer to the MAC PCS operations structure 855 * @sw_setup: Holding the handler to a device initialization 856 * @phy_read_c22: Holding the way reading PHY port using C22 857 * @phy_write_c22: Holding the way writing PHY port using C22 858 * @phy_read_c45: Holding the way reading PHY port using C45 859 * @phy_write_c45: Holding the way writing PHY port using C45 860 * @mac_port_get_caps: Holding the handler that provides MAC capabilities 861 * @mac_port_config: Holding the way setting up the PHY attribute to a 862 * certain MAC port 863 */ 864 struct mt753x_info { 865 enum mt753x_id id; 866 867 const struct phylink_pcs_ops *pcs_ops; 868 869 int (*sw_setup)(struct dsa_switch *ds); 870 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); 871 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, 872 u16 val); 873 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, 874 int regnum); 875 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, 876 int regnum, u16 val); 877 void (*mac_port_get_caps)(struct dsa_switch *ds, int port, 878 struct phylink_config *config); 879 void (*mac_port_config)(struct dsa_switch *ds, int port, 880 unsigned int mode, 881 phy_interface_t interface); 882 }; 883 884 /* struct mt7530_priv - This is the main data structure for holding the state 885 * of the driver 886 * @dev: The device pointer 887 * @ds: The pointer to the dsa core structure 888 * @bus: The bus used for the device and built-in PHY 889 * @regmap: The regmap instance representing all switch registers 890 * @rstc: The pointer to reset control used by MCM 891 * @core_pwr: The power supplied into the core 892 * @io_pwr: The power supplied into the I/O 893 * @reset: The descriptor for GPIO line tied to its reset pin 894 * @mcm: Flag for distinguishing if standalone IC or module 895 * coupling 896 * @ports: Holding the state among ports 897 * @reg_mutex: The lock for protecting among process accessing 898 * registers 899 * @p5_mode: Holding the current mode of port 5 of the MT7530 switch 900 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch 901 * has got SGMII 902 * @irq_domain: IRQ domain of the switch irq_chip 903 * @create_sgmii: Pointer to function creating SGMII PCS instance(s) 904 * @active_cpu_ports: Holding the active CPU ports 905 * @mdiodev: The pointer to the MDIO device structure 906 * @stats_lock: Protects cached per-port stats from concurrent access 907 * @stats_work: Delayed work for polling MIB counters on MDIO switches 908 * @stats_last: Jiffies timestamp of last MIB counter poll 909 */ 910 struct mt7530_priv { 911 struct device *dev; 912 struct dsa_switch *ds; 913 struct mii_bus *bus; 914 struct regmap *regmap; 915 struct reset_control *rstc; 916 struct regulator *core_pwr; 917 struct regulator *io_pwr; 918 struct gpio_desc *reset; 919 const struct mt753x_info *info; 920 unsigned int id; 921 bool mcm; 922 enum mt7530_p5_mode p5_mode; 923 bool p5_sgmii; 924 u8 mirror_rx; 925 u8 mirror_tx; 926 struct mt7530_port ports[MT7530_NUM_PORTS]; 927 struct mt753x_pcs pcs[MT7530_NUM_PORTS]; 928 /* protect among processes for registers access*/ 929 struct mutex reg_mutex; 930 struct irq_domain *irq_domain; 931 int (*create_sgmii)(struct mt7530_priv *priv); 932 u8 active_cpu_ports; 933 struct mdio_device *mdiodev; 934 spinlock_t stats_lock; /* protects cached stats counters */ 935 struct delayed_work stats_work; 936 unsigned long stats_last; 937 }; 938 939 struct mt7530_hw_vlan_entry { 940 int port; 941 u8 old_members; 942 bool untagged; 943 }; 944 945 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 946 int port, bool untagged) 947 { 948 e->port = port; 949 e->untagged = untagged; 950 } 951 952 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 953 struct mt7530_hw_vlan_entry *); 954 955 struct mt7530_hw_stats { 956 const char *string; 957 u16 reg; 958 u8 sizeof_stat; 959 }; 960 961 int mt7530_probe_common(struct mt7530_priv *priv); 962 void mt7530_remove_common(struct mt7530_priv *priv); 963 964 extern const struct mt753x_info mt753x_table[]; 965 966 #endif /* __MT7530_H */ 967