1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020 Intel Corporation. */
3
4 #ifndef __CXL_CORE_H__
5 #define __CXL_CORE_H__
6
7 #include <cxl/mailbox.h>
8 #include <linux/rwsem.h>
9
10 extern const struct device_type cxl_nvdimm_bridge_type;
11 extern const struct device_type cxl_nvdimm_type;
12 extern const struct device_type cxl_pmu_type;
13
14 extern struct attribute_group cxl_base_attribute_group;
15
16 enum cxl_detach_mode {
17 DETACH_ONLY,
18 DETACH_INVALIDATE,
19 };
20
21 #ifdef CONFIG_CXL_REGION
22
23 struct cxl_region_context {
24 struct cxl_endpoint_decoder *cxled;
25 struct range hpa_range;
26 int interleave_ways;
27 int interleave_granularity;
28 };
29
30 extern struct device_attribute dev_attr_create_pmem_region;
31 extern struct device_attribute dev_attr_create_ram_region;
32 extern struct device_attribute dev_attr_delete_region;
33 extern struct device_attribute dev_attr_region;
34 extern const struct device_type cxl_pmem_region_type;
35 extern const struct device_type cxl_dax_region_type;
36 extern const struct device_type cxl_region_type;
37
38 int cxl_decoder_detach(struct cxl_region *cxlr,
39 struct cxl_endpoint_decoder *cxled, int pos,
40 enum cxl_detach_mode mode);
41
42 #define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
43 #define CXL_REGION_TYPE(x) (&cxl_region_type)
44 #define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
45 #define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
46 #define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type)
47 int cxl_region_init(void);
48 void cxl_region_exit(void);
49 int cxl_get_poison_by_endpoint(struct cxl_port *port);
50 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa);
51 u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
52 u64 dpa);
53 int devm_cxl_add_dax_region(struct cxl_region *cxlr);
54 int devm_cxl_add_pmem_region(struct cxl_region *cxlr);
55 void kill_regions(struct cxl_root_decoder *cxlrd);
56
57 #else
cxl_dpa_to_hpa(struct cxl_region * cxlr,const struct cxl_memdev * cxlmd,u64 dpa)58 static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr,
59 const struct cxl_memdev *cxlmd, u64 dpa)
60 {
61 return ULLONG_MAX;
62 }
63 static inline
cxl_dpa_to_region(const struct cxl_memdev * cxlmd,u64 dpa)64 struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa)
65 {
66 return NULL;
67 }
cxl_get_poison_by_endpoint(struct cxl_port * port)68 static inline int cxl_get_poison_by_endpoint(struct cxl_port *port)
69 {
70 return 0;
71 }
cxl_decoder_detach(struct cxl_region * cxlr,struct cxl_endpoint_decoder * cxled,int pos,enum cxl_detach_mode mode)72 static inline int cxl_decoder_detach(struct cxl_region *cxlr,
73 struct cxl_endpoint_decoder *cxled,
74 int pos, enum cxl_detach_mode mode)
75 {
76 return 0;
77 }
cxl_region_init(void)78 static inline int cxl_region_init(void)
79 {
80 return 0;
81 }
cxl_region_exit(void)82 static inline void cxl_region_exit(void)
83 {
84 }
kill_regions(struct cxl_root_decoder * cxlrd)85 static inline void kill_regions(struct cxl_root_decoder *cxlrd) { };
86 #define CXL_REGION_ATTR(x) NULL
87 #define CXL_REGION_TYPE(x) NULL
88 #define SET_CXL_REGION_ATTR(x)
89 #define CXL_PMEM_REGION_TYPE(x) NULL
90 #define CXL_DAX_REGION_TYPE(x) NULL
91 #endif
92
93 struct cxl_send_command;
94 struct cxl_mem_query_commands;
95 int cxl_query_cmd(struct cxl_mailbox *cxl_mbox,
96 struct cxl_mem_query_commands __user *q);
97 int cxl_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_send_command __user *s);
98 void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
99 resource_size_t length);
100
101 struct dentry *cxl_debugfs_create_dir(const char *dir);
102 int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled,
103 enum cxl_partition_mode mode);
104 struct cxl_memdev_state;
105 int cxl_mem_get_partition_info(struct cxl_memdev_state *mds);
106 int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size);
107 int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
108 resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
109 resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled);
110 bool cxl_resource_contains_addr(const struct resource *res, const resource_size_t addr);
111
112 enum cxl_rcrb {
113 CXL_RCRB_DOWNSTREAM,
114 CXL_RCRB_UPSTREAM,
115 };
116 struct cxl_rcrb_info;
117 resource_size_t __rcrb_to_component(struct device *dev,
118 struct cxl_rcrb_info *ri,
119 enum cxl_rcrb which);
120 u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
121
122 #define PCI_RCRB_CAP_LIST_ID_MASK GENMASK(7, 0)
123 #define PCI_RCRB_CAP_HDR_ID_MASK GENMASK(7, 0)
124 #define PCI_RCRB_CAP_HDR_NEXT_MASK GENMASK(15, 8)
125 #define PCI_CAP_EXP_SIZEOF 0x3c
126
127 struct cxl_rwsem {
128 /*
129 * All changes to HPA (interleave configuration) occur with this
130 * lock held for write.
131 */
132 struct rw_semaphore region;
133 /*
134 * All changes to a device DPA space occur with this lock held
135 * for write.
136 */
137 struct rw_semaphore dpa;
138 };
139
140 extern struct cxl_rwsem cxl_rwsem;
141
142 int cxl_memdev_init(void);
143 void cxl_memdev_exit(void);
144 void cxl_mbox_init(void);
145
146 enum cxl_poison_trace_type {
147 CXL_POISON_TRACE_LIST,
148 CXL_POISON_TRACE_INJECT,
149 CXL_POISON_TRACE_CLEAR,
150 };
151
152 enum poison_cmd_enabled_bits;
153 bool cxl_memdev_has_poison_cmd(struct cxl_memdev *cxlmd,
154 enum poison_cmd_enabled_bits cmd);
155
156 long cxl_pci_get_latency(struct pci_dev *pdev);
157 int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c);
158 int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
159 struct access_coordinate *c);
160
port_to_host(struct cxl_port * port)161 static inline struct device *port_to_host(struct cxl_port *port)
162 {
163 struct cxl_port *parent = is_cxl_root(port) ? NULL :
164 to_cxl_port(port->dev.parent);
165
166 /*
167 * The host of CXL root port and the first level of ports is
168 * the platform firmware device, the host of all other ports
169 * is their parent port.
170 */
171 if (!parent)
172 return port->uport_dev;
173 else if (is_cxl_root(parent))
174 return parent->uport_dev;
175 else
176 return &parent->dev;
177 }
178
dport_to_host(struct cxl_dport * dport)179 static inline struct device *dport_to_host(struct cxl_dport *dport)
180 {
181 struct cxl_port *port = dport->port;
182
183 if (is_cxl_root(port))
184 return port->uport_dev;
185 return &port->dev;
186 }
187 #ifdef CONFIG_CXL_RAS
188 void cxl_ras_init(void);
189 void cxl_ras_exit(void);
190 bool cxl_handle_ras(struct device *dev, void __iomem *ras_base);
191 void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);
192 void cxl_dport_map_rch_aer(struct cxl_dport *dport);
193 void cxl_disable_rch_root_ints(struct cxl_dport *dport);
194 void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds);
195 void devm_cxl_dport_ras_setup(struct cxl_dport *dport);
196 #else
cxl_ras_init(void)197 static inline void cxl_ras_init(void) { }
cxl_ras_exit(void)198 static inline void cxl_ras_exit(void) { }
cxl_handle_ras(struct device * dev,void __iomem * ras_base)199 static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)
200 {
201 return false;
202 }
cxl_handle_cor_ras(struct device * dev,void __iomem * ras_base)203 static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }
cxl_dport_map_rch_aer(struct cxl_dport * dport)204 static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }
cxl_disable_rch_root_ints(struct cxl_dport * dport)205 static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }
cxl_handle_rdport_errors(struct cxl_dev_state * cxlds)206 static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }
devm_cxl_dport_ras_setup(struct cxl_dport * dport)207 static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { }
208 #endif /* CONFIG_CXL_RAS */
209
210 int cxl_gpf_port_setup(struct cxl_dport *dport);
211
212 struct cxl_hdm;
213 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,
214 struct cxl_endpoint_dvsec_info *info);
215 int cxl_port_get_possible_dports(struct cxl_port *port);
216
217 #ifdef CONFIG_CXL_FEATURES
218 struct cxl_feat_entry *
219 cxl_feature_info(struct cxl_features_state *cxlfs, const uuid_t *uuid);
220 size_t cxl_get_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
221 enum cxl_get_feat_selection selection,
222 void *feat_out, size_t feat_out_size, u16 offset,
223 u16 *return_code);
224 int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
225 u8 feat_version, const void *feat_data,
226 size_t feat_data_size, u32 feat_flag, u16 offset,
227 u16 *return_code);
228 #endif
229
230 resource_size_t cxl_rcd_component_reg_phys(struct device *dev,
231 struct cxl_dport *dport);
232 #endif /* __CXL_CORE_H__ */
233