1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/math.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/tty.h>
18 #include <linux/serial_reg.h>
19 #include <linux/serial_core.h>
20 #include <linux/8250_pci.h>
21 #include <linux/bitops.h>
22 #include <linux/bitfield.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28 #include "8250_pcilib.h"
29
30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
32 #define PCI_DEVICE_ID_OCTPRO 0x0001
33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600
42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611
43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
46 #define PCI_DEVICE_ID_TITAN_200I 0x8028
47 #define PCI_DEVICE_ID_TITAN_400I 0x8048
48 #define PCI_DEVICE_ID_TITAN_800I 0x8088
49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
52 #define PCI_DEVICE_ID_TITAN_100E 0xA010
53 #define PCI_DEVICE_ID_TITAN_200E 0xA012
54 #define PCI_DEVICE_ID_TITAN_400E 0xA013
55 #define PCI_DEVICE_ID_TITAN_800E 0xA014
56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
67 #define PCI_VENDOR_ID_WCH 0x4348
68 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
69 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
70 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
71 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
72 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
73 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
74 #define PCI_VENDOR_ID_AGESTAR 0x5372
75 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
76 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
77 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
78
79 #define PCIE_VENDOR_ID_WCH 0x1c00
80 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
81 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
82 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853
83 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
84
85 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
86 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
87 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027
88 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
89 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046
90 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121
91 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
92 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145
93 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
94 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
95 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
96 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
97 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
98 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323
99 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
100 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343
101 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
102 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
103
104 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
105 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
106 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
107
108 /*
109 * init function returns:
110 * > 0 - number of ports
111 * = 0 - use board->num_ports
112 * < 0 - error
113 */
114 struct pci_serial_quirk {
115 u32 vendor;
116 u32 device;
117 u32 subvendor;
118 u32 subdevice;
119 int (*probe)(struct pci_dev *dev);
120 int (*init)(struct pci_dev *dev);
121 int (*setup)(struct serial_private *,
122 const struct pciserial_board *,
123 struct uart_8250_port *, int);
124 void (*exit)(struct pci_dev *dev);
125 };
126
127 struct f815xxa_data {
128 spinlock_t lock;
129 int idx;
130 };
131
132 struct serial_private {
133 struct pci_dev *dev;
134 unsigned int nr;
135 struct pci_serial_quirk *quirk;
136 const struct pciserial_board *board;
137 int line[];
138 };
139
140 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e
141
142 static const struct pci_device_id pci_use_msi[] = {
143 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
144 0xA000, 0x1000) },
145 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
146 0xA000, 0x1000) },
147 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
148 0xA000, 0x1000) },
149 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
150 0xA000, 0x1000) },
151 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
152 PCI_ANY_ID, PCI_ANY_ID) },
153 { }
154 };
155
156 static int pci_default_setup(struct serial_private*,
157 const struct pciserial_board*, struct uart_8250_port *, int);
158
moan_device(const char * str,struct pci_dev * dev)159 static void moan_device(const char *str, struct pci_dev *dev)
160 {
161 pci_err(dev, "%s\n"
162 "Please send the output of lspci -vv, this\n"
163 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
164 "manufacturer and name of serial board or\n"
165 "modem board to <linux-serial@vger.kernel.org>.\n",
166 str, dev->vendor, dev->device,
167 dev->subsystem_vendor, dev->subsystem_device);
168 }
169
170 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,u8 bar,unsigned int offset,int regshift)171 setup_port(struct serial_private *priv, struct uart_8250_port *port,
172 u8 bar, unsigned int offset, int regshift)
173 {
174 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift);
175 }
176
177 /*
178 * ADDI-DATA GmbH communication cards <info@addi-data.com>
179 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)180 static int addidata_apci7800_setup(struct serial_private *priv,
181 const struct pciserial_board *board,
182 struct uart_8250_port *port, int idx)
183 {
184 unsigned int bar = 0, offset = board->first_offset;
185 bar = FL_GET_BASE(board->flags);
186
187 if (idx < 2) {
188 offset += idx * board->uart_offset;
189 } else if ((idx >= 2) && (idx < 4)) {
190 bar += 1;
191 offset += ((idx - 2) * board->uart_offset);
192 } else if ((idx >= 4) && (idx < 6)) {
193 bar += 2;
194 offset += ((idx - 4) * board->uart_offset);
195 } else if (idx >= 6) {
196 bar += 3;
197 offset += ((idx - 6) * board->uart_offset);
198 }
199
200 return setup_port(priv, port, bar, offset, board->reg_shift);
201 }
202
203 /*
204 * AFAVLAB uses a different mixture of BARs and offsets
205 * Not that ugly ;) -- HW
206 */
207 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)208 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
209 struct uart_8250_port *port, int idx)
210 {
211 unsigned int bar, offset = board->first_offset;
212
213 bar = FL_GET_BASE(board->flags);
214 if (idx < 4)
215 bar += idx;
216 else {
217 bar = 4;
218 offset += (idx - 4) * board->uart_offset;
219 }
220
221 return setup_port(priv, port, bar, offset, board->reg_shift);
222 }
223
224 /*
225 * HP's Remote Management Console. The Diva chip came in several
226 * different versions. N-class, L2000 and A500 have two Diva chips, each
227 * with 3 UARTs (the third UART on the second chip is unused). Superdome
228 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
229 * one Diva chip, but it has been expanded to 5 UARTs.
230 */
pci_hp_diva_init(struct pci_dev * dev)231 static int pci_hp_diva_init(struct pci_dev *dev)
232 {
233 int rc = 0;
234
235 switch (dev->subsystem_device) {
236 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
237 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
238 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
239 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
240 rc = 3;
241 break;
242 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
243 rc = 2;
244 break;
245 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
246 rc = 4;
247 break;
248 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
249 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
250 rc = 1;
251 break;
252 }
253
254 return rc;
255 }
256
257 /*
258 * HP's Diva chip puts the 4th/5th serial port further out, and
259 * some serial ports are supposed to be hidden on certain models.
260 */
261 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)262 pci_hp_diva_setup(struct serial_private *priv,
263 const struct pciserial_board *board,
264 struct uart_8250_port *port, int idx)
265 {
266 unsigned int offset = board->first_offset;
267 unsigned int bar = FL_GET_BASE(board->flags);
268
269 switch (priv->dev->subsystem_device) {
270 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
271 if (idx == 3)
272 idx++;
273 break;
274 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
275 if (idx > 0)
276 idx++;
277 if (idx > 2)
278 idx++;
279 break;
280 }
281 if (idx > 2)
282 offset = 0x18;
283
284 offset += idx * board->uart_offset;
285
286 return setup_port(priv, port, bar, offset, board->reg_shift);
287 }
288
289 /*
290 * Added for EKF Intel i960 serial boards
291 */
pci_inteli960ni_init(struct pci_dev * dev)292 static int pci_inteli960ni_init(struct pci_dev *dev)
293 {
294 u32 oldval;
295
296 if (!(dev->subsystem_device & 0x1000))
297 return -ENODEV;
298
299 /* is firmware started? */
300 pci_read_config_dword(dev, 0x44, &oldval);
301 if (oldval == 0x00001000L) { /* RESET value */
302 pci_dbg(dev, "Local i960 firmware missing\n");
303 return -ENODEV;
304 }
305 return 0;
306 }
307
308 /*
309 * Some PCI serial cards using the PLX 9050 PCI interface chip require
310 * that the card interrupt be explicitly enabled or disabled. This
311 * seems to be mainly needed on card using the PLX which also use I/O
312 * mapped memory.
313 */
pci_plx9050_init(struct pci_dev * dev)314 static int pci_plx9050_init(struct pci_dev *dev)
315 {
316 u8 irq_config;
317 void __iomem *p;
318
319 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar 0", dev);
321 return 0;
322 }
323
324 irq_config = 0x41;
325 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
326 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
327 irq_config = 0x43;
328
329 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
330 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
331 /*
332 * As the megawolf cards have the int pins active
333 * high, and have 2 UART chips, both ints must be
334 * enabled on the 9050. Also, the UARTS are set in
335 * 16450 mode by default, so we have to enable the
336 * 16C950 'enhanced' mode so that we can use the
337 * deep FIFOs
338 */
339 irq_config = 0x5b;
340 /*
341 * enable/disable interrupts
342 */
343 p = ioremap(pci_resource_start(dev, 0), 0x80);
344 if (p == NULL)
345 return -ENOMEM;
346 writel(irq_config, p + 0x4c);
347
348 /*
349 * Read the register back to ensure that it took effect.
350 */
351 readl(p + 0x4c);
352 iounmap(p);
353
354 return 0;
355 }
356
pci_plx9050_exit(struct pci_dev * dev)357 static void pci_plx9050_exit(struct pci_dev *dev)
358 {
359 u8 __iomem *p;
360
361 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
362 return;
363
364 /*
365 * disable interrupts
366 */
367 p = ioremap(pci_resource_start(dev, 0), 0x80);
368 if (p != NULL) {
369 writel(0, p + 0x4c);
370
371 /*
372 * Read the register back to ensure that it took effect.
373 */
374 readl(p + 0x4c);
375 iounmap(p);
376 }
377 }
378
379 #define NI8420_INT_ENABLE_REG 0x38
380 #define NI8420_INT_ENABLE_BIT 0x2000
381
pci_ni8420_exit(struct pci_dev * dev)382 static void pci_ni8420_exit(struct pci_dev *dev)
383 {
384 void __iomem *p;
385 unsigned int bar = 0;
386
387 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
388 moan_device("no memory in bar", dev);
389 return;
390 }
391
392 p = pci_ioremap_bar(dev, bar);
393 if (p == NULL)
394 return;
395
396 /* Disable the CPU Interrupt */
397 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
398 p + NI8420_INT_ENABLE_REG);
399 iounmap(p);
400 }
401
402
403 /* MITE registers */
404 #define MITE_IOWBSR1 0xc4
405 #define MITE_IOWCR1 0xf4
406 #define MITE_LCIMR1 0x08
407 #define MITE_LCIMR2 0x10
408
409 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
410
pci_ni8430_exit(struct pci_dev * dev)411 static void pci_ni8430_exit(struct pci_dev *dev)
412 {
413 void __iomem *p;
414 unsigned int bar = 0;
415
416 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
417 moan_device("no memory in bar", dev);
418 return;
419 }
420
421 p = pci_ioremap_bar(dev, bar);
422 if (p == NULL)
423 return;
424
425 /* Disable the CPU Interrupt */
426 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
427 iounmap(p);
428 }
429
430 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
431 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)432 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
433 struct uart_8250_port *port, int idx)
434 {
435 unsigned int bar, offset = board->first_offset;
436
437 bar = 0;
438
439 if (idx < 4) {
440 /* first four channels map to 0, 0x100, 0x200, 0x300 */
441 offset += idx * board->uart_offset;
442 } else if (idx < 8) {
443 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
444 offset += idx * board->uart_offset + 0xC00;
445 } else /* we have only 8 ports on PMC-OCTALPRO */
446 return 1;
447
448 return setup_port(priv, port, bar, offset, board->reg_shift);
449 }
450
451 /*
452 * This does initialization for PMC OCTALPRO cards:
453 * maps the device memory, resets the UARTs (needed, bc
454 * if the module is removed and inserted again, the card
455 * is in the sleep mode) and enables global interrupt.
456 */
457
458 /* global control register offset for SBS PMC-OctalPro */
459 #define OCT_REG_CR_OFF 0x500
460
sbs_init(struct pci_dev * dev)461 static int sbs_init(struct pci_dev *dev)
462 {
463 u8 __iomem *p;
464
465 p = pci_ioremap_bar(dev, 0);
466
467 if (p == NULL)
468 return -ENOMEM;
469 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
470 writeb(0x10, p + OCT_REG_CR_OFF);
471 udelay(50);
472 writeb(0x0, p + OCT_REG_CR_OFF);
473
474 /* Set bit-2 (INTENABLE) of Control Register */
475 writeb(0x4, p + OCT_REG_CR_OFF);
476 iounmap(p);
477
478 return 0;
479 }
480
481 /*
482 * Disables the global interrupt of PMC-OctalPro
483 */
484
sbs_exit(struct pci_dev * dev)485 static void sbs_exit(struct pci_dev *dev)
486 {
487 u8 __iomem *p;
488
489 p = pci_ioremap_bar(dev, 0);
490 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
491 if (p != NULL)
492 writeb(0, p + OCT_REG_CR_OFF);
493 iounmap(p);
494 }
495
496 /*
497 * SIIG serial cards have an PCI interface chip which also controls
498 * the UART clocking frequency. Each UART can be clocked independently
499 * (except cards equipped with 4 UARTs) and initial clocking settings
500 * are stored in the EEPROM chip. It can cause problems because this
501 * version of serial driver doesn't support differently clocked UART's
502 * on single PCI card. To prevent this, initialization functions set
503 * high frequency clocking for all UART's on given card. It is safe (I
504 * hope) because it doesn't touch EEPROM settings to prevent conflicts
505 * with other OSes (like M$ DOS).
506 *
507 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
508 *
509 * There is two family of SIIG serial cards with different PCI
510 * interface chip and different configuration methods:
511 * - 10x cards have control registers in IO and/or memory space;
512 * - 20x cards have control registers in standard PCI configuration space.
513 *
514 * Note: all 10x cards have PCI device ids 0x10..
515 * all 20x cards have PCI device ids 0x20..
516 *
517 * There are also Quartet Serial cards which use Oxford Semiconductor
518 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
519 *
520 * Note: some SIIG cards are probed by the parport_serial object.
521 */
522
523 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
524 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
525
pci_siig10x_init(struct pci_dev * dev)526 static int pci_siig10x_init(struct pci_dev *dev)
527 {
528 u16 data;
529 void __iomem *p;
530
531 switch (dev->device & 0xfff8) {
532 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
533 data = 0xffdf;
534 break;
535 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
536 data = 0xf7ff;
537 break;
538 default: /* 1S1P, 4S */
539 data = 0xfffb;
540 break;
541 }
542
543 p = ioremap(pci_resource_start(dev, 0), 0x80);
544 if (p == NULL)
545 return -ENOMEM;
546
547 writew(readw(p + 0x28) & data, p + 0x28);
548 readw(p + 0x28);
549 iounmap(p);
550 return 0;
551 }
552
553 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
554 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
555
pci_siig20x_init(struct pci_dev * dev)556 static int pci_siig20x_init(struct pci_dev *dev)
557 {
558 u8 data;
559
560 /* Change clock frequency for the first UART. */
561 pci_read_config_byte(dev, 0x6f, &data);
562 pci_write_config_byte(dev, 0x6f, data & 0xef);
563
564 /* If this card has 2 UART, we have to do the same with second UART. */
565 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
566 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
567 pci_read_config_byte(dev, 0x73, &data);
568 pci_write_config_byte(dev, 0x73, data & 0xef);
569 }
570 return 0;
571 }
572
pci_siig_init(struct pci_dev * dev)573 static int pci_siig_init(struct pci_dev *dev)
574 {
575 unsigned int type = dev->device & 0xff00;
576
577 if (type == 0x1000)
578 return pci_siig10x_init(dev);
579 if (type == 0x2000)
580 return pci_siig20x_init(dev);
581
582 moan_device("Unknown SIIG card", dev);
583 return -ENODEV;
584 }
585
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)586 static int pci_siig_setup(struct serial_private *priv,
587 const struct pciserial_board *board,
588 struct uart_8250_port *port, int idx)
589 {
590 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
591
592 if (idx > 3) {
593 bar = 4;
594 offset = (idx - 4) * 8;
595 }
596
597 return setup_port(priv, port, bar, offset, 0);
598 }
599
600 /*
601 * Timedia has an explosion of boards, and to avoid the PCI table from
602 * growing *huge*, we use this function to collapse some 70 entries
603 * in the PCI table into one, for sanity's and compactness's sake.
604 */
605 static const unsigned short timedia_single_port[] = {
606 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
607 };
608
609 static const unsigned short timedia_dual_port[] = {
610 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
611 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
612 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
613 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
614 0xD079, 0
615 };
616
617 static const unsigned short timedia_quad_port[] = {
618 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
619 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
620 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
621 0xB157, 0
622 };
623
624 static const unsigned short timedia_eight_port[] = {
625 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
626 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
627 };
628
629 static const struct timedia_struct {
630 int num;
631 const unsigned short *ids;
632 } timedia_data[] = {
633 { 1, timedia_single_port },
634 { 2, timedia_dual_port },
635 { 4, timedia_quad_port },
636 { 8, timedia_eight_port }
637 };
638
639 /*
640 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
641 * listing them individually, this driver merely grabs them all with
642 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
643 * and should be left free to be claimed by parport_serial instead.
644 */
pci_timedia_probe(struct pci_dev * dev)645 static int pci_timedia_probe(struct pci_dev *dev)
646 {
647 /*
648 * Check the third digit of the subdevice ID
649 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
650 */
651 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
652 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n",
653 dev->subsystem_device);
654 return -ENODEV;
655 }
656
657 return 0;
658 }
659
pci_timedia_init(struct pci_dev * dev)660 static int pci_timedia_init(struct pci_dev *dev)
661 {
662 const unsigned short *ids;
663 int i, j;
664
665 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
666 ids = timedia_data[i].ids;
667 for (j = 0; ids[j]; j++)
668 if (dev->subsystem_device == ids[j])
669 return timedia_data[i].num;
670 }
671 return 0;
672 }
673
674 /*
675 * Timedia/SUNIX uses a mixture of BARs and offsets
676 * Ugh, this is ugly as all hell --- TYT
677 */
678 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)679 pci_timedia_setup(struct serial_private *priv,
680 const struct pciserial_board *board,
681 struct uart_8250_port *port, int idx)
682 {
683 unsigned int bar = 0, offset = board->first_offset;
684
685 switch (idx) {
686 case 0:
687 bar = 0;
688 break;
689 case 1:
690 offset = board->uart_offset;
691 bar = 0;
692 break;
693 case 2:
694 bar = 1;
695 break;
696 case 3:
697 offset = board->uart_offset;
698 fallthrough;
699 case 4: /* BAR 2 */
700 case 5: /* BAR 3 */
701 case 6: /* BAR 4 */
702 case 7: /* BAR 5 */
703 bar = idx - 2;
704 }
705
706 return setup_port(priv, port, bar, offset, board->reg_shift);
707 }
708
709 /*
710 * Some Titan cards are also a little weird
711 */
712 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)713 titan_400l_800l_setup(struct serial_private *priv,
714 const struct pciserial_board *board,
715 struct uart_8250_port *port, int idx)
716 {
717 unsigned int bar, offset = board->first_offset;
718
719 switch (idx) {
720 case 0:
721 bar = 1;
722 break;
723 case 1:
724 bar = 2;
725 break;
726 default:
727 bar = 4;
728 offset = (idx - 2) * board->uart_offset;
729 }
730
731 return setup_port(priv, port, bar, offset, board->reg_shift);
732 }
733
pci_xircom_init(struct pci_dev * dev)734 static int pci_xircom_init(struct pci_dev *dev)
735 {
736 msleep(100);
737 return 0;
738 }
739
pci_ni8420_init(struct pci_dev * dev)740 static int pci_ni8420_init(struct pci_dev *dev)
741 {
742 void __iomem *p;
743 unsigned int bar = 0;
744
745 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
746 moan_device("no memory in bar", dev);
747 return 0;
748 }
749
750 p = pci_ioremap_bar(dev, bar);
751 if (p == NULL)
752 return -ENOMEM;
753
754 /* Enable CPU Interrupt */
755 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
756 p + NI8420_INT_ENABLE_REG);
757
758 iounmap(p);
759 return 0;
760 }
761
762 #define MITE_IOWBSR1_WSIZE 0xa
763 #define MITE_IOWBSR1_WIN_OFFSET 0x800
764 #define MITE_IOWBSR1_WENAB (1 << 7)
765 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
766 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
767 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
768
pci_ni8430_init(struct pci_dev * dev)769 static int pci_ni8430_init(struct pci_dev *dev)
770 {
771 void __iomem *p;
772 struct pci_bus_region region;
773 u32 device_window;
774 unsigned int bar = 0;
775
776 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
777 moan_device("no memory in bar", dev);
778 return 0;
779 }
780
781 p = pci_ioremap_bar(dev, bar);
782 if (p == NULL)
783 return -ENOMEM;
784
785 /*
786 * Set device window address and size in BAR0, while acknowledging that
787 * the resource structure may contain a translated address that differs
788 * from the address the device responds to.
789 */
790 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
791 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
792 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
793 writel(device_window, p + MITE_IOWBSR1);
794
795 /* Set window access to go to RAMSEL IO address space */
796 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
797 p + MITE_IOWCR1);
798
799 /* Enable IO Bus Interrupt 0 */
800 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
801
802 /* Enable CPU Interrupt */
803 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
804
805 iounmap(p);
806 return 0;
807 }
808
809 /* UART Port Control Register */
810 #define NI8430_PORTCON 0x0f
811 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
812
813 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)814 pci_ni8430_setup(struct serial_private *priv,
815 const struct pciserial_board *board,
816 struct uart_8250_port *port, int idx)
817 {
818 struct pci_dev *dev = priv->dev;
819 void __iomem *p;
820 unsigned int bar, offset = board->first_offset;
821
822 if (idx >= board->num_ports)
823 return 1;
824
825 bar = FL_GET_BASE(board->flags);
826 offset += idx * board->uart_offset;
827
828 p = pci_ioremap_bar(dev, bar);
829 if (!p)
830 return -ENOMEM;
831
832 /* enable the transceiver */
833 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
834 p + offset + NI8430_PORTCON);
835
836 iounmap(p);
837
838 return setup_port(priv, port, bar, offset, board->reg_shift);
839 }
840
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)841 static int pci_netmos_9900_setup(struct serial_private *priv,
842 const struct pciserial_board *board,
843 struct uart_8250_port *port, int idx)
844 {
845 unsigned int bar;
846
847 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
848 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
849 /* netmos apparently orders BARs by datasheet layout, so serial
850 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
851 */
852 bar = 3 * idx;
853
854 return setup_port(priv, port, bar, 0, board->reg_shift);
855 }
856
857 return pci_default_setup(priv, board, port, idx);
858 }
859
860 /* the 99xx series comes with a range of device IDs and a variety
861 * of capabilities:
862 *
863 * 9900 has varying capabilities and can cascade to sub-controllers
864 * (cascading should be purely internal)
865 * 9904 is hardwired with 4 serial ports
866 * 9912 and 9922 are hardwired with 2 serial ports
867 */
pci_netmos_9900_numports(struct pci_dev * dev)868 static int pci_netmos_9900_numports(struct pci_dev *dev)
869 {
870 unsigned int c = dev->class;
871 unsigned int pi;
872 unsigned short sub_serports;
873
874 pi = c & 0xff;
875
876 if (pi == 2)
877 return 1;
878
879 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
880 /* two possibilities: 0x30ps encodes number of parallel and
881 * serial ports, or 0x1000 indicates *something*. This is not
882 * immediately obvious, since the 2s1p+4s configuration seems
883 * to offer all functionality on functions 0..2, while still
884 * advertising the same function 3 as the 4s+2s1p config.
885 */
886 sub_serports = dev->subsystem_device & 0xf;
887 if (sub_serports > 0)
888 return sub_serports;
889
890 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
891 return 0;
892 }
893
894 moan_device("unknown NetMos/Mostech program interface", dev);
895 return 0;
896 }
897
pci_netmos_init(struct pci_dev * dev)898 static int pci_netmos_init(struct pci_dev *dev)
899 {
900 /* subdevice 0x00PS means <P> parallel, <S> serial */
901 unsigned int num_serial = dev->subsystem_device & 0xf;
902
903 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
904 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
905 return 0;
906
907 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
908 dev->subsystem_device == 0x0299)
909 return 0;
910
911 switch (dev->device) { /* FALLTHROUGH on all */
912 case PCI_DEVICE_ID_NETMOS_9904:
913 case PCI_DEVICE_ID_NETMOS_9912:
914 case PCI_DEVICE_ID_NETMOS_9922:
915 case PCI_DEVICE_ID_NETMOS_9900:
916 num_serial = pci_netmos_9900_numports(dev);
917 break;
918
919 default:
920 break;
921 }
922
923 if (num_serial == 0) {
924 moan_device("unknown NetMos/Mostech device", dev);
925 return -ENODEV;
926 }
927
928 return num_serial;
929 }
930
931 /*
932 * These chips are available with optionally one parallel port and up to
933 * two serial ports. Unfortunately they all have the same product id.
934 *
935 * Basic configuration is done over a region of 32 I/O ports. The base
936 * ioport is called INTA or INTC, depending on docs/other drivers.
937 *
938 * The region of the 32 I/O ports is configured in POSIO0R...
939 */
940
941 /* registers */
942 #define ITE_887x_MISCR 0x9c
943 #define ITE_887x_INTCBAR 0x78
944 #define ITE_887x_UARTBAR 0x7c
945 #define ITE_887x_PS0BAR 0x10
946 #define ITE_887x_POSIO0 0x60
947
948 /* I/O space size */
949 #define ITE_887x_IOSIZE 32
950 /* I/O space size (bits 26-24; 8 bytes = 011b) */
951 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
952 /* I/O space size (bits 26-24; 32 bytes = 101b) */
953 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
954 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
955 #define ITE_887x_POSIO_SPEED (3 << 29)
956 /* enable IO_Space bit */
957 #define ITE_887x_POSIO_ENABLE (1 << 31)
958
959 /* inta_addr are the configuration addresses of the ITE */
960 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 };
pci_ite887x_init(struct pci_dev * dev)961 static int pci_ite887x_init(struct pci_dev *dev)
962 {
963 int ret, i, type;
964 struct resource *iobase = NULL;
965 u32 miscr, uartbar, ioport;
966
967 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
968 return serial_8250_warn_need_ioport(dev);
969
970 /* search for the base-ioport */
971 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) {
972 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
973 "ite887x");
974 if (iobase != NULL) {
975 /* write POSIO0R - speed | size | ioport */
976 pci_write_config_dword(dev, ITE_887x_POSIO0,
977 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
978 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
979 /* write INTCBAR - ioport */
980 pci_write_config_dword(dev, ITE_887x_INTCBAR,
981 inta_addr[i]);
982 ret = inb(inta_addr[i]);
983 if (ret != 0xff) {
984 /* ioport connected */
985 break;
986 }
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989 }
990
991 if (i == ARRAY_SIZE(inta_addr)) {
992 pci_err(dev, "could not find iobase\n");
993 return -ENODEV;
994 }
995
996 /* start of undocumented type checking (see parport_pc.c) */
997 type = inb(iobase->start + 0x18) & 0x0f;
998
999 switch (type) {
1000 case 0x2: /* ITE8871 (1P) */
1001 case 0xa: /* ITE8875 (1P) */
1002 ret = 0;
1003 break;
1004 case 0xe: /* ITE8872 (2S1P) */
1005 ret = 2;
1006 break;
1007 case 0x6: /* ITE8873 (1S) */
1008 ret = 1;
1009 break;
1010 case 0x8: /* ITE8874 (2S) */
1011 ret = 2;
1012 break;
1013 default:
1014 moan_device("Unknown ITE887x", dev);
1015 ret = -ENODEV;
1016 }
1017
1018 /* configure all serial ports */
1019 for (i = 0; i < ret; i++) {
1020 /* read the I/O port from the device */
1021 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1022 &ioport);
1023 ioport &= 0x0000FF00; /* the actual base address */
1024 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1025 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1026 ITE_887x_POSIO_IOSIZE_8 | ioport);
1027
1028 /* write the ioport to the UARTBAR */
1029 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1030 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1031 uartbar |= (ioport << (16 * i)); /* set the ioport */
1032 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1033
1034 /* get current config */
1035 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1036 /* disable interrupts (UARTx_Routing[3:0]) */
1037 miscr &= ~(0xf << (12 - 4 * i));
1038 /* activate the UART (UARTx_En) */
1039 miscr |= 1 << (23 - i);
1040 /* write new config with activated UART */
1041 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1042 }
1043
1044 if (ret <= 0) {
1045 /* the device has no UARTs if we get here */
1046 release_region(iobase->start, ITE_887x_IOSIZE);
1047 }
1048
1049 return ret;
1050 }
1051
pci_ite887x_exit(struct pci_dev * dev)1052 static void pci_ite887x_exit(struct pci_dev *dev)
1053 {
1054 u32 ioport;
1055 /* the ioport is bit 0-15 in POSIO0R */
1056 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1057 ioport &= 0xffff;
1058 release_region(ioport, ITE_887x_IOSIZE);
1059 }
1060
1061 /*
1062 * Oxford Semiconductor Inc.
1063 * Check if an OxSemi device is part of the Tornado range of devices.
1064 */
1065 #define PCI_VENDOR_ID_ENDRUN 0x7401
1066 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1067
pci_oxsemi_tornado_p(struct pci_dev * dev)1068 static bool pci_oxsemi_tornado_p(struct pci_dev *dev)
1069 {
1070 /* OxSemi Tornado devices are all 0xCxxx */
1071 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1072 (dev->device & 0xf000) != 0xc000)
1073 return false;
1074
1075 /* EndRun devices are all 0xExxx */
1076 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1077 (dev->device & 0xf000) != 0xe000)
1078 return false;
1079
1080 return true;
1081 }
1082
1083 /*
1084 * Determine the number of ports available on a Tornado device.
1085 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1086 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1087 {
1088 u8 __iomem *p;
1089 unsigned long deviceID;
1090 unsigned int number_uarts = 0;
1091
1092 if (!pci_oxsemi_tornado_p(dev))
1093 return 0;
1094
1095 p = pci_iomap(dev, 0, 5);
1096 if (p == NULL)
1097 return -ENOMEM;
1098
1099 deviceID = ioread32(p);
1100 /* Tornado device */
1101 if (deviceID == 0x07000200) {
1102 number_uarts = ioread8(p + 4);
1103 pci_dbg(dev, "%d ports detected on %s PCI Express device\n",
1104 number_uarts,
1105 dev->vendor == PCI_VENDOR_ID_ENDRUN ?
1106 "EndRun" : "Oxford");
1107 }
1108 pci_iounmap(dev, p);
1109 return number_uarts;
1110 }
1111
1112 /* Tornado-specific constants for the TCR and CPR registers; see below. */
1113 #define OXSEMI_TORNADO_TCR_MASK 0xf
1114 #define OXSEMI_TORNADO_CPR_MASK 0x1ff
1115 #define OXSEMI_TORNADO_CPR_MIN 0x008
1116 #define OXSEMI_TORNADO_CPR_DEF 0x10f
1117
1118 /*
1119 * Determine the oversampling rate, the clock prescaler, and the clock
1120 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1121 * which is four times the baud base, and the prescaler increments in
1122 * steps of 1/8. Therefore to make calculations on integers we need
1123 * to use a scaled clock rate, which is the baud base multiplied by 32
1124 * (or our assumed UART clock rate multiplied by 2).
1125 *
1126 * The allowed oversampling rates are from 4 up to 16 inclusive (values
1127 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1128 * values between 1.000 and 63.875 inclusive (operation for values from
1129 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1130 * unsigned 16-bit integer.
1131 *
1132 * For the most accurate baud rate we use a table of predetermined
1133 * oversampling rates and clock prescalers that records all possible
1134 * products of the two parameters in the range from 4 up to 255 inclusive,
1135 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
1136 * by 8. The table is sorted by the decreasing value of the oversampling
1137 * rate and ties are resolved by sorting by the decreasing value of the
1138 * product. This way preference is given to higher oversampling rates.
1139 *
1140 * We iterate over the table and choose the product of an oversampling
1141 * rate and a clock prescaler that gives the lowest integer division
1142 * result deviation, or if an exact integer divider is found we stop
1143 * looking for it right away. We do some fixup if the resulting clock
1144 * divisor required would be out of its unsigned 16-bit integer range.
1145 *
1146 * Finally we abuse the supposed fractional part returned to encode the
1147 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1148 * prescaler which will end up in the TCR and CPR/CPR2 registers.
1149 */
pci_oxsemi_tornado_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)1150 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
1151 unsigned int baud,
1152 unsigned int *frac)
1153 {
1154 static u8 p[][2] = {
1155 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
1156 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
1157 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
1158 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
1159 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
1160 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
1161 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
1162 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
1163 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
1164 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
1165 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
1166 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
1167 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
1168 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
1169 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
1170 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
1171 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
1172 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
1173 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
1174 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
1175 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
1176 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
1177 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
1178 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
1179 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
1180 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
1181 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
1182 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
1183 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
1184 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
1185 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
1186 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
1187 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
1188 { 4, 9, }, { 4, 8, },
1189 };
1190 /* Scale the quotient for comparison to get the fractional part. */
1191 const unsigned int quot_scale = 65536;
1192 unsigned int sclk = port->uartclk * 2;
1193 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);
1194 unsigned int best_squot;
1195 unsigned int squot;
1196 unsigned int quot;
1197 u16 cpr;
1198 u8 tcr;
1199 int i;
1200
1201 /* Old custom speed handling. */
1202 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
1203 unsigned int cust_div = port->custom_divisor;
1204
1205 quot = cust_div & UART_DIV_MAX;
1206 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
1207 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
1208 if (cpr < OXSEMI_TORNADO_CPR_MIN)
1209 cpr = OXSEMI_TORNADO_CPR_DEF;
1210 } else {
1211 best_squot = quot_scale;
1212 for (i = 0; i < ARRAY_SIZE(p); i++) {
1213 unsigned int spre;
1214 unsigned int srem;
1215 u8 cp;
1216 u8 tc;
1217
1218 tc = p[i][0];
1219 cp = p[i][1];
1220 spre = tc * cp;
1221
1222 srem = sdiv % spre;
1223 if (srem > spre / 2)
1224 srem = spre - srem;
1225 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre);
1226
1227 if (srem == 0) {
1228 tcr = tc;
1229 cpr = cp;
1230 quot = sdiv / spre;
1231 break;
1232 } else if (squot < best_squot) {
1233 best_squot = squot;
1234 tcr = tc;
1235 cpr = cp;
1236 quot = DIV_ROUND_CLOSEST(sdiv, spre);
1237 }
1238 }
1239 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
1240 quot % 2 == 0) {
1241 quot >>= 1;
1242 tcr <<= 1;
1243 }
1244 while (quot > UART_DIV_MAX) {
1245 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
1246 quot >>= 1;
1247 tcr <<= 1;
1248 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
1249 quot >>= 1;
1250 cpr <<= 1;
1251 } else {
1252 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
1253 cpr = OXSEMI_TORNADO_CPR_MASK;
1254 }
1255 }
1256 }
1257
1258 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
1259 return quot;
1260 }
1261
1262 /*
1263 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1264 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1265 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1266 * backwards compatibility any write to CPR clears CPR2 and therefore CPR
1267 * has to be written first, followed by CPR2, which occupies the location
1268 * of CKS used with earlier UART designs.
1269 */
pci_oxsemi_tornado_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1270 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,
1271 unsigned int baud,
1272 unsigned int quot,
1273 unsigned int quot_frac)
1274 {
1275 struct uart_8250_port *up = up_to_u8250p(port);
1276 u8 cpr2 = quot_frac >> 16;
1277 u8 cpr = quot_frac >> 8;
1278 u8 tcr = quot_frac;
1279
1280 serial_icr_write(up, UART_TCR, tcr);
1281 serial_icr_write(up, UART_CPR, cpr);
1282 serial_icr_write(up, UART_CKS, cpr2);
1283 serial8250_do_set_divisor(port, baud, quot);
1284 }
1285
1286 /*
1287 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate
1288 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used.
1289 */
pci_oxsemi_tornado_set_mctrl(struct uart_port * port,unsigned int mctrl)1290 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,
1291 unsigned int mctrl)
1292 {
1293 struct uart_8250_port *up = up_to_u8250p(port);
1294
1295 up->mcr |= UART_MCR_CLKSEL;
1296 serial8250_do_set_mctrl(port, mctrl);
1297 }
1298
1299 /*
1300 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1301 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting.
1302 */
pci_oxsemi_tornado_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * up,int idx)1303 static int pci_oxsemi_tornado_setup(struct serial_private *priv,
1304 const struct pciserial_board *board,
1305 struct uart_8250_port *up, int idx)
1306 {
1307 struct pci_dev *dev = priv->dev;
1308
1309 if (pci_oxsemi_tornado_p(dev)) {
1310 up->port.flags |= UPF_FULL_PROBE;
1311 up->port.get_divisor = pci_oxsemi_tornado_get_divisor;
1312 up->port.set_divisor = pci_oxsemi_tornado_set_divisor;
1313 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl;
1314 }
1315
1316 return pci_default_setup(priv, board, up, idx);
1317 }
1318
1319 #define QPCR_TEST_FOR1 0x3F
1320 #define QPCR_TEST_GET1 0x00
1321 #define QPCR_TEST_FOR2 0x40
1322 #define QPCR_TEST_GET2 0x40
1323 #define QPCR_TEST_FOR3 0x80
1324 #define QPCR_TEST_GET3 0x40
1325 #define QPCR_TEST_FOR4 0xC0
1326 #define QPCR_TEST_GET4 0x80
1327
1328 #define QOPR_CLOCK_X1 0x0000
1329 #define QOPR_CLOCK_X2 0x0001
1330 #define QOPR_CLOCK_X4 0x0002
1331 #define QOPR_CLOCK_X8 0x0003
1332 #define QOPR_CLOCK_RATE_MASK 0x0003
1333
1334 /* Quatech devices have their own extra interface features */
1335 static struct pci_device_id quatech_cards[] = {
1336 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) },
1337 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) },
1338 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) },
1339 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) },
1340 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) },
1341 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) },
1342 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) },
1343 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) },
1344 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) },
1345 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) },
1346 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) },
1347 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) },
1348 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) },
1349 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) },
1350 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) },
1351 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) },
1352 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) },
1353 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) },
1354 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) },
1355 { 0, }
1356 };
1357
pci_quatech_rqopr(struct uart_8250_port * port)1358 static int pci_quatech_rqopr(struct uart_8250_port *port)
1359 {
1360 unsigned long base = port->port.iobase;
1361 u8 LCR, val;
1362
1363 LCR = inb(base + UART_LCR);
1364 outb(0xBF, base + UART_LCR);
1365 val = inb(base + UART_SCR);
1366 outb(LCR, base + UART_LCR);
1367 return val;
1368 }
1369
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1370 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1371 {
1372 unsigned long base = port->port.iobase;
1373 u8 LCR;
1374
1375 LCR = inb(base + UART_LCR);
1376 outb(0xBF, base + UART_LCR);
1377 inb(base + UART_SCR);
1378 outb(qopr, base + UART_SCR);
1379 outb(LCR, base + UART_LCR);
1380 }
1381
pci_quatech_rqmcr(struct uart_8250_port * port)1382 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1383 {
1384 unsigned long base = port->port.iobase;
1385 u8 LCR, val, qmcr;
1386
1387 LCR = inb(base + UART_LCR);
1388 outb(0xBF, base + UART_LCR);
1389 val = inb(base + UART_SCR);
1390 outb(val | 0x10, base + UART_SCR);
1391 qmcr = inb(base + UART_MCR);
1392 outb(val, base + UART_SCR);
1393 outb(LCR, base + UART_LCR);
1394
1395 return qmcr;
1396 }
1397
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1398 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1399 {
1400 unsigned long base = port->port.iobase;
1401 u8 LCR, val;
1402
1403 LCR = inb(base + UART_LCR);
1404 outb(0xBF, base + UART_LCR);
1405 val = inb(base + UART_SCR);
1406 outb(val | 0x10, base + UART_SCR);
1407 outb(qmcr, base + UART_MCR);
1408 outb(val, base + UART_SCR);
1409 outb(LCR, base + UART_LCR);
1410 }
1411
pci_quatech_has_qmcr(struct uart_8250_port * port)1412 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1413 {
1414 unsigned long base = port->port.iobase;
1415 u8 LCR, val;
1416
1417 LCR = inb(base + UART_LCR);
1418 outb(0xBF, base + UART_LCR);
1419 val = inb(base + UART_SCR);
1420 if (val & 0x20) {
1421 outb(0x80, UART_LCR);
1422 if (!(inb(UART_SCR) & 0x20)) {
1423 outb(LCR, base + UART_LCR);
1424 return 1;
1425 }
1426 }
1427 return 0;
1428 }
1429
pci_quatech_test(struct uart_8250_port * port)1430 static int pci_quatech_test(struct uart_8250_port *port)
1431 {
1432 u8 reg, qopr;
1433
1434 qopr = pci_quatech_rqopr(port);
1435 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1436 reg = pci_quatech_rqopr(port) & 0xC0;
1437 if (reg != QPCR_TEST_GET1)
1438 return -EINVAL;
1439 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1440 reg = pci_quatech_rqopr(port) & 0xC0;
1441 if (reg != QPCR_TEST_GET2)
1442 return -EINVAL;
1443 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1444 reg = pci_quatech_rqopr(port) & 0xC0;
1445 if (reg != QPCR_TEST_GET3)
1446 return -EINVAL;
1447 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1448 reg = pci_quatech_rqopr(port) & 0xC0;
1449 if (reg != QPCR_TEST_GET4)
1450 return -EINVAL;
1451
1452 pci_quatech_wqopr(port, qopr);
1453 return 0;
1454 }
1455
pci_quatech_clock(struct uart_8250_port * port)1456 static int pci_quatech_clock(struct uart_8250_port *port)
1457 {
1458 u8 qopr, reg, set;
1459 unsigned long clock;
1460
1461 if (pci_quatech_test(port) < 0)
1462 return 1843200;
1463
1464 qopr = pci_quatech_rqopr(port);
1465
1466 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1467 reg = pci_quatech_rqopr(port);
1468 if (reg & QOPR_CLOCK_X8) {
1469 clock = 1843200;
1470 goto out;
1471 }
1472 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1473 reg = pci_quatech_rqopr(port);
1474 if (!(reg & QOPR_CLOCK_X8)) {
1475 clock = 1843200;
1476 goto out;
1477 }
1478 reg &= QOPR_CLOCK_X8;
1479 if (reg == QOPR_CLOCK_X2) {
1480 clock = 3685400;
1481 set = QOPR_CLOCK_X2;
1482 } else if (reg == QOPR_CLOCK_X4) {
1483 clock = 7372800;
1484 set = QOPR_CLOCK_X4;
1485 } else if (reg == QOPR_CLOCK_X8) {
1486 clock = 14745600;
1487 set = QOPR_CLOCK_X8;
1488 } else {
1489 clock = 1843200;
1490 set = QOPR_CLOCK_X1;
1491 }
1492 qopr &= ~QOPR_CLOCK_RATE_MASK;
1493 qopr |= set;
1494
1495 out:
1496 pci_quatech_wqopr(port, qopr);
1497 return clock;
1498 }
1499
pci_quatech_rs422(struct uart_8250_port * port)1500 static int pci_quatech_rs422(struct uart_8250_port *port)
1501 {
1502 u8 qmcr;
1503 int rs422 = 0;
1504
1505 if (!pci_quatech_has_qmcr(port))
1506 return 0;
1507 qmcr = pci_quatech_rqmcr(port);
1508 pci_quatech_wqmcr(port, 0xFF);
1509 if (pci_quatech_rqmcr(port))
1510 rs422 = 1;
1511 pci_quatech_wqmcr(port, qmcr);
1512 return rs422;
1513 }
1514
pci_quatech_init(struct pci_dev * dev)1515 static int pci_quatech_init(struct pci_dev *dev)
1516 {
1517 const struct pci_device_id *match;
1518 bool amcc = false;
1519
1520 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1521 return serial_8250_warn_need_ioport(dev);
1522
1523 match = pci_match_id(quatech_cards, dev);
1524 if (match)
1525 amcc = match->driver_data;
1526 else
1527 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device);
1528
1529 if (amcc) {
1530 unsigned long base = pci_resource_start(dev, 0);
1531 if (base) {
1532 u32 tmp;
1533
1534 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1535 tmp = inl(base + 0x3c);
1536 outl(tmp | 0x01000000, base + 0x3c);
1537 outl(tmp & ~0x01000000, base + 0x3c);
1538 }
1539 }
1540 return 0;
1541 }
1542
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1543 static int pci_quatech_setup(struct serial_private *priv,
1544 const struct pciserial_board *board,
1545 struct uart_8250_port *port, int idx)
1546 {
1547 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1548 return serial_8250_warn_need_ioport(priv->dev);
1549
1550 /* Needed by pci_quatech calls below */
1551 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1552 /* Set up the clocking */
1553 port->port.uartclk = pci_quatech_clock(port);
1554 /* For now just warn about RS422 */
1555 if (pci_quatech_rs422(port))
1556 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n");
1557 return pci_default_setup(priv, board, port, idx);
1558 }
1559
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1560 static int pci_default_setup(struct serial_private *priv,
1561 const struct pciserial_board *board,
1562 struct uart_8250_port *port, int idx)
1563 {
1564 unsigned int bar, offset = board->first_offset, maxnr;
1565
1566 bar = FL_GET_BASE(board->flags);
1567 if (board->flags & FL_BASE_BARS)
1568 bar += idx;
1569 else
1570 offset += idx * board->uart_offset;
1571
1572 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1573 (board->reg_shift + 3);
1574
1575 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1576 return 1;
1577
1578 return setup_port(priv, port, bar, offset, board->reg_shift);
1579 }
1580
1581 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1582 ce4100_serial_setup(struct serial_private *priv,
1583 const struct pciserial_board *board,
1584 struct uart_8250_port *port, int idx)
1585 {
1586 int ret;
1587
1588 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1589 port->port.iotype = UPIO_MEM32;
1590 port->port.type = PORT_XSCALE;
1591 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1592 port->port.regshift = 2;
1593
1594 return ret;
1595 }
1596
1597 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1598 pci_omegapci_setup(struct serial_private *priv,
1599 const struct pciserial_board *board,
1600 struct uart_8250_port *port, int idx)
1601 {
1602 return setup_port(priv, port, 2, idx * 8, 0);
1603 }
1604
1605 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1606 pci_brcm_trumanage_setup(struct serial_private *priv,
1607 const struct pciserial_board *board,
1608 struct uart_8250_port *port, int idx)
1609 {
1610 int ret = pci_default_setup(priv, board, port, idx);
1611
1612 port->port.type = PORT_BRCM_TRUMANAGE;
1613 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1614 return ret;
1615 }
1616
1617 /* RTS will control by MCR if this bit is 0 */
1618 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1619 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1620 #define FINTEK_RTS_INVERT BIT(5)
1621
1622 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1623 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,
1624 struct serial_rs485 *rs485)
1625 {
1626 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1627 u8 setting;
1628 u8 *index = (u8 *) port->private_data;
1629
1630 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1631
1632 if (rs485->flags & SER_RS485_ENABLED) {
1633 /* Enable RTS H/W control mode */
1634 setting |= FINTEK_RTS_CONTROL_BY_HW;
1635
1636 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1637 /* RTS driving high on TX */
1638 setting &= ~FINTEK_RTS_INVERT;
1639 } else {
1640 /* RTS driving low on TX */
1641 setting |= FINTEK_RTS_INVERT;
1642 }
1643 } else {
1644 /* Disable RTS H/W control mode */
1645 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1646 }
1647
1648 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1649
1650 return 0;
1651 }
1652
1653 static const struct serial_rs485 pci_fintek_rs485_supported = {
1654 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND,
1655 /* F81504/508/512 does not support RTS delay before or after send */
1656 };
1657
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1658 static int pci_fintek_setup(struct serial_private *priv,
1659 const struct pciserial_board *board,
1660 struct uart_8250_port *port, int idx)
1661 {
1662 struct pci_dev *pdev = priv->dev;
1663 u8 *data;
1664 u8 config_base;
1665 u16 iobase;
1666
1667 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1668 return serial_8250_warn_need_ioport(pdev);
1669
1670 config_base = 0x40 + 0x08 * idx;
1671
1672 /* Get the io address from configuration space */
1673 pci_read_config_word(pdev, config_base + 4, &iobase);
1674
1675 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase);
1676
1677 port->port.iotype = UPIO_PORT;
1678 port->port.iobase = iobase;
1679 port->port.rs485_config = pci_fintek_rs485_config;
1680 port->port.rs485_supported = pci_fintek_rs485_supported;
1681
1682 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1683 if (!data)
1684 return -ENOMEM;
1685
1686 /* preserve index in PCI configuration space */
1687 *data = idx;
1688 port->port.private_data = data;
1689
1690 return 0;
1691 }
1692
pci_fintek_init(struct pci_dev * dev)1693 static int pci_fintek_init(struct pci_dev *dev)
1694 {
1695 unsigned long iobase;
1696 u32 max_port, i;
1697 resource_size_t bar_data[3];
1698 u8 config_base;
1699 struct serial_private *priv = pci_get_drvdata(dev);
1700
1701 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1702 return serial_8250_warn_need_ioport(dev);
1703
1704 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1705 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1706 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1707 return -ENODEV;
1708
1709 switch (dev->device) {
1710 case 0x1104: /* 4 ports */
1711 case 0x1108: /* 8 ports */
1712 max_port = dev->device & 0xff;
1713 break;
1714 case 0x1112: /* 12 ports */
1715 max_port = 12;
1716 break;
1717 default:
1718 return -EINVAL;
1719 }
1720
1721 /* Get the io address dispatch from the BIOS */
1722 bar_data[0] = pci_resource_start(dev, 5);
1723 bar_data[1] = pci_resource_start(dev, 4);
1724 bar_data[2] = pci_resource_start(dev, 3);
1725
1726 for (i = 0; i < max_port; ++i) {
1727 /* UART0 configuration offset start from 0x40 */
1728 config_base = 0x40 + 0x08 * i;
1729
1730 /* Calculate Real IO Port */
1731 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1732
1733 /* Enable UART I/O port */
1734 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1735
1736 /* Select 128-byte FIFO and 8x FIFO threshold */
1737 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1738
1739 /* LSB UART */
1740 pci_write_config_byte(dev, config_base + 0x04,
1741 (u8)(iobase & 0xff));
1742
1743 /* MSB UART */
1744 pci_write_config_byte(dev, config_base + 0x05,
1745 (u8)((iobase & 0xff00) >> 8));
1746
1747 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1748
1749 if (!priv) {
1750 /* First init without port data
1751 * force init to RS232 Mode
1752 */
1753 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1754 }
1755 }
1756
1757 return max_port;
1758 }
1759
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1760 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1761 {
1762 struct f815xxa_data *data = p->private_data;
1763 unsigned long flags;
1764
1765 spin_lock_irqsave(&data->lock, flags);
1766 writeb(value, p->membase + offset);
1767 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1768 spin_unlock_irqrestore(&data->lock, flags);
1769 }
1770
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1771 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1772 const struct pciserial_board *board,
1773 struct uart_8250_port *port, int idx)
1774 {
1775 struct pci_dev *pdev = priv->dev;
1776 struct f815xxa_data *data;
1777
1778 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1779 if (!data)
1780 return -ENOMEM;
1781
1782 data->idx = idx;
1783 spin_lock_init(&data->lock);
1784
1785 port->port.private_data = data;
1786 port->port.iotype = UPIO_MEM;
1787 port->port.flags |= UPF_IOREMAP;
1788 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1789 port->port.serial_out = f815xxa_mem_serial_out;
1790
1791 return 0;
1792 }
1793
pci_fintek_f815xxa_init(struct pci_dev * dev)1794 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1795 {
1796 u32 max_port, i;
1797 int config_base;
1798
1799 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1800 return -ENODEV;
1801
1802 switch (dev->device) {
1803 case 0x1204: /* 4 ports */
1804 case 0x1208: /* 8 ports */
1805 max_port = dev->device & 0xff;
1806 break;
1807 case 0x1212: /* 12 ports */
1808 max_port = 12;
1809 break;
1810 default:
1811 return -EINVAL;
1812 }
1813
1814 /* Set to mmio decode */
1815 pci_write_config_byte(dev, 0x209, 0x40);
1816
1817 for (i = 0; i < max_port; ++i) {
1818 /* UART0 configuration offset start from 0x2A0 */
1819 config_base = 0x2A0 + 0x08 * i;
1820
1821 /* Select 128-byte FIFO and 8x FIFO threshold */
1822 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1823
1824 /* Enable UART I/O port */
1825 pci_write_config_byte(dev, config_base + 0, 0x01);
1826 }
1827
1828 return max_port;
1829 }
1830
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1831 static int skip_tx_en_setup(struct serial_private *priv,
1832 const struct pciserial_board *board,
1833 struct uart_8250_port *port, int idx)
1834 {
1835 port->port.quirks |= UPQ_NO_TXEN_TEST;
1836 pci_dbg(priv->dev,
1837 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1838 priv->dev->vendor, priv->dev->device,
1839 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1840
1841 return pci_default_setup(priv, board, port, idx);
1842 }
1843
kt_handle_break(struct uart_port * p)1844 static void kt_handle_break(struct uart_port *p)
1845 {
1846 struct uart_8250_port *up = up_to_u8250p(p);
1847 /*
1848 * On receipt of a BI, serial device in Intel ME (Intel
1849 * management engine) needs to have its fifos cleared for sane
1850 * SOL (Serial Over Lan) output.
1851 */
1852 serial8250_clear_and_reinit_fifos(up);
1853 }
1854
kt_serial_in(struct uart_port * p,int offset)1855 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1856 {
1857 struct uart_8250_port *up = up_to_u8250p(p);
1858 unsigned int val;
1859
1860 /*
1861 * When the Intel ME (management engine) gets reset its serial
1862 * port registers could return 0 momentarily. Functions like
1863 * serial8250_console_write, read and save the IER, perform
1864 * some operation and then restore it. In order to avoid
1865 * setting IER register inadvertently to 0, if the value read
1866 * is 0, double check with ier value in uart_8250_port and use
1867 * that instead. up->ier should be the same value as what is
1868 * currently configured.
1869 */
1870 val = inb(p->iobase + offset);
1871 if (offset == UART_IER) {
1872 if (val == 0)
1873 val = up->ier;
1874 }
1875 return val;
1876 }
1877
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1878 static int kt_serial_setup(struct serial_private *priv,
1879 const struct pciserial_board *board,
1880 struct uart_8250_port *port, int idx)
1881 {
1882 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1883 return serial_8250_warn_need_ioport(priv->dev);
1884
1885 port->port.flags |= UPF_BUG_THRE;
1886 port->port.serial_in = kt_serial_in;
1887 port->port.handle_break = kt_handle_break;
1888 return skip_tx_en_setup(priv, board, port, idx);
1889 }
1890
pci_eg20t_init(struct pci_dev * dev)1891 static int pci_eg20t_init(struct pci_dev *dev)
1892 {
1893 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1894 return -ENODEV;
1895 #else
1896 return 0;
1897 #endif
1898 }
1899
1900 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1901 pci_wch_ch353_setup(struct serial_private *priv,
1902 const struct pciserial_board *board,
1903 struct uart_8250_port *port, int idx)
1904 {
1905 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1906 return serial_8250_warn_need_ioport(priv->dev);
1907
1908 port->port.flags |= UPF_FIXED_TYPE;
1909 port->port.type = PORT_16550A;
1910 return pci_default_setup(priv, board, port, idx);
1911 }
1912
1913 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1914 pci_wch_ch355_setup(struct serial_private *priv,
1915 const struct pciserial_board *board,
1916 struct uart_8250_port *port, int idx)
1917 {
1918 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1919 return serial_8250_warn_need_ioport(priv->dev);
1920
1921 port->port.flags |= UPF_FIXED_TYPE;
1922 port->port.type = PORT_16550A;
1923 return pci_default_setup(priv, board, port, idx);
1924 }
1925
1926 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1927 pci_wch_ch38x_setup(struct serial_private *priv,
1928 const struct pciserial_board *board,
1929 struct uart_8250_port *port, int idx)
1930 {
1931 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1932 return serial_8250_warn_need_ioport(priv->dev);
1933
1934 port->port.flags |= UPF_FIXED_TYPE;
1935 port->port.type = PORT_16850;
1936 return pci_default_setup(priv, board, port, idx);
1937 }
1938
1939
1940 #define CH384_XINT_ENABLE_REG 0xEB
1941 #define CH384_XINT_ENABLE_BIT 0x02
1942
pci_wch_ch38x_init(struct pci_dev * dev)1943 static int pci_wch_ch38x_init(struct pci_dev *dev)
1944 {
1945 int max_port;
1946 unsigned long iobase;
1947
1948 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
1949 return serial_8250_warn_need_ioport(dev);
1950
1951 switch (dev->device) {
1952 case 0x3853: /* 8 ports */
1953 max_port = 8;
1954 break;
1955 default:
1956 return -EINVAL;
1957 }
1958
1959 iobase = pci_resource_start(dev, 0);
1960 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1961
1962 return max_port;
1963 }
1964
pci_wch_ch38x_exit(struct pci_dev * dev)1965 static void pci_wch_ch38x_exit(struct pci_dev *dev)
1966 {
1967 unsigned long iobase;
1968
1969 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {
1970 serial_8250_warn_need_ioport(dev);
1971 return;
1972 }
1973
1974 iobase = pci_resource_start(dev, 0);
1975 outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1976 }
1977
1978
1979 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1980 pci_sunix_setup(struct serial_private *priv,
1981 const struct pciserial_board *board,
1982 struct uart_8250_port *port, int idx)
1983 {
1984 int bar;
1985 int offset;
1986
1987 port->port.flags |= UPF_FIXED_TYPE;
1988 port->port.type = PORT_SUNIX;
1989
1990 if (idx < 4) {
1991 bar = 0;
1992 offset = idx * board->uart_offset;
1993 } else {
1994 bar = 1;
1995 idx -= 4;
1996 idx = div_s64_rem(idx, 4, &offset);
1997 offset = idx * 64 + offset * board->uart_offset;
1998 }
1999
2000 return setup_port(priv, port, bar, offset, 0);
2001 }
2002
2003 #define MOXA_PUART_GPIO_EN 0x09
2004 #define MOXA_PUART_GPIO_OUT 0x0A
2005
2006 #define MOXA_GPIO_PIN2 BIT(2)
2007
2008 #define MOXA_RS232 0x00
2009 #define MOXA_RS422 0x01
2010 #define MOXA_RS485_4W 0x0B
2011 #define MOXA_RS485_2W 0x0F
2012 #define MOXA_UIR_OFFSET 0x04
2013 #define MOXA_EVEN_RS_MASK GENMASK(3, 0)
2014 #define MOXA_ODD_RS_MASK GENMASK(7, 4)
2015
2016 enum {
2017 MOXA_SUPP_RS232 = BIT(0),
2018 MOXA_SUPP_RS422 = BIT(1),
2019 MOXA_SUPP_RS485 = BIT(2),
2020 };
2021
moxa_get_nports(unsigned short device)2022 static unsigned short moxa_get_nports(unsigned short device)
2023 {
2024 switch (device) {
2025 case PCI_DEVICE_ID_MOXA_CP116E_A_A:
2026 case PCI_DEVICE_ID_MOXA_CP116E_A_B:
2027 return 8;
2028 }
2029
2030 return FIELD_GET(0x00F0, device);
2031 }
2032
pci_moxa_is_mini_pcie(unsigned short device)2033 static bool pci_moxa_is_mini_pcie(unsigned short device)
2034 {
2035 if (device == PCI_DEVICE_ID_MOXA_CP102N ||
2036 device == PCI_DEVICE_ID_MOXA_CP104N ||
2037 device == PCI_DEVICE_ID_MOXA_CP112N ||
2038 device == PCI_DEVICE_ID_MOXA_CP114N ||
2039 device == PCI_DEVICE_ID_MOXA_CP132N ||
2040 device == PCI_DEVICE_ID_MOXA_CP134N)
2041 return true;
2042
2043 return false;
2044 }
2045
pci_moxa_supported_rs(struct pci_dev * dev)2046 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)
2047 {
2048 switch (dev->device & 0x0F00) {
2049 case 0x0000:
2050 case 0x0600:
2051 return MOXA_SUPP_RS232;
2052 case 0x0100:
2053 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2054 case 0x0300:
2055 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;
2056 }
2057 return 0;
2058 }
2059
pci_moxa_set_interface(const struct pci_dev * dev,unsigned int port_idx,u8 mode)2060 static int pci_moxa_set_interface(const struct pci_dev *dev,
2061 unsigned int port_idx,
2062 u8 mode)
2063 {
2064 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2065 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2;
2066 u8 val;
2067
2068 val = inb(UIR_addr);
2069
2070 if (port_idx % 2) {
2071 val &= ~MOXA_ODD_RS_MASK;
2072 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode);
2073 } else {
2074 val &= ~MOXA_EVEN_RS_MASK;
2075 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode);
2076 }
2077 outb(val, UIR_addr);
2078
2079 return 0;
2080 }
2081
pci_moxa_init(struct pci_dev * dev)2082 static int pci_moxa_init(struct pci_dev *dev)
2083 {
2084 unsigned short device = dev->device;
2085 resource_size_t iobar_addr = pci_resource_start(dev, 2);
2086 unsigned int i, num_ports = moxa_get_nports(device);
2087 u8 val, init_mode = MOXA_RS232;
2088
2089 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2090 return serial_8250_warn_need_ioport(dev);
2091
2092 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {
2093 init_mode = MOXA_RS422;
2094 }
2095 for (i = 0; i < num_ports; ++i)
2096 pci_moxa_set_interface(dev, i, init_mode);
2097
2098 /*
2099 * Enable hardware buffer to prevent break signal output when system boots up.
2100 * This hardware buffer is only supported on Mini PCIe series.
2101 */
2102 if (pci_moxa_is_mini_pcie(device)) {
2103 /* Set GPIO direction */
2104 val = inb(iobar_addr + MOXA_PUART_GPIO_EN);
2105 val |= MOXA_GPIO_PIN2;
2106 outb(val, iobar_addr + MOXA_PUART_GPIO_EN);
2107 /* Enable low GPIO */
2108 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT);
2109 val &= ~MOXA_GPIO_PIN2;
2110 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT);
2111 }
2112
2113 return num_ports;
2114 }
2115
2116 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)2117 pci_moxa_setup(struct serial_private *priv,
2118 const struct pciserial_board *board,
2119 struct uart_8250_port *port, int idx)
2120 {
2121 unsigned int bar = FL_GET_BASE(board->flags);
2122 int offset;
2123
2124 if (!IS_ENABLED(CONFIG_HAS_IOPORT))
2125 return serial_8250_warn_need_ioport(priv->dev);
2126
2127 if (board->num_ports == 4 && idx == 3)
2128 offset = 7 * board->uart_offset;
2129 else
2130 offset = idx * board->uart_offset;
2131
2132 return setup_port(priv, port, bar, offset, 0);
2133 }
2134
2135 /*
2136 * Master list of serial port init/setup/exit quirks.
2137 * This does not describe the general nature of the port.
2138 * (ie, baud base, number and location of ports, etc)
2139 *
2140 * This list is ordered alphabetically by vendor then device.
2141 * Specific entries must come before more generic entries.
2142 */
2143 static struct pci_serial_quirk pci_serial_quirks[] = {
2144 /*
2145 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2146 */
2147 {
2148 .vendor = PCI_VENDOR_ID_AMCC,
2149 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2150 .subvendor = PCI_ANY_ID,
2151 .subdevice = PCI_ANY_ID,
2152 .setup = addidata_apci7800_setup,
2153 },
2154 /*
2155 * AFAVLAB cards - these may be called via parport_serial
2156 * It is not clear whether this applies to all products.
2157 */
2158 {
2159 .vendor = PCI_VENDOR_ID_AFAVLAB,
2160 .device = PCI_ANY_ID,
2161 .subvendor = PCI_ANY_ID,
2162 .subdevice = PCI_ANY_ID,
2163 .setup = afavlab_setup,
2164 },
2165 /*
2166 * HP Diva
2167 */
2168 {
2169 .vendor = PCI_VENDOR_ID_HP,
2170 .device = PCI_DEVICE_ID_HP_DIVA,
2171 .subvendor = PCI_ANY_ID,
2172 .subdevice = PCI_ANY_ID,
2173 .init = pci_hp_diva_init,
2174 .setup = pci_hp_diva_setup,
2175 },
2176 /*
2177 * HPE PCI serial device
2178 */
2179 {
2180 .vendor = PCI_VENDOR_ID_HP_3PAR,
2181 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2182 .subvendor = PCI_ANY_ID,
2183 .subdevice = PCI_ANY_ID,
2184 .setup = pci_hp_diva_setup,
2185 },
2186 /*
2187 * Intel
2188 */
2189 {
2190 .vendor = PCI_VENDOR_ID_INTEL,
2191 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2192 .subvendor = 0xe4bf,
2193 .subdevice = PCI_ANY_ID,
2194 .init = pci_inteli960ni_init,
2195 .setup = pci_default_setup,
2196 },
2197 {
2198 .vendor = PCI_VENDOR_ID_INTEL,
2199 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2200 .subvendor = PCI_ANY_ID,
2201 .subdevice = PCI_ANY_ID,
2202 .setup = skip_tx_en_setup,
2203 },
2204 {
2205 .vendor = PCI_VENDOR_ID_INTEL,
2206 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2207 .subvendor = PCI_ANY_ID,
2208 .subdevice = PCI_ANY_ID,
2209 .setup = skip_tx_en_setup,
2210 },
2211 {
2212 .vendor = PCI_VENDOR_ID_INTEL,
2213 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2214 .subvendor = PCI_ANY_ID,
2215 .subdevice = PCI_ANY_ID,
2216 .setup = skip_tx_en_setup,
2217 },
2218 {
2219 .vendor = PCI_VENDOR_ID_INTEL,
2220 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .setup = ce4100_serial_setup,
2224 },
2225 {
2226 .vendor = PCI_VENDOR_ID_INTEL,
2227 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2228 .subvendor = PCI_ANY_ID,
2229 .subdevice = PCI_ANY_ID,
2230 .setup = kt_serial_setup,
2231 },
2232 /*
2233 * ITE
2234 */
2235 {
2236 .vendor = PCI_VENDOR_ID_ITE,
2237 .device = PCI_DEVICE_ID_ITE_8872,
2238 .subvendor = PCI_ANY_ID,
2239 .subdevice = PCI_ANY_ID,
2240 .init = pci_ite887x_init,
2241 .setup = pci_default_setup,
2242 .exit = pci_ite887x_exit,
2243 },
2244 /*
2245 * National Instruments
2246 */
2247 {
2248 .vendor = PCI_VENDOR_ID_NI,
2249 .device = PCI_DEVICE_ID_NI_PCI23216,
2250 .subvendor = PCI_ANY_ID,
2251 .subdevice = PCI_ANY_ID,
2252 .init = pci_ni8420_init,
2253 .setup = pci_default_setup,
2254 .exit = pci_ni8420_exit,
2255 },
2256 {
2257 .vendor = PCI_VENDOR_ID_NI,
2258 .device = PCI_DEVICE_ID_NI_PCI2328,
2259 .subvendor = PCI_ANY_ID,
2260 .subdevice = PCI_ANY_ID,
2261 .init = pci_ni8420_init,
2262 .setup = pci_default_setup,
2263 .exit = pci_ni8420_exit,
2264 },
2265 {
2266 .vendor = PCI_VENDOR_ID_NI,
2267 .device = PCI_DEVICE_ID_NI_PCI2324,
2268 .subvendor = PCI_ANY_ID,
2269 .subdevice = PCI_ANY_ID,
2270 .init = pci_ni8420_init,
2271 .setup = pci_default_setup,
2272 .exit = pci_ni8420_exit,
2273 },
2274 {
2275 .vendor = PCI_VENDOR_ID_NI,
2276 .device = PCI_DEVICE_ID_NI_PCI2322,
2277 .subvendor = PCI_ANY_ID,
2278 .subdevice = PCI_ANY_ID,
2279 .init = pci_ni8420_init,
2280 .setup = pci_default_setup,
2281 .exit = pci_ni8420_exit,
2282 },
2283 {
2284 .vendor = PCI_VENDOR_ID_NI,
2285 .device = PCI_DEVICE_ID_NI_PCI2324I,
2286 .subvendor = PCI_ANY_ID,
2287 .subdevice = PCI_ANY_ID,
2288 .init = pci_ni8420_init,
2289 .setup = pci_default_setup,
2290 .exit = pci_ni8420_exit,
2291 },
2292 {
2293 .vendor = PCI_VENDOR_ID_NI,
2294 .device = PCI_DEVICE_ID_NI_PCI2322I,
2295 .subvendor = PCI_ANY_ID,
2296 .subdevice = PCI_ANY_ID,
2297 .init = pci_ni8420_init,
2298 .setup = pci_default_setup,
2299 .exit = pci_ni8420_exit,
2300 },
2301 {
2302 .vendor = PCI_VENDOR_ID_NI,
2303 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
2306 .init = pci_ni8420_init,
2307 .setup = pci_default_setup,
2308 .exit = pci_ni8420_exit,
2309 },
2310 {
2311 .vendor = PCI_VENDOR_ID_NI,
2312 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2313 .subvendor = PCI_ANY_ID,
2314 .subdevice = PCI_ANY_ID,
2315 .init = pci_ni8420_init,
2316 .setup = pci_default_setup,
2317 .exit = pci_ni8420_exit,
2318 },
2319 {
2320 .vendor = PCI_VENDOR_ID_NI,
2321 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2322 .subvendor = PCI_ANY_ID,
2323 .subdevice = PCI_ANY_ID,
2324 .init = pci_ni8420_init,
2325 .setup = pci_default_setup,
2326 .exit = pci_ni8420_exit,
2327 },
2328 {
2329 .vendor = PCI_VENDOR_ID_NI,
2330 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2331 .subvendor = PCI_ANY_ID,
2332 .subdevice = PCI_ANY_ID,
2333 .init = pci_ni8420_init,
2334 .setup = pci_default_setup,
2335 .exit = pci_ni8420_exit,
2336 },
2337 {
2338 .vendor = PCI_VENDOR_ID_NI,
2339 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2340 .subvendor = PCI_ANY_ID,
2341 .subdevice = PCI_ANY_ID,
2342 .init = pci_ni8420_init,
2343 .setup = pci_default_setup,
2344 .exit = pci_ni8420_exit,
2345 },
2346 {
2347 .vendor = PCI_VENDOR_ID_NI,
2348 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2349 .subvendor = PCI_ANY_ID,
2350 .subdevice = PCI_ANY_ID,
2351 .init = pci_ni8420_init,
2352 .setup = pci_default_setup,
2353 .exit = pci_ni8420_exit,
2354 },
2355 {
2356 .vendor = PCI_VENDOR_ID_NI,
2357 .device = PCI_ANY_ID,
2358 .subvendor = PCI_ANY_ID,
2359 .subdevice = PCI_ANY_ID,
2360 .init = pci_ni8430_init,
2361 .setup = pci_ni8430_setup,
2362 .exit = pci_ni8430_exit,
2363 },
2364 /* Quatech */
2365 {
2366 .vendor = PCI_VENDOR_ID_QUATECH,
2367 .device = PCI_ANY_ID,
2368 .subvendor = PCI_ANY_ID,
2369 .subdevice = PCI_ANY_ID,
2370 .init = pci_quatech_init,
2371 .setup = pci_quatech_setup,
2372 },
2373 /*
2374 * Panacom
2375 */
2376 {
2377 .vendor = PCI_VENDOR_ID_PANACOM,
2378 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2379 .subvendor = PCI_ANY_ID,
2380 .subdevice = PCI_ANY_ID,
2381 .init = pci_plx9050_init,
2382 .setup = pci_default_setup,
2383 .exit = pci_plx9050_exit,
2384 },
2385 {
2386 .vendor = PCI_VENDOR_ID_PANACOM,
2387 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2388 .subvendor = PCI_ANY_ID,
2389 .subdevice = PCI_ANY_ID,
2390 .init = pci_plx9050_init,
2391 .setup = pci_default_setup,
2392 .exit = pci_plx9050_exit,
2393 },
2394 /*
2395 * PLX
2396 */
2397 {
2398 .vendor = PCI_VENDOR_ID_PLX,
2399 .device = PCI_DEVICE_ID_PLX_9050,
2400 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2401 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2402 .init = pci_plx9050_init,
2403 .setup = pci_default_setup,
2404 .exit = pci_plx9050_exit,
2405 },
2406 {
2407 .vendor = PCI_VENDOR_ID_PLX,
2408 .device = PCI_DEVICE_ID_PLX_9050,
2409 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2410 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2411 .init = pci_plx9050_init,
2412 .setup = pci_default_setup,
2413 .exit = pci_plx9050_exit,
2414 },
2415 {
2416 .vendor = PCI_VENDOR_ID_PLX,
2417 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2418 .subvendor = PCI_VENDOR_ID_PLX,
2419 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2420 .init = pci_plx9050_init,
2421 .setup = pci_default_setup,
2422 .exit = pci_plx9050_exit,
2423 },
2424 /*
2425 * SBS Technologies, Inc., PMC-OCTALPRO 232
2426 */
2427 {
2428 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2429 .device = PCI_DEVICE_ID_OCTPRO,
2430 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2431 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2432 .init = sbs_init,
2433 .setup = sbs_setup,
2434 .exit = sbs_exit,
2435 },
2436 /*
2437 * SBS Technologies, Inc., PMC-OCTALPRO 422
2438 */
2439 {
2440 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2441 .device = PCI_DEVICE_ID_OCTPRO,
2442 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2443 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2444 .init = sbs_init,
2445 .setup = sbs_setup,
2446 .exit = sbs_exit,
2447 },
2448 /*
2449 * SBS Technologies, Inc., P-Octal 232
2450 */
2451 {
2452 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2453 .device = PCI_DEVICE_ID_OCTPRO,
2454 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2455 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2456 .init = sbs_init,
2457 .setup = sbs_setup,
2458 .exit = sbs_exit,
2459 },
2460 /*
2461 * SBS Technologies, Inc., P-Octal 422
2462 */
2463 {
2464 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2465 .device = PCI_DEVICE_ID_OCTPRO,
2466 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2467 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2468 .init = sbs_init,
2469 .setup = sbs_setup,
2470 .exit = sbs_exit,
2471 },
2472 /*
2473 * SIIG cards - these may be called via parport_serial
2474 */
2475 {
2476 .vendor = PCI_VENDOR_ID_SIIG,
2477 .device = PCI_ANY_ID,
2478 .subvendor = PCI_ANY_ID,
2479 .subdevice = PCI_ANY_ID,
2480 .init = pci_siig_init,
2481 .setup = pci_siig_setup,
2482 },
2483 /*
2484 * Titan cards
2485 */
2486 {
2487 .vendor = PCI_VENDOR_ID_TITAN,
2488 .device = PCI_DEVICE_ID_TITAN_400L,
2489 .subvendor = PCI_ANY_ID,
2490 .subdevice = PCI_ANY_ID,
2491 .setup = titan_400l_800l_setup,
2492 },
2493 {
2494 .vendor = PCI_VENDOR_ID_TITAN,
2495 .device = PCI_DEVICE_ID_TITAN_800L,
2496 .subvendor = PCI_ANY_ID,
2497 .subdevice = PCI_ANY_ID,
2498 .setup = titan_400l_800l_setup,
2499 },
2500 /*
2501 * Timedia cards
2502 */
2503 {
2504 .vendor = PCI_VENDOR_ID_TIMEDIA,
2505 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2506 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2507 .subdevice = PCI_ANY_ID,
2508 .probe = pci_timedia_probe,
2509 .init = pci_timedia_init,
2510 .setup = pci_timedia_setup,
2511 },
2512 {
2513 .vendor = PCI_VENDOR_ID_TIMEDIA,
2514 .device = PCI_ANY_ID,
2515 .subvendor = PCI_ANY_ID,
2516 .subdevice = PCI_ANY_ID,
2517 .setup = pci_timedia_setup,
2518 },
2519 /*
2520 * Sunix PCI serial boards
2521 */
2522 {
2523 .vendor = PCI_VENDOR_ID_SUNIX,
2524 .device = PCI_DEVICE_ID_SUNIX_1999,
2525 .subvendor = PCI_VENDOR_ID_SUNIX,
2526 .subdevice = PCI_ANY_ID,
2527 .setup = pci_sunix_setup,
2528 },
2529 /*
2530 * Xircom cards
2531 */
2532 {
2533 .vendor = PCI_VENDOR_ID_XIRCOM,
2534 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2535 .subvendor = PCI_ANY_ID,
2536 .subdevice = PCI_ANY_ID,
2537 .init = pci_xircom_init,
2538 .setup = pci_default_setup,
2539 },
2540 /*
2541 * Netmos cards - these may be called via parport_serial
2542 */
2543 {
2544 .vendor = PCI_VENDOR_ID_NETMOS,
2545 .device = PCI_ANY_ID,
2546 .subvendor = PCI_ANY_ID,
2547 .subdevice = PCI_ANY_ID,
2548 .init = pci_netmos_init,
2549 .setup = pci_netmos_9900_setup,
2550 },
2551 /*
2552 * EndRun Technologies
2553 */
2554 {
2555 .vendor = PCI_VENDOR_ID_ENDRUN,
2556 .device = PCI_ANY_ID,
2557 .subvendor = PCI_ANY_ID,
2558 .subdevice = PCI_ANY_ID,
2559 .init = pci_oxsemi_tornado_init,
2560 .setup = pci_default_setup,
2561 },
2562 /*
2563 * For Oxford Semiconductor Tornado based devices
2564 */
2565 {
2566 .vendor = PCI_VENDOR_ID_OXSEMI,
2567 .device = PCI_ANY_ID,
2568 .subvendor = PCI_ANY_ID,
2569 .subdevice = PCI_ANY_ID,
2570 .init = pci_oxsemi_tornado_init,
2571 .setup = pci_oxsemi_tornado_setup,
2572 },
2573 {
2574 .vendor = PCI_VENDOR_ID_MAINPINE,
2575 .device = PCI_ANY_ID,
2576 .subvendor = PCI_ANY_ID,
2577 .subdevice = PCI_ANY_ID,
2578 .init = pci_oxsemi_tornado_init,
2579 .setup = pci_oxsemi_tornado_setup,
2580 },
2581 {
2582 .vendor = PCI_VENDOR_ID_DIGI,
2583 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2584 .subvendor = PCI_SUBVENDOR_ID_IBM,
2585 .subdevice = PCI_ANY_ID,
2586 .init = pci_oxsemi_tornado_init,
2587 .setup = pci_oxsemi_tornado_setup,
2588 },
2589 /*
2590 * Brainboxes devices - all Oxsemi based
2591 */
2592 {
2593 .vendor = PCI_VENDOR_ID_INTASHIELD,
2594 .device = 0x4027,
2595 .subvendor = PCI_ANY_ID,
2596 .subdevice = PCI_ANY_ID,
2597 .init = pci_oxsemi_tornado_init,
2598 .setup = pci_oxsemi_tornado_setup,
2599 },
2600 {
2601 .vendor = PCI_VENDOR_ID_INTASHIELD,
2602 .device = 0x4028,
2603 .subvendor = PCI_ANY_ID,
2604 .subdevice = PCI_ANY_ID,
2605 .init = pci_oxsemi_tornado_init,
2606 .setup = pci_oxsemi_tornado_setup,
2607 },
2608 {
2609 .vendor = PCI_VENDOR_ID_INTASHIELD,
2610 .device = 0x4029,
2611 .subvendor = PCI_ANY_ID,
2612 .subdevice = PCI_ANY_ID,
2613 .init = pci_oxsemi_tornado_init,
2614 .setup = pci_oxsemi_tornado_setup,
2615 },
2616 {
2617 .vendor = PCI_VENDOR_ID_INTASHIELD,
2618 .device = 0x4019,
2619 .subvendor = PCI_ANY_ID,
2620 .subdevice = PCI_ANY_ID,
2621 .init = pci_oxsemi_tornado_init,
2622 .setup = pci_oxsemi_tornado_setup,
2623 },
2624 {
2625 .vendor = PCI_VENDOR_ID_INTASHIELD,
2626 .device = 0x4016,
2627 .subvendor = PCI_ANY_ID,
2628 .subdevice = PCI_ANY_ID,
2629 .init = pci_oxsemi_tornado_init,
2630 .setup = pci_oxsemi_tornado_setup,
2631 },
2632 {
2633 .vendor = PCI_VENDOR_ID_INTASHIELD,
2634 .device = 0x4015,
2635 .subvendor = PCI_ANY_ID,
2636 .subdevice = PCI_ANY_ID,
2637 .init = pci_oxsemi_tornado_init,
2638 .setup = pci_oxsemi_tornado_setup,
2639 },
2640 {
2641 .vendor = PCI_VENDOR_ID_INTASHIELD,
2642 .device = 0x400A,
2643 .subvendor = PCI_ANY_ID,
2644 .subdevice = PCI_ANY_ID,
2645 .init = pci_oxsemi_tornado_init,
2646 .setup = pci_oxsemi_tornado_setup,
2647 },
2648 {
2649 .vendor = PCI_VENDOR_ID_INTASHIELD,
2650 .device = 0x400E,
2651 .subvendor = PCI_ANY_ID,
2652 .subdevice = PCI_ANY_ID,
2653 .init = pci_oxsemi_tornado_init,
2654 .setup = pci_oxsemi_tornado_setup,
2655 },
2656 {
2657 .vendor = PCI_VENDOR_ID_INTASHIELD,
2658 .device = 0x400C,
2659 .subvendor = PCI_ANY_ID,
2660 .subdevice = PCI_ANY_ID,
2661 .init = pci_oxsemi_tornado_init,
2662 .setup = pci_oxsemi_tornado_setup,
2663 },
2664 {
2665 .vendor = PCI_VENDOR_ID_INTASHIELD,
2666 .device = 0x400B,
2667 .subvendor = PCI_ANY_ID,
2668 .subdevice = PCI_ANY_ID,
2669 .init = pci_oxsemi_tornado_init,
2670 .setup = pci_oxsemi_tornado_setup,
2671 },
2672 {
2673 .vendor = PCI_VENDOR_ID_INTASHIELD,
2674 .device = 0x400F,
2675 .subvendor = PCI_ANY_ID,
2676 .subdevice = PCI_ANY_ID,
2677 .init = pci_oxsemi_tornado_init,
2678 .setup = pci_oxsemi_tornado_setup,
2679 },
2680 {
2681 .vendor = PCI_VENDOR_ID_INTASHIELD,
2682 .device = 0x4010,
2683 .subvendor = PCI_ANY_ID,
2684 .subdevice = PCI_ANY_ID,
2685 .init = pci_oxsemi_tornado_init,
2686 .setup = pci_oxsemi_tornado_setup,
2687 },
2688 {
2689 .vendor = PCI_VENDOR_ID_INTASHIELD,
2690 .device = 0x4011,
2691 .subvendor = PCI_ANY_ID,
2692 .subdevice = PCI_ANY_ID,
2693 .init = pci_oxsemi_tornado_init,
2694 .setup = pci_oxsemi_tornado_setup,
2695 },
2696 {
2697 .vendor = PCI_VENDOR_ID_INTASHIELD,
2698 .device = 0x401D,
2699 .subvendor = PCI_ANY_ID,
2700 .subdevice = PCI_ANY_ID,
2701 .init = pci_oxsemi_tornado_init,
2702 .setup = pci_oxsemi_tornado_setup,
2703 },
2704 {
2705 .vendor = PCI_VENDOR_ID_INTASHIELD,
2706 .device = 0x401E,
2707 .subvendor = PCI_ANY_ID,
2708 .subdevice = PCI_ANY_ID,
2709 .init = pci_oxsemi_tornado_init,
2710 .setup = pci_oxsemi_tornado_setup,
2711 },
2712 {
2713 .vendor = PCI_VENDOR_ID_INTASHIELD,
2714 .device = 0x4013,
2715 .subvendor = PCI_ANY_ID,
2716 .subdevice = PCI_ANY_ID,
2717 .init = pci_oxsemi_tornado_init,
2718 .setup = pci_oxsemi_tornado_setup,
2719 },
2720 {
2721 .vendor = PCI_VENDOR_ID_INTASHIELD,
2722 .device = 0x4017,
2723 .subvendor = PCI_ANY_ID,
2724 .subdevice = PCI_ANY_ID,
2725 .init = pci_oxsemi_tornado_init,
2726 .setup = pci_oxsemi_tornado_setup,
2727 },
2728 {
2729 .vendor = PCI_VENDOR_ID_INTASHIELD,
2730 .device = 0x4018,
2731 .subvendor = PCI_ANY_ID,
2732 .subdevice = PCI_ANY_ID,
2733 .init = pci_oxsemi_tornado_init,
2734 .setup = pci_oxsemi_tornado_setup,
2735 },
2736 {
2737 .vendor = PCI_VENDOR_ID_INTEL,
2738 .device = 0x8811,
2739 .subvendor = PCI_ANY_ID,
2740 .subdevice = PCI_ANY_ID,
2741 .init = pci_eg20t_init,
2742 .setup = pci_default_setup,
2743 },
2744 {
2745 .vendor = PCI_VENDOR_ID_INTEL,
2746 .device = 0x8812,
2747 .subvendor = PCI_ANY_ID,
2748 .subdevice = PCI_ANY_ID,
2749 .init = pci_eg20t_init,
2750 .setup = pci_default_setup,
2751 },
2752 {
2753 .vendor = PCI_VENDOR_ID_INTEL,
2754 .device = 0x8813,
2755 .subvendor = PCI_ANY_ID,
2756 .subdevice = PCI_ANY_ID,
2757 .init = pci_eg20t_init,
2758 .setup = pci_default_setup,
2759 },
2760 {
2761 .vendor = PCI_VENDOR_ID_INTEL,
2762 .device = 0x8814,
2763 .subvendor = PCI_ANY_ID,
2764 .subdevice = PCI_ANY_ID,
2765 .init = pci_eg20t_init,
2766 .setup = pci_default_setup,
2767 },
2768 {
2769 .vendor = 0x10DB,
2770 .device = 0x8027,
2771 .subvendor = PCI_ANY_ID,
2772 .subdevice = PCI_ANY_ID,
2773 .init = pci_eg20t_init,
2774 .setup = pci_default_setup,
2775 },
2776 {
2777 .vendor = 0x10DB,
2778 .device = 0x8028,
2779 .subvendor = PCI_ANY_ID,
2780 .subdevice = PCI_ANY_ID,
2781 .init = pci_eg20t_init,
2782 .setup = pci_default_setup,
2783 },
2784 {
2785 .vendor = 0x10DB,
2786 .device = 0x8029,
2787 .subvendor = PCI_ANY_ID,
2788 .subdevice = PCI_ANY_ID,
2789 .init = pci_eg20t_init,
2790 .setup = pci_default_setup,
2791 },
2792 {
2793 .vendor = 0x10DB,
2794 .device = 0x800C,
2795 .subvendor = PCI_ANY_ID,
2796 .subdevice = PCI_ANY_ID,
2797 .init = pci_eg20t_init,
2798 .setup = pci_default_setup,
2799 },
2800 {
2801 .vendor = 0x10DB,
2802 .device = 0x800D,
2803 .subvendor = PCI_ANY_ID,
2804 .subdevice = PCI_ANY_ID,
2805 .init = pci_eg20t_init,
2806 .setup = pci_default_setup,
2807 },
2808 /*
2809 * Cronyx Omega PCI (PLX-chip based)
2810 */
2811 {
2812 .vendor = PCI_VENDOR_ID_PLX,
2813 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2814 .subvendor = PCI_ANY_ID,
2815 .subdevice = PCI_ANY_ID,
2816 .setup = pci_omegapci_setup,
2817 },
2818 /* WCH CH353 1S1P card (16550 clone) */
2819 {
2820 .vendor = PCI_VENDOR_ID_WCH,
2821 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2822 .subvendor = PCI_ANY_ID,
2823 .subdevice = PCI_ANY_ID,
2824 .setup = pci_wch_ch353_setup,
2825 },
2826 /* WCH CH353 2S1P card (16550 clone) */
2827 {
2828 .vendor = PCI_VENDOR_ID_WCH,
2829 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2830 .subvendor = PCI_ANY_ID,
2831 .subdevice = PCI_ANY_ID,
2832 .setup = pci_wch_ch353_setup,
2833 },
2834 /* WCH CH353 4S card (16550 clone) */
2835 {
2836 .vendor = PCI_VENDOR_ID_WCH,
2837 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2838 .subvendor = PCI_ANY_ID,
2839 .subdevice = PCI_ANY_ID,
2840 .setup = pci_wch_ch353_setup,
2841 },
2842 /* WCH CH353 2S1PF card (16550 clone) */
2843 {
2844 .vendor = PCI_VENDOR_ID_WCH,
2845 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2846 .subvendor = PCI_ANY_ID,
2847 .subdevice = PCI_ANY_ID,
2848 .setup = pci_wch_ch353_setup,
2849 },
2850 /* WCH CH352 2S card (16550 clone) */
2851 {
2852 .vendor = PCI_VENDOR_ID_WCH,
2853 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2854 .subvendor = PCI_ANY_ID,
2855 .subdevice = PCI_ANY_ID,
2856 .setup = pci_wch_ch353_setup,
2857 },
2858 /* WCH CH355 4S card (16550 clone) */
2859 {
2860 .vendor = PCI_VENDOR_ID_WCH,
2861 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2862 .subvendor = PCI_ANY_ID,
2863 .subdevice = PCI_ANY_ID,
2864 .setup = pci_wch_ch355_setup,
2865 },
2866 /* WCH CH382 2S card (16850 clone) */
2867 {
2868 .vendor = PCIE_VENDOR_ID_WCH,
2869 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2870 .subvendor = PCI_ANY_ID,
2871 .subdevice = PCI_ANY_ID,
2872 .setup = pci_wch_ch38x_setup,
2873 },
2874 /* WCH CH382 2S1P card (16850 clone) */
2875 {
2876 .vendor = PCIE_VENDOR_ID_WCH,
2877 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2878 .subvendor = PCI_ANY_ID,
2879 .subdevice = PCI_ANY_ID,
2880 .setup = pci_wch_ch38x_setup,
2881 },
2882 /* WCH CH384 4S card (16850 clone) */
2883 {
2884 .vendor = PCIE_VENDOR_ID_WCH,
2885 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2886 .subvendor = PCI_ANY_ID,
2887 .subdevice = PCI_ANY_ID,
2888 .setup = pci_wch_ch38x_setup,
2889 },
2890 /* WCH CH384 8S card (16850 clone) */
2891 {
2892 .vendor = PCIE_VENDOR_ID_WCH,
2893 .device = PCIE_DEVICE_ID_WCH_CH384_8S,
2894 .subvendor = PCI_ANY_ID,
2895 .subdevice = PCI_ANY_ID,
2896 .init = pci_wch_ch38x_init,
2897 .exit = pci_wch_ch38x_exit,
2898 .setup = pci_wch_ch38x_setup,
2899 },
2900 /*
2901 * Broadcom TruManage (NetXtreme)
2902 */
2903 {
2904 .vendor = PCI_VENDOR_ID_BROADCOM,
2905 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2906 .subvendor = PCI_ANY_ID,
2907 .subdevice = PCI_ANY_ID,
2908 .setup = pci_brcm_trumanage_setup,
2909 },
2910 {
2911 .vendor = 0x1c29,
2912 .device = 0x1104,
2913 .subvendor = PCI_ANY_ID,
2914 .subdevice = PCI_ANY_ID,
2915 .setup = pci_fintek_setup,
2916 .init = pci_fintek_init,
2917 },
2918 {
2919 .vendor = 0x1c29,
2920 .device = 0x1108,
2921 .subvendor = PCI_ANY_ID,
2922 .subdevice = PCI_ANY_ID,
2923 .setup = pci_fintek_setup,
2924 .init = pci_fintek_init,
2925 },
2926 {
2927 .vendor = 0x1c29,
2928 .device = 0x1112,
2929 .subvendor = PCI_ANY_ID,
2930 .subdevice = PCI_ANY_ID,
2931 .setup = pci_fintek_setup,
2932 .init = pci_fintek_init,
2933 },
2934 /*
2935 * MOXA
2936 */
2937 {
2938 .vendor = PCI_VENDOR_ID_MOXA,
2939 .device = PCI_ANY_ID,
2940 .subvendor = PCI_ANY_ID,
2941 .subdevice = PCI_ANY_ID,
2942 .init = pci_moxa_init,
2943 .setup = pci_moxa_setup,
2944 },
2945 {
2946 .vendor = 0x1c29,
2947 .device = 0x1204,
2948 .subvendor = PCI_ANY_ID,
2949 .subdevice = PCI_ANY_ID,
2950 .setup = pci_fintek_f815xxa_setup,
2951 .init = pci_fintek_f815xxa_init,
2952 },
2953 {
2954 .vendor = 0x1c29,
2955 .device = 0x1208,
2956 .subvendor = PCI_ANY_ID,
2957 .subdevice = PCI_ANY_ID,
2958 .setup = pci_fintek_f815xxa_setup,
2959 .init = pci_fintek_f815xxa_init,
2960 },
2961 {
2962 .vendor = 0x1c29,
2963 .device = 0x1212,
2964 .subvendor = PCI_ANY_ID,
2965 .subdevice = PCI_ANY_ID,
2966 .setup = pci_fintek_f815xxa_setup,
2967 .init = pci_fintek_f815xxa_init,
2968 },
2969
2970 /*
2971 * Default "match everything" terminator entry
2972 */
2973 {
2974 .vendor = PCI_ANY_ID,
2975 .device = PCI_ANY_ID,
2976 .subvendor = PCI_ANY_ID,
2977 .subdevice = PCI_ANY_ID,
2978 .setup = pci_default_setup,
2979 }
2980 };
2981
quirk_id_matches(u32 quirk_id,u32 dev_id)2982 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2983 {
2984 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2985 }
2986
find_quirk(struct pci_dev * dev)2987 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2988 {
2989 struct pci_serial_quirk *quirk;
2990
2991 for (quirk = pci_serial_quirks; ; quirk++)
2992 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2993 quirk_id_matches(quirk->device, dev->device) &&
2994 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2995 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2996 break;
2997 return quirk;
2998 }
2999
3000 /*
3001 * This is the configuration table for all of the PCI serial boards
3002 * which we support. It is directly indexed by the pci_board_num_t enum
3003 * value, which is encoded in the pci_device_id PCI probe table's
3004 * driver_data member.
3005 *
3006 * The makeup of these names are:
3007 * pbn_bn{_bt}_n_baud{_offsetinhex}
3008 *
3009 * bn = PCI BAR number
3010 * bt = Index using PCI BARs
3011 * n = number of serial ports
3012 * baud = baud rate
3013 * offsetinhex = offset for each sequential port (in hex)
3014 *
3015 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
3016 *
3017 * Please note: in theory if n = 1, _bt infix should make no difference.
3018 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
3019 */
3020 enum pci_board_num_t {
3021 pbn_default = 0,
3022
3023 pbn_b0_1_115200,
3024 pbn_b0_2_115200,
3025 pbn_b0_4_115200,
3026 pbn_b0_5_115200,
3027 pbn_b0_8_115200,
3028
3029 pbn_b0_1_921600,
3030 pbn_b0_2_921600,
3031 pbn_b0_4_921600,
3032
3033 pbn_b0_2_1130000,
3034
3035 pbn_b0_4_1152000,
3036
3037 pbn_b0_4_1250000,
3038
3039 pbn_b0_2_1843200,
3040 pbn_b0_4_1843200,
3041
3042 pbn_b0_1_15625000,
3043
3044 pbn_b0_bt_1_115200,
3045 pbn_b0_bt_2_115200,
3046 pbn_b0_bt_4_115200,
3047 pbn_b0_bt_8_115200,
3048
3049 pbn_b0_bt_1_460800,
3050 pbn_b0_bt_2_460800,
3051 pbn_b0_bt_4_460800,
3052
3053 pbn_b0_bt_1_921600,
3054 pbn_b0_bt_2_921600,
3055 pbn_b0_bt_4_921600,
3056 pbn_b0_bt_8_921600,
3057
3058 pbn_b1_1_115200,
3059 pbn_b1_2_115200,
3060 pbn_b1_4_115200,
3061 pbn_b1_8_115200,
3062 pbn_b1_16_115200,
3063
3064 pbn_b1_1_921600,
3065 pbn_b1_2_921600,
3066 pbn_b1_4_921600,
3067 pbn_b1_8_921600,
3068
3069 pbn_b1_2_1250000,
3070
3071 pbn_b1_bt_1_115200,
3072 pbn_b1_bt_2_115200,
3073 pbn_b1_bt_4_115200,
3074
3075 pbn_b1_bt_2_921600,
3076
3077 pbn_b1_1_1382400,
3078 pbn_b1_2_1382400,
3079 pbn_b1_4_1382400,
3080 pbn_b1_8_1382400,
3081
3082 pbn_b2_1_115200,
3083 pbn_b2_2_115200,
3084 pbn_b2_4_115200,
3085 pbn_b2_8_115200,
3086
3087 pbn_b2_1_460800,
3088 pbn_b2_4_460800,
3089 pbn_b2_8_460800,
3090 pbn_b2_16_460800,
3091
3092 pbn_b2_1_921600,
3093 pbn_b2_4_921600,
3094 pbn_b2_8_921600,
3095
3096 pbn_b2_8_1152000,
3097
3098 pbn_b2_bt_1_115200,
3099 pbn_b2_bt_2_115200,
3100 pbn_b2_bt_4_115200,
3101
3102 pbn_b2_bt_2_921600,
3103 pbn_b2_bt_4_921600,
3104
3105 pbn_b3_2_115200,
3106 pbn_b3_4_115200,
3107 pbn_b3_8_115200,
3108
3109 pbn_b4_bt_2_921600,
3110 pbn_b4_bt_4_921600,
3111 pbn_b4_bt_8_921600,
3112
3113 /*
3114 * Board-specific versions.
3115 */
3116 pbn_panacom,
3117 pbn_panacom2,
3118 pbn_panacom4,
3119 pbn_plx_romulus,
3120 pbn_oxsemi,
3121 pbn_oxsemi_1_15625000,
3122 pbn_oxsemi_2_15625000,
3123 pbn_oxsemi_4_15625000,
3124 pbn_oxsemi_8_15625000,
3125 pbn_intel_i960,
3126 pbn_sgi_ioc3,
3127 pbn_computone_4,
3128 pbn_computone_6,
3129 pbn_computone_8,
3130 pbn_sbsxrsio,
3131 pbn_pasemi_1682M,
3132 pbn_ni8430_2,
3133 pbn_ni8430_4,
3134 pbn_ni8430_8,
3135 pbn_ni8430_16,
3136 pbn_ADDIDATA_PCIe_1_3906250,
3137 pbn_ADDIDATA_PCIe_2_3906250,
3138 pbn_ADDIDATA_PCIe_4_3906250,
3139 pbn_ADDIDATA_PCIe_8_3906250,
3140 pbn_ce4100_1_115200,
3141 pbn_omegapci,
3142 pbn_NETMOS9900_2s_115200,
3143 pbn_brcm_trumanage,
3144 pbn_fintek_4,
3145 pbn_fintek_8,
3146 pbn_fintek_12,
3147 pbn_fintek_F81504A,
3148 pbn_fintek_F81508A,
3149 pbn_fintek_F81512A,
3150 pbn_wch382_2,
3151 pbn_wch384_4,
3152 pbn_wch384_8,
3153 pbn_sunix_pci_1s,
3154 pbn_sunix_pci_2s,
3155 pbn_sunix_pci_4s,
3156 pbn_sunix_pci_8s,
3157 pbn_sunix_pci_16s,
3158 pbn_titan_1_4000000,
3159 pbn_titan_2_4000000,
3160 pbn_titan_4_4000000,
3161 pbn_titan_8_4000000,
3162 pbn_moxa_2,
3163 pbn_moxa_4,
3164 pbn_moxa_8,
3165 };
3166
3167 /*
3168 * uart_offset - the space between channels
3169 * reg_shift - describes how the UART registers are mapped
3170 * to PCI memory by the card.
3171 * For example IER register on SBS, Inc. PMC-OctPro is located at
3172 * offset 0x10 from the UART base, while UART_IER is defined as 1
3173 * in include/linux/serial_reg.h,
3174 * see first lines of serial_in() and serial_out() in 8250.c
3175 */
3176
3177 static struct pciserial_board pci_boards[] = {
3178 [pbn_default] = {
3179 .flags = FL_BASE0,
3180 .num_ports = 1,
3181 .base_baud = 115200,
3182 .uart_offset = 8,
3183 },
3184 [pbn_b0_1_115200] = {
3185 .flags = FL_BASE0,
3186 .num_ports = 1,
3187 .base_baud = 115200,
3188 .uart_offset = 8,
3189 },
3190 [pbn_b0_2_115200] = {
3191 .flags = FL_BASE0,
3192 .num_ports = 2,
3193 .base_baud = 115200,
3194 .uart_offset = 8,
3195 },
3196 [pbn_b0_4_115200] = {
3197 .flags = FL_BASE0,
3198 .num_ports = 4,
3199 .base_baud = 115200,
3200 .uart_offset = 8,
3201 },
3202 [pbn_b0_5_115200] = {
3203 .flags = FL_BASE0,
3204 .num_ports = 5,
3205 .base_baud = 115200,
3206 .uart_offset = 8,
3207 },
3208 [pbn_b0_8_115200] = {
3209 .flags = FL_BASE0,
3210 .num_ports = 8,
3211 .base_baud = 115200,
3212 .uart_offset = 8,
3213 },
3214 [pbn_b0_1_921600] = {
3215 .flags = FL_BASE0,
3216 .num_ports = 1,
3217 .base_baud = 921600,
3218 .uart_offset = 8,
3219 },
3220 [pbn_b0_2_921600] = {
3221 .flags = FL_BASE0,
3222 .num_ports = 2,
3223 .base_baud = 921600,
3224 .uart_offset = 8,
3225 },
3226 [pbn_b0_4_921600] = {
3227 .flags = FL_BASE0,
3228 .num_ports = 4,
3229 .base_baud = 921600,
3230 .uart_offset = 8,
3231 },
3232
3233 [pbn_b0_2_1130000] = {
3234 .flags = FL_BASE0,
3235 .num_ports = 2,
3236 .base_baud = 1130000,
3237 .uart_offset = 8,
3238 },
3239
3240 [pbn_b0_4_1152000] = {
3241 .flags = FL_BASE0,
3242 .num_ports = 4,
3243 .base_baud = 1152000,
3244 .uart_offset = 8,
3245 },
3246
3247 [pbn_b0_4_1250000] = {
3248 .flags = FL_BASE0,
3249 .num_ports = 4,
3250 .base_baud = 1250000,
3251 .uart_offset = 8,
3252 },
3253
3254 [pbn_b0_2_1843200] = {
3255 .flags = FL_BASE0,
3256 .num_ports = 2,
3257 .base_baud = 1843200,
3258 .uart_offset = 8,
3259 },
3260 [pbn_b0_4_1843200] = {
3261 .flags = FL_BASE0,
3262 .num_ports = 4,
3263 .base_baud = 1843200,
3264 .uart_offset = 8,
3265 },
3266
3267 [pbn_b0_1_15625000] = {
3268 .flags = FL_BASE0,
3269 .num_ports = 1,
3270 .base_baud = 15625000,
3271 .uart_offset = 8,
3272 },
3273
3274 [pbn_b0_bt_1_115200] = {
3275 .flags = FL_BASE0|FL_BASE_BARS,
3276 .num_ports = 1,
3277 .base_baud = 115200,
3278 .uart_offset = 8,
3279 },
3280 [pbn_b0_bt_2_115200] = {
3281 .flags = FL_BASE0|FL_BASE_BARS,
3282 .num_ports = 2,
3283 .base_baud = 115200,
3284 .uart_offset = 8,
3285 },
3286 [pbn_b0_bt_4_115200] = {
3287 .flags = FL_BASE0|FL_BASE_BARS,
3288 .num_ports = 4,
3289 .base_baud = 115200,
3290 .uart_offset = 8,
3291 },
3292 [pbn_b0_bt_8_115200] = {
3293 .flags = FL_BASE0|FL_BASE_BARS,
3294 .num_ports = 8,
3295 .base_baud = 115200,
3296 .uart_offset = 8,
3297 },
3298
3299 [pbn_b0_bt_1_460800] = {
3300 .flags = FL_BASE0|FL_BASE_BARS,
3301 .num_ports = 1,
3302 .base_baud = 460800,
3303 .uart_offset = 8,
3304 },
3305 [pbn_b0_bt_2_460800] = {
3306 .flags = FL_BASE0|FL_BASE_BARS,
3307 .num_ports = 2,
3308 .base_baud = 460800,
3309 .uart_offset = 8,
3310 },
3311 [pbn_b0_bt_4_460800] = {
3312 .flags = FL_BASE0|FL_BASE_BARS,
3313 .num_ports = 4,
3314 .base_baud = 460800,
3315 .uart_offset = 8,
3316 },
3317
3318 [pbn_b0_bt_1_921600] = {
3319 .flags = FL_BASE0|FL_BASE_BARS,
3320 .num_ports = 1,
3321 .base_baud = 921600,
3322 .uart_offset = 8,
3323 },
3324 [pbn_b0_bt_2_921600] = {
3325 .flags = FL_BASE0|FL_BASE_BARS,
3326 .num_ports = 2,
3327 .base_baud = 921600,
3328 .uart_offset = 8,
3329 },
3330 [pbn_b0_bt_4_921600] = {
3331 .flags = FL_BASE0|FL_BASE_BARS,
3332 .num_ports = 4,
3333 .base_baud = 921600,
3334 .uart_offset = 8,
3335 },
3336 [pbn_b0_bt_8_921600] = {
3337 .flags = FL_BASE0|FL_BASE_BARS,
3338 .num_ports = 8,
3339 .base_baud = 921600,
3340 .uart_offset = 8,
3341 },
3342
3343 [pbn_b1_1_115200] = {
3344 .flags = FL_BASE1,
3345 .num_ports = 1,
3346 .base_baud = 115200,
3347 .uart_offset = 8,
3348 },
3349 [pbn_b1_2_115200] = {
3350 .flags = FL_BASE1,
3351 .num_ports = 2,
3352 .base_baud = 115200,
3353 .uart_offset = 8,
3354 },
3355 [pbn_b1_4_115200] = {
3356 .flags = FL_BASE1,
3357 .num_ports = 4,
3358 .base_baud = 115200,
3359 .uart_offset = 8,
3360 },
3361 [pbn_b1_8_115200] = {
3362 .flags = FL_BASE1,
3363 .num_ports = 8,
3364 .base_baud = 115200,
3365 .uart_offset = 8,
3366 },
3367 [pbn_b1_16_115200] = {
3368 .flags = FL_BASE1,
3369 .num_ports = 16,
3370 .base_baud = 115200,
3371 .uart_offset = 8,
3372 },
3373
3374 [pbn_b1_1_921600] = {
3375 .flags = FL_BASE1,
3376 .num_ports = 1,
3377 .base_baud = 921600,
3378 .uart_offset = 8,
3379 },
3380 [pbn_b1_2_921600] = {
3381 .flags = FL_BASE1,
3382 .num_ports = 2,
3383 .base_baud = 921600,
3384 .uart_offset = 8,
3385 },
3386 [pbn_b1_4_921600] = {
3387 .flags = FL_BASE1,
3388 .num_ports = 4,
3389 .base_baud = 921600,
3390 .uart_offset = 8,
3391 },
3392 [pbn_b1_8_921600] = {
3393 .flags = FL_BASE1,
3394 .num_ports = 8,
3395 .base_baud = 921600,
3396 .uart_offset = 8,
3397 },
3398 [pbn_b1_2_1250000] = {
3399 .flags = FL_BASE1,
3400 .num_ports = 2,
3401 .base_baud = 1250000,
3402 .uart_offset = 8,
3403 },
3404
3405 [pbn_b1_bt_1_115200] = {
3406 .flags = FL_BASE1|FL_BASE_BARS,
3407 .num_ports = 1,
3408 .base_baud = 115200,
3409 .uart_offset = 8,
3410 },
3411 [pbn_b1_bt_2_115200] = {
3412 .flags = FL_BASE1|FL_BASE_BARS,
3413 .num_ports = 2,
3414 .base_baud = 115200,
3415 .uart_offset = 8,
3416 },
3417 [pbn_b1_bt_4_115200] = {
3418 .flags = FL_BASE1|FL_BASE_BARS,
3419 .num_ports = 4,
3420 .base_baud = 115200,
3421 .uart_offset = 8,
3422 },
3423
3424 [pbn_b1_bt_2_921600] = {
3425 .flags = FL_BASE1|FL_BASE_BARS,
3426 .num_ports = 2,
3427 .base_baud = 921600,
3428 .uart_offset = 8,
3429 },
3430
3431 [pbn_b1_1_1382400] = {
3432 .flags = FL_BASE1,
3433 .num_ports = 1,
3434 .base_baud = 1382400,
3435 .uart_offset = 8,
3436 },
3437 [pbn_b1_2_1382400] = {
3438 .flags = FL_BASE1,
3439 .num_ports = 2,
3440 .base_baud = 1382400,
3441 .uart_offset = 8,
3442 },
3443 [pbn_b1_4_1382400] = {
3444 .flags = FL_BASE1,
3445 .num_ports = 4,
3446 .base_baud = 1382400,
3447 .uart_offset = 8,
3448 },
3449 [pbn_b1_8_1382400] = {
3450 .flags = FL_BASE1,
3451 .num_ports = 8,
3452 .base_baud = 1382400,
3453 .uart_offset = 8,
3454 },
3455
3456 [pbn_b2_1_115200] = {
3457 .flags = FL_BASE2,
3458 .num_ports = 1,
3459 .base_baud = 115200,
3460 .uart_offset = 8,
3461 },
3462 [pbn_b2_2_115200] = {
3463 .flags = FL_BASE2,
3464 .num_ports = 2,
3465 .base_baud = 115200,
3466 .uart_offset = 8,
3467 },
3468 [pbn_b2_4_115200] = {
3469 .flags = FL_BASE2,
3470 .num_ports = 4,
3471 .base_baud = 115200,
3472 .uart_offset = 8,
3473 },
3474 [pbn_b2_8_115200] = {
3475 .flags = FL_BASE2,
3476 .num_ports = 8,
3477 .base_baud = 115200,
3478 .uart_offset = 8,
3479 },
3480
3481 [pbn_b2_1_460800] = {
3482 .flags = FL_BASE2,
3483 .num_ports = 1,
3484 .base_baud = 460800,
3485 .uart_offset = 8,
3486 },
3487 [pbn_b2_4_460800] = {
3488 .flags = FL_BASE2,
3489 .num_ports = 4,
3490 .base_baud = 460800,
3491 .uart_offset = 8,
3492 },
3493 [pbn_b2_8_460800] = {
3494 .flags = FL_BASE2,
3495 .num_ports = 8,
3496 .base_baud = 460800,
3497 .uart_offset = 8,
3498 },
3499 [pbn_b2_16_460800] = {
3500 .flags = FL_BASE2,
3501 .num_ports = 16,
3502 .base_baud = 460800,
3503 .uart_offset = 8,
3504 },
3505
3506 [pbn_b2_1_921600] = {
3507 .flags = FL_BASE2,
3508 .num_ports = 1,
3509 .base_baud = 921600,
3510 .uart_offset = 8,
3511 },
3512 [pbn_b2_4_921600] = {
3513 .flags = FL_BASE2,
3514 .num_ports = 4,
3515 .base_baud = 921600,
3516 .uart_offset = 8,
3517 },
3518 [pbn_b2_8_921600] = {
3519 .flags = FL_BASE2,
3520 .num_ports = 8,
3521 .base_baud = 921600,
3522 .uart_offset = 8,
3523 },
3524
3525 [pbn_b2_8_1152000] = {
3526 .flags = FL_BASE2,
3527 .num_ports = 8,
3528 .base_baud = 1152000,
3529 .uart_offset = 8,
3530 },
3531
3532 [pbn_b2_bt_1_115200] = {
3533 .flags = FL_BASE2|FL_BASE_BARS,
3534 .num_ports = 1,
3535 .base_baud = 115200,
3536 .uart_offset = 8,
3537 },
3538 [pbn_b2_bt_2_115200] = {
3539 .flags = FL_BASE2|FL_BASE_BARS,
3540 .num_ports = 2,
3541 .base_baud = 115200,
3542 .uart_offset = 8,
3543 },
3544 [pbn_b2_bt_4_115200] = {
3545 .flags = FL_BASE2|FL_BASE_BARS,
3546 .num_ports = 4,
3547 .base_baud = 115200,
3548 .uart_offset = 8,
3549 },
3550
3551 [pbn_b2_bt_2_921600] = {
3552 .flags = FL_BASE2|FL_BASE_BARS,
3553 .num_ports = 2,
3554 .base_baud = 921600,
3555 .uart_offset = 8,
3556 },
3557 [pbn_b2_bt_4_921600] = {
3558 .flags = FL_BASE2|FL_BASE_BARS,
3559 .num_ports = 4,
3560 .base_baud = 921600,
3561 .uart_offset = 8,
3562 },
3563
3564 [pbn_b3_2_115200] = {
3565 .flags = FL_BASE3,
3566 .num_ports = 2,
3567 .base_baud = 115200,
3568 .uart_offset = 8,
3569 },
3570 [pbn_b3_4_115200] = {
3571 .flags = FL_BASE3,
3572 .num_ports = 4,
3573 .base_baud = 115200,
3574 .uart_offset = 8,
3575 },
3576 [pbn_b3_8_115200] = {
3577 .flags = FL_BASE3,
3578 .num_ports = 8,
3579 .base_baud = 115200,
3580 .uart_offset = 8,
3581 },
3582
3583 [pbn_b4_bt_2_921600] = {
3584 .flags = FL_BASE4,
3585 .num_ports = 2,
3586 .base_baud = 921600,
3587 .uart_offset = 8,
3588 },
3589 [pbn_b4_bt_4_921600] = {
3590 .flags = FL_BASE4,
3591 .num_ports = 4,
3592 .base_baud = 921600,
3593 .uart_offset = 8,
3594 },
3595 [pbn_b4_bt_8_921600] = {
3596 .flags = FL_BASE4,
3597 .num_ports = 8,
3598 .base_baud = 921600,
3599 .uart_offset = 8,
3600 },
3601
3602 /*
3603 * Entries following this are board-specific.
3604 */
3605
3606 /*
3607 * Panacom - IOMEM
3608 */
3609 [pbn_panacom] = {
3610 .flags = FL_BASE2,
3611 .num_ports = 2,
3612 .base_baud = 921600,
3613 .uart_offset = 0x400,
3614 .reg_shift = 7,
3615 },
3616 [pbn_panacom2] = {
3617 .flags = FL_BASE2|FL_BASE_BARS,
3618 .num_ports = 2,
3619 .base_baud = 921600,
3620 .uart_offset = 0x400,
3621 .reg_shift = 7,
3622 },
3623 [pbn_panacom4] = {
3624 .flags = FL_BASE2|FL_BASE_BARS,
3625 .num_ports = 4,
3626 .base_baud = 921600,
3627 .uart_offset = 0x400,
3628 .reg_shift = 7,
3629 },
3630
3631 /* I think this entry is broken - the first_offset looks wrong --rmk */
3632 [pbn_plx_romulus] = {
3633 .flags = FL_BASE2,
3634 .num_ports = 4,
3635 .base_baud = 921600,
3636 .uart_offset = 8 << 2,
3637 .reg_shift = 2,
3638 .first_offset = 0x03,
3639 },
3640
3641 /*
3642 * This board uses the size of PCI Base region 0 to
3643 * signal now many ports are available
3644 */
3645 [pbn_oxsemi] = {
3646 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3647 .num_ports = 32,
3648 .base_baud = 115200,
3649 .uart_offset = 8,
3650 },
3651 [pbn_oxsemi_1_15625000] = {
3652 .flags = FL_BASE0,
3653 .num_ports = 1,
3654 .base_baud = 15625000,
3655 .uart_offset = 0x200,
3656 .first_offset = 0x1000,
3657 },
3658 [pbn_oxsemi_2_15625000] = {
3659 .flags = FL_BASE0,
3660 .num_ports = 2,
3661 .base_baud = 15625000,
3662 .uart_offset = 0x200,
3663 .first_offset = 0x1000,
3664 },
3665 [pbn_oxsemi_4_15625000] = {
3666 .flags = FL_BASE0,
3667 .num_ports = 4,
3668 .base_baud = 15625000,
3669 .uart_offset = 0x200,
3670 .first_offset = 0x1000,
3671 },
3672 [pbn_oxsemi_8_15625000] = {
3673 .flags = FL_BASE0,
3674 .num_ports = 8,
3675 .base_baud = 15625000,
3676 .uart_offset = 0x200,
3677 .first_offset = 0x1000,
3678 },
3679
3680
3681 /*
3682 * EKF addition for i960 Boards form EKF with serial port.
3683 * Max 256 ports.
3684 */
3685 [pbn_intel_i960] = {
3686 .flags = FL_BASE0,
3687 .num_ports = 32,
3688 .base_baud = 921600,
3689 .uart_offset = 8 << 2,
3690 .reg_shift = 2,
3691 .first_offset = 0x10000,
3692 },
3693 [pbn_sgi_ioc3] = {
3694 .flags = FL_BASE0|FL_NOIRQ,
3695 .num_ports = 1,
3696 .base_baud = 458333,
3697 .uart_offset = 8,
3698 .reg_shift = 0,
3699 .first_offset = 0x20178,
3700 },
3701
3702 /*
3703 * Computone - uses IOMEM.
3704 */
3705 [pbn_computone_4] = {
3706 .flags = FL_BASE0,
3707 .num_ports = 4,
3708 .base_baud = 921600,
3709 .uart_offset = 0x40,
3710 .reg_shift = 2,
3711 .first_offset = 0x200,
3712 },
3713 [pbn_computone_6] = {
3714 .flags = FL_BASE0,
3715 .num_ports = 6,
3716 .base_baud = 921600,
3717 .uart_offset = 0x40,
3718 .reg_shift = 2,
3719 .first_offset = 0x200,
3720 },
3721 [pbn_computone_8] = {
3722 .flags = FL_BASE0,
3723 .num_ports = 8,
3724 .base_baud = 921600,
3725 .uart_offset = 0x40,
3726 .reg_shift = 2,
3727 .first_offset = 0x200,
3728 },
3729 [pbn_sbsxrsio] = {
3730 .flags = FL_BASE0,
3731 .num_ports = 8,
3732 .base_baud = 460800,
3733 .uart_offset = 256,
3734 .reg_shift = 4,
3735 },
3736 /*
3737 * PA Semi PWRficient PA6T-1682M on-chip UART
3738 */
3739 [pbn_pasemi_1682M] = {
3740 .flags = FL_BASE0,
3741 .num_ports = 1,
3742 .base_baud = 8333333,
3743 },
3744 /*
3745 * National Instruments 843x
3746 */
3747 [pbn_ni8430_16] = {
3748 .flags = FL_BASE0,
3749 .num_ports = 16,
3750 .base_baud = 3686400,
3751 .uart_offset = 0x10,
3752 .first_offset = 0x800,
3753 },
3754 [pbn_ni8430_8] = {
3755 .flags = FL_BASE0,
3756 .num_ports = 8,
3757 .base_baud = 3686400,
3758 .uart_offset = 0x10,
3759 .first_offset = 0x800,
3760 },
3761 [pbn_ni8430_4] = {
3762 .flags = FL_BASE0,
3763 .num_ports = 4,
3764 .base_baud = 3686400,
3765 .uart_offset = 0x10,
3766 .first_offset = 0x800,
3767 },
3768 [pbn_ni8430_2] = {
3769 .flags = FL_BASE0,
3770 .num_ports = 2,
3771 .base_baud = 3686400,
3772 .uart_offset = 0x10,
3773 .first_offset = 0x800,
3774 },
3775 /*
3776 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3777 */
3778 [pbn_ADDIDATA_PCIe_1_3906250] = {
3779 .flags = FL_BASE0,
3780 .num_ports = 1,
3781 .base_baud = 3906250,
3782 .uart_offset = 0x200,
3783 .first_offset = 0x1000,
3784 },
3785 [pbn_ADDIDATA_PCIe_2_3906250] = {
3786 .flags = FL_BASE0,
3787 .num_ports = 2,
3788 .base_baud = 3906250,
3789 .uart_offset = 0x200,
3790 .first_offset = 0x1000,
3791 },
3792 [pbn_ADDIDATA_PCIe_4_3906250] = {
3793 .flags = FL_BASE0,
3794 .num_ports = 4,
3795 .base_baud = 3906250,
3796 .uart_offset = 0x200,
3797 .first_offset = 0x1000,
3798 },
3799 [pbn_ADDIDATA_PCIe_8_3906250] = {
3800 .flags = FL_BASE0,
3801 .num_ports = 8,
3802 .base_baud = 3906250,
3803 .uart_offset = 0x200,
3804 .first_offset = 0x1000,
3805 },
3806 [pbn_ce4100_1_115200] = {
3807 .flags = FL_BASE_BARS,
3808 .num_ports = 2,
3809 .base_baud = 921600,
3810 .reg_shift = 2,
3811 },
3812 [pbn_omegapci] = {
3813 .flags = FL_BASE0,
3814 .num_ports = 8,
3815 .base_baud = 115200,
3816 .uart_offset = 0x200,
3817 },
3818 [pbn_NETMOS9900_2s_115200] = {
3819 .flags = FL_BASE0,
3820 .num_ports = 2,
3821 .base_baud = 115200,
3822 },
3823 [pbn_brcm_trumanage] = {
3824 .flags = FL_BASE0,
3825 .num_ports = 1,
3826 .reg_shift = 2,
3827 .base_baud = 115200,
3828 },
3829 [pbn_fintek_4] = {
3830 .num_ports = 4,
3831 .uart_offset = 8,
3832 .base_baud = 115200,
3833 .first_offset = 0x40,
3834 },
3835 [pbn_fintek_8] = {
3836 .num_ports = 8,
3837 .uart_offset = 8,
3838 .base_baud = 115200,
3839 .first_offset = 0x40,
3840 },
3841 [pbn_fintek_12] = {
3842 .num_ports = 12,
3843 .uart_offset = 8,
3844 .base_baud = 115200,
3845 .first_offset = 0x40,
3846 },
3847 [pbn_fintek_F81504A] = {
3848 .num_ports = 4,
3849 .uart_offset = 8,
3850 .base_baud = 115200,
3851 },
3852 [pbn_fintek_F81508A] = {
3853 .num_ports = 8,
3854 .uart_offset = 8,
3855 .base_baud = 115200,
3856 },
3857 [pbn_fintek_F81512A] = {
3858 .num_ports = 12,
3859 .uart_offset = 8,
3860 .base_baud = 115200,
3861 },
3862 [pbn_wch382_2] = {
3863 .flags = FL_BASE0,
3864 .num_ports = 2,
3865 .base_baud = 115200,
3866 .uart_offset = 8,
3867 .first_offset = 0xC0,
3868 },
3869 [pbn_wch384_4] = {
3870 .flags = FL_BASE0,
3871 .num_ports = 4,
3872 .base_baud = 115200,
3873 .uart_offset = 8,
3874 .first_offset = 0xC0,
3875 },
3876 [pbn_wch384_8] = {
3877 .flags = FL_BASE0,
3878 .num_ports = 8,
3879 .base_baud = 115200,
3880 .uart_offset = 8,
3881 .first_offset = 0x00,
3882 },
3883 [pbn_sunix_pci_1s] = {
3884 .num_ports = 1,
3885 .base_baud = 921600,
3886 .uart_offset = 0x8,
3887 },
3888 [pbn_sunix_pci_2s] = {
3889 .num_ports = 2,
3890 .base_baud = 921600,
3891 .uart_offset = 0x8,
3892 },
3893 [pbn_sunix_pci_4s] = {
3894 .num_ports = 4,
3895 .base_baud = 921600,
3896 .uart_offset = 0x8,
3897 },
3898 [pbn_sunix_pci_8s] = {
3899 .num_ports = 8,
3900 .base_baud = 921600,
3901 .uart_offset = 0x8,
3902 },
3903 [pbn_sunix_pci_16s] = {
3904 .num_ports = 16,
3905 .base_baud = 921600,
3906 .uart_offset = 0x8,
3907 },
3908 [pbn_titan_1_4000000] = {
3909 .flags = FL_BASE0,
3910 .num_ports = 1,
3911 .base_baud = 4000000,
3912 .uart_offset = 0x200,
3913 .first_offset = 0x1000,
3914 },
3915 [pbn_titan_2_4000000] = {
3916 .flags = FL_BASE0,
3917 .num_ports = 2,
3918 .base_baud = 4000000,
3919 .uart_offset = 0x200,
3920 .first_offset = 0x1000,
3921 },
3922 [pbn_titan_4_4000000] = {
3923 .flags = FL_BASE0,
3924 .num_ports = 4,
3925 .base_baud = 4000000,
3926 .uart_offset = 0x200,
3927 .first_offset = 0x1000,
3928 },
3929 [pbn_titan_8_4000000] = {
3930 .flags = FL_BASE0,
3931 .num_ports = 8,
3932 .base_baud = 4000000,
3933 .uart_offset = 0x200,
3934 .first_offset = 0x1000,
3935 },
3936 [pbn_moxa_2] = {
3937 .flags = FL_BASE1,
3938 .num_ports = 2,
3939 .base_baud = 921600,
3940 .uart_offset = 0x200,
3941 },
3942 [pbn_moxa_4] = {
3943 .flags = FL_BASE1,
3944 .num_ports = 4,
3945 .base_baud = 921600,
3946 .uart_offset = 0x200,
3947 },
3948 [pbn_moxa_8] = {
3949 .flags = FL_BASE1,
3950 .num_ports = 8,
3951 .base_baud = 921600,
3952 .uart_offset = 0x200,
3953 },
3954 };
3955
3956 #define REPORT_CONFIG(option) \
3957 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option)
3958 #define REPORT_8250_CONFIG(option) \
3959 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \
3960 0 : (kernel_ulong_t)&"SERIAL_8250_"#option)
3961
3962 static const struct pci_device_id blacklist[] = {
3963 /* softmodems */
3964 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3965 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3966 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3967
3968 /* multi-io cards handled by parport_serial */
3969 /* WCH CH353 2S1P */
3970 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3971 /* WCH CH353 1S1P */
3972 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3973 /* WCH CH382 2S1P */
3974 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), },
3975
3976 /* Intel platforms with MID UART */
3977 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), },
3978 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), },
3979 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), },
3980 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), },
3981 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), },
3982 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), },
3983
3984 /* Intel platforms with DesignWare UART */
3985 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), },
3986 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), },
3987 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), },
3988 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), },
3989 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), },
3990 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), },
3991 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), },
3992 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), },
3993 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), },
3994 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), },
3995 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), },
3996 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), },
3997 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), },
3998
3999 /* Exar devices */
4000 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4001 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), },
4002
4003 /* Pericom devices */
4004 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4005 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), },
4006
4007 /* End of the black list */
4008 { }
4009 };
4010
serial_pci_is_class_communication(struct pci_dev * dev)4011 static int serial_pci_is_class_communication(struct pci_dev *dev)
4012 {
4013 /*
4014 * If it is not a communications device or the programming
4015 * interface is greater than 6, give up.
4016 */
4017 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4018 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
4019 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4020 (dev->class & 0xff) > 6)
4021 return -ENODEV;
4022
4023 return 0;
4024 }
4025
4026 /*
4027 * Given a complete unknown PCI device, try to use some heuristics to
4028 * guess what the configuration might be, based on the pitiful PCI
4029 * serial specs. Returns 0 on success, -ENODEV on failure.
4030 */
4031 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)4032 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4033 {
4034 int num_iomem, num_port, first_port = -1, i;
4035 int rc;
4036
4037 rc = serial_pci_is_class_communication(dev);
4038 if (rc)
4039 return rc;
4040
4041 /*
4042 * Should we try to make guesses for multiport serial devices later?
4043 */
4044 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4045 return -ENODEV;
4046
4047 num_iomem = num_port = 0;
4048 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4049 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4050 num_port++;
4051 if (first_port == -1)
4052 first_port = i;
4053 }
4054 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4055 num_iomem++;
4056 }
4057
4058 /*
4059 * If there is 1 or 0 iomem regions, and exactly one port,
4060 * use it. We guess the number of ports based on the IO
4061 * region size.
4062 */
4063 if (num_iomem <= 1 && num_port == 1) {
4064 board->flags = first_port;
4065 board->num_ports = pci_resource_len(dev, first_port) / 8;
4066 return 0;
4067 }
4068
4069 /*
4070 * Now guess if we've got a board which indexes by BARs.
4071 * Each IO BAR should be 8 bytes, and they should follow
4072 * consecutively.
4073 */
4074 first_port = -1;
4075 num_port = 0;
4076 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
4077 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4078 pci_resource_len(dev, i) == 8 &&
4079 (first_port == -1 || (first_port + num_port) == i)) {
4080 num_port++;
4081 if (first_port == -1)
4082 first_port = i;
4083 }
4084 }
4085
4086 if (num_port > 1) {
4087 board->flags = first_port | FL_BASE_BARS;
4088 board->num_ports = num_port;
4089 return 0;
4090 }
4091
4092 return -ENODEV;
4093 }
4094
4095 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)4096 serial_pci_matches(const struct pciserial_board *board,
4097 const struct pciserial_board *guessed)
4098 {
4099 return
4100 board->num_ports == guessed->num_ports &&
4101 board->base_baud == guessed->base_baud &&
4102 board->uart_offset == guessed->uart_offset &&
4103 board->reg_shift == guessed->reg_shift &&
4104 board->first_offset == guessed->first_offset;
4105 }
4106
4107 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)4108 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4109 {
4110 struct uart_8250_port uart;
4111 struct serial_private *priv;
4112 struct pci_serial_quirk *quirk;
4113 int rc, nr_ports, i;
4114
4115 nr_ports = board->num_ports;
4116
4117 /*
4118 * Find an init and setup quirks.
4119 */
4120 quirk = find_quirk(dev);
4121
4122 /*
4123 * Run the new-style initialization function.
4124 * The initialization function returns:
4125 * <0 - error
4126 * 0 - use board->num_ports
4127 * >0 - number of ports
4128 */
4129 if (quirk->init) {
4130 rc = quirk->init(dev);
4131 if (rc < 0) {
4132 priv = ERR_PTR(rc);
4133 goto err_out;
4134 }
4135 if (rc)
4136 nr_ports = rc;
4137 }
4138
4139 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL);
4140 if (!priv) {
4141 priv = ERR_PTR(-ENOMEM);
4142 goto err_deinit;
4143 }
4144
4145 priv->dev = dev;
4146 priv->quirk = quirk;
4147
4148 memset(&uart, 0, sizeof(uart));
4149 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4150 uart.port.uartclk = board->base_baud * 16;
4151
4152 if (board->flags & FL_NOIRQ) {
4153 uart.port.irq = 0;
4154 } else {
4155 if (pci_match_id(pci_use_msi, dev)) {
4156 pci_dbg(dev, "Using MSI(-X) interrupts\n");
4157 pci_set_master(dev);
4158 uart.port.flags &= ~UPF_SHARE_IRQ;
4159 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4160 } else {
4161 pci_dbg(dev, "Using legacy interrupts\n");
4162 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX);
4163 }
4164 if (rc < 0) {
4165 kfree(priv);
4166 priv = ERR_PTR(rc);
4167 goto err_deinit;
4168 }
4169
4170 uart.port.irq = pci_irq_vector(dev, 0);
4171 }
4172
4173 uart.port.dev = &dev->dev;
4174
4175 for (i = 0; i < nr_ports; i++) {
4176 if (quirk->setup(priv, board, &uart, i))
4177 break;
4178
4179 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4180 uart.port.iobase, uart.port.irq, uart.port.iotype);
4181
4182 priv->line[i] = serial8250_register_8250_port(&uart);
4183 if (priv->line[i] < 0) {
4184 pci_err(dev,
4185 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4186 uart.port.iobase, uart.port.irq,
4187 uart.port.iotype, priv->line[i]);
4188 break;
4189 }
4190 }
4191 priv->nr = i;
4192 priv->board = board;
4193 return priv;
4194
4195 err_deinit:
4196 if (quirk->exit)
4197 quirk->exit(dev);
4198 err_out:
4199 return priv;
4200 }
4201 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4202
pciserial_detach_ports(struct serial_private * priv)4203 static void pciserial_detach_ports(struct serial_private *priv)
4204 {
4205 struct pci_serial_quirk *quirk;
4206 int i;
4207
4208 for (i = 0; i < priv->nr; i++)
4209 serial8250_unregister_port(priv->line[i]);
4210
4211 /*
4212 * Find the exit quirks.
4213 */
4214 quirk = find_quirk(priv->dev);
4215 if (quirk->exit)
4216 quirk->exit(priv->dev);
4217 }
4218
pciserial_remove_ports(struct serial_private * priv)4219 void pciserial_remove_ports(struct serial_private *priv)
4220 {
4221 pciserial_detach_ports(priv);
4222 kfree(priv);
4223 }
4224 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4225
pciserial_suspend_ports(struct serial_private * priv)4226 void pciserial_suspend_ports(struct serial_private *priv)
4227 {
4228 int i;
4229
4230 for (i = 0; i < priv->nr; i++)
4231 if (priv->line[i] >= 0)
4232 serial8250_suspend_port(priv->line[i]);
4233
4234 /*
4235 * Ensure that every init quirk is properly torn down
4236 */
4237 if (priv->quirk->exit)
4238 priv->quirk->exit(priv->dev);
4239 }
4240 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4241
pciserial_resume_ports(struct serial_private * priv)4242 void pciserial_resume_ports(struct serial_private *priv)
4243 {
4244 int i;
4245
4246 /*
4247 * Ensure that the board is correctly configured.
4248 */
4249 if (priv->quirk->init)
4250 priv->quirk->init(priv->dev);
4251
4252 for (i = 0; i < priv->nr; i++)
4253 if (priv->line[i] >= 0)
4254 serial8250_resume_port(priv->line[i]);
4255 }
4256 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4257
4258 /*
4259 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4260 * to the arrangement of serial ports on a PCI card.
4261 */
4262 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4263 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4264 {
4265 struct pci_serial_quirk *quirk;
4266 struct serial_private *priv;
4267 const struct pciserial_board *board;
4268 const struct pci_device_id *exclude;
4269 struct pciserial_board tmp;
4270 int rc;
4271
4272 quirk = find_quirk(dev);
4273 if (quirk->probe) {
4274 rc = quirk->probe(dev);
4275 if (rc)
4276 return rc;
4277 }
4278
4279 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4280 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data);
4281 return -EINVAL;
4282 }
4283
4284 board = &pci_boards[ent->driver_data];
4285
4286 exclude = pci_match_id(blacklist, dev);
4287 if (exclude) {
4288 if (exclude->driver_data)
4289 pci_warn(dev, "ignoring port, enable %s to handle\n",
4290 (const char *)exclude->driver_data);
4291 return -ENODEV;
4292 }
4293
4294 rc = pcim_enable_device(dev);
4295 pci_save_state(dev);
4296 if (rc)
4297 return rc;
4298
4299 if (ent->driver_data == pbn_default) {
4300 /*
4301 * Use a copy of the pci_board entry for this;
4302 * avoid changing entries in the table.
4303 */
4304 memcpy(&tmp, board, sizeof(struct pciserial_board));
4305 board = &tmp;
4306
4307 /*
4308 * We matched one of our class entries. Try to
4309 * determine the parameters of this board.
4310 */
4311 rc = serial_pci_guess_board(dev, &tmp);
4312 if (rc)
4313 return rc;
4314 } else {
4315 /*
4316 * We matched an explicit entry. If we are able to
4317 * detect this boards settings with our heuristic,
4318 * then we no longer need this entry.
4319 */
4320 memcpy(&tmp, &pci_boards[pbn_default],
4321 sizeof(struct pciserial_board));
4322 rc = serial_pci_guess_board(dev, &tmp);
4323 if (rc == 0 && serial_pci_matches(board, &tmp))
4324 moan_device("Redundant entry in serial pci_table.",
4325 dev);
4326 }
4327
4328 priv = pciserial_init_ports(dev, board);
4329 if (IS_ERR(priv))
4330 return PTR_ERR(priv);
4331
4332 pci_set_drvdata(dev, priv);
4333 return 0;
4334 }
4335
pciserial_remove_one(struct pci_dev * dev)4336 static void pciserial_remove_one(struct pci_dev *dev)
4337 {
4338 struct serial_private *priv = pci_get_drvdata(dev);
4339
4340 pciserial_remove_ports(priv);
4341 }
4342
4343 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4344 static int pciserial_suspend_one(struct device *dev)
4345 {
4346 struct serial_private *priv = dev_get_drvdata(dev);
4347
4348 if (priv)
4349 pciserial_suspend_ports(priv);
4350
4351 return 0;
4352 }
4353
pciserial_resume_one(struct device * dev)4354 static int pciserial_resume_one(struct device *dev)
4355 {
4356 struct pci_dev *pdev = to_pci_dev(dev);
4357 struct serial_private *priv = pci_get_drvdata(pdev);
4358 int err;
4359
4360 if (priv) {
4361 /*
4362 * The device may have been disabled. Re-enable it.
4363 */
4364 err = pci_enable_device(pdev);
4365 /* FIXME: We cannot simply error out here */
4366 if (err)
4367 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n");
4368 pciserial_resume_ports(priv);
4369 }
4370 return 0;
4371 }
4372 #endif
4373
4374 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4375 pciserial_resume_one);
4376
4377 static const struct pci_device_id serial_pci_tbl[] = {
4378 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600,
4379 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0,
4380 pbn_b0_4_921600 },
4381 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4382 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4383 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4384 pbn_b2_8_921600 },
4385 /* Advantech also use 0x3618 and 0xf618 */
4386 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4387 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4388 pbn_b0_4_921600 },
4389 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4390 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4391 pbn_b0_4_921600 },
4392 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4393 PCI_SUBVENDOR_ID_CONNECT_TECH,
4394 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4395 pbn_b1_8_1382400 },
4396 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4397 PCI_SUBVENDOR_ID_CONNECT_TECH,
4398 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4399 pbn_b1_4_1382400 },
4400 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4401 PCI_SUBVENDOR_ID_CONNECT_TECH,
4402 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4403 pbn_b1_2_1382400 },
4404 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4405 PCI_SUBVENDOR_ID_CONNECT_TECH,
4406 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4407 pbn_b1_8_1382400 },
4408 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4409 PCI_SUBVENDOR_ID_CONNECT_TECH,
4410 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4411 pbn_b1_4_1382400 },
4412 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4413 PCI_SUBVENDOR_ID_CONNECT_TECH,
4414 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4415 pbn_b1_2_1382400 },
4416 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4417 PCI_SUBVENDOR_ID_CONNECT_TECH,
4418 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4419 pbn_b1_8_921600 },
4420 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4421 PCI_SUBVENDOR_ID_CONNECT_TECH,
4422 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4423 pbn_b1_8_921600 },
4424 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4425 PCI_SUBVENDOR_ID_CONNECT_TECH,
4426 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4427 pbn_b1_4_921600 },
4428 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4429 PCI_SUBVENDOR_ID_CONNECT_TECH,
4430 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4431 pbn_b1_4_921600 },
4432 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4433 PCI_SUBVENDOR_ID_CONNECT_TECH,
4434 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4435 pbn_b1_2_921600 },
4436 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4437 PCI_SUBVENDOR_ID_CONNECT_TECH,
4438 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4439 pbn_b1_8_921600 },
4440 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4441 PCI_SUBVENDOR_ID_CONNECT_TECH,
4442 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4443 pbn_b1_8_921600 },
4444 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4445 PCI_SUBVENDOR_ID_CONNECT_TECH,
4446 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4447 pbn_b1_4_921600 },
4448 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4449 PCI_SUBVENDOR_ID_CONNECT_TECH,
4450 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4451 pbn_b1_2_1250000 },
4452 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4453 PCI_SUBVENDOR_ID_CONNECT_TECH,
4454 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4455 pbn_b0_2_1843200 },
4456 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4457 PCI_SUBVENDOR_ID_CONNECT_TECH,
4458 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4459 pbn_b0_4_1843200 },
4460 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4461 PCI_VENDOR_ID_AFAVLAB,
4462 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4463 pbn_b0_4_1152000 },
4464 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_b2_bt_1_115200 },
4467 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_b2_bt_2_115200 },
4470 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 pbn_b2_bt_4_115200 },
4473 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 pbn_b2_bt_2_115200 },
4476 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_b2_bt_4_115200 },
4479 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 pbn_b2_8_115200 },
4482 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 pbn_b2_8_460800 },
4485 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_b2_8_115200 },
4488
4489 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_b2_bt_2_115200 },
4492 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b2_bt_2_921600 },
4495 /*
4496 * VScom SPCOM800, from sl@s.pl
4497 */
4498 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_b2_8_921600 },
4501 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b2_4_921600 },
4504 /* Unknown card - subdevice 0x1584 */
4505 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4506 PCI_VENDOR_ID_PLX,
4507 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4508 pbn_b2_4_115200 },
4509 /* Unknown card - subdevice 0x1588 */
4510 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4511 PCI_VENDOR_ID_PLX,
4512 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4513 pbn_b2_8_115200 },
4514 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4515 PCI_SUBVENDOR_ID_KEYSPAN,
4516 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4517 pbn_panacom },
4518 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4520 pbn_panacom4 },
4521 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4523 pbn_panacom2 },
4524 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4525 PCI_VENDOR_ID_ESDGMBH,
4526 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4527 pbn_b2_4_115200 },
4528 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4529 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4530 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4531 pbn_b2_4_460800 },
4532 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4533 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4534 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4535 pbn_b2_8_460800 },
4536 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4537 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4538 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4539 pbn_b2_16_460800 },
4540 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4541 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4542 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4543 pbn_b2_16_460800 },
4544 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4545 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4546 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4547 pbn_b2_4_460800 },
4548 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4549 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4550 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4551 pbn_b2_8_460800 },
4552 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4553 PCI_SUBVENDOR_ID_EXSYS,
4554 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4555 pbn_b2_4_115200 },
4556 /*
4557 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4558 * (Exoray@isys.ca)
4559 */
4560 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4561 0x10b5, 0x106a, 0, 0,
4562 pbn_plx_romulus },
4563 /*
4564 * Quatech cards. These actually have configurable clocks but for
4565 * now we just use the default.
4566 *
4567 * 100 series are RS232, 200 series RS422,
4568 */
4569 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_b1_4_115200 },
4572 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_b1_2_115200 },
4575 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_b2_2_115200 },
4578 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_b1_2_115200 },
4581 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_b2_2_115200 },
4584 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_b1_4_115200 },
4587 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b1_8_115200 },
4590 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b1_8_115200 },
4593 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b1_4_115200 },
4596 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_b1_2_115200 },
4599 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_b1_4_115200 },
4602 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_b1_2_115200 },
4605 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b2_4_115200 },
4608 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_b2_2_115200 },
4611 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_b2_1_115200 },
4614 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_b2_4_115200 },
4617 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b2_2_115200 },
4620 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_b2_1_115200 },
4623 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_b0_8_115200 },
4626
4627 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4628 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4629 0, 0,
4630 pbn_b0_4_921600 },
4631 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4632 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4633 0, 0,
4634 pbn_b0_4_1152000 },
4635 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_b0_bt_2_921600 },
4638
4639 /*
4640 * The below card is a little controversial since it is the
4641 * subject of a PCI vendor/device ID clash. (See
4642 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4643 * For now just used the hex ID 0x950a.
4644 */
4645 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4646 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4647 0, 0, pbn_b0_2_115200 },
4648 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4649 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4650 0, 0, pbn_b0_2_115200 },
4651 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_b0_2_1130000 },
4654 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4655 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4656 pbn_b0_1_921600 },
4657 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_b0_4_115200 },
4660 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b0_bt_2_921600 },
4663 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_b2_8_1152000 },
4666
4667 /*
4668 * Oxford Semiconductor Inc. Tornado PCI express device range.
4669 */
4670 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_b0_1_15625000 },
4673 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_b0_1_15625000 },
4676 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_oxsemi_1_15625000 },
4679 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_oxsemi_1_15625000 },
4682 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b0_1_15625000 },
4685 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_1_15625000 },
4688 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_oxsemi_1_15625000 },
4691 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_oxsemi_1_15625000 },
4694 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b0_1_15625000 },
4697 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_b0_1_15625000 },
4700 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_b0_1_15625000 },
4703 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_b0_1_15625000 },
4706 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_oxsemi_2_15625000 },
4709 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_oxsemi_2_15625000 },
4712 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_oxsemi_4_15625000 },
4715 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_oxsemi_4_15625000 },
4718 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_oxsemi_8_15625000 },
4721 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_oxsemi_8_15625000 },
4724 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_oxsemi_1_15625000 },
4727 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 pbn_oxsemi_1_15625000 },
4730 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_oxsemi_1_15625000 },
4733 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_oxsemi_1_15625000 },
4736 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_oxsemi_1_15625000 },
4739 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_oxsemi_1_15625000 },
4742 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 pbn_oxsemi_1_15625000 },
4745 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 pbn_oxsemi_1_15625000 },
4748 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_oxsemi_1_15625000 },
4751 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 pbn_oxsemi_1_15625000 },
4754 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_oxsemi_1_15625000 },
4757 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 pbn_oxsemi_1_15625000 },
4760 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 pbn_oxsemi_1_15625000 },
4763 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 pbn_oxsemi_1_15625000 },
4766 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_oxsemi_1_15625000 },
4769 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_oxsemi_1_15625000 },
4772 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 pbn_oxsemi_1_15625000 },
4775 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 pbn_oxsemi_1_15625000 },
4778 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 pbn_oxsemi_1_15625000 },
4781 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 pbn_oxsemi_1_15625000 },
4784 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 pbn_oxsemi_1_15625000 },
4787 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 pbn_oxsemi_1_15625000 },
4790 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 pbn_oxsemi_1_15625000 },
4793 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 pbn_oxsemi_1_15625000 },
4796 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 pbn_oxsemi_1_15625000 },
4799 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 pbn_oxsemi_1_15625000 },
4802 /*
4803 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4804 */
4805 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4806 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4807 pbn_oxsemi_1_15625000 },
4808 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4809 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4810 pbn_oxsemi_2_15625000 },
4811 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4812 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4813 pbn_oxsemi_4_15625000 },
4814 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4815 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4816 pbn_oxsemi_8_15625000 },
4817
4818 /*
4819 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4820 */
4821 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4822 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4823 pbn_oxsemi_2_15625000 },
4824 /*
4825 * EndRun Technologies. PCI express device range.
4826 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952.
4827 */
4828 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4830 pbn_oxsemi_2_15625000 },
4831
4832 /*
4833 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4834 * from skokodyn@yahoo.com
4835 */
4836 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4837 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4838 pbn_sbsxrsio },
4839 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4840 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4841 pbn_sbsxrsio },
4842 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4843 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4844 pbn_sbsxrsio },
4845 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4846 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4847 pbn_sbsxrsio },
4848
4849 /*
4850 * Digitan DS560-558, from jimd@esoft.com
4851 */
4852 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_b1_1_115200 },
4855
4856 /*
4857 * Titan Electronic cards
4858 * The 400L and 800L have a custom setup quirk.
4859 */
4860 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_b0_1_921600 },
4863 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4865 pbn_b0_2_921600 },
4866 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868 pbn_b0_4_921600 },
4869 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4871 pbn_b0_4_921600 },
4872 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4874 pbn_b1_1_921600 },
4875 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4877 pbn_b1_bt_2_921600 },
4878 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4880 pbn_b0_bt_4_921600 },
4881 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4883 pbn_b0_bt_8_921600 },
4884 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_b4_bt_2_921600 },
4887 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 pbn_b4_bt_4_921600 },
4890 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 pbn_b4_bt_8_921600 },
4893 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_b0_4_921600 },
4896 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b0_4_921600 },
4899 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b0_4_921600 },
4902 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_titan_1_4000000 },
4905 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_titan_2_4000000 },
4908 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 pbn_titan_4_4000000 },
4911 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913 pbn_titan_8_4000000 },
4914 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916 pbn_titan_2_4000000 },
4917 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4919 pbn_titan_2_4000000 },
4920 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4922 pbn_b0_bt_2_921600 },
4923 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925 pbn_b0_4_921600 },
4926 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928 pbn_b0_4_921600 },
4929 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931 pbn_b0_4_921600 },
4932 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 pbn_b0_4_921600 },
4935
4936 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_b2_1_460800 },
4939 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_b2_1_460800 },
4942 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b2_1_460800 },
4945 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_b2_bt_2_921600 },
4948 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b2_bt_2_921600 },
4951 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_b2_bt_2_921600 },
4954 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_b2_bt_4_921600 },
4957 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 pbn_b2_bt_4_921600 },
4960 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_b2_bt_4_921600 },
4963 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b0_1_921600 },
4966 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b0_1_921600 },
4969 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b0_1_921600 },
4972 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 pbn_b0_bt_2_921600 },
4975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 pbn_b0_bt_2_921600 },
4978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 pbn_b0_bt_2_921600 },
4981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 pbn_b0_bt_4_921600 },
4984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 pbn_b0_bt_4_921600 },
4987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_b0_bt_4_921600 },
4990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 pbn_b0_bt_8_921600 },
4993 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995 pbn_b0_bt_8_921600 },
4996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 pbn_b0_bt_8_921600 },
4999
5000 /*
5001 * Computone devices submitted by Doug McNash dmcnash@computone.com
5002 */
5003 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5004 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5005 0, 0, pbn_computone_4 },
5006 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5007 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5008 0, 0, pbn_computone_8 },
5009 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5010 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5011 0, 0, pbn_computone_6 },
5012
5013 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5015 pbn_oxsemi },
5016 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5017 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5018 pbn_b0_bt_1_921600 },
5019
5020 /*
5021 * Sunix PCI serial boards
5022 */
5023 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5024 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5025 pbn_sunix_pci_1s },
5026 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5027 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5028 pbn_sunix_pci_2s },
5029 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5030 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5031 pbn_sunix_pci_4s },
5032 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5033 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5034 pbn_sunix_pci_4s },
5035 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5036 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5037 pbn_sunix_pci_8s },
5038 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5039 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5040 pbn_sunix_pci_8s },
5041 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5042 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5043 pbn_sunix_pci_16s },
5044
5045 /*
5046 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5047 */
5048 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050 pbn_b0_bt_8_115200 },
5051 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 pbn_b0_bt_8_115200 },
5054
5055 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5057 pbn_b0_bt_2_115200 },
5058 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5060 pbn_b0_bt_2_115200 },
5061 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5063 pbn_b0_bt_2_115200 },
5064 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5066 pbn_b0_bt_4_460800 },
5067 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5069 pbn_b0_bt_4_460800 },
5070 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5072 pbn_b0_bt_2_460800 },
5073 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 pbn_b0_bt_2_460800 },
5076 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078 pbn_b0_bt_2_460800 },
5079 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5081 pbn_b0_bt_1_115200 },
5082 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5084 pbn_b0_bt_1_460800 },
5085
5086 /*
5087 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5088 * Cards are identified by their subsystem vendor IDs, which
5089 * (in hex) match the model number.
5090 *
5091 * Note that JC140x are RS422/485 cards which require ox950
5092 * ACR = 0x10, and as such are not currently fully supported.
5093 */
5094 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5095 0x1204, 0x0004, 0, 0,
5096 pbn_b0_4_921600 },
5097 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5098 0x1208, 0x0004, 0, 0,
5099 pbn_b0_4_921600 },
5100 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5101 0x1402, 0x0002, 0, 0,
5102 pbn_b0_2_921600 }, */
5103 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5104 0x1404, 0x0004, 0, 0,
5105 pbn_b0_4_921600 }, */
5106 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5107 0x1208, 0x0004, 0, 0,
5108 pbn_b0_4_921600 },
5109
5110 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5111 0x1204, 0x0004, 0, 0,
5112 pbn_b0_4_921600 },
5113 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5114 0x1208, 0x0004, 0, 0,
5115 pbn_b0_4_921600 },
5116 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5117 0x1208, 0x0004, 0, 0,
5118 pbn_b0_4_921600 },
5119 /*
5120 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5121 */
5122 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124 pbn_b1_1_1382400 },
5125
5126 /*
5127 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5128 */
5129 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5131 pbn_b1_1_1382400 },
5132
5133 /*
5134 * RAStel 2 port modem, gerg@moreton.com.au
5135 */
5136 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5138 pbn_b2_bt_2_115200 },
5139
5140 /*
5141 * EKF addition for i960 Boards form EKF with serial port
5142 */
5143 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5144 0xE4BF, PCI_ANY_ID, 0, 0,
5145 pbn_intel_i960 },
5146
5147 /*
5148 * Xircom Cardbus/Ethernet combos
5149 */
5150 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5152 pbn_b0_1_115200 },
5153 /*
5154 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5155 */
5156 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5158 pbn_b0_1_115200 },
5159
5160 /*
5161 * Untested PCI modems, sent in from various folks...
5162 */
5163
5164 /*
5165 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5166 */
5167 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5168 0x1048, 0x1500, 0, 0,
5169 pbn_b1_1_115200 },
5170
5171 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5172 0xFF00, 0, 0, 0,
5173 pbn_sgi_ioc3 },
5174
5175 /*
5176 * HP Diva card
5177 */
5178 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5179 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5180 pbn_b1_1_115200 },
5181 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5183 pbn_b0_5_115200 },
5184 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5186 pbn_b2_1_115200 },
5187 /* HPE PCI serial device */
5188 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
5189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5190 pbn_b1_1_115200 },
5191
5192 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5194 pbn_b3_2_115200 },
5195 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5197 pbn_b3_4_115200 },
5198 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5200 pbn_b3_8_115200 },
5201 /*
5202 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5203 */
5204 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206 pbn_b0_1_115200 },
5207 /*
5208 * ITE
5209 */
5210 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5211 PCI_ANY_ID, PCI_ANY_ID,
5212 0, 0,
5213 pbn_b1_bt_1_115200 },
5214
5215 /*
5216 * IntaShield IS-100
5217 */
5218 { PCI_VENDOR_ID_INTASHIELD, 0x0D60,
5219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5220 pbn_b2_1_115200 },
5221 /*
5222 * IntaShield IS-200
5223 */
5224 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */
5226 pbn_b2_2_115200 },
5227 /*
5228 * IntaShield IS-400
5229 */
5230 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5232 pbn_b2_4_115200 },
5233 /*
5234 * IntaShield IX-100
5235 */
5236 { PCI_VENDOR_ID_INTASHIELD, 0x4027,
5237 PCI_ANY_ID, PCI_ANY_ID,
5238 0, 0,
5239 pbn_oxsemi_1_15625000 },
5240 /*
5241 * IntaShield IX-200
5242 */
5243 { PCI_VENDOR_ID_INTASHIELD, 0x4028,
5244 PCI_ANY_ID, PCI_ANY_ID,
5245 0, 0,
5246 pbn_oxsemi_2_15625000 },
5247 /*
5248 * IntaShield IX-400
5249 */
5250 { PCI_VENDOR_ID_INTASHIELD, 0x4029,
5251 PCI_ANY_ID, PCI_ANY_ID,
5252 0, 0,
5253 pbn_oxsemi_4_15625000 },
5254 /* Brainboxes Devices */
5255 /*
5256 * Brainboxes UC-101
5257 */
5258 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1,
5259 PCI_ANY_ID, PCI_ANY_ID,
5260 0, 0,
5261 pbn_b2_2_115200 },
5262 /*
5263 * Brainboxes UC-235/246
5264 */
5265 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1,
5266 PCI_ANY_ID, PCI_ANY_ID,
5267 0, 0,
5268 pbn_b2_1_115200 },
5269 { PCI_VENDOR_ID_INTASHIELD, 0x0AA2,
5270 PCI_ANY_ID, PCI_ANY_ID,
5271 0, 0,
5272 pbn_b2_1_115200 },
5273 /*
5274 * Brainboxes UC-253/UC-734
5275 */
5276 { PCI_VENDOR_ID_INTASHIELD, 0x0CA1,
5277 PCI_ANY_ID, PCI_ANY_ID,
5278 0, 0,
5279 pbn_b2_2_115200 },
5280 /*
5281 * Brainboxes UC-260/271/701/756
5282 */
5283 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5284 PCI_ANY_ID, PCI_ANY_ID,
5285 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5286 pbn_b2_4_115200 },
5287 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5288 PCI_ANY_ID, PCI_ANY_ID,
5289 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5290 pbn_b2_4_115200 },
5291 /*
5292 * Brainboxes UC-268
5293 */
5294 { PCI_VENDOR_ID_INTASHIELD, 0x0841,
5295 PCI_ANY_ID, PCI_ANY_ID,
5296 0, 0,
5297 pbn_b2_4_115200 },
5298 /*
5299 * Brainboxes UC-275/279
5300 */
5301 { PCI_VENDOR_ID_INTASHIELD, 0x0881,
5302 PCI_ANY_ID, PCI_ANY_ID,
5303 0, 0,
5304 pbn_b2_8_115200 },
5305 /*
5306 * Brainboxes UC-302
5307 */
5308 { PCI_VENDOR_ID_INTASHIELD, 0x08E1,
5309 PCI_ANY_ID, PCI_ANY_ID,
5310 0, 0,
5311 pbn_b2_2_115200 },
5312 { PCI_VENDOR_ID_INTASHIELD, 0x08E2,
5313 PCI_ANY_ID, PCI_ANY_ID,
5314 0, 0,
5315 pbn_b2_2_115200 },
5316 { PCI_VENDOR_ID_INTASHIELD, 0x08E3,
5317 PCI_ANY_ID, PCI_ANY_ID,
5318 0, 0,
5319 pbn_b2_2_115200 },
5320 /*
5321 * Brainboxes UC-310
5322 */
5323 { PCI_VENDOR_ID_INTASHIELD, 0x08C1,
5324 PCI_ANY_ID, PCI_ANY_ID,
5325 0, 0,
5326 pbn_b2_2_115200 },
5327 /*
5328 * Brainboxes UC-313
5329 */
5330 { PCI_VENDOR_ID_INTASHIELD, 0x08A1,
5331 PCI_ANY_ID, PCI_ANY_ID,
5332 0, 0,
5333 pbn_b2_2_115200 },
5334 { PCI_VENDOR_ID_INTASHIELD, 0x08A2,
5335 PCI_ANY_ID, PCI_ANY_ID,
5336 0, 0,
5337 pbn_b2_2_115200 },
5338 { PCI_VENDOR_ID_INTASHIELD, 0x08A3,
5339 PCI_ANY_ID, PCI_ANY_ID,
5340 0, 0,
5341 pbn_b2_2_115200 },
5342 /*
5343 * Brainboxes UC-320/324
5344 */
5345 { PCI_VENDOR_ID_INTASHIELD, 0x0A61,
5346 PCI_ANY_ID, PCI_ANY_ID,
5347 0, 0,
5348 pbn_b2_1_115200 },
5349 /*
5350 * Brainboxes UC-346
5351 */
5352 { PCI_VENDOR_ID_INTASHIELD, 0x0B01,
5353 PCI_ANY_ID, PCI_ANY_ID,
5354 0, 0,
5355 pbn_b2_4_115200 },
5356 { PCI_VENDOR_ID_INTASHIELD, 0x0B02,
5357 PCI_ANY_ID, PCI_ANY_ID,
5358 0, 0,
5359 pbn_b2_4_115200 },
5360 /*
5361 * Brainboxes UC-357
5362 */
5363 { PCI_VENDOR_ID_INTASHIELD, 0x0A81,
5364 PCI_ANY_ID, PCI_ANY_ID,
5365 0, 0,
5366 pbn_b2_2_115200 },
5367 { PCI_VENDOR_ID_INTASHIELD, 0x0A82,
5368 PCI_ANY_ID, PCI_ANY_ID,
5369 0, 0,
5370 pbn_b2_2_115200 },
5371 { PCI_VENDOR_ID_INTASHIELD, 0x0A83,
5372 PCI_ANY_ID, PCI_ANY_ID,
5373 0, 0,
5374 pbn_b2_2_115200 },
5375 /*
5376 * Brainboxes UC-368
5377 */
5378 { PCI_VENDOR_ID_INTASHIELD, 0x0C41,
5379 PCI_ANY_ID, PCI_ANY_ID,
5380 0, 0,
5381 pbn_b2_4_115200 },
5382 /*
5383 * Brainboxes UC-420
5384 */
5385 { PCI_VENDOR_ID_INTASHIELD, 0x0921,
5386 PCI_ANY_ID, PCI_ANY_ID,
5387 0, 0,
5388 pbn_b2_4_115200 },
5389 /*
5390 * Brainboxes UC-607
5391 */
5392 { PCI_VENDOR_ID_INTASHIELD, 0x09A1,
5393 PCI_ANY_ID, PCI_ANY_ID,
5394 0, 0,
5395 pbn_b2_2_115200 },
5396 { PCI_VENDOR_ID_INTASHIELD, 0x09A2,
5397 PCI_ANY_ID, PCI_ANY_ID,
5398 0, 0,
5399 pbn_b2_2_115200 },
5400 { PCI_VENDOR_ID_INTASHIELD, 0x09A3,
5401 PCI_ANY_ID, PCI_ANY_ID,
5402 0, 0,
5403 pbn_b2_2_115200 },
5404 /*
5405 * Brainboxes UC-836
5406 */
5407 { PCI_VENDOR_ID_INTASHIELD, 0x0D41,
5408 PCI_ANY_ID, PCI_ANY_ID,
5409 0, 0,
5410 pbn_b2_4_115200 },
5411 /*
5412 * Brainboxes UP-189
5413 */
5414 { PCI_VENDOR_ID_INTASHIELD, 0x0AC1,
5415 PCI_ANY_ID, PCI_ANY_ID,
5416 0, 0,
5417 pbn_b2_2_115200 },
5418 { PCI_VENDOR_ID_INTASHIELD, 0x0AC2,
5419 PCI_ANY_ID, PCI_ANY_ID,
5420 0, 0,
5421 pbn_b2_2_115200 },
5422 { PCI_VENDOR_ID_INTASHIELD, 0x0AC3,
5423 PCI_ANY_ID, PCI_ANY_ID,
5424 0, 0,
5425 pbn_b2_2_115200 },
5426 /*
5427 * Brainboxes UP-200
5428 */
5429 { PCI_VENDOR_ID_INTASHIELD, 0x0B21,
5430 PCI_ANY_ID, PCI_ANY_ID,
5431 0, 0,
5432 pbn_b2_2_115200 },
5433 { PCI_VENDOR_ID_INTASHIELD, 0x0B22,
5434 PCI_ANY_ID, PCI_ANY_ID,
5435 0, 0,
5436 pbn_b2_2_115200 },
5437 { PCI_VENDOR_ID_INTASHIELD, 0x0B23,
5438 PCI_ANY_ID, PCI_ANY_ID,
5439 0, 0,
5440 pbn_b2_2_115200 },
5441 /*
5442 * Brainboxes UP-869
5443 */
5444 { PCI_VENDOR_ID_INTASHIELD, 0x0C01,
5445 PCI_ANY_ID, PCI_ANY_ID,
5446 0, 0,
5447 pbn_b2_2_115200 },
5448 { PCI_VENDOR_ID_INTASHIELD, 0x0C02,
5449 PCI_ANY_ID, PCI_ANY_ID,
5450 0, 0,
5451 pbn_b2_2_115200 },
5452 { PCI_VENDOR_ID_INTASHIELD, 0x0C03,
5453 PCI_ANY_ID, PCI_ANY_ID,
5454 0, 0,
5455 pbn_b2_2_115200 },
5456 /*
5457 * Brainboxes UP-880
5458 */
5459 { PCI_VENDOR_ID_INTASHIELD, 0x0C21,
5460 PCI_ANY_ID, PCI_ANY_ID,
5461 0, 0,
5462 pbn_b2_2_115200 },
5463 { PCI_VENDOR_ID_INTASHIELD, 0x0C22,
5464 PCI_ANY_ID, PCI_ANY_ID,
5465 0, 0,
5466 pbn_b2_2_115200 },
5467 { PCI_VENDOR_ID_INTASHIELD, 0x0C23,
5468 PCI_ANY_ID, PCI_ANY_ID,
5469 0, 0,
5470 pbn_b2_2_115200 },
5471 /*
5472 * Brainboxes PX-101
5473 */
5474 { PCI_VENDOR_ID_INTASHIELD, 0x4005,
5475 PCI_ANY_ID, PCI_ANY_ID,
5476 0, 0,
5477 pbn_b0_2_115200 },
5478 { PCI_VENDOR_ID_INTASHIELD, 0x4019,
5479 PCI_ANY_ID, PCI_ANY_ID,
5480 0, 0,
5481 pbn_oxsemi_2_15625000 },
5482 /*
5483 * Brainboxes PX-235/246
5484 */
5485 { PCI_VENDOR_ID_INTASHIELD, 0x4004,
5486 PCI_ANY_ID, PCI_ANY_ID,
5487 0, 0,
5488 pbn_b0_1_115200 },
5489 { PCI_VENDOR_ID_INTASHIELD, 0x4016,
5490 PCI_ANY_ID, PCI_ANY_ID,
5491 0, 0,
5492 pbn_oxsemi_1_15625000 },
5493 /*
5494 * Brainboxes PX-203/PX-257
5495 */
5496 { PCI_VENDOR_ID_INTASHIELD, 0x4006,
5497 PCI_ANY_ID, PCI_ANY_ID,
5498 0, 0,
5499 pbn_b0_2_115200 },
5500 { PCI_VENDOR_ID_INTASHIELD, 0x4015,
5501 PCI_ANY_ID, PCI_ANY_ID,
5502 0, 0,
5503 pbn_oxsemi_2_15625000 },
5504 /*
5505 * Brainboxes PX-260/PX-701
5506 */
5507 { PCI_VENDOR_ID_INTASHIELD, 0x400A,
5508 PCI_ANY_ID, PCI_ANY_ID,
5509 0, 0,
5510 pbn_oxsemi_4_15625000 },
5511 /*
5512 * Brainboxes PX-275/279
5513 */
5514 { PCI_VENDOR_ID_INTASHIELD, 0x0E41,
5515 PCI_ANY_ID, PCI_ANY_ID,
5516 0, 0,
5517 pbn_b2_8_115200 },
5518 /*
5519 * Brainboxes PX-310
5520 */
5521 { PCI_VENDOR_ID_INTASHIELD, 0x400E,
5522 PCI_ANY_ID, PCI_ANY_ID,
5523 0, 0,
5524 pbn_oxsemi_2_15625000 },
5525 /*
5526 * Brainboxes PX-313
5527 */
5528 { PCI_VENDOR_ID_INTASHIELD, 0x400C,
5529 PCI_ANY_ID, PCI_ANY_ID,
5530 0, 0,
5531 pbn_oxsemi_2_15625000 },
5532 /*
5533 * Brainboxes PX-320/324/PX-376/PX-387
5534 */
5535 { PCI_VENDOR_ID_INTASHIELD, 0x400B,
5536 PCI_ANY_ID, PCI_ANY_ID,
5537 0, 0,
5538 pbn_oxsemi_1_15625000 },
5539 /*
5540 * Brainboxes PX-335/346
5541 */
5542 { PCI_VENDOR_ID_INTASHIELD, 0x400F,
5543 PCI_ANY_ID, PCI_ANY_ID,
5544 0, 0,
5545 pbn_oxsemi_4_15625000 },
5546 /*
5547 * Brainboxes PX-368
5548 */
5549 { PCI_VENDOR_ID_INTASHIELD, 0x4010,
5550 PCI_ANY_ID, PCI_ANY_ID,
5551 0, 0,
5552 pbn_oxsemi_4_15625000 },
5553 /*
5554 * Brainboxes PX-420
5555 */
5556 { PCI_VENDOR_ID_INTASHIELD, 0x4000,
5557 PCI_ANY_ID, PCI_ANY_ID,
5558 0, 0,
5559 pbn_b0_4_115200 },
5560 { PCI_VENDOR_ID_INTASHIELD, 0x4011,
5561 PCI_ANY_ID, PCI_ANY_ID,
5562 0, 0,
5563 pbn_oxsemi_4_15625000 },
5564 /*
5565 * Brainboxes PX-475
5566 */
5567 { PCI_VENDOR_ID_INTASHIELD, 0x401D,
5568 PCI_ANY_ID, PCI_ANY_ID,
5569 0, 0,
5570 pbn_oxsemi_1_15625000 },
5571 /*
5572 * Brainboxes PX-803/PX-857
5573 */
5574 { PCI_VENDOR_ID_INTASHIELD, 0x4009,
5575 PCI_ANY_ID, PCI_ANY_ID,
5576 0, 0,
5577 pbn_b0_2_115200 },
5578 { PCI_VENDOR_ID_INTASHIELD, 0x4018,
5579 PCI_ANY_ID, PCI_ANY_ID,
5580 0, 0,
5581 pbn_oxsemi_2_15625000 },
5582 { PCI_VENDOR_ID_INTASHIELD, 0x401E,
5583 PCI_ANY_ID, PCI_ANY_ID,
5584 0, 0,
5585 pbn_oxsemi_2_15625000 },
5586 /*
5587 * Brainboxes PX-820
5588 */
5589 { PCI_VENDOR_ID_INTASHIELD, 0x4002,
5590 PCI_ANY_ID, PCI_ANY_ID,
5591 0, 0,
5592 pbn_b0_4_115200 },
5593 { PCI_VENDOR_ID_INTASHIELD, 0x4013,
5594 PCI_ANY_ID, PCI_ANY_ID,
5595 0, 0,
5596 pbn_oxsemi_4_15625000 },
5597 /*
5598 * Brainboxes PX-835/PX-846
5599 */
5600 { PCI_VENDOR_ID_INTASHIELD, 0x4008,
5601 PCI_ANY_ID, PCI_ANY_ID,
5602 0, 0,
5603 pbn_b0_1_115200 },
5604 { PCI_VENDOR_ID_INTASHIELD, 0x4017,
5605 PCI_ANY_ID, PCI_ANY_ID,
5606 0, 0,
5607 pbn_oxsemi_1_15625000 },
5608
5609 /*
5610 * Perle PCI-RAS cards
5611 */
5612 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5613 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5614 0, 0, pbn_b2_4_921600 },
5615 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5616 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5617 0, 0, pbn_b2_8_921600 },
5618
5619 /*
5620 * Mainpine series cards: Fairly standard layout but fools
5621 * parts of the autodetect in some cases and uses otherwise
5622 * unmatched communications subclasses in the PCI Express case
5623 */
5624
5625 { /* RockForceDUO */
5626 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5627 PCI_VENDOR_ID_MAINPINE, 0x0200,
5628 0, 0, pbn_b0_2_115200 },
5629 { /* RockForceQUATRO */
5630 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5631 PCI_VENDOR_ID_MAINPINE, 0x0300,
5632 0, 0, pbn_b0_4_115200 },
5633 { /* RockForceDUO+ */
5634 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5635 PCI_VENDOR_ID_MAINPINE, 0x0400,
5636 0, 0, pbn_b0_2_115200 },
5637 { /* RockForceQUATRO+ */
5638 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5639 PCI_VENDOR_ID_MAINPINE, 0x0500,
5640 0, 0, pbn_b0_4_115200 },
5641 { /* RockForce+ */
5642 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5643 PCI_VENDOR_ID_MAINPINE, 0x0600,
5644 0, 0, pbn_b0_2_115200 },
5645 { /* RockForce+ */
5646 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5647 PCI_VENDOR_ID_MAINPINE, 0x0700,
5648 0, 0, pbn_b0_4_115200 },
5649 { /* RockForceOCTO+ */
5650 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5651 PCI_VENDOR_ID_MAINPINE, 0x0800,
5652 0, 0, pbn_b0_8_115200 },
5653 { /* RockForceDUO+ */
5654 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5655 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5656 0, 0, pbn_b0_2_115200 },
5657 { /* RockForceQUARTRO+ */
5658 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5659 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5660 0, 0, pbn_b0_4_115200 },
5661 { /* RockForceOCTO+ */
5662 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5663 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5664 0, 0, pbn_b0_8_115200 },
5665 { /* RockForceD1 */
5666 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5667 PCI_VENDOR_ID_MAINPINE, 0x2000,
5668 0, 0, pbn_b0_1_115200 },
5669 { /* RockForceF1 */
5670 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5671 PCI_VENDOR_ID_MAINPINE, 0x2100,
5672 0, 0, pbn_b0_1_115200 },
5673 { /* RockForceD2 */
5674 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5675 PCI_VENDOR_ID_MAINPINE, 0x2200,
5676 0, 0, pbn_b0_2_115200 },
5677 { /* RockForceF2 */
5678 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5679 PCI_VENDOR_ID_MAINPINE, 0x2300,
5680 0, 0, pbn_b0_2_115200 },
5681 { /* RockForceD4 */
5682 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5683 PCI_VENDOR_ID_MAINPINE, 0x2400,
5684 0, 0, pbn_b0_4_115200 },
5685 { /* RockForceF4 */
5686 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5687 PCI_VENDOR_ID_MAINPINE, 0x2500,
5688 0, 0, pbn_b0_4_115200 },
5689 { /* RockForceD8 */
5690 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5691 PCI_VENDOR_ID_MAINPINE, 0x2600,
5692 0, 0, pbn_b0_8_115200 },
5693 { /* RockForceF8 */
5694 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5695 PCI_VENDOR_ID_MAINPINE, 0x2700,
5696 0, 0, pbn_b0_8_115200 },
5697 { /* IQ Express D1 */
5698 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5699 PCI_VENDOR_ID_MAINPINE, 0x3000,
5700 0, 0, pbn_b0_1_115200 },
5701 { /* IQ Express F1 */
5702 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5703 PCI_VENDOR_ID_MAINPINE, 0x3100,
5704 0, 0, pbn_b0_1_115200 },
5705 { /* IQ Express D2 */
5706 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5707 PCI_VENDOR_ID_MAINPINE, 0x3200,
5708 0, 0, pbn_b0_2_115200 },
5709 { /* IQ Express F2 */
5710 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5711 PCI_VENDOR_ID_MAINPINE, 0x3300,
5712 0, 0, pbn_b0_2_115200 },
5713 { /* IQ Express D4 */
5714 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5715 PCI_VENDOR_ID_MAINPINE, 0x3400,
5716 0, 0, pbn_b0_4_115200 },
5717 { /* IQ Express F4 */
5718 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5719 PCI_VENDOR_ID_MAINPINE, 0x3500,
5720 0, 0, pbn_b0_4_115200 },
5721 { /* IQ Express D8 */
5722 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5723 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5724 0, 0, pbn_b0_8_115200 },
5725 { /* IQ Express F8 */
5726 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5727 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5728 0, 0, pbn_b0_8_115200 },
5729
5730
5731 /*
5732 * PA Semi PA6T-1682M on-chip UART
5733 */
5734 { PCI_VENDOR_ID_PASEMI, 0xa004,
5735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5736 pbn_pasemi_1682M },
5737
5738 /*
5739 * National Instruments
5740 */
5741 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5743 pbn_b1_16_115200 },
5744 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5746 pbn_b1_8_115200 },
5747 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5749 pbn_b1_bt_4_115200 },
5750 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5752 pbn_b1_bt_2_115200 },
5753 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5755 pbn_b1_bt_4_115200 },
5756 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5758 pbn_b1_bt_2_115200 },
5759 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5761 pbn_b1_16_115200 },
5762 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5764 pbn_b1_8_115200 },
5765 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5767 pbn_b1_bt_4_115200 },
5768 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5770 pbn_b1_bt_2_115200 },
5771 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5773 pbn_b1_bt_4_115200 },
5774 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5776 pbn_b1_bt_2_115200 },
5777 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5779 pbn_ni8430_2 },
5780 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5782 pbn_ni8430_2 },
5783 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5785 pbn_ni8430_4 },
5786 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5788 pbn_ni8430_4 },
5789 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5791 pbn_ni8430_8 },
5792 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5794 pbn_ni8430_8 },
5795 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5797 pbn_ni8430_16 },
5798 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5800 pbn_ni8430_16 },
5801 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5803 pbn_ni8430_2 },
5804 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5806 pbn_ni8430_2 },
5807 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5809 pbn_ni8430_4 },
5810 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5812 pbn_ni8430_4 },
5813
5814 /*
5815 * MOXA
5816 */
5817 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 },
5818 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 },
5819 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 },
5820 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 },
5821 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 },
5822 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 },
5823 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 },
5824 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 },
5825 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 },
5826 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 },
5827 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 },
5828 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 },
5829 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 },
5830 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 },
5831 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 },
5832 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 },
5833 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 },
5834 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 },
5835
5836 /*
5837 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5838 */
5839 { PCI_VENDOR_ID_ADDIDATA,
5840 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5841 PCI_ANY_ID,
5842 PCI_ANY_ID,
5843 0,
5844 0,
5845 pbn_b0_4_115200 },
5846
5847 { PCI_VENDOR_ID_ADDIDATA,
5848 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5849 PCI_ANY_ID,
5850 PCI_ANY_ID,
5851 0,
5852 0,
5853 pbn_b0_2_115200 },
5854
5855 { PCI_VENDOR_ID_ADDIDATA,
5856 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5857 PCI_ANY_ID,
5858 PCI_ANY_ID,
5859 0,
5860 0,
5861 pbn_b0_1_115200 },
5862
5863 { PCI_VENDOR_ID_AMCC,
5864 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5865 PCI_ANY_ID,
5866 PCI_ANY_ID,
5867 0,
5868 0,
5869 pbn_b1_8_115200 },
5870
5871 { PCI_VENDOR_ID_ADDIDATA,
5872 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5873 PCI_ANY_ID,
5874 PCI_ANY_ID,
5875 0,
5876 0,
5877 pbn_b0_4_115200 },
5878
5879 { PCI_VENDOR_ID_ADDIDATA,
5880 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5881 PCI_ANY_ID,
5882 PCI_ANY_ID,
5883 0,
5884 0,
5885 pbn_b0_2_115200 },
5886
5887 { PCI_VENDOR_ID_ADDIDATA,
5888 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5889 PCI_ANY_ID,
5890 PCI_ANY_ID,
5891 0,
5892 0,
5893 pbn_b0_1_115200 },
5894
5895 { PCI_VENDOR_ID_ADDIDATA,
5896 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5897 PCI_ANY_ID,
5898 PCI_ANY_ID,
5899 0,
5900 0,
5901 pbn_b0_4_115200 },
5902
5903 { PCI_VENDOR_ID_ADDIDATA,
5904 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5905 PCI_ANY_ID,
5906 PCI_ANY_ID,
5907 0,
5908 0,
5909 pbn_b0_2_115200 },
5910
5911 { PCI_VENDOR_ID_ADDIDATA,
5912 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5913 PCI_ANY_ID,
5914 PCI_ANY_ID,
5915 0,
5916 0,
5917 pbn_b0_1_115200 },
5918
5919 { PCI_VENDOR_ID_ADDIDATA,
5920 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5921 PCI_ANY_ID,
5922 PCI_ANY_ID,
5923 0,
5924 0,
5925 pbn_b0_8_115200 },
5926
5927 { PCI_VENDOR_ID_ADDIDATA,
5928 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5929 PCI_ANY_ID,
5930 PCI_ANY_ID,
5931 0,
5932 0,
5933 pbn_ADDIDATA_PCIe_4_3906250 },
5934
5935 { PCI_VENDOR_ID_ADDIDATA,
5936 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5937 PCI_ANY_ID,
5938 PCI_ANY_ID,
5939 0,
5940 0,
5941 pbn_ADDIDATA_PCIe_2_3906250 },
5942
5943 { PCI_VENDOR_ID_ADDIDATA,
5944 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5945 PCI_ANY_ID,
5946 PCI_ANY_ID,
5947 0,
5948 0,
5949 pbn_ADDIDATA_PCIe_1_3906250 },
5950
5951 { PCI_VENDOR_ID_ADDIDATA,
5952 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5953 PCI_ANY_ID,
5954 PCI_ANY_ID,
5955 0,
5956 0,
5957 pbn_ADDIDATA_PCIe_8_3906250 },
5958
5959 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5960 PCI_VENDOR_ID_IBM, 0x0299,
5961 0, 0, pbn_b0_bt_2_115200 },
5962
5963 /*
5964 * other NetMos 9835 devices are most likely handled by the
5965 * parport_serial driver, check drivers/parport/parport_serial.c
5966 * before adding them here.
5967 */
5968
5969 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5970 0xA000, 0x1000,
5971 0, 0, pbn_b0_1_115200 },
5972
5973 /* the 9901 is a rebranded 9912 */
5974 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5975 0xA000, 0x1000,
5976 0, 0, pbn_b0_1_115200 },
5977
5978 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5979 0xA000, 0x1000,
5980 0, 0, pbn_b0_1_115200 },
5981
5982 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5983 0xA000, 0x1000,
5984 0, 0, pbn_b0_1_115200 },
5985
5986 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5987 0xA000, 0x1000,
5988 0, 0, pbn_b0_1_115200 },
5989
5990 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5991 0xA000, 0x3002,
5992 0, 0, pbn_NETMOS9900_2s_115200 },
5993
5994 /*
5995 * Best Connectivity and Rosewill PCI Multi I/O cards
5996 */
5997
5998 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5999 0xA000, 0x1000,
6000 0, 0, pbn_b0_1_115200 },
6001
6002 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6003 0xA000, 0x3002,
6004 0, 0, pbn_b0_bt_2_115200 },
6005
6006 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
6007 0xA000, 0x3004,
6008 0, 0, pbn_b0_bt_4_115200 },
6009
6010 /*
6011 * ASIX AX99100 PCIe to Multi I/O Controller
6012 */
6013 { PCI_VENDOR_ID_ASIX, PCI_DEVICE_ID_ASIX_AX99100,
6014 0xA000, 0x1000,
6015 0, 0, pbn_b0_1_115200 },
6016
6017 /* Intel CE4100 */
6018 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
6019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6020 pbn_ce4100_1_115200 },
6021
6022 /*
6023 * Cronyx Omega PCI
6024 */
6025 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
6026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6027 pbn_omegapci },
6028
6029 /*
6030 * Broadcom TruManage
6031 */
6032 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
6033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
6034 pbn_brcm_trumanage },
6035
6036 /*
6037 * AgeStar as-prs2-009
6038 */
6039 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
6040 PCI_ANY_ID, PCI_ANY_ID,
6041 0, 0, pbn_b0_bt_2_115200 },
6042
6043 /*
6044 * WCH CH353 series devices: The 2S1P is handled by parport_serial
6045 * so not listed here.
6046 */
6047 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
6048 PCI_ANY_ID, PCI_ANY_ID,
6049 0, 0, pbn_b0_bt_4_115200 },
6050
6051 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
6052 PCI_ANY_ID, PCI_ANY_ID,
6053 0, 0, pbn_b0_bt_2_115200 },
6054
6055 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
6056 PCI_ANY_ID, PCI_ANY_ID,
6057 0, 0, pbn_b0_bt_4_115200 },
6058
6059 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
6060 PCI_ANY_ID, PCI_ANY_ID,
6061 0, 0, pbn_wch382_2 },
6062
6063 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
6064 PCI_ANY_ID, PCI_ANY_ID,
6065 0, 0, pbn_wch384_4 },
6066
6067 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S,
6068 PCI_ANY_ID, PCI_ANY_ID,
6069 0, 0, pbn_wch384_8 },
6070 /*
6071 * Realtek RealManage
6072 */
6073 { PCI_VENDOR_ID_REALTEK, 0x816a,
6074 PCI_ANY_ID, PCI_ANY_ID,
6075 0, 0, pbn_b0_1_115200 },
6076
6077 { PCI_VENDOR_ID_REALTEK, 0x816b,
6078 PCI_ANY_ID, PCI_ANY_ID,
6079 0, 0, pbn_b0_1_115200 },
6080
6081 /* Fintek PCI serial cards */
6082 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
6083 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
6084 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
6085 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
6086 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
6087 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
6088
6089 /* MKS Tenta SCOM-080x serial cards */
6090 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
6091 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
6092
6093 /* Amazon PCI serial device */
6094 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
6095
6096 /*
6097 * These entries match devices with class COMMUNICATION_SERIAL,
6098 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
6099 */
6100 { PCI_ANY_ID, PCI_ANY_ID,
6101 PCI_ANY_ID, PCI_ANY_ID,
6102 PCI_CLASS_COMMUNICATION_SERIAL << 8,
6103 0xffff00, pbn_default },
6104 { PCI_ANY_ID, PCI_ANY_ID,
6105 PCI_ANY_ID, PCI_ANY_ID,
6106 PCI_CLASS_COMMUNICATION_MODEM << 8,
6107 0xffff00, pbn_default },
6108 { PCI_ANY_ID, PCI_ANY_ID,
6109 PCI_ANY_ID, PCI_ANY_ID,
6110 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
6111 0xffff00, pbn_default },
6112 { 0, }
6113 };
6114
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)6115 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
6116 pci_channel_state_t state)
6117 {
6118 struct serial_private *priv = pci_get_drvdata(dev);
6119
6120 if (state == pci_channel_io_perm_failure)
6121 return PCI_ERS_RESULT_DISCONNECT;
6122
6123 if (priv)
6124 pciserial_detach_ports(priv);
6125
6126 pci_disable_device(dev);
6127
6128 return PCI_ERS_RESULT_NEED_RESET;
6129 }
6130
serial8250_io_slot_reset(struct pci_dev * dev)6131 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
6132 {
6133 int rc;
6134
6135 rc = pci_enable_device(dev);
6136
6137 if (rc)
6138 return PCI_ERS_RESULT_DISCONNECT;
6139
6140 pci_restore_state(dev);
6141 pci_save_state(dev);
6142
6143 return PCI_ERS_RESULT_RECOVERED;
6144 }
6145
serial8250_io_resume(struct pci_dev * dev)6146 static void serial8250_io_resume(struct pci_dev *dev)
6147 {
6148 struct serial_private *priv = pci_get_drvdata(dev);
6149 struct serial_private *new;
6150
6151 if (!priv)
6152 return;
6153
6154 new = pciserial_init_ports(dev, priv->board);
6155 if (!IS_ERR(new)) {
6156 pci_set_drvdata(dev, new);
6157 kfree(priv);
6158 }
6159 }
6160
6161 static const struct pci_error_handlers serial8250_err_handler = {
6162 .error_detected = serial8250_io_error_detected,
6163 .slot_reset = serial8250_io_slot_reset,
6164 .resume = serial8250_io_resume,
6165 };
6166
6167 static struct pci_driver serial_pci_driver = {
6168 .name = "serial",
6169 .probe = pciserial_init_one,
6170 .remove = pciserial_remove_one,
6171 .driver = {
6172 .pm = &pciserial_pm_ops,
6173 },
6174 .id_table = serial_pci_tbl,
6175 .err_handler = &serial8250_err_handler,
6176 };
6177
6178 module_pci_driver(serial_pci_driver);
6179
6180 MODULE_LICENSE("GPL");
6181 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
6182 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
6183 MODULE_IMPORT_NS("SERIAL_8250_PCI");
6184