1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * pci.h 4 * 5 * PCI defines and function prototypes 6 * Copyright 1994, Drew Eckhardt 7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 8 * 9 * PCI Express ASPM defines and function prototypes 10 * Copyright (c) 2007 Intel Corp. 11 * Zhang Yanmin (yanmin.zhang@intel.com) 12 * Shaohua Li (shaohua.li@intel.com) 13 * 14 * For more information, please consult the following manuals (look at 15 * http://www.pcisig.com/ for how to get them): 16 * 17 * PCI BIOS Specification 18 * PCI Local Bus Specification 19 * PCI to PCI Bridge Specification 20 * PCI Express Specification 21 * PCI System Design Guide 22 */ 23 #ifndef LINUX_PCI_H 24 #define LINUX_PCI_H 25 26 #include <linux/args.h> 27 #include <linux/device-id/pci.h> 28 29 #include <linux/types.h> 30 #include <linux/sizes.h> 31 #include <linux/init.h> 32 #include <linux/ioport.h> 33 #include <linux/list.h> 34 #include <linux/compiler.h> 35 #include <linux/errno.h> 36 #include <linux/kobject.h> 37 #include <linux/atomic.h> 38 #include <linux/device.h> 39 #include <linux/interrupt.h> 40 #include <linux/io.h> 41 #include <linux/resource_ext.h> 42 #include <linux/msi_api.h> 43 #include <uapi/linux/pci.h> 44 45 #include <linux/pci_ids.h> 46 47 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 48 PCI_STATUS_SIG_SYSTEM_ERROR | \ 49 PCI_STATUS_REC_MASTER_ABORT | \ 50 PCI_STATUS_REC_TARGET_ABORT | \ 51 PCI_STATUS_SIG_TARGET_ABORT | \ 52 PCI_STATUS_PARITY) 53 54 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ 55 #define PCI_NUM_RESET_METHODS 8 56 57 #define PCI_RESET_PROBE true 58 #define PCI_RESET_DO_RESET false 59 60 /* 61 * The PCI interface treats multi-function devices as independent 62 * devices. The slot/function address of each device is encoded 63 * in a single byte as follows: 64 * 65 * 7:3 = slot 66 * 2:0 = function 67 * 68 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. 69 * In the interest of not exposing interfaces to user-space unnecessarily, 70 * the following kernel-only defines are being added here. 71 */ 72 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 73 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 74 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 75 76 /* 77 * PCI_SLOT_ALL_DEVICES indicates a slot that covers all devices on the bus. 78 * Used for PCIe hotplug where the physical slot is the entire secondary bus, 79 * and, if ARI Forwarding is enabled, functions may appear to be on multiple 80 * devices. 81 */ 82 #define PCI_SLOT_ALL_DEVICES 0xfeff 83 84 /* Used to identify a slot as a placeholder */ 85 #define PCI_SLOT_PLACEHOLDER 0xffff 86 87 /* pci_slot represents a physical slot */ 88 struct pci_slot { 89 struct pci_bus *bus; /* Bus this slot is on */ 90 struct list_head list; /* Node in list of slots */ 91 struct hotplug_slot *hotplug; /* Hotplug info (move here) */ 92 u16 number; /* Device nr, or PCI_SLOT_ALL_DEVICES */ 93 unsigned int per_func_slot:1; /* Allow per function slot */ 94 struct kobject kobj; 95 }; 96 97 static inline const char *pci_slot_name(const struct pci_slot *slot) 98 { 99 return kobject_name(&slot->kobj); 100 } 101 102 /* File state for mmap()s on /proc/bus/pci/X/Y */ 103 enum pci_mmap_state { 104 pci_mmap_io, 105 pci_mmap_mem 106 }; 107 108 /* For PCI devices, the region numbers are assigned this way: */ 109 enum { 110 /* #0-5: standard PCI resources */ 111 PCI_STD_RESOURCES, 112 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1, 113 114 /* #6: expansion ROM resource */ 115 PCI_ROM_RESOURCE, 116 117 /* Device-specific resources */ 118 #ifdef CONFIG_PCI_IOV 119 PCI_IOV_RESOURCES, 120 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 121 #endif 122 123 /* PCI-to-PCI (P2P) bridge windows */ 124 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0) 125 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1) 126 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2) 127 128 /* CardBus bridge windows */ 129 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0) 130 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1) 131 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2) 132 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3) 133 134 /* Total number of bridge resources for P2P and CardBus */ 135 #define PCI_P2P_BRIDGE_RESOURCE_NUM 3 136 #define PCI_BRIDGE_RESOURCE_NUM 4 137 138 /* Resources assigned to buses behind the bridge */ 139 PCI_BRIDGE_RESOURCES, 140 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 141 PCI_BRIDGE_RESOURCE_NUM - 1, 142 143 /* Total resources associated with a PCI device */ 144 PCI_NUM_RESOURCES, 145 146 /* Preserve this for compatibility */ 147 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 148 }; 149 150 /** 151 * enum pci_interrupt_pin - PCI INTx interrupt values 152 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt 153 * @PCI_INTERRUPT_INTA: PCI INTA pin 154 * @PCI_INTERRUPT_INTB: PCI INTB pin 155 * @PCI_INTERRUPT_INTC: PCI INTC pin 156 * @PCI_INTERRUPT_INTD: PCI INTD pin 157 * 158 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the 159 * PCI_INTERRUPT_PIN register. 160 */ 161 enum pci_interrupt_pin { 162 PCI_INTERRUPT_UNKNOWN, 163 PCI_INTERRUPT_INTA, 164 PCI_INTERRUPT_INTB, 165 PCI_INTERRUPT_INTC, 166 PCI_INTERRUPT_INTD, 167 }; 168 169 /* The number of legacy PCI INTx interrupts */ 170 #define PCI_NUM_INTX 4 171 172 /* 173 * Reading from a device that doesn't respond typically returns ~0. A 174 * successful read from a device may also return ~0, so you need additional 175 * information to reliably identify errors. 176 */ 177 #define PCI_ERROR_RESPONSE (~0ULL) 178 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) 179 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) 180 181 /* 182 * pci_power_t values must match the bits in the Capabilities PME_Support 183 * and Control/Status PowerState fields in the Power Management capability. 184 */ 185 typedef int __bitwise pci_power_t; 186 187 #define PCI_D0 ((pci_power_t __force) 0) 188 #define PCI_D1 ((pci_power_t __force) 1) 189 #define PCI_D2 ((pci_power_t __force) 2) 190 #define PCI_D3hot ((pci_power_t __force) 3) 191 #define PCI_D3cold ((pci_power_t __force) 4) 192 #define PCI_UNKNOWN ((pci_power_t __force) 5) 193 #define PCI_POWER_ERROR ((pci_power_t __force) -1) 194 195 /* Remember to update this when the list above changes! */ 196 extern const char *pci_power_names[]; 197 198 static inline const char *pci_power_name(pci_power_t state) 199 { 200 return pci_power_names[1 + (__force int) state]; 201 } 202 203 /** 204 * typedef pci_channel_state_t 205 * 206 * The pci_channel state describes connectivity between the CPU and 207 * the PCI device. If some PCI bus between here and the PCI device 208 * has crashed or locked up, this info is reflected here. 209 */ 210 typedef unsigned int __bitwise pci_channel_state_t; 211 212 enum { 213 /* I/O channel is in normal state */ 214 pci_channel_io_normal = (__force pci_channel_state_t) 1, 215 216 /* I/O to channel is blocked */ 217 pci_channel_io_frozen = (__force pci_channel_state_t) 2, 218 219 /* PCI card is dead */ 220 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, 221 }; 222 223 typedef unsigned int __bitwise pcie_reset_state_t; 224 225 enum pcie_reset_state { 226 /* Reset is NOT asserted (Use to deassert reset) */ 227 pcie_deassert_reset = (__force pcie_reset_state_t) 1, 228 229 /* Use #PERST to reset PCIe device */ 230 pcie_warm_reset = (__force pcie_reset_state_t) 2, 231 232 /* Use PCIe Hot Reset to reset device */ 233 pcie_hot_reset = (__force pcie_reset_state_t) 3 234 }; 235 236 typedef unsigned short __bitwise pci_dev_flags_t; 237 enum pci_dev_flags { 238 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */ 239 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 240 /* Device configuration is irrevocably lost if disabled into D3 */ 241 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 242 /* Provide indication device is assigned by a Virtual Machine Manager */ 243 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), 244 /* Flag for quirk use to store if quirk-specific ACS is enabled */ 245 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), 246 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ 247 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), 248 /* Do not use bus resets for device */ 249 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), 250 /* Do not use PM reset even if device advertises NoSoftRst- */ 251 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 252 /* Get VPD from function 0 VPD */ 253 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 254 /* A non-root bridge where translation occurs, stop alias search here */ 255 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 256 /* Do not use FLR even if device advertises PCI_AF_CAP */ 257 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 258 /* Don't use Relaxed Ordering for TLPs directed at this device */ 259 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), 260 /* Device does honor MSI masking despite saying otherwise */ 261 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), 262 /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */ 263 PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (1 << 13), 264 /* 265 * PCIe to PCI bridge does not create RID aliases because the bridge is 266 * integrated with the downstream devices and doesn't use real PCI. 267 */ 268 PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS = (__force pci_dev_flags_t) (1 << 14), 269 }; 270 271 enum pci_irq_reroute_variant { 272 INTEL_IRQ_REROUTE_VARIANT = 1, 273 MAX_IRQ_REROUTE_VARIANTS = 3 274 }; 275 276 typedef unsigned short __bitwise pci_bus_flags_t; 277 enum pci_bus_flags { 278 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, 279 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, 280 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 281 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8, 282 }; 283 284 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 285 enum pcie_link_width { 286 PCIE_LNK_WIDTH_RESRV = 0x00, 287 PCIE_LNK_X1 = 0x01, 288 PCIE_LNK_X2 = 0x02, 289 PCIE_LNK_X4 = 0x04, 290 PCIE_LNK_X8 = 0x08, 291 PCIE_LNK_X12 = 0x0c, 292 PCIE_LNK_X16 = 0x10, 293 PCIE_LNK_X32 = 0x20, 294 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 295 }; 296 297 /* See matching string table in pci_speed_string() */ 298 enum pci_bus_speed { 299 PCI_SPEED_33MHz = 0x00, 300 PCI_SPEED_66MHz = 0x01, 301 PCI_SPEED_66MHz_PCIX = 0x02, 302 PCI_SPEED_100MHz_PCIX = 0x03, 303 PCI_SPEED_133MHz_PCIX = 0x04, 304 PCI_SPEED_66MHz_PCIX_ECC = 0x05, 305 PCI_SPEED_100MHz_PCIX_ECC = 0x06, 306 PCI_SPEED_133MHz_PCIX_ECC = 0x07, 307 PCI_SPEED_66MHz_PCIX_266 = 0x09, 308 PCI_SPEED_100MHz_PCIX_266 = 0x0a, 309 PCI_SPEED_133MHz_PCIX_266 = 0x0b, 310 AGP_UNKNOWN = 0x0c, 311 AGP_1X = 0x0d, 312 AGP_2X = 0x0e, 313 AGP_4X = 0x0f, 314 AGP_8X = 0x10, 315 PCI_SPEED_66MHz_PCIX_533 = 0x11, 316 PCI_SPEED_100MHz_PCIX_533 = 0x12, 317 PCI_SPEED_133MHz_PCIX_533 = 0x13, 318 PCIE_SPEED_2_5GT = 0x14, 319 PCIE_SPEED_5_0GT = 0x15, 320 PCIE_SPEED_8_0GT = 0x16, 321 PCIE_SPEED_16_0GT = 0x17, 322 PCIE_SPEED_32_0GT = 0x18, 323 PCIE_SPEED_64_0GT = 0x19, 324 PCI_SPEED_UNKNOWN = 0xff, 325 }; 326 327 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); 328 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); 329 330 struct pci_vpd { 331 struct mutex lock; 332 unsigned int len; 333 u8 cap; 334 }; 335 336 struct irq_affinity; 337 struct pcie_bwctrl_data; 338 struct pcie_link_state; 339 struct pci_sriov; 340 struct pci_p2pdma; 341 struct rcec_ea; 342 343 /* struct pci_dev - describes a PCI device 344 * 345 * @supported_speeds: PCIe Supported Link Speeds Vector (+ reserved 0 at 346 * LSB). 0 when the supported speeds cannot be 347 * determined (e.g., for Root Complex Integrated 348 * Endpoints without the relevant Capability 349 * Registers). 350 * @is_hotplug_bridge: Hotplug bridge of any kind (e.g. PCIe Hot-Plug Capable, 351 * Conventional PCI Hot-Plug, ACPI slot). 352 * Such bridges are allocated additional MMIO and bus 353 * number resources to allow for hierarchy expansion. 354 * @is_pciehp: PCIe Hot-Plug Capable bridge. 355 */ 356 struct pci_dev { 357 struct list_head bus_list; /* Node in per-bus list */ 358 struct pci_bus *bus; /* Bus this device is on */ 359 struct pci_bus *subordinate; /* Bus this device bridges to */ 360 361 void *sysdata; /* Hook for sys-specific extension */ 362 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */ 363 struct pci_slot *slot; /* Physical slot this device is in */ 364 365 unsigned int devfn; /* Encoded device & function index */ 366 unsigned short vendor; 367 unsigned short device; 368 unsigned short subsystem_vendor; 369 unsigned short subsystem_device; 370 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 371 u8 revision; /* PCI revision, low byte of class word */ 372 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 373 #ifdef CONFIG_PCIEAER 374 u16 aer_cap; /* AER capability offset */ 375 struct aer_info *aer_info; /* AER info for this device */ 376 #endif 377 #ifdef CONFIG_PCIEPORTBUS 378 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ 379 struct pci_dev *rcec; /* Associated RCEC device */ 380 #endif 381 u32 devcap; /* PCIe Device Capabilities */ 382 u16 rebar_cap; /* Resizable BAR capability offset */ 383 u8 pcie_cap; /* PCIe capability offset */ 384 u8 msi_cap; /* MSI capability offset */ 385 u8 msix_cap; /* MSI-X capability offset */ 386 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 387 u8 rom_base_reg; /* Config register controlling ROM */ 388 u8 pin; /* Interrupt pin this device uses */ 389 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ 390 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ 391 392 struct pci_driver *driver; /* Driver bound to this device */ 393 u64 dma_mask; /* Mask of the bits of bus address this 394 device implements. Normally this is 395 0xffffffff. You only need to change 396 this if your device has broken DMA 397 or supports 64-bit transfers. */ 398 u64 msi_addr_mask; /* Mask of the bits of bus address for 399 MSI that this device implements. 400 Normally set based on device 401 capabilities. You only need to 402 change this if your device claims 403 to support 64-bit MSI but implements 404 fewer than 64 address bits. */ 405 406 struct device_dma_parameters dma_parms; 407 408 pci_power_t current_state; /* Current operating state. In ACPI, 409 this is D0-D3, D0 being fully 410 functional, and D3 being off. */ 411 u8 pm_cap; /* PM capability offset */ 412 unsigned int pme_support:5; /* Bitmask of states from which PME# 413 can be generated */ 414 unsigned int pme_poll:1; /* Poll device's PME status bit */ 415 unsigned int pinned:1; /* Whether this dev is pinned */ 416 unsigned int config_rrs_sv:1; /* Config RRS software visibility */ 417 unsigned int imm_ready:1; /* Supports Immediate Readiness */ 418 unsigned int d1_support:1; /* Low power state D1 is supported */ 419 unsigned int d2_support:1; /* Low power state D2 is supported */ 420 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ 421 unsigned int no_d3cold:1; /* D3cold is forbidden */ 422 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 423 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 424 unsigned int mmio_always_on:1; /* Disallow turning off io/mem 425 decoding during BAR sizing */ 426 unsigned int wakeup_prepared:1; 427 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */ 428 unsigned int ignore_hotplug:1; /* Ignore hotplug events */ 429 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators 430 controlled exclusively by 431 user sysfs */ 432 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link 433 bit manually */ 434 unsigned int no_bw_notif:1; /* BW notifications may cause issues */ 435 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */ 436 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ 437 438 u16 l1ss; /* L1SS Capability pointer */ 439 #ifdef CONFIG_PCIEASPM 440 struct pcie_link_state *link_state; /* ASPM link state */ 441 unsigned int aspm_l0s_support:1; /* ASPM L0s support */ 442 unsigned int aspm_l1_support:1; /* ASPM L1 support */ 443 unsigned int ltr_path:1; /* Latency Tolerance Reporting 444 supported from root to here */ 445 #endif 446 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */ 447 unsigned int eetlp_prefix_max:3; /* Max # of End-End TLP Prefixes, 0=not supported */ 448 449 pci_channel_state_t error_state; /* Current connectivity state */ 450 struct device dev; /* Generic device interface */ 451 452 int cfg_size; /* Size of config space */ 453 454 /* 455 * Instead of touching interrupt line and base address registers 456 * directly, use the values stored here. They might be different! 457 */ 458 unsigned int irq; 459 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 460 struct resource driver_exclusive_resource; /* driver exclusive resource ranges */ 461 462 unsigned int transparent:1; /* Subtractive decode bridge */ 463 unsigned int io_window:1; /* Bridge has I/O window */ 464 unsigned int pref_window:1; /* Bridge has pref mem window */ 465 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */ 466 unsigned int multifunction:1; /* Multi-function device */ 467 468 unsigned int is_busmaster:1; /* Is busmaster */ 469 unsigned int no_msi:1; /* May not use MSI */ 470 unsigned int no_aer_anfe:1; /* Do not unmask ANFE */ 471 unsigned int block_cfg_access:1; /* Config space access blocked */ 472 unsigned int broken_parity_status:1; /* Generates false positive parity */ 473 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */ 474 unsigned int msi_enabled:1; 475 unsigned int msix_enabled:1; 476 unsigned int ari_enabled:1; /* ARI forwarding */ 477 unsigned int ats_enabled:1; /* Address Translation Svc */ 478 unsigned int pasid_enabled:1; /* Process Address Space ID */ 479 unsigned int pri_enabled:1; /* Page Request Interface */ 480 unsigned int tph_enabled:1; /* TLP Processing Hints */ 481 unsigned int fm_enabled:1; /* Flit Mode (segment captured) */ 482 unsigned int is_managed:1; /* Managed via devres */ 483 unsigned int is_msi_managed:1; /* MSI release via devres installed */ 484 unsigned int needs_freset:1; /* Requires fundamental reset */ 485 unsigned int state_saved:1; 486 unsigned int is_physfn:1; 487 unsigned int is_virtfn:1; 488 unsigned int is_hotplug_bridge:1; 489 unsigned int is_pciehp:1; 490 unsigned int shpc_managed:1; /* SHPC owned by shpchp */ 491 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 492 unsigned int is_cxl:1; /* Compute Express Link (CXL) */ 493 /* 494 * Devices marked being untrusted are the ones that can potentially 495 * execute DMA attacks and similar. They are typically connected 496 * through external ports such as Thunderbolt but not limited to 497 * that. When an IOMMU is enabled they should be getting full 498 * mappings to make sure they cannot access arbitrary memory. 499 */ 500 unsigned int untrusted:1; 501 /* 502 * Info from the platform, e.g., ACPI or device tree, may mark a 503 * device as "external-facing". An external-facing device is 504 * itself internal but devices downstream from it are external. 505 */ 506 unsigned int external_facing:1; 507 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 508 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */ 509 unsigned int irq_managed:1; 510 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */ 511 unsigned int is_probed:1; /* Device probing in progress */ 512 unsigned int link_active_reporting:1;/* Device capable of reporting link active */ 513 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ 514 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ 515 unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ 516 unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ 517 unsigned int non_mappable_bars:1; /* BARs can't be mapped by CPU or peers */ 518 pci_dev_flags_t dev_flags; 519 atomic_t enable_cnt; /* pci_enable_device has been called */ 520 521 spinlock_t pcie_cap_lock; /* Protects RMW ops in capability accessors */ 522 u32 saved_config_space[16]; /* Config space saved at suspend time */ 523 struct hlist_head saved_cap_space; 524 525 #ifdef CONFIG_HOTPLUG_PCI_PCIE 526 unsigned int broken_cmd_compl:1; /* No compl for some cmds */ 527 #endif 528 #ifdef CONFIG_PCIE_PTM 529 u16 ptm_cap; /* PTM Capability */ 530 unsigned int ptm_root:1; 531 unsigned int ptm_responder:1; 532 unsigned int ptm_requester:1; 533 atomic_t ptm_enable_cnt; 534 u8 ptm_granularity; 535 #endif 536 #ifdef CONFIG_PCI_MSI 537 void __iomem *msix_base; 538 raw_spinlock_t msi_lock; 539 #endif 540 struct pci_vpd vpd; 541 #ifdef CONFIG_PCIE_DPC 542 u16 dpc_cap; 543 unsigned int dpc_rp_extensions:1; 544 u8 dpc_rp_log_size; 545 #endif 546 struct pcie_bwctrl_data *link_bwctrl; 547 #ifdef CONFIG_PCI_ATS 548 union { 549 struct pci_sriov *sriov; /* PF: SR-IOV info */ 550 struct pci_dev *physfn; /* VF: related PF */ 551 }; 552 u16 ats_cap; /* ATS Capability offset */ 553 u8 ats_stu; /* ATS Smallest Translation Unit */ 554 #endif 555 #ifdef CONFIG_PCI_PRI 556 u16 pri_cap; /* PRI Capability offset */ 557 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 558 unsigned int pasid_required:1; /* PRG Response PASID Required */ 559 #endif 560 #ifdef CONFIG_PCI_PASID 561 u16 pasid_cap; /* PASID Capability offset */ 562 u16 pasid_features; 563 #endif 564 #ifdef CONFIG_PCI_P2PDMA 565 struct pci_p2pdma __rcu *p2pdma; 566 #endif 567 #ifdef CONFIG_PCI_DOE 568 struct xarray doe_mbs; /* Data Object Exchange mailboxes */ 569 #endif 570 #ifdef CONFIG_PCI_NPEM 571 struct npem *npem; /* Native PCIe Enclosure Management */ 572 #endif 573 #ifdef CONFIG_PCI_IDE 574 u16 ide_cap; /* Link Integrity & Data Encryption */ 575 u8 nr_ide_mem; /* Address association resources for streams */ 576 u8 nr_link_ide; /* Link Stream count (Selective Stream offset) */ 577 u16 nr_sel_ide; /* Selective Stream count (register block allocator) */ 578 struct ida ide_stream_ida; 579 unsigned int ide_cfg:1; /* Config cycles over IDE */ 580 unsigned int ide_tee_limit:1; /* Disallow T=0 traffic over IDE */ 581 #endif 582 #ifdef CONFIG_PCI_TSM 583 struct pci_tsm *tsm; /* TSM operation state */ 584 #endif 585 u16 acs_cap; /* ACS Capability offset */ 586 u16 acs_capabilities; /* ACS Capabilities */ 587 u8 supported_speeds; /* Supported Link Speeds Vector */ 588 phys_addr_t rom; /* Physical address if not from BAR */ 589 size_t romlen; /* Length if not from BAR */ 590 unsigned long priv_flags; /* Private flags for the PCI driver */ 591 592 /* These methods index pci_reset_fn_methods[] */ 593 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ 594 595 struct gpio_desc *wake; /* WAKE# GPIO */ 596 597 #ifdef CONFIG_PCIE_TPH 598 u16 tph_cap; /* TPH capability offset */ 599 u8 tph_mode; /* TPH mode */ 600 u8 tph_req_type; /* TPH requester type */ 601 #endif 602 }; 603 604 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 605 { 606 #ifdef CONFIG_PCI_IOV 607 if (dev->is_virtfn) 608 dev = dev->physfn; 609 #endif 610 return dev; 611 } 612 613 struct pci_dev *pci_alloc_dev(struct pci_bus *bus); 614 615 #define to_pci_dev(n) container_of(n, struct pci_dev, dev) 616 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 617 #define for_each_pci_dev_reverse(d) \ 618 while ((d = pci_get_device_reverse(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) 619 620 static inline int pci_channel_offline(struct pci_dev *pdev) 621 { 622 return (pdev->error_state != pci_channel_io_normal); 623 } 624 625 /* 626 * Currently in ACPI spec, for each PCI host bridge, PCI Segment 627 * Group number is limited to a 16-bit value, therefore (int)-1 is 628 * not a valid PCI domain number, and can be used as a sentinel 629 * value indicating ->domain_nr is not set by the driver (and 630 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with 631 * pci_bus_find_domain_nr()). 632 */ 633 #define PCI_DOMAIN_NR_NOT_SET (-1) 634 635 struct pci_host_bridge { 636 struct device dev; 637 struct pci_bus *bus; /* Root bus */ 638 struct pci_ops *ops; 639 struct pci_ops *child_ops; 640 void *sysdata; 641 int busnr; 642 int domain_nr; 643 struct list_head windows; /* resource_entry */ 644 struct list_head dma_ranges; /* dma ranges resource list */ 645 struct list_head ports; /* Root Port list (pci_host_port) */ 646 #ifdef CONFIG_PCI_IDE 647 u16 nr_ide_streams; /* Max streams possibly active in @ide_stream_ida */ 648 struct ida ide_stream_ida; 649 struct ida ide_stream_ids_ida; /* track unique ids per domain */ 650 #endif 651 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */ 652 int (*map_irq)(const struct pci_dev *, u8, u8); 653 void (*release_fn)(struct pci_host_bridge *); 654 int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); 655 void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); 656 int (*reset_root_port)(struct pci_host_bridge *bridge, struct pci_dev *dev); 657 void *release_data; 658 unsigned int ignore_reset_delay:1; /* For entire hierarchy */ 659 unsigned int no_ext_tags:1; /* No Extended Tags */ 660 unsigned int no_inc_mrrs:1; /* No Increase MRRS */ 661 unsigned int native_aer:1; /* OS may use PCIe AER */ 662 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */ 663 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */ 664 unsigned int native_pme:1; /* OS may use PCIe PME */ 665 unsigned int native_ltr:1; /* OS may use PCIe LTR */ 666 unsigned int native_dpc:1; /* OS may use PCIe DPC */ 667 unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */ 668 unsigned int preserve_config:1; /* Preserve FW resource setup */ 669 unsigned int size_windows:1; /* Enable root bus sizing */ 670 unsigned int msi_domain:1; /* Bridge wants MSI domain */ 671 unsigned int broken_l1ss_resume:1; /* Resuming from L1SS during 672 system suspend is broken */ 673 674 /* Resource alignment requirements */ 675 resource_size_t (*align_resource)(struct pci_dev *dev, 676 const struct resource *res, 677 resource_size_t start, 678 resource_size_t size, 679 resource_size_t align); 680 unsigned long private[] ____cacheline_aligned; 681 }; 682 683 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 684 685 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge) 686 { 687 return (void *)bridge->private; 688 } 689 690 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv) 691 { 692 return container_of(priv, struct pci_host_bridge, private); 693 } 694 695 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv); 696 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 697 size_t priv); 698 void pci_free_host_bridge(struct pci_host_bridge *bridge); 699 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 700 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 701 702 void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 703 void (*release_fn)(struct pci_host_bridge *), 704 void *release_data); 705 706 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 707 708 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 709 710 struct pci_bus { 711 struct list_head node; /* Node in list of buses */ 712 struct pci_bus *parent; /* Parent bus this bridge is on */ 713 struct list_head children; /* List of child buses */ 714 struct list_head devices; /* List of devices on this bus */ 715 struct pci_dev *self; /* Bridge device as seen by parent */ 716 struct list_head slots; /* List of slots on this bus; 717 protected by pci_slot_mutex */ 718 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 719 struct list_head resources; /* Address space routed to this bus */ 720 struct resource busn_res; /* Bus numbers routed to this bus */ 721 722 struct pci_ops *ops; /* Configuration access functions */ 723 void *sysdata; /* Hook for sys-specific extension */ 724 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */ 725 726 unsigned char number; /* Bus number */ 727 unsigned char primary; /* Number of primary bridge */ 728 unsigned char max_bus_speed; /* enum pci_bus_speed */ 729 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 730 #ifdef CONFIG_PCI_DOMAINS_GENERIC 731 int domain_nr; 732 #endif 733 734 char name[48]; 735 736 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */ 737 pci_bus_flags_t bus_flags; /* Inherited by child buses */ 738 struct device *bridge; 739 struct device dev; 740 unsigned int is_added:1; 741 unsigned int unsafe_warn:1; /* warned about RW1C config write */ 742 unsigned int flit_mode:1; /* Link in Flit mode */ 743 }; 744 745 #define to_pci_bus(n) container_of(n, struct pci_bus, dev) 746 747 static inline u16 pci_dev_id(struct pci_dev *dev) 748 { 749 return PCI_DEVID(dev->bus->number, dev->devfn); 750 } 751 752 /* 753 * Returns true if the PCI bus is root (behind host-PCI bridge), 754 * false otherwise 755 * 756 * Some code assumes that "bus->self == NULL" means that bus is a root bus. 757 * This is incorrect because "virtual" buses added for SR-IOV (via 758 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. 759 */ 760 static inline bool pci_is_root_bus(struct pci_bus *pbus) 761 { 762 return !(pbus->parent); 763 } 764 765 /** 766 * pci_is_bridge - check if the PCI device is a bridge 767 * @dev: PCI device 768 * 769 * Return true if the PCI device is bridge whether it has subordinate 770 * or not. 771 */ 772 static inline bool pci_is_bridge(struct pci_dev *dev) 773 { 774 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || 775 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 776 } 777 778 /** 779 * pci_is_vga - check if the PCI device is a VGA device 780 * @pdev: PCI device 781 * 782 * The PCI Code and ID Assignment spec, r1.15, secs 1.4 and 1.1, define 783 * VGA Base Class and Sub-Classes: 784 * 785 * 03 00 PCI_CLASS_DISPLAY_VGA VGA-compatible or 8514-compatible 786 * 00 01 PCI_CLASS_NOT_DEFINED_VGA VGA-compatible (before Class Code) 787 * 788 * Return true if the PCI device is a VGA device and uses the legacy VGA 789 * resources ([mem 0xa0000-0xbffff], [io 0x3b0-0x3bb], [io 0x3c0-0x3df] and 790 * aliases). 791 */ 792 static inline bool pci_is_vga(struct pci_dev *pdev) 793 { 794 if ((pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) 795 return true; 796 797 if ((pdev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA) 798 return true; 799 800 return false; 801 } 802 803 /** 804 * pci_is_display - check if the PCI device is a display controller 805 * @pdev: PCI device 806 * 807 * Determine whether the given PCI device corresponds to a display 808 * controller. Display controllers are typically used for graphical output 809 * and are identified based on their class code. 810 * 811 * Return: true if the PCI device is a display controller, false otherwise. 812 */ 813 static inline bool pci_is_display(struct pci_dev *pdev) 814 { 815 return (pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY; 816 } 817 818 static inline bool pcie_is_cxl(struct pci_dev *pci_dev) 819 { 820 return pci_dev->is_cxl; 821 } 822 823 #define for_each_pci_bridge(dev, bus) \ 824 list_for_each_entry(dev, &bus->devices, bus_list) \ 825 if (!pci_is_bridge(dev)) {} else 826 827 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) 828 { 829 dev = pci_physfn(dev); 830 if (pci_is_root_bus(dev->bus)) 831 return NULL; 832 833 return dev->bus->self; 834 } 835 836 #ifdef CONFIG_PCI_MSI 837 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) 838 { 839 return pci_dev->msi_enabled || pci_dev->msix_enabled; 840 } 841 #else 842 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 843 #endif 844 845 /* Error values that may be returned by PCI functions */ 846 #define PCIBIOS_SUCCESSFUL 0x00 847 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 848 #define PCIBIOS_BAD_VENDOR_ID 0x83 849 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 850 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 851 #define PCIBIOS_SET_FAILED 0x88 852 #define PCIBIOS_BUFFER_TOO_SMALL 0x89 853 854 /* Translate above to generic errno for passing back through non-PCI code */ 855 static inline int pcibios_err_to_errno(int err) 856 { 857 if (err <= PCIBIOS_SUCCESSFUL) 858 return err; /* Assume already errno */ 859 860 switch (err) { 861 case PCIBIOS_FUNC_NOT_SUPPORTED: 862 return -ENOENT; 863 case PCIBIOS_BAD_VENDOR_ID: 864 return -ENOTTY; 865 case PCIBIOS_DEVICE_NOT_FOUND: 866 return -ENODEV; 867 case PCIBIOS_BAD_REGISTER_NUMBER: 868 return -EFAULT; 869 case PCIBIOS_SET_FAILED: 870 return -EIO; 871 case PCIBIOS_BUFFER_TOO_SMALL: 872 return -ENOSPC; 873 } 874 875 return -ERANGE; 876 } 877 878 /* Low-level architecture-dependent routines */ 879 880 struct pci_ops { 881 int (*add_bus)(struct pci_bus *bus); 882 void (*remove_bus)(struct pci_bus *bus); 883 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); 884 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); 885 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); 886 }; 887 888 /* 889 * ACPI needs to be able to access PCI config space before we've done a 890 * PCI bus scan and created pci_bus structures. 891 */ 892 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, 893 int reg, int len, u32 *val); 894 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, 895 int reg, int len, u32 val); 896 897 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 898 typedef u64 pci_bus_addr_t; 899 #else 900 typedef u32 pci_bus_addr_t; 901 #endif 902 903 struct pci_bus_region { 904 pci_bus_addr_t start; 905 pci_bus_addr_t end; 906 }; 907 908 static inline pci_bus_addr_t pci_bus_region_size(const struct pci_bus_region *region) 909 { 910 return region->end - region->start + 1; 911 } 912 913 struct pci_dynids { 914 spinlock_t lock; /* Protects list, index */ 915 struct list_head list; /* For IDs added at runtime */ 916 }; 917 918 919 /* 920 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides 921 * a set of callbacks in struct pci_error_handlers, that device driver 922 * will be notified of PCI bus errors, and will be driven to recovery 923 * when an error occurs. 924 */ 925 926 typedef unsigned int __bitwise pci_ers_result_t; 927 928 enum pci_ers_result { 929 /* No result/none/not supported in device driver */ 930 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 931 932 /* Device driver can recover without slot reset */ 933 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 934 935 /* Device driver wants slot to be reset */ 936 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 937 938 /* Device has completely failed, is unrecoverable */ 939 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, 940 941 /* Device driver is fully recovered and operational */ 942 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, 943 944 /* No AER capabilities registered for the driver */ 945 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, 946 }; 947 948 /* PCI bus error event callbacks */ 949 struct pci_error_handlers { 950 /* PCI bus error detected on this device */ 951 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 952 pci_channel_state_t error); 953 954 /* MMIO has been re-enabled, but not DMA */ 955 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 956 957 /* PCI slot has been reset */ 958 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 959 960 /* PCI function reset prepare or completed */ 961 void (*reset_prepare)(struct pci_dev *dev); 962 void (*reset_done)(struct pci_dev *dev); 963 964 /* Device driver may resume normal operations */ 965 void (*resume)(struct pci_dev *dev); 966 967 /* Allow device driver to record more details of a correctable error */ 968 void (*cor_error_detected)(struct pci_dev *dev); 969 }; 970 971 972 struct module; 973 974 /** 975 * struct pci_driver - PCI driver structure 976 * @name: Driver name. 977 * @id_table: Pointer to table of device IDs the driver is 978 * interested in. Most drivers should export this 979 * table using MODULE_DEVICE_TABLE(pci,...). 980 * @probe: This probing function gets called (during execution 981 * of pci_register_driver() for already existing 982 * devices or later if a new device gets inserted) for 983 * all PCI devices which match the ID table and are not 984 * "owned" by the other drivers yet. This function gets 985 * passed a "struct pci_dev \*" for each device whose 986 * entry in the ID table matches the device. The probe 987 * function returns zero when the driver chooses to 988 * take "ownership" of the device or an error code 989 * (negative number) otherwise. 990 * The pci_device_id parameter is only valid during probe. 991 * The probe function always gets called from process 992 * context, so it can sleep. 993 * @remove: The remove() function gets called whenever a device 994 * being handled by this driver is removed (either during 995 * deregistration of the driver or when it's manually 996 * pulled out of a hot-pluggable slot). 997 * The remove function always gets called from process 998 * context, so it can sleep. 999 * @suspend: Put device into low power state. 1000 * @resume: Wake device from low power state. 1001 * (Please see Documentation/power/pci.rst for descriptions 1002 * of PCI Power Management and the related functions.) 1003 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c). 1004 * Intended to stop any idling DMA operations. 1005 * Useful for enabling wake-on-lan (NIC) or changing 1006 * the power state of a device before reboot. 1007 * e.g. drivers/net/e100.c. 1008 * @sriov_configure: Optional driver callback to allow configuration of 1009 * number of VFs to enable via sysfs "sriov_numvfs" file. 1010 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X 1011 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count". 1012 * This will change MSI-X Table Size in the VF Message Control 1013 * registers. 1014 * @sriov_get_vf_total_msix: PF driver callback to get the total number of 1015 * MSI-X vectors available for distribution to the VFs. 1016 * @err_handler: See Documentation/PCI/pci-error-recovery.rst 1017 * @groups: Sysfs attribute groups. 1018 * @dev_groups: Attributes attached to the device that will be 1019 * created once it is bound to the driver. 1020 * @driver: Driver model structure. 1021 * @dynids: List of dynamically added device IDs. 1022 * @driver_managed_dma: Device driver doesn't use kernel DMA API for DMA. 1023 * For most device drivers, no need to care about this flag 1024 * as long as all DMAs are handled through the kernel DMA API. 1025 * For some special ones, for example VFIO drivers, they know 1026 * how to manage the DMA themselves and set this flag so that 1027 * the IOMMU layer will allow them to setup and manage their 1028 * own I/O address space. 1029 */ 1030 struct pci_driver { 1031 const char *name; 1032 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */ 1033 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 1034 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 1035 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */ 1036 int (*resume)(struct pci_dev *dev); /* Device woken up */ 1037 void (*shutdown)(struct pci_dev *dev); 1038 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */ 1039 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */ 1040 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf); 1041 const struct pci_error_handlers *err_handler; 1042 const struct attribute_group **groups; 1043 const struct attribute_group **dev_groups; 1044 struct device_driver driver; 1045 struct pci_dynids dynids; 1046 bool driver_managed_dma; 1047 }; 1048 1049 #define to_pci_driver(__drv) \ 1050 ( __drv ? container_of_const(__drv, struct pci_driver, driver) : NULL ) 1051 1052 /** 1053 * PCI_DEVICE - macro used to describe a specific PCI device 1054 * @vend: the 16 bit PCI Vendor ID 1055 * @dev: the 16 bit PCI Device ID 1056 * 1057 * This macro is used to create a struct pci_device_id that matches a 1058 * specific device. The subvendor and subdevice fields will be set to 1059 * PCI_ANY_ID. 1060 */ 1061 #define PCI_DEVICE(vend,dev) \ 1062 .vendor = (vend), .device = (dev), \ 1063 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1064 1065 /** 1066 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with 1067 * override_only flags. 1068 * @vend: the 16 bit PCI Vendor ID 1069 * @dev: the 16 bit PCI Device ID 1070 * @driver_override: the 32 bit PCI Device override_only 1071 * 1072 * This macro is used to create a struct pci_device_id that matches only a 1073 * driver_override device. The subvendor and subdevice fields will be set to 1074 * PCI_ANY_ID. 1075 */ 1076 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \ 1077 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \ 1078 .subdevice = PCI_ANY_ID, .override_only = (driver_override) 1079 1080 /** 1081 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO 1082 * "driver_override" PCI device. 1083 * @vend: the 16 bit PCI Vendor ID 1084 * @dev: the 16 bit PCI Device ID 1085 * 1086 * This macro is used to create a struct pci_device_id that matches a 1087 * specific device. The subvendor and subdevice fields will be set to 1088 * PCI_ANY_ID and the driver_override will be set to 1089 * PCI_ID_F_VFIO_DRIVER_OVERRIDE. 1090 */ 1091 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \ 1092 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE) 1093 1094 /** 1095 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem 1096 * @vend: the 16 bit PCI Vendor ID 1097 * @dev: the 16 bit PCI Device ID 1098 * @subvend: the 16 bit PCI Subvendor ID 1099 * @subdev: the 16 bit PCI Subdevice ID 1100 * 1101 * This macro is used to create a struct pci_device_id that matches a 1102 * specific device with subsystem information. 1103 */ 1104 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1105 .vendor = (vend), .device = (dev), \ 1106 .subvendor = (subvend), .subdevice = (subdev) 1107 1108 /** 1109 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class 1110 * @dev_class: the class, subclass, prog-if triple for this device 1111 * @dev_class_mask: the class mask for this device 1112 * 1113 * This macro is used to create a struct pci_device_id that matches a 1114 * specific PCI class. The vendor, device, subvendor, and subdevice 1115 * fields will be set to PCI_ANY_ID. 1116 */ 1117 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ 1118 .class = (dev_class), .class_mask = (dev_class_mask), \ 1119 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1120 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1121 1122 /** 1123 * PCI_VDEVICE - macro used to describe a specific PCI device in short form 1124 * @vend: the vendor name 1125 * @dev: the 16 bit PCI Device ID 1126 * 1127 * This macro is used to create a struct pci_device_id that matches a 1128 * specific PCI device. The subvendor, and subdevice fields will be set 1129 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1130 * private data. 1131 */ 1132 #define PCI_VDEVICE(vend, dev) \ 1133 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1134 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1135 1136 /** 1137 * PCI_VDEVICE_SUB - describe a specific PCI device/subdevice in a short form 1138 * @vend: the vendor name 1139 * @dev: the 16 bit PCI Device ID 1140 * @subvend: the 16 bit PCI Subvendor ID 1141 * @subdev: the 16 bit PCI Subdevice ID 1142 * 1143 * Generate the pci_device_id struct layout for the specific PCI 1144 * device/subdevice. Private data may follow the output. 1145 */ 1146 #define PCI_VDEVICE_SUB(vend, dev, subvend, subdev) \ 1147 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1148 .subvendor = (subvend), .subdevice = (subdev), 0, 0 1149 1150 /** 1151 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form 1152 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix) 1153 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix) 1154 * @data: the driver data to be filled 1155 * 1156 * This macro is used to create a struct pci_device_id that matches a 1157 * specific PCI device. The subvendor, and subdevice fields will be set 1158 * to PCI_ANY_ID. 1159 */ 1160 #define PCI_DEVICE_DATA(vend, dev, data) \ 1161 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \ 1162 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \ 1163 .driver_data = (kernel_ulong_t)(data) 1164 1165 enum { 1166 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */ 1167 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */ 1168 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */ 1169 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */ 1170 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */ 1171 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 1172 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */ 1173 }; 1174 1175 #define PCI_IRQ_INTX (1 << 0) /* Allow INTx interrupts */ 1176 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */ 1177 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */ 1178 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */ 1179 1180 /* These external functions are only available when PCI support is enabled */ 1181 #ifdef CONFIG_PCI 1182 1183 /* PCI legacy I/O port and memory address space sizes. */ 1184 #define PCI_LEGACY_IO_SIZE (SZ_64K - 1) 1185 #define PCI_LEGACY_MEM_SIZE SZ_1M 1186 1187 extern unsigned int pci_flags; 1188 1189 static inline void pci_set_flags(int flags) { pci_flags = flags; } 1190 static inline void pci_add_flags(int flags) { pci_flags |= flags; } 1191 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } 1192 static inline int pci_has_flag(int flag) { return pci_flags & flag; } 1193 1194 void pcie_bus_configure_settings(struct pci_bus *bus); 1195 1196 enum pcie_bus_config_types { 1197 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */ 1198 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */ 1199 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */ 1200 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */ 1201 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */ 1202 }; 1203 1204 extern enum pcie_bus_config_types pcie_bus_config; 1205 1206 extern const struct bus_type pci_bus_type; 1207 1208 /* Do NOT directly access these two variables, unless you are arch-specific PCI 1209 * code, or PCI core code. */ 1210 extern struct list_head pci_root_buses; /* List of all known PCI buses */ 1211 1212 void pcibios_resource_survey_bus(struct pci_bus *bus); 1213 void pcibios_bus_add_device(struct pci_dev *pdev); 1214 void pcibios_add_bus(struct pci_bus *bus); 1215 void pcibios_remove_bus(struct pci_bus *bus); 1216 void pcibios_fixup_bus(struct pci_bus *); 1217 int __must_check pcibios_enable_device(struct pci_dev *, int mask); 1218 /* Architecture-specific versions may override this (weak) */ 1219 char *pcibios_setup(char *str); 1220 1221 /* Used only when drivers/pci/setup.c is used */ 1222 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1223 const struct resource *empty_res, 1224 resource_size_t size, 1225 resource_size_t align); 1226 resource_size_t pci_align_resource(struct pci_dev *dev, 1227 const struct resource *res, 1228 const struct resource *empty_res, 1229 resource_size_t size, 1230 resource_size_t align); 1231 1232 /* Generic PCI functions used internally */ 1233 1234 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, 1235 struct resource *res); 1236 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, 1237 struct pci_bus_region *region); 1238 void pcibios_scan_specific_bus(int busn); 1239 struct pci_bus *pci_find_bus(int domain, int busnr); 1240 void pci_bus_add_devices(const struct pci_bus *bus); 1241 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 1242 struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 1243 struct pci_ops *ops, void *sysdata, 1244 struct list_head *resources); 1245 int pci_host_probe(struct pci_host_bridge *bridge); 1246 void pci_probe_flush_workqueue(void); 1247 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 1248 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 1249 void pci_bus_release_busn_res(struct pci_bus *b); 1250 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 1251 struct pci_ops *ops, void *sysdata, 1252 struct list_head *resources); 1253 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 1254 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1255 int busnr); 1256 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, 1257 const char *name, 1258 struct hotplug_slot *hotplug); 1259 void pci_destroy_slot(struct pci_slot *slot); 1260 #ifdef CONFIG_SYSFS 1261 void pci_dev_assign_slot(struct pci_dev *dev); 1262 #else 1263 static inline void pci_dev_assign_slot(struct pci_dev *dev) { } 1264 #endif 1265 int pci_scan_slot(struct pci_bus *bus, int devfn); 1266 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); 1267 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); 1268 unsigned int pci_scan_child_bus(struct pci_bus *bus); 1269 void pci_bus_add_device(struct pci_dev *dev); 1270 void pci_read_bridge_bases(struct pci_bus *child); 1271 struct resource *pci_find_parent_resource(const struct pci_dev *dev, 1272 struct resource *res); 1273 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin); 1274 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 1275 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); 1276 struct pci_dev *pci_dev_get(struct pci_dev *dev); 1277 void pci_dev_put(struct pci_dev *dev); 1278 DEFINE_FREE(pci_dev_put, struct pci_dev *, if (_T) pci_dev_put(_T)) 1279 void pci_remove_bus(struct pci_bus *b); 1280 void pci_stop_and_remove_bus_device(struct pci_dev *dev); 1281 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); 1282 void pci_stop_root_bus(struct pci_bus *bus); 1283 void pci_remove_root_bus(struct pci_bus *bus); 1284 #ifdef CONFIG_CARDBUS 1285 void pci_setup_cardbus_bridge(struct pci_bus *bus); 1286 #else 1287 static inline void pci_setup_cardbus_bridge(struct pci_bus *bus) { } 1288 #endif 1289 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type); 1290 void pci_sort_breadthfirst(void); 1291 #define dev_is_pci(d) ((d)->bus == &pci_bus_type) 1292 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) 1293 1294 /* Generic PCI functions exported to card drivers */ 1295 1296 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); 1297 u8 pci_find_capability(struct pci_dev *dev, int cap); 1298 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); 1299 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); 1300 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); 1301 u16 pci_find_ext_capability(struct pci_dev *dev, int cap); 1302 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); 1303 struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 1304 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); 1305 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); 1306 1307 u64 pci_get_dsn(struct pci_dev *dev); 1308 1309 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 1310 struct pci_dev *from); 1311 struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device, 1312 struct pci_dev *from); 1313 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 1314 unsigned int ss_vendor, unsigned int ss_device, 1315 struct pci_dev *from); 1316 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 1317 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 1318 unsigned int devfn); 1319 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); 1320 struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); 1321 1322 int pci_dev_present(const struct pci_device_id *ids); 1323 1324 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 1325 int where, u8 *val); 1326 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 1327 int where, u16 *val); 1328 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, 1329 int where, u32 *val); 1330 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 1331 int where, u8 val); 1332 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, 1333 int where, u16 val); 1334 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, 1335 int where, u32 val); 1336 1337 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, 1338 int where, int size, u32 *val); 1339 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, 1340 int where, int size, u32 val); 1341 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, 1342 int where, int size, u32 *val); 1343 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, 1344 int where, int size, u32 val); 1345 1346 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); 1347 1348 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val); 1349 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val); 1350 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val); 1351 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val); 1352 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val); 1353 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val); 1354 void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos, 1355 u32 clear, u32 set); 1356 1357 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); 1358 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 1359 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); 1360 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); 1361 int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos, 1362 u16 clear, u16 set); 1363 int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos, 1364 u16 clear, u16 set); 1365 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, 1366 u32 clear, u32 set); 1367 1368 /** 1369 * pcie_capability_clear_and_set_word - RMW accessor for PCI Express Capability Registers 1370 * @dev: PCI device structure of the PCI Express device 1371 * @pos: PCI Express Capability Register 1372 * @clear: Clear bitmask 1373 * @set: Set bitmask 1374 * 1375 * Perform a Read-Modify-Write (RMW) operation using @clear and @set 1376 * bitmasks on PCI Express Capability Register at @pos. Certain PCI Express 1377 * Capability Registers are accessed concurrently in RMW fashion, hence 1378 * require locking which is handled transparently to the caller. 1379 */ 1380 static inline int pcie_capability_clear_and_set_word(struct pci_dev *dev, 1381 int pos, 1382 u16 clear, u16 set) 1383 { 1384 switch (pos) { 1385 case PCI_EXP_LNKCTL: 1386 case PCI_EXP_LNKCTL2: 1387 case PCI_EXP_RTCTL: 1388 return pcie_capability_clear_and_set_word_locked(dev, pos, 1389 clear, set); 1390 default: 1391 return pcie_capability_clear_and_set_word_unlocked(dev, pos, 1392 clear, set); 1393 } 1394 } 1395 1396 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, 1397 u16 set) 1398 { 1399 return pcie_capability_clear_and_set_word(dev, pos, 0, set); 1400 } 1401 1402 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, 1403 u32 set) 1404 { 1405 return pcie_capability_clear_and_set_dword(dev, pos, 0, set); 1406 } 1407 1408 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, 1409 u16 clear) 1410 { 1411 return pcie_capability_clear_and_set_word(dev, pos, clear, 0); 1412 } 1413 1414 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, 1415 u32 clear) 1416 { 1417 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1418 } 1419 1420 /* User-space driven config access */ 1421 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1422 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1423 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1424 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); 1425 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); 1426 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); 1427 1428 int __must_check pci_enable_device(struct pci_dev *dev); 1429 int __must_check pci_enable_device_mem(struct pci_dev *dev); 1430 int __must_check pci_reenable_device(struct pci_dev *); 1431 int __must_check pcim_enable_device(struct pci_dev *pdev); 1432 void pcim_pin_device(struct pci_dev *pdev); 1433 1434 static inline bool pci_intx_mask_supported(struct pci_dev *pdev) 1435 { 1436 /* 1437 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is 1438 * writable and no quirk has marked the feature broken. 1439 */ 1440 return !pdev->broken_intx_masking; 1441 } 1442 1443 static inline int pci_is_enabled(struct pci_dev *pdev) 1444 { 1445 return (atomic_read(&pdev->enable_cnt) > 0); 1446 } 1447 1448 static inline int pci_is_managed(struct pci_dev *pdev) 1449 { 1450 return pdev->is_managed; 1451 } 1452 1453 void pci_disable_device(struct pci_dev *dev); 1454 1455 extern unsigned int pcibios_max_latency; 1456 void pci_set_master(struct pci_dev *dev); 1457 void pci_clear_master(struct pci_dev *dev); 1458 1459 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); 1460 int pci_set_cacheline_size(struct pci_dev *dev); 1461 int __must_check pci_set_mwi(struct pci_dev *dev); 1462 int __must_check pcim_set_mwi(struct pci_dev *dev); 1463 int pci_try_set_mwi(struct pci_dev *dev); 1464 void pci_clear_mwi(struct pci_dev *dev); 1465 void pci_disable_parity(struct pci_dev *dev); 1466 void pci_intx(struct pci_dev *dev, int enable); 1467 bool pci_check_and_mask_intx(struct pci_dev *dev); 1468 bool pci_check_and_unmask_intx(struct pci_dev *dev); 1469 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); 1470 int pci_wait_for_pending_transaction(struct pci_dev *dev); 1471 int pcix_get_max_mmrbc(struct pci_dev *dev); 1472 int pcix_get_mmrbc(struct pci_dev *dev); 1473 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 1474 int pcie_get_readrq(struct pci_dev *dev); 1475 int pcie_set_readrq(struct pci_dev *dev, int rq); 1476 int pcie_get_mps(struct pci_dev *dev); 1477 int pcie_set_mps(struct pci_dev *dev, int mps); 1478 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, 1479 enum pci_bus_speed *speed, 1480 enum pcie_link_width *width); 1481 int pcie_link_speed_mbps(struct pci_dev *pdev); 1482 void pcie_print_link_status(struct pci_dev *dev); 1483 int pcie_reset_flr(struct pci_dev *dev, bool probe); 1484 int pcie_flr(struct pci_dev *dev); 1485 int __pci_reset_function_locked(struct pci_dev *dev); 1486 int pci_reset_function(struct pci_dev *dev); 1487 int pci_reset_function_locked(struct pci_dev *dev); 1488 int pci_try_reset_function(struct pci_dev *dev); 1489 int pci_probe_reset_slot(struct pci_slot *slot); 1490 int pci_probe_reset_bus(struct pci_bus *bus); 1491 int pci_reset_bus(struct pci_dev *dev); 1492 void pci_reset_secondary_bus(struct pci_dev *dev); 1493 void pcibios_reset_secondary_bus(struct pci_dev *dev); 1494 void pci_update_resource(struct pci_dev *dev, int resno); 1495 int __must_check pci_assign_resource(struct pci_dev *dev, int i); 1496 int pci_release_resource(struct pci_dev *dev, int resno); 1497 1498 /* Resizable BAR related routines */ 1499 int pci_rebar_bytes_to_size(u64 bytes); 1500 resource_size_t pci_rebar_size_to_bytes(int size); 1501 u64 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); 1502 bool pci_rebar_size_supported(struct pci_dev *pdev, int bar, int size); 1503 int pci_rebar_get_max_size(struct pci_dev *pdev, int bar); 1504 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size, 1505 int exclude_bars); 1506 1507 int pci_select_bars(struct pci_dev *dev, unsigned long flags); 1508 bool pci_device_is_present(struct pci_dev *pdev); 1509 void pci_ignore_hotplug(struct pci_dev *dev); 1510 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); 1511 int pci_status_get_and_clear_errors(struct pci_dev *pdev); 1512 1513 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr, 1514 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, 1515 const char *fmt, ...); 1516 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id); 1517 1518 /* ROM control related routines */ 1519 int pci_enable_rom(struct pci_dev *pdev); 1520 void pci_disable_rom(struct pci_dev *pdev); 1521 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); 1522 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); 1523 1524 /* Power management related routines */ 1525 int pci_save_state(struct pci_dev *dev); 1526 void pci_restore_state(struct pci_dev *dev); 1527 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); 1528 int pci_load_saved_state(struct pci_dev *dev, 1529 struct pci_saved_state *state); 1530 int pci_load_and_free_saved_state(struct pci_dev *dev, 1531 struct pci_saved_state **state); 1532 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); 1533 int pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1534 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state); 1535 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 1536 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); 1537 void pci_pme_active(struct pci_dev *dev, bool enable); 1538 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); 1539 int pci_wake_from_d3(struct pci_dev *dev, bool enable); 1540 int pci_prepare_to_sleep(struct pci_dev *dev); 1541 int pci_back_from_sleep(struct pci_dev *dev); 1542 bool pci_dev_run_wake(struct pci_dev *dev); 1543 void pci_d3cold_enable(struct pci_dev *dev); 1544 void pci_d3cold_disable(struct pci_dev *dev); 1545 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); 1546 void pci_resume_bus(struct pci_bus *bus); 1547 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state); 1548 1549 /* For use by arch with custom probe code */ 1550 void set_pcie_port_type(struct pci_dev *pdev); 1551 void set_pcie_hotplug_bridge(struct pci_dev *pdev); 1552 1553 /* Functions for PCI Hotplug drivers to use */ 1554 unsigned int pci_rescan_bus(struct pci_bus *bus); 1555 void pci_lock_rescan_remove(void); 1556 void pci_unlock_rescan_remove(void); 1557 1558 /* Vital Product Data routines */ 1559 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1560 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1561 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1562 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1563 1564 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 1565 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); 1566 void pci_bus_assign_resources(const struct pci_bus *bus); 1567 void pci_bus_claim_resources(struct pci_bus *bus); 1568 void pci_bus_size_bridges(struct pci_bus *bus); 1569 int pci_claim_resource(struct pci_dev *, int); 1570 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); 1571 void pci_assign_unassigned_resources(void); 1572 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); 1573 void pci_assign_unassigned_bus_resources(struct pci_bus *bus); 1574 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); 1575 int pci_enable_resources(struct pci_dev *, int mask); 1576 void pci_assign_irq(struct pci_dev *dev); 1577 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res); 1578 #define HAVE_PCI_REQ_REGIONS 2 1579 int __must_check pci_request_regions(struct pci_dev *, const char *); 1580 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); 1581 void pci_release_regions(struct pci_dev *); 1582 int __must_check pci_request_region(struct pci_dev *, int, const char *); 1583 void pci_release_region(struct pci_dev *, int); 1584 int pci_request_selected_regions(struct pci_dev *, int, const char *); 1585 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); 1586 void pci_release_selected_regions(struct pci_dev *, int); 1587 1588 static inline __must_check struct resource * 1589 pci_request_config_region_exclusive(struct pci_dev *pdev, unsigned int offset, 1590 unsigned int len, const char *name) 1591 { 1592 return __request_region(&pdev->driver_exclusive_resource, offset, len, 1593 name, IORESOURCE_EXCLUSIVE); 1594 } 1595 1596 static inline void pci_release_config_region(struct pci_dev *pdev, 1597 unsigned int offset, 1598 unsigned int len) 1599 { 1600 __release_region(&pdev->driver_exclusive_resource, offset, len); 1601 } 1602 1603 /* drivers/pci/bus.c */ 1604 void pci_add_resource(struct list_head *resources, struct resource *res); 1605 void pci_add_resource_offset(struct list_head *resources, struct resource *res, 1606 resource_size_t offset); 1607 void pci_free_resource_list(struct list_head *resources); 1608 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res); 1609 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); 1610 void pci_bus_remove_resources(struct pci_bus *bus); 1611 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res); 1612 int devm_request_pci_bus_resources(struct device *dev, 1613 struct list_head *resources); 1614 1615 /* Temporary until new and working PCI SBR API in place */ 1616 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 1617 1618 #define __pci_bus_for_each_res0(bus, res, ...) \ 1619 for (unsigned int __b = 0; \ 1620 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1621 __b++) 1622 1623 #define __pci_bus_for_each_res1(bus, res, __b) \ 1624 for (__b = 0; \ 1625 (res = pci_bus_resource_n(bus, __b)) || __b < PCI_BRIDGE_RESOURCE_NUM; \ 1626 __b++) 1627 1628 /** 1629 * pci_bus_for_each_resource - iterate over PCI bus resources 1630 * @bus: the PCI bus 1631 * @res: pointer to the current resource 1632 * @...: optional index of the current resource 1633 * 1634 * Iterate over PCI bus resources. The first part is to go over PCI bus 1635 * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM entries. 1636 * After that continue with the separate list of the additional resources, 1637 * if not empty. That's why the Logical OR is being used. 1638 * 1639 * Possible usage: 1640 * 1641 * struct pci_bus *bus = ...; 1642 * struct resource *res; 1643 * unsigned int i; 1644 * 1645 * // With optional index 1646 * pci_bus_for_each_resource(bus, res, i) 1647 * pr_info("PCI bus resource[%u]: %pR\n", i, res); 1648 * 1649 * // Without index 1650 * pci_bus_for_each_resource(bus, res) 1651 * _do_something_(res); 1652 */ 1653 #define pci_bus_for_each_resource(bus, res, ...) \ 1654 CONCATENATE(__pci_bus_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 1655 (bus, res, __VA_ARGS__) 1656 1657 int __must_check pci_bus_alloc_resource(struct pci_bus *bus, 1658 struct resource *res, resource_size_t size, 1659 resource_size_t align, resource_size_t min, 1660 unsigned long type_mask, 1661 resource_alignf alignf, 1662 void *alignf_data); 1663 1664 1665 int pci_register_io_range(const struct fwnode_handle *fwnode, phys_addr_t addr, 1666 resource_size_t size); 1667 unsigned long pci_address_to_pio(phys_addr_t addr); 1668 phys_addr_t pci_pio_to_address(unsigned long pio); 1669 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); 1670 int devm_pci_remap_iospace(struct device *dev, const struct resource *res, 1671 phys_addr_t phys_addr); 1672 void pci_unmap_iospace(struct resource *res); 1673 void __iomem *devm_pci_remap_cfgspace(struct device *dev, 1674 resource_size_t offset, 1675 resource_size_t size); 1676 void __iomem *devm_pci_remap_cfg_resource(struct device *dev, 1677 struct resource *res); 1678 1679 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) 1680 { 1681 struct pci_bus_region region; 1682 1683 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]); 1684 return region.start; 1685 } 1686 1687 /* Proper probing supporting hot-pluggable devices */ 1688 int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1689 const char *mod_name); 1690 1691 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ 1692 #define pci_register_driver(driver) \ 1693 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1694 1695 void pci_unregister_driver(struct pci_driver *dev); 1696 1697 /** 1698 * module_pci_driver() - Helper macro for registering a PCI driver 1699 * @__pci_driver: pci_driver struct 1700 * 1701 * Helper macro for PCI drivers which do not do anything special in module 1702 * init/exit. This eliminates a lot of boilerplate. Each module may only 1703 * use this macro once, and calling it replaces module_init() and module_exit() 1704 */ 1705 #define module_pci_driver(__pci_driver) \ 1706 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver) 1707 1708 /** 1709 * builtin_pci_driver() - Helper macro for registering a PCI driver 1710 * @__pci_driver: pci_driver struct 1711 * 1712 * Helper macro for PCI drivers which do not do anything special in their 1713 * init code. This eliminates a lot of boilerplate. Each driver may only 1714 * use this macro once, and calling it replaces device_initcall(...) 1715 */ 1716 #define builtin_pci_driver(__pci_driver) \ 1717 builtin_driver(__pci_driver, pci_register_driver) 1718 1719 struct pci_driver *pci_dev_driver(const struct pci_dev *dev); 1720 int pci_add_dynid(struct pci_driver *drv, 1721 unsigned int vendor, unsigned int device, 1722 unsigned int subvendor, unsigned int subdevice, 1723 unsigned int class, unsigned int class_mask, 1724 unsigned long driver_data); 1725 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 1726 struct pci_dev *dev); 1727 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, 1728 int pass); 1729 1730 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), 1731 void *userdata); 1732 void pci_walk_bus_reverse(struct pci_bus *top, 1733 int (*cb)(struct pci_dev *, void *), void *userdata); 1734 int pci_cfg_space_size(struct pci_dev *dev); 1735 unsigned char pci_bus_max_busnr(struct pci_bus *bus); 1736 resource_size_t pcibios_window_alignment(struct pci_bus *bus, 1737 unsigned long type); 1738 1739 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) 1740 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) 1741 1742 int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1743 unsigned int command_bits, u32 flags); 1744 1745 /* 1746 * Virtual interrupts allow for more interrupts to be allocated 1747 * than the device has interrupts for. These are not programmed 1748 * into the device's MSI-X table and must be handled by some 1749 * other driver means. 1750 */ 1751 #define PCI_IRQ_VIRTUAL (1 << 4) 1752 1753 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_INTX | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1754 1755 #include <linux/dmapool.h> 1756 1757 struct msix_entry { 1758 u32 vector; /* Kernel uses to write allocated vector */ 1759 u16 entry; /* Driver uses to specify entry, OS writes */ 1760 }; 1761 1762 #ifdef CONFIG_PCI_MSI 1763 int pci_msi_vec_count(struct pci_dev *dev); 1764 void pci_disable_msi(struct pci_dev *dev); 1765 int pci_msix_vec_count(struct pci_dev *dev); 1766 void pci_disable_msix(struct pci_dev *dev); 1767 void pci_restore_msi_state(struct pci_dev *dev); 1768 bool pci_msi_enabled(void); 1769 int pci_enable_msi(struct pci_dev *dev); 1770 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 1771 int minvec, int maxvec); 1772 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1773 struct msix_entry *entries, int nvec) 1774 { 1775 int rc = pci_enable_msix_range(dev, entries, nvec, nvec); 1776 if (rc < 0) 1777 return rc; 1778 return 0; 1779 } 1780 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1781 unsigned int max_vecs, unsigned int flags); 1782 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1783 unsigned int max_vecs, unsigned int flags, 1784 struct irq_affinity *affd); 1785 1786 bool pci_msix_can_alloc_dyn(struct pci_dev *dev); 1787 struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1788 const struct irq_affinity_desc *affdesc); 1789 void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map); 1790 1791 void pci_free_irq_vectors(struct pci_dev *dev); 1792 int pci_irq_vector(struct pci_dev *dev, unsigned int nr); 1793 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec); 1794 1795 /** 1796 * pci_irq_type - Get the interrupt type of a PCI device 1797 * @pdev: the PCI device to operate on 1798 * 1799 * Discriminate the interrupt type the PCI core selected for this device 1800 * after a successful pci_alloc_irq_vectors() call. 1801 * 1802 * Return: %PCI_IRQ_MSIX, %PCI_IRQ_MSI, or %PCI_IRQ_INTX. 1803 */ 1804 static inline unsigned int pci_irq_type(struct pci_dev *pdev) 1805 { 1806 if (pdev->msix_enabled) 1807 return PCI_IRQ_MSIX; 1808 1809 if (pdev->msi_enabled) 1810 return PCI_IRQ_MSI; 1811 1812 return PCI_IRQ_INTX; 1813 } 1814 1815 #else 1816 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1817 static inline void pci_disable_msi(struct pci_dev *dev) { } 1818 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } 1819 static inline void pci_disable_msix(struct pci_dev *dev) { } 1820 static inline void pci_restore_msi_state(struct pci_dev *dev) { } 1821 static inline bool pci_msi_enabled(void) { return false; } 1822 static inline int pci_enable_msi(struct pci_dev *dev) 1823 { return -ENOSYS; } 1824 static inline int pci_enable_msix_range(struct pci_dev *dev, 1825 struct msix_entry *entries, int minvec, int maxvec) 1826 { return -ENOSYS; } 1827 static inline int pci_enable_msix_exact(struct pci_dev *dev, 1828 struct msix_entry *entries, int nvec) 1829 { return -ENOSYS; } 1830 1831 static inline int 1832 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 1833 unsigned int max_vecs, unsigned int flags, 1834 struct irq_affinity *aff_desc) 1835 { 1836 if ((flags & PCI_IRQ_INTX) && min_vecs == 1 && dev->irq) 1837 return 1; 1838 return -ENOSPC; 1839 } 1840 static inline int 1841 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 1842 unsigned int max_vecs, unsigned int flags) 1843 { 1844 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, 1845 flags, NULL); 1846 } 1847 1848 static inline bool pci_msix_can_alloc_dyn(struct pci_dev *dev) 1849 { return false; } 1850 static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index, 1851 const struct irq_affinity_desc *affdesc) 1852 { 1853 struct msi_map map = { .index = -ENOSYS, }; 1854 1855 return map; 1856 } 1857 1858 static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map) 1859 { 1860 } 1861 1862 static inline void pci_free_irq_vectors(struct pci_dev *dev) 1863 { 1864 } 1865 1866 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 1867 { 1868 if (WARN_ON_ONCE(nr > 0)) 1869 return -EINVAL; 1870 return dev->irq; 1871 } 1872 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, 1873 int vec) 1874 { 1875 return cpu_possible_mask; 1876 } 1877 1878 static inline unsigned int pci_irq_type(struct pci_dev *pdev) 1879 { 1880 return PCI_IRQ_INTX; 1881 } 1882 #endif 1883 1884 /** 1885 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq 1886 * @d: the INTx IRQ domain 1887 * @node: the DT node for the device whose interrupt we're translating 1888 * @intspec: the interrupt specifier data from the DT 1889 * @intsize: the number of entries in @intspec 1890 * @out_hwirq: pointer at which to write the hwirq number 1891 * @out_type: pointer at which to write the interrupt type 1892 * 1893 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as 1894 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range 1895 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the 1896 * INTx value to obtain the hwirq number. 1897 * 1898 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range. 1899 */ 1900 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 1901 struct device_node *node, 1902 const u32 *intspec, 1903 unsigned int intsize, 1904 unsigned long *out_hwirq, 1905 unsigned int *out_type) 1906 { 1907 const u32 intx = intspec[0]; 1908 1909 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD) 1910 return -EINVAL; 1911 1912 *out_hwirq = intx - PCI_INTERRUPT_INTA; 1913 return 0; 1914 } 1915 1916 #ifdef CONFIG_PCIEPORTBUS 1917 extern bool pcie_ports_disabled; 1918 extern bool pcie_ports_native; 1919 1920 int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_req, 1921 bool use_lt); 1922 #else 1923 #define pcie_ports_disabled true 1924 #define pcie_ports_native false 1925 1926 static inline int pcie_set_target_speed(struct pci_dev *port, 1927 enum pci_bus_speed speed_req, 1928 bool use_lt) 1929 { 1930 return -EOPNOTSUPP; 1931 } 1932 #endif 1933 1934 #define PCIE_LINK_STATE_L0S (BIT(0) | BIT(1)) /* Upstr/dwnstr L0s */ 1935 #define PCIE_LINK_STATE_L1 BIT(2) /* L1 state */ 1936 #define PCIE_LINK_STATE_L1_1 BIT(3) /* ASPM L1.1 state */ 1937 #define PCIE_LINK_STATE_L1_2 BIT(4) /* ASPM L1.2 state */ 1938 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5) /* PCI-PM L1.1 state */ 1939 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6) /* PCI-PM L1.2 state */ 1940 #define PCIE_LINK_STATE_ASPM_ALL (PCIE_LINK_STATE_L0S |\ 1941 PCIE_LINK_STATE_L1 |\ 1942 PCIE_LINK_STATE_L1_1 |\ 1943 PCIE_LINK_STATE_L1_2 |\ 1944 PCIE_LINK_STATE_L1_1_PCIPM |\ 1945 PCIE_LINK_STATE_L1_2_PCIPM) 1946 #define PCIE_LINK_STATE_CLKPM BIT(7) 1947 #define PCIE_LINK_STATE_ALL (PCIE_LINK_STATE_ASPM_ALL |\ 1948 PCIE_LINK_STATE_CLKPM) 1949 1950 #ifdef CONFIG_PCIEASPM 1951 int pci_disable_link_state(struct pci_dev *pdev, int state); 1952 int pci_disable_link_state_locked(struct pci_dev *pdev, int state); 1953 int pci_enable_link_state(struct pci_dev *pdev, int state); 1954 int pci_enable_link_state_locked(struct pci_dev *pdev, int state); 1955 void pcie_no_aspm(void); 1956 bool pcie_aspm_support_enabled(void); 1957 bool pcie_aspm_enabled(struct pci_dev *pdev); 1958 #else 1959 static inline int pci_disable_link_state(struct pci_dev *pdev, int state) 1960 { return 0; } 1961 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state) 1962 { return 0; } 1963 static inline int pci_enable_link_state(struct pci_dev *pdev, int state) 1964 { return 0; } 1965 static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state) 1966 { return 0; } 1967 static inline void pcie_no_aspm(void) { } 1968 static inline bool pcie_aspm_support_enabled(void) { return false; } 1969 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; } 1970 #endif 1971 1972 #ifdef CONFIG_HOTPLUG_PCI 1973 void pci_hp_ignore_link_change(struct pci_dev *pdev); 1974 void pci_hp_unignore_link_change(struct pci_dev *pdev); 1975 #else 1976 static inline void pci_hp_ignore_link_change(struct pci_dev *pdev) { } 1977 static inline void pci_hp_unignore_link_change(struct pci_dev *pdev) { } 1978 #endif 1979 1980 #ifdef CONFIG_PCIEAER 1981 bool pci_aer_available(void); 1982 #else 1983 static inline bool pci_aer_available(void) { return false; } 1984 #endif 1985 1986 bool pci_ats_disabled(void); 1987 1988 #define PCIE_PTM_CONTEXT_UPDATE_AUTO 0 1989 #define PCIE_PTM_CONTEXT_UPDATE_MANUAL 1 1990 1991 struct pcie_ptm_ops { 1992 int (*check_capability)(void *drvdata); 1993 int (*context_update_write)(void *drvdata, u8 mode); 1994 int (*context_update_read)(void *drvdata, u8 *mode); 1995 int (*context_valid_write)(void *drvdata, bool valid); 1996 int (*context_valid_read)(void *drvdata, bool *valid); 1997 int (*local_clock_read)(void *drvdata, u64 *clock); 1998 int (*master_clock_read)(void *drvdata, u64 *clock); 1999 int (*t1_read)(void *drvdata, u64 *clock); 2000 int (*t2_read)(void *drvdata, u64 *clock); 2001 int (*t3_read)(void *drvdata, u64 *clock); 2002 int (*t4_read)(void *drvdata, u64 *clock); 2003 2004 bool (*context_update_visible)(void *drvdata); 2005 bool (*context_valid_visible)(void *drvdata); 2006 bool (*local_clock_visible)(void *drvdata); 2007 bool (*master_clock_visible)(void *drvdata); 2008 bool (*t1_visible)(void *drvdata); 2009 bool (*t2_visible)(void *drvdata); 2010 bool (*t3_visible)(void *drvdata); 2011 bool (*t4_visible)(void *drvdata); 2012 }; 2013 2014 struct pci_ptm_debugfs { 2015 struct dentry *debugfs; 2016 const struct pcie_ptm_ops *ops; 2017 struct mutex lock; 2018 void *pdata; 2019 }; 2020 2021 #ifdef CONFIG_PCIE_PTM 2022 int pci_enable_ptm(struct pci_dev *dev); 2023 void pci_disable_ptm(struct pci_dev *dev); 2024 bool pcie_ptm_enabled(struct pci_dev *dev); 2025 #else 2026 static inline int pci_enable_ptm(struct pci_dev *dev) 2027 { return -EINVAL; } 2028 static inline void pci_disable_ptm(struct pci_dev *dev) { } 2029 static inline bool pcie_ptm_enabled(struct pci_dev *dev) 2030 { return false; } 2031 #endif 2032 2033 #if IS_ENABLED(CONFIG_DEBUG_FS) && IS_ENABLED(CONFIG_PCIE_PTM) 2034 struct pci_ptm_debugfs *pcie_ptm_create_debugfs(struct device *dev, void *pdata, 2035 const struct pcie_ptm_ops *ops); 2036 void pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs); 2037 #else 2038 static inline struct pci_ptm_debugfs 2039 *pcie_ptm_create_debugfs(struct device *dev, void *pdata, 2040 const struct pcie_ptm_ops *ops) { return NULL; } 2041 static inline void 2042 pcie_ptm_destroy_debugfs(struct pci_ptm_debugfs *ptm_debugfs) { } 2043 #endif 2044 2045 void pci_cfg_access_lock(struct pci_dev *dev); 2046 bool pci_cfg_access_trylock(struct pci_dev *dev); 2047 void pci_cfg_access_unlock(struct pci_dev *dev); 2048 2049 void pci_dev_lock(struct pci_dev *dev); 2050 int pci_dev_trylock(struct pci_dev *dev); 2051 void pci_dev_unlock(struct pci_dev *dev); 2052 DEFINE_GUARD(pci_dev, struct pci_dev *, pci_dev_lock(_T), pci_dev_unlock(_T)) 2053 2054 /* 2055 * PCI domain support. Sometimes called PCI segment (eg by ACPI), 2056 * a PCI domain is defined to be a set of PCI buses which share 2057 * configuration space. 2058 */ 2059 #ifdef CONFIG_PCI_DOMAINS 2060 extern int pci_domains_supported; 2061 int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max); 2062 void pci_bus_release_emul_domain_nr(int domain_nr); 2063 #else 2064 enum { pci_domains_supported = 0 }; 2065 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2066 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } 2067 static inline int pci_bus_find_emul_domain_nr(u32 hint, u32 min, u32 max) 2068 { 2069 return 0; 2070 } 2071 static inline void pci_bus_release_emul_domain_nr(int domain_nr) { } 2072 #endif /* CONFIG_PCI_DOMAINS */ 2073 2074 /* 2075 * Generic implementation for PCI domain support. If your 2076 * architecture does not need custom management of PCI 2077 * domains then this implementation will be used 2078 */ 2079 #ifdef CONFIG_PCI_DOMAINS_GENERIC 2080 static inline int pci_domain_nr(struct pci_bus *bus) 2081 { 2082 return bus->domain_nr; 2083 } 2084 #ifdef CONFIG_ACPI 2085 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus); 2086 #else 2087 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) 2088 { return 0; } 2089 #endif 2090 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 2091 void pci_bus_release_domain_nr(struct device *parent, int domain_nr); 2092 #endif 2093 2094 /* Some architectures require additional setup to direct VGA traffic */ 2095 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 2096 unsigned int command_bits, u32 flags); 2097 void pci_register_set_vga_state(arch_set_vga_state_t func); 2098 2099 static inline int 2100 pci_request_io_regions(struct pci_dev *pdev, const char *name) 2101 { 2102 return pci_request_selected_regions(pdev, 2103 pci_select_bars(pdev, IORESOURCE_IO), name); 2104 } 2105 2106 static inline void 2107 pci_release_io_regions(struct pci_dev *pdev) 2108 { 2109 return pci_release_selected_regions(pdev, 2110 pci_select_bars(pdev, IORESOURCE_IO)); 2111 } 2112 2113 static inline int 2114 pci_request_mem_regions(struct pci_dev *pdev, const char *name) 2115 { 2116 return pci_request_selected_regions(pdev, 2117 pci_select_bars(pdev, IORESOURCE_MEM), name); 2118 } 2119 2120 static inline void 2121 pci_release_mem_regions(struct pci_dev *pdev) 2122 { 2123 return pci_release_selected_regions(pdev, 2124 pci_select_bars(pdev, IORESOURCE_MEM)); 2125 } 2126 2127 bool pci_suspend_retains_context(struct pci_dev *pdev); 2128 2129 #else /* CONFIG_PCI is not enabled */ 2130 2131 static inline void pci_set_flags(int flags) { } 2132 static inline void pci_add_flags(int flags) { } 2133 static inline void pci_clear_flags(int flags) { } 2134 static inline int pci_has_flag(int flag) { return 0; } 2135 2136 /* 2137 * If the system does not have PCI, clearly these return errors. Define 2138 * these as simple inline functions to avoid hair in drivers. 2139 */ 2140 #define _PCI_NOP(o, s, t) \ 2141 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 2142 int where, t val) \ 2143 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 2144 2145 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ 2146 _PCI_NOP(o, word, u16 x) \ 2147 _PCI_NOP(o, dword, u32 x) 2148 _PCI_NOP_ALL(read, *) 2149 _PCI_NOP_ALL(write,) 2150 2151 static inline void pci_probe_flush_workqueue(void) { } 2152 2153 static inline struct pci_dev *pci_get_device(unsigned int vendor, 2154 unsigned int device, 2155 struct pci_dev *from) 2156 { return NULL; } 2157 2158 static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor, 2159 unsigned int device, 2160 struct pci_dev *from) 2161 { return NULL; } 2162 2163 static inline struct pci_dev *pci_get_subsys(unsigned int vendor, 2164 unsigned int device, 2165 unsigned int ss_vendor, 2166 unsigned int ss_device, 2167 struct pci_dev *from) 2168 { return NULL; } 2169 2170 static inline struct pci_dev *pci_get_class(unsigned int class, 2171 struct pci_dev *from) 2172 { return NULL; } 2173 2174 static inline struct pci_dev *pci_get_base_class(unsigned int class, 2175 struct pci_dev *from) 2176 { return NULL; } 2177 2178 static inline int pci_dev_present(const struct pci_device_id *ids) 2179 { return 0; } 2180 2181 #define pci_dev_put(dev) do { } while (0) 2182 2183 static inline void pci_set_master(struct pci_dev *dev) { } 2184 static inline void pci_clear_master(struct pci_dev *dev) { } 2185 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 2186 static inline void pci_disable_device(struct pci_dev *dev) { } 2187 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; } 2188 static inline int pci_assign_resource(struct pci_dev *dev, int i) 2189 { return -EBUSY; } 2190 static inline int __must_check __pci_register_driver(struct pci_driver *drv, 2191 struct module *owner, 2192 const char *mod_name) 2193 { return 0; } 2194 static inline int pci_register_driver(struct pci_driver *drv) 2195 { return 0; } 2196 static inline void pci_unregister_driver(struct pci_driver *drv) { } 2197 static inline u8 pci_find_capability(struct pci_dev *dev, int cap) 2198 { return 0; } 2199 static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap) 2200 { return 0; } 2201 static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap) 2202 { return 0; } 2203 2204 static inline u64 pci_get_dsn(struct pci_dev *dev) 2205 { return 0; } 2206 2207 /* Power management related routines */ 2208 static inline int pci_save_state(struct pci_dev *dev) { return 0; } 2209 static inline void pci_restore_state(struct pci_dev *dev) { } 2210 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 2211 { return 0; } 2212 static inline int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state) 2213 { return 0; } 2214 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) 2215 { return 0; } 2216 static inline pci_power_t pci_choose_state(struct pci_dev *dev, 2217 pm_message_t state) 2218 { return PCI_D0; } 2219 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, 2220 int enable) 2221 { return 0; } 2222 2223 static inline struct resource *pci_find_resource(struct pci_dev *dev, 2224 struct resource *res) 2225 { return NULL; } 2226 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) 2227 { return -EIO; } 2228 static inline void pci_release_regions(struct pci_dev *dev) { } 2229 2230 static inline int pci_register_io_range(const struct fwnode_handle *fwnode, 2231 phys_addr_t addr, resource_size_t size) 2232 { return -EINVAL; } 2233 2234 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; } 2235 2236 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) 2237 { return NULL; } 2238 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, 2239 unsigned int devfn) 2240 { return NULL; } 2241 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain, 2242 unsigned int bus, unsigned int devfn) 2243 { return NULL; } 2244 2245 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } 2246 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } 2247 2248 #define dev_is_pci(d) (false) 2249 #define dev_is_pf(d) (false) 2250 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 2251 { return false; } 2252 static inline int pci_irqd_intx_xlate(struct irq_domain *d, 2253 struct device_node *node, 2254 const u32 *intspec, 2255 unsigned int intsize, 2256 unsigned long *out_hwirq, 2257 unsigned int *out_type) 2258 { return -EINVAL; } 2259 2260 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, 2261 struct pci_dev *dev) 2262 { return NULL; } 2263 static inline bool pci_ats_disabled(void) { return true; } 2264 2265 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) 2266 { 2267 return -EINVAL; 2268 } 2269 2270 static inline int 2271 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs, 2272 unsigned int max_vecs, unsigned int flags, 2273 struct irq_affinity *aff_desc) 2274 { 2275 return -ENOSPC; 2276 } 2277 static inline int 2278 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs, 2279 unsigned int max_vecs, unsigned int flags) 2280 { 2281 return -ENOSPC; 2282 } 2283 2284 static inline void pci_free_irq_vectors(struct pci_dev *dev) 2285 { 2286 } 2287 2288 static inline bool pci_suspend_retains_context(struct pci_dev *pdev) 2289 { 2290 return true; 2291 } 2292 2293 static inline unsigned int pci_irq_type(struct pci_dev *pdev) 2294 { 2295 return 0; 2296 } 2297 #endif /* CONFIG_PCI */ 2298 2299 /* Include architecture-dependent settings and functions */ 2300 2301 #include <asm/pci.h> 2302 2303 /* 2304 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff 2305 * is expected to be an offset within that region. 2306 * 2307 */ 2308 int pci_mmap_resource_range(struct pci_dev *dev, int bar, 2309 struct vm_area_struct *vma, 2310 enum pci_mmap_state mmap_state, int write_combine); 2311 2312 #ifndef arch_can_pci_mmap_wc 2313 #define arch_can_pci_mmap_wc() 0 2314 #endif 2315 2316 #ifndef arch_can_pci_mmap_io 2317 #define arch_can_pci_mmap_io() 0 2318 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL) 2319 #else 2320 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma); 2321 #endif 2322 2323 #ifndef pci_root_bus_fwnode 2324 #define pci_root_bus_fwnode(bus) NULL 2325 #endif 2326 2327 /* 2328 * These helpers provide future and backwards compatibility 2329 * for accessing popular PCI BAR info 2330 */ 2331 #define pci_resource_n(dev, bar) (&(dev)->resource[(bar)]) 2332 #define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start) 2333 #define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end) 2334 #define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags) 2335 #define pci_resource_len(dev,bar) \ 2336 (pci_resource_end((dev), (bar)) ? \ 2337 resource_size(pci_resource_n((dev), (bar))) : 0) 2338 2339 #define __pci_dev_for_each_res0(dev, res, ...) \ 2340 for (unsigned int __b = 0; \ 2341 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2342 __b++) 2343 2344 #define __pci_dev_for_each_res1(dev, res, __b) \ 2345 for (__b = 0; \ 2346 __b < PCI_NUM_RESOURCES && (res = pci_resource_n(dev, __b)); \ 2347 __b++) 2348 2349 #define pci_dev_for_each_resource(dev, res, ...) \ 2350 CONCATENATE(__pci_dev_for_each_res, COUNT_ARGS(__VA_ARGS__)) \ 2351 (dev, res, __VA_ARGS__) 2352 2353 /** 2354 * pci_resource_is_io - check if a PCI resource is of I/O port type. 2355 * @dev: PCI device to check. 2356 * @resno: The resource number (BAR index) to check. 2357 * 2358 * Returns true if the resource type is I/O port. 2359 */ 2360 static inline bool pci_resource_is_io(const struct pci_dev *dev, int resno) 2361 { 2362 return resource_type(pci_resource_n(dev, resno)) == IORESOURCE_IO; 2363 } 2364 2365 /** 2366 * pci_resource_is_mem - check if a PCI resource is of memory type. 2367 * @dev: PCI device to check. 2368 * @resno: The resource number (BAR index) to check. 2369 * 2370 * Returns true if the resource type is memory, including 2371 * prefetchable memory. 2372 */ 2373 static inline bool pci_resource_is_mem(const struct pci_dev *dev, int resno) 2374 { 2375 return resource_type(pci_resource_n(dev, resno)) == IORESOURCE_MEM; 2376 } 2377 2378 /* 2379 * Similar to the helpers above, these manipulate per-pci_dev 2380 * driver-specific data. They are really just a wrapper around 2381 * the generic device structure functions of these calls. 2382 */ 2383 static inline void *pci_get_drvdata(struct pci_dev *pdev) 2384 { 2385 return dev_get_drvdata(&pdev->dev); 2386 } 2387 2388 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) 2389 { 2390 dev_set_drvdata(&pdev->dev, data); 2391 } 2392 2393 static inline const char *pci_name(const struct pci_dev *pdev) 2394 { 2395 return dev_name(&pdev->dev); 2396 } 2397 2398 void pci_resource_to_user(const struct pci_dev *dev, int bar, 2399 const struct resource *rsrc, 2400 resource_size_t *start, resource_size_t *end); 2401 2402 /* 2403 * The world is not perfect and supplies us with broken PCI devices. 2404 * For at least a part of these bugs we need a work-around, so both 2405 * generic (drivers/pci/quirks.c) and per-architecture code can define 2406 * fixup hooks to be called for particular buggy devices. 2407 */ 2408 2409 struct pci_fixup { 2410 u16 vendor; /* Or PCI_ANY_ID */ 2411 u16 device; /* Or PCI_ANY_ID */ 2412 u32 class; /* Or PCI_ANY_ID */ 2413 unsigned int class_shift; /* should be 0, 8, 16 */ 2414 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2415 int hook_offset; 2416 #else 2417 void (*hook)(struct pci_dev *dev); 2418 #endif 2419 }; 2420 2421 enum pci_fixup_pass { 2422 pci_fixup_early, /* Before probing BARs */ 2423 pci_fixup_header, /* After reading configuration header */ 2424 pci_fixup_final, /* Final phase of device fixups */ 2425 pci_fixup_enable, /* pci_enable_device() time */ 2426 pci_fixup_resume, /* pci_device_resume() */ 2427 pci_fixup_suspend, /* pci_device_suspend() */ 2428 pci_fixup_resume_early, /* pci_device_resume_early() */ 2429 pci_fixup_suspend_late, /* pci_device_suspend_late() */ 2430 }; 2431 2432 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 2433 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2434 class_shift, hook) \ 2435 __ADDRESSABLE(hook) \ 2436 asm(".section " #sec ", \"a\" \n" \ 2437 ".balign 16 \n" \ 2438 ".short " #vendor ", " #device " \n" \ 2439 ".long " #class ", " #class_shift " \n" \ 2440 ".long " #hook " - . \n" \ 2441 ".previous \n"); 2442 2443 /* 2444 * Clang's LTO may rename static functions in C, but has no way to 2445 * handle such renamings when referenced from inline asm. To work 2446 * around this, create global C stubs for these cases. 2447 */ 2448 #ifdef CONFIG_LTO_CLANG 2449 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2450 class_shift, hook, stub) \ 2451 void stub(struct pci_dev *dev); \ 2452 void stub(struct pci_dev *dev) \ 2453 { \ 2454 hook(dev); \ 2455 } \ 2456 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2457 class_shift, stub) 2458 #else 2459 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2460 class_shift, hook, stub) \ 2461 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2462 class_shift, hook) 2463 #endif 2464 2465 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2466 class_shift, hook) \ 2467 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \ 2468 class_shift, hook, __UNIQUE_ID(hook)) 2469 #else 2470 /* Anonymous variables would be nice... */ 2471 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ 2472 class_shift, hook) \ 2473 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ 2474 __attribute__((__section__(#section), aligned((sizeof(void *))))) \ 2475 = { vendor, device, class, class_shift, hook }; 2476 #endif 2477 2478 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ 2479 class_shift, hook) \ 2480 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2481 hook, vendor, device, class, class_shift, hook) 2482 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ 2483 class_shift, hook) \ 2484 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2485 hook, vendor, device, class, class_shift, hook) 2486 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ 2487 class_shift, hook) \ 2488 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2489 hook, vendor, device, class, class_shift, hook) 2490 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ 2491 class_shift, hook) \ 2492 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2493 hook, vendor, device, class, class_shift, hook) 2494 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 2495 class_shift, hook) \ 2496 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2497 resume##hook, vendor, device, class, class_shift, hook) 2498 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 2499 class_shift, hook) \ 2500 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2501 resume_early##hook, vendor, device, class, class_shift, hook) 2502 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 2503 class_shift, hook) \ 2504 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2505 suspend##hook, vendor, device, class, class_shift, hook) 2506 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 2507 class_shift, hook) \ 2508 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2509 suspend_late##hook, vendor, device, class, class_shift, hook) 2510 2511 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 2512 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 2513 hook, vendor, device, PCI_ANY_ID, 0, hook) 2514 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ 2515 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ 2516 hook, vendor, device, PCI_ANY_ID, 0, hook) 2517 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ 2518 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ 2519 hook, vendor, device, PCI_ANY_ID, 0, hook) 2520 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ 2521 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ 2522 hook, vendor, device, PCI_ANY_ID, 0, hook) 2523 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 2524 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 2525 resume##hook, vendor, device, PCI_ANY_ID, 0, hook) 2526 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 2527 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 2528 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook) 2529 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 2530 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 2531 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook) 2532 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 2533 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 2534 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook) 2535 2536 #ifdef CONFIG_PCI_QUIRKS 2537 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 2538 #else 2539 static inline void pci_fixup_device(enum pci_fixup_pass pass, 2540 struct pci_dev *dev) { } 2541 #endif 2542 2543 int pcim_intx(struct pci_dev *pdev, int enabled); 2544 int pcim_request_all_regions(struct pci_dev *pdev, const char *name); 2545 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); 2546 void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar, 2547 const char *name); 2548 void pcim_iounmap_region(struct pci_dev *pdev, int bar); 2549 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); 2550 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); 2551 int pcim_request_region(struct pci_dev *pdev, int bar, const char *name); 2552 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); 2553 void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar, 2554 unsigned long offset, unsigned long len); 2555 2556 extern int pci_pci_problems; 2557 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ 2558 #define PCIPCI_TRITON 2 2559 #define PCIPCI_NATOMA 4 2560 #define PCIPCI_VIAETBF 8 2561 #define PCIPCI_VSFX 16 2562 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ 2563 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ 2564 2565 extern u8 pci_dfl_cache_line_size; 2566 extern u8 pci_cache_line_size; 2567 2568 /* Architecture-specific versions may override these (weak) */ 2569 void pcibios_disable_device(struct pci_dev *dev); 2570 void pcibios_set_master(struct pci_dev *dev); 2571 int pcibios_set_pcie_reset_state(struct pci_dev *dev, 2572 enum pcie_reset_state state); 2573 int pcibios_device_add(struct pci_dev *dev); 2574 void pcibios_release_device(struct pci_dev *dev); 2575 #ifdef CONFIG_PCI 2576 void pcibios_penalize_isa_irq(int irq, int active); 2577 #else 2578 static inline void pcibios_penalize_isa_irq(int irq, int active) {} 2579 #endif 2580 int pcibios_alloc_irq(struct pci_dev *dev); 2581 void pcibios_free_irq(struct pci_dev *dev); 2582 resource_size_t pcibios_default_alignment(void); 2583 2584 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG) 2585 void __init pci_mmcfg_early_init(void); 2586 void __init pci_mmcfg_late_init(void); 2587 #else 2588 static inline void pci_mmcfg_early_init(void) { } 2589 static inline void pci_mmcfg_late_init(void) { } 2590 #endif 2591 2592 int pci_ext_cfg_avail(void); 2593 2594 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); 2595 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); 2596 2597 #ifdef CONFIG_PCI_IOV 2598 int pci_iov_virtfn_bus(struct pci_dev *dev, int id); 2599 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); 2600 int pci_iov_vf_id(struct pci_dev *dev); 2601 void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver); 2602 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); 2603 void pci_disable_sriov(struct pci_dev *dev); 2604 2605 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id); 2606 int pci_iov_add_virtfn(struct pci_dev *dev, int id); 2607 void pci_iov_remove_virtfn(struct pci_dev *dev, int id); 2608 int pci_num_vf(struct pci_dev *dev); 2609 int pci_vfs_assigned(struct pci_dev *dev); 2610 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); 2611 unsigned int pci_sriov_get_totalvfs(struct pci_dev *dev); 2612 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); 2613 resource_size_t pci_iov_resource_size(const struct pci_dev *dev, int resno); 2614 int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size); 2615 u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs); 2616 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); 2617 2618 /* Arch may override these (weak) */ 2619 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs); 2620 int pcibios_sriov_disable(struct pci_dev *pdev); 2621 resource_size_t pcibios_iov_resource_alignment(const struct pci_dev *dev, 2622 int resno); 2623 #else 2624 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) 2625 { 2626 return -ENOSYS; 2627 } 2628 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) 2629 { 2630 return -ENOSYS; 2631 } 2632 2633 static inline int pci_iov_vf_id(struct pci_dev *dev) 2634 { 2635 return -ENOSYS; 2636 } 2637 2638 static inline void *pci_iov_get_pf_drvdata(struct pci_dev *dev, 2639 struct pci_driver *pf_driver) 2640 { 2641 return ERR_PTR(-EINVAL); 2642 } 2643 2644 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 2645 { return -ENODEV; } 2646 2647 static inline int pci_iov_sysfs_link(struct pci_dev *dev, 2648 struct pci_dev *virtfn, int id) 2649 { 2650 return -ENODEV; 2651 } 2652 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id) 2653 { 2654 return -ENOSYS; 2655 } 2656 static inline void pci_iov_remove_virtfn(struct pci_dev *dev, 2657 int id) { } 2658 static inline void pci_disable_sriov(struct pci_dev *dev) { } 2659 static inline int pci_num_vf(struct pci_dev *dev) { return 0; } 2660 static inline int pci_vfs_assigned(struct pci_dev *dev) 2661 { return 0; } 2662 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) 2663 { return 0; } 2664 static inline unsigned int pci_sriov_get_totalvfs(struct pci_dev *dev) 2665 { return 0; } 2666 #define pci_sriov_configure_simple NULL 2667 static inline resource_size_t pci_iov_resource_size(const struct pci_dev *dev, 2668 int resno) 2669 { return 0; } 2670 static inline int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) 2671 { return -ENODEV; } 2672 static inline u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) 2673 { return 0; } 2674 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { } 2675 #endif 2676 2677 /** 2678 * pci_pcie_cap - get the saved PCIe capability offset 2679 * @dev: PCI device 2680 * 2681 * PCIe capability offset is calculated at PCI device initialization 2682 * time and saved in the data structure. This function returns saved 2683 * PCIe capability offset. Using this instead of pci_find_capability() 2684 * reduces unnecessary search in the PCI configuration space. If you 2685 * need to calculate PCIe capability offset from raw device for some 2686 * reasons, please use pci_find_capability() instead. 2687 */ 2688 static inline int pci_pcie_cap(struct pci_dev *dev) 2689 { 2690 return dev->pcie_cap; 2691 } 2692 2693 /** 2694 * pci_is_pcie - check if the PCI device is PCI Express capable 2695 * @dev: PCI device 2696 * 2697 * Returns: true if the PCI device is PCI Express capable, false otherwise. 2698 */ 2699 static inline bool pci_is_pcie(struct pci_dev *dev) 2700 { 2701 return pci_pcie_cap(dev); 2702 } 2703 2704 /** 2705 * pcie_caps_reg - get the PCIe Capabilities Register 2706 * @dev: PCI device 2707 */ 2708 static inline u16 pcie_caps_reg(const struct pci_dev *dev) 2709 { 2710 return dev->pcie_flags_reg; 2711 } 2712 2713 /** 2714 * pci_pcie_type - get the PCIe device/port type 2715 * @dev: PCI device 2716 */ 2717 static inline int pci_pcie_type(const struct pci_dev *dev) 2718 { 2719 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 2720 } 2721 2722 /** 2723 * pcie_find_root_port - Get the PCIe root port device 2724 * @dev: PCI device 2725 * 2726 * Traverse up the parent chain and return the PCIe Root Port PCI Device 2727 * for a given PCI/PCIe Device. 2728 */ 2729 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev) 2730 { 2731 while (dev) { 2732 if (pci_is_pcie(dev) && 2733 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 2734 return dev; 2735 dev = pci_upstream_bridge(dev); 2736 } 2737 2738 return NULL; 2739 } 2740 2741 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev) 2742 { 2743 /* 2744 * error_state is set in pci_dev_set_io_state() using xchg/cmpxchg() 2745 * and read w/o common lock. READ_ONCE() ensures compiler cannot cache 2746 * the value (e.g. inside the loop in pci_dev_wait()). 2747 */ 2748 return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure; 2749 } 2750 2751 void pci_request_acs(void); 2752 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2753 bool pci_acs_path_enabled(struct pci_dev *start, 2754 struct pci_dev *end, u16 acs_flags); 2755 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); 2756 2757 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2758 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2759 2760 /* Large Resource Data Type Tag Item Names */ 2761 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ 2762 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ 2763 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ 2764 2765 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) 2766 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) 2767 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) 2768 2769 #define PCI_VPD_RO_KEYWORD_PARTNO "PN" 2770 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN" 2771 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" 2772 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" 2773 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" 2774 2775 /** 2776 * pci_vpd_alloc - Allocate buffer and read VPD into it 2777 * @dev: PCI device 2778 * @size: pointer to field where VPD length is returned 2779 * 2780 * Returns pointer to allocated buffer or an ERR_PTR in case of failure 2781 */ 2782 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size); 2783 2784 /** 2785 * pci_vpd_find_id_string - Locate id string in VPD 2786 * @buf: Pointer to buffered VPD data 2787 * @len: The length of the buffer area in which to search 2788 * @size: Pointer to field where length of id string is returned 2789 * 2790 * Returns the index of the id string or -ENOENT if not found. 2791 */ 2792 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size); 2793 2794 /** 2795 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section 2796 * @buf: Pointer to buffered VPD data 2797 * @len: The length of the buffer area in which to search 2798 * @kw: The keyword to search for 2799 * @size: Pointer to field where length of found keyword data is returned 2800 * 2801 * Returns the index of the information field keyword data or -ENOENT if 2802 * not found. 2803 */ 2804 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len, 2805 const char *kw, unsigned int *size); 2806 2807 /** 2808 * pci_vpd_check_csum - Check VPD checksum 2809 * @buf: Pointer to buffered VPD data 2810 * @len: VPD size 2811 * 2812 * Returns 1 if VPD has no checksum, otherwise 0 or an errno 2813 */ 2814 int pci_vpd_check_csum(const void *buf, unsigned int len); 2815 2816 /* PCI <-> OF binding helpers */ 2817 #ifdef CONFIG_OF 2818 struct device_node; 2819 struct irq_domain; 2820 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2821 bool pci_host_of_has_msi_map(struct device *dev); 2822 2823 /* Arch may override this (weak) */ 2824 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2825 2826 #else /* CONFIG_OF */ 2827 static inline struct irq_domain * 2828 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2829 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; } 2830 #endif /* CONFIG_OF */ 2831 2832 static inline struct device_node * 2833 pci_device_to_OF_node(const struct pci_dev *pdev) 2834 { 2835 return pdev ? pdev->dev.of_node : NULL; 2836 } 2837 2838 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 2839 { 2840 return bus ? bus->dev.of_node : NULL; 2841 } 2842 2843 #ifdef CONFIG_ACPI 2844 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2845 2846 void 2847 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); 2848 bool pci_pr3_present(struct pci_dev *pdev); 2849 #else 2850 static inline struct irq_domain * 2851 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } 2852 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } 2853 #endif 2854 2855 #if defined(CONFIG_X86) && defined(CONFIG_ACPI) 2856 bool arch_pci_dev_is_removable(struct pci_dev *pdev); 2857 #else 2858 static inline bool arch_pci_dev_is_removable(struct pci_dev *pdev) { return false; } 2859 #endif 2860 2861 #ifdef CONFIG_EEH 2862 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) 2863 { 2864 return pdev->dev.archdata.edev; 2865 } 2866 #endif 2867 2868 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns); 2869 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2); 2870 int pci_for_each_dma_alias(struct pci_dev *pdev, 2871 int (*fn)(struct pci_dev *pdev, 2872 u16 alias, void *data), void *data); 2873 2874 /* Helper functions for operation of device flag */ 2875 static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2876 { 2877 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2878 } 2879 static inline void pci_clear_dev_assigned(struct pci_dev *pdev) 2880 { 2881 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; 2882 } 2883 static inline bool pci_is_dev_assigned(struct pci_dev *pdev) 2884 { 2885 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; 2886 } 2887 2888 /** 2889 * pci_ari_enabled - query ARI forwarding status 2890 * @bus: the PCI bus 2891 * 2892 * Returns true if ARI forwarding is enabled. 2893 */ 2894 static inline bool pci_ari_enabled(struct pci_bus *bus) 2895 { 2896 return bus->self && bus->self->ari_enabled; 2897 } 2898 2899 /** 2900 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain 2901 * @pdev: PCI device to check 2902 * 2903 * Walk upwards from @pdev and check for each encountered bridge if it's part 2904 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not 2905 * Thunderbolt-attached. (But rather soldered to the mainboard usually.) 2906 */ 2907 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev) 2908 { 2909 struct pci_dev *parent = pdev; 2910 2911 if (pdev->is_thunderbolt) 2912 return true; 2913 2914 while ((parent = pci_upstream_bridge(parent))) 2915 if (parent->is_thunderbolt) 2916 return true; 2917 2918 return false; 2919 } 2920 2921 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH) || defined(CONFIG_S390) 2922 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type); 2923 #endif 2924 2925 #include <linux/dma-mapping.h> 2926 2927 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg) 2928 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg) 2929 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg) 2930 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg) 2931 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg) 2932 #define pci_warn_once(pdev, fmt, arg...) dev_warn_once(&(pdev)->dev, fmt, ##arg) 2933 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg) 2934 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg) 2935 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg) 2936 2937 #define pci_notice_ratelimited(pdev, fmt, arg...) \ 2938 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg) 2939 2940 #define pci_info_ratelimited(pdev, fmt, arg...) \ 2941 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg) 2942 2943 #define pci_WARN(pdev, condition, fmt, arg...) \ 2944 WARN(condition, "%s %s: " fmt, \ 2945 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2946 2947 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \ 2948 WARN_ONCE(condition, "%s %s: " fmt, \ 2949 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg) 2950 2951 #endif /* LINUX_PCI_H */ 2952