1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28 #ifndef __AST_DRV_H__
29 #define __AST_DRV_H__
30
31 #include <linux/io.h>
32 #include <linux/types.h>
33
34 #include <drm/drm_connector.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_mode.h>
38 #include <drm/drm_framebuffer.h>
39
40 #include "ast_reg.h"
41
42 #define DRIVER_AUTHOR "Dave Airlie"
43
44 #define DRIVER_NAME "ast"
45 #define DRIVER_DESC "AST"
46 #define DRIVER_DATE "20120228"
47
48 #define DRIVER_MAJOR 0
49 #define DRIVER_MINOR 1
50 #define DRIVER_PATCHLEVEL 0
51
52 #define PCI_CHIP_AST2000 0x2000
53 #define PCI_CHIP_AST2100 0x2010
54
55 #define __AST_CHIP(__gen, __index) ((__gen) << 16 | (__index))
56
57 enum ast_chip {
58 /* 1st gen */
59 AST1000 = __AST_CHIP(1, 0), // unused
60 AST2000 = __AST_CHIP(1, 1),
61 /* 2nd gen */
62 AST1100 = __AST_CHIP(2, 0),
63 AST2100 = __AST_CHIP(2, 1),
64 AST2050 = __AST_CHIP(2, 2), // unused
65 /* 3rd gen */
66 AST2200 = __AST_CHIP(3, 0),
67 AST2150 = __AST_CHIP(3, 1),
68 /* 4th gen */
69 AST2300 = __AST_CHIP(4, 0),
70 AST1300 = __AST_CHIP(4, 1),
71 AST1050 = __AST_CHIP(4, 2), // unused
72 /* 5th gen */
73 AST2400 = __AST_CHIP(5, 0),
74 AST1400 = __AST_CHIP(5, 1),
75 AST1250 = __AST_CHIP(5, 2), // unused
76 /* 6th gen */
77 AST2500 = __AST_CHIP(6, 0),
78 AST2510 = __AST_CHIP(6, 1),
79 AST2520 = __AST_CHIP(6, 2), // unused
80 /* 7th gen */
81 AST2600 = __AST_CHIP(7, 0),
82 AST2620 = __AST_CHIP(7, 1), // unused
83 };
84
85 #define __AST_CHIP_GEN(__chip) (((unsigned long)(__chip)) >> 16)
86
87 enum ast_tx_chip {
88 AST_TX_NONE,
89 AST_TX_SIL164,
90 AST_TX_DP501,
91 AST_TX_ASTDP,
92 };
93
94 #define AST_TX_NONE_BIT BIT(AST_TX_NONE)
95 #define AST_TX_SIL164_BIT BIT(AST_TX_SIL164)
96 #define AST_TX_DP501_BIT BIT(AST_TX_DP501)
97 #define AST_TX_ASTDP_BIT BIT(AST_TX_ASTDP)
98
99 enum ast_config_mode {
100 ast_use_p2a,
101 ast_use_dt,
102 ast_use_defaults
103 };
104
105 #define AST_DRAM_512Mx16 0
106 #define AST_DRAM_1Gx16 1
107 #define AST_DRAM_512Mx32 2
108 #define AST_DRAM_1Gx32 3
109 #define AST_DRAM_2Gx16 6
110 #define AST_DRAM_4Gx16 7
111 #define AST_DRAM_8Gx16 8
112
113 /*
114 * Hardware cursor
115 */
116
117 #define AST_MAX_HWC_WIDTH 64
118 #define AST_MAX_HWC_HEIGHT 64
119
120 #define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
121 #define AST_HWC_SIGNATURE_SIZE 32
122
123 /* define for signature structure */
124 #define AST_HWC_SIGNATURE_CHECKSUM 0x00
125 #define AST_HWC_SIGNATURE_SizeX 0x04
126 #define AST_HWC_SIGNATURE_SizeY 0x08
127 #define AST_HWC_SIGNATURE_X 0x0C
128 #define AST_HWC_SIGNATURE_Y 0x10
129 #define AST_HWC_SIGNATURE_HOTSPOTX 0x14
130 #define AST_HWC_SIGNATURE_HOTSPOTY 0x18
131
132 /*
133 * Planes
134 */
135
136 struct ast_plane {
137 struct drm_plane base;
138
139 void __iomem *vaddr;
140 u64 offset;
141 unsigned long size;
142 };
143
to_ast_plane(struct drm_plane * plane)144 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane)
145 {
146 return container_of(plane, struct ast_plane, base);
147 }
148
149 /*
150 * Connector
151 */
152
153 struct ast_connector {
154 struct drm_connector base;
155
156 enum drm_connector_status physical_status;
157 };
158
159 static inline struct ast_connector *
to_ast_connector(struct drm_connector * connector)160 to_ast_connector(struct drm_connector *connector)
161 {
162 return container_of(connector, struct ast_connector, base);
163 }
164
165 /*
166 * Device
167 */
168
169 struct ast_device {
170 struct drm_device base;
171
172 void __iomem *regs;
173 void __iomem *ioregs;
174 void __iomem *dp501_fw_buf;
175
176 enum ast_config_mode config_mode;
177 enum ast_chip chip;
178
179 uint32_t dram_bus_width;
180 uint32_t dram_type;
181 uint32_t mclk;
182
183 void __iomem *vram;
184 unsigned long vram_base;
185 unsigned long vram_size;
186 unsigned long vram_fb_available;
187
188 struct mutex modeset_lock; /* Protects access to modeset I/O registers in ioregs */
189
190 struct ast_plane primary_plane;
191 struct ast_plane cursor_plane;
192 struct drm_crtc crtc;
193 struct {
194 struct {
195 struct drm_encoder encoder;
196 struct ast_connector connector;
197 } vga;
198 struct {
199 struct drm_encoder encoder;
200 struct ast_connector connector;
201 } sil164;
202 struct {
203 struct drm_encoder encoder;
204 struct ast_connector connector;
205 } dp501;
206 struct {
207 struct drm_encoder encoder;
208 struct ast_connector connector;
209 } astdp;
210 } output;
211
212 bool support_wide_screen;
213
214 unsigned long tx_chip_types; /* bitfield of enum ast_chip_type */
215 u8 *dp501_fw_addr;
216 const struct firmware *dp501_fw; /* dp501 fw */
217 };
218
to_ast_device(struct drm_device * dev)219 static inline struct ast_device *to_ast_device(struct drm_device *dev)
220 {
221 return container_of(dev, struct ast_device, base);
222 }
223
224 struct drm_device *ast_device_create(struct pci_dev *pdev,
225 const struct drm_driver *drv,
226 enum ast_chip chip,
227 enum ast_config_mode config_mode,
228 void __iomem *regs,
229 void __iomem *ioregs,
230 bool need_post);
231
__ast_gen(struct ast_device * ast)232 static inline unsigned long __ast_gen(struct ast_device *ast)
233 {
234 return __AST_CHIP_GEN(ast->chip);
235 }
236 #define AST_GEN(__ast) __ast_gen(__ast)
237
__ast_gen_is_eq(struct ast_device * ast,unsigned long gen)238 static inline bool __ast_gen_is_eq(struct ast_device *ast, unsigned long gen)
239 {
240 return __ast_gen(ast) == gen;
241 }
242 #define IS_AST_GEN1(__ast) __ast_gen_is_eq(__ast, 1)
243 #define IS_AST_GEN2(__ast) __ast_gen_is_eq(__ast, 2)
244 #define IS_AST_GEN3(__ast) __ast_gen_is_eq(__ast, 3)
245 #define IS_AST_GEN4(__ast) __ast_gen_is_eq(__ast, 4)
246 #define IS_AST_GEN5(__ast) __ast_gen_is_eq(__ast, 5)
247 #define IS_AST_GEN6(__ast) __ast_gen_is_eq(__ast, 6)
248 #define IS_AST_GEN7(__ast) __ast_gen_is_eq(__ast, 7)
249
__ast_read8(const void __iomem * addr,u32 reg)250 static inline u8 __ast_read8(const void __iomem *addr, u32 reg)
251 {
252 return ioread8(addr + reg);
253 }
254
__ast_read32(const void __iomem * addr,u32 reg)255 static inline u32 __ast_read32(const void __iomem *addr, u32 reg)
256 {
257 return ioread32(addr + reg);
258 }
259
__ast_write8(void __iomem * addr,u32 reg,u8 val)260 static inline void __ast_write8(void __iomem *addr, u32 reg, u8 val)
261 {
262 iowrite8(val, addr + reg);
263 }
264
__ast_write32(void __iomem * addr,u32 reg,u32 val)265 static inline void __ast_write32(void __iomem *addr, u32 reg, u32 val)
266 {
267 iowrite32(val, addr + reg);
268 }
269
__ast_read8_i(void __iomem * addr,u32 reg,u8 index)270 static inline u8 __ast_read8_i(void __iomem *addr, u32 reg, u8 index)
271 {
272 __ast_write8(addr, reg, index);
273 return __ast_read8(addr, reg + 1);
274 }
275
__ast_read8_i_masked(void __iomem * addr,u32 reg,u8 index,u8 read_mask)276 static inline u8 __ast_read8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask)
277 {
278 u8 val = __ast_read8_i(addr, reg, index);
279
280 return val & read_mask;
281 }
282
__ast_write8_i(void __iomem * addr,u32 reg,u8 index,u8 val)283 static inline void __ast_write8_i(void __iomem *addr, u32 reg, u8 index, u8 val)
284 {
285 __ast_write8(addr, reg, index);
286 __ast_write8(addr, reg + 1, val);
287 }
288
__ast_write8_i_masked(void __iomem * addr,u32 reg,u8 index,u8 read_mask,u8 val)289 static inline void __ast_write8_i_masked(void __iomem *addr, u32 reg, u8 index, u8 read_mask,
290 u8 val)
291 {
292 u8 tmp = __ast_read8_i_masked(addr, reg, index, read_mask);
293
294 tmp |= val;
295 __ast_write8_i(addr, reg, index, tmp);
296 }
297
ast_read32(struct ast_device * ast,u32 reg)298 static inline u32 ast_read32(struct ast_device *ast, u32 reg)
299 {
300 return __ast_read32(ast->regs, reg);
301 }
302
ast_write32(struct ast_device * ast,u32 reg,u32 val)303 static inline void ast_write32(struct ast_device *ast, u32 reg, u32 val)
304 {
305 __ast_write32(ast->regs, reg, val);
306 }
307
ast_io_read8(struct ast_device * ast,u32 reg)308 static inline u8 ast_io_read8(struct ast_device *ast, u32 reg)
309 {
310 return __ast_read8(ast->ioregs, reg);
311 }
312
ast_io_write8(struct ast_device * ast,u32 reg,u8 val)313 static inline void ast_io_write8(struct ast_device *ast, u32 reg, u8 val)
314 {
315 __ast_write8(ast->ioregs, reg, val);
316 }
317
ast_get_index_reg(struct ast_device * ast,u32 base,u8 index)318 static inline u8 ast_get_index_reg(struct ast_device *ast, u32 base, u8 index)
319 {
320 return __ast_read8_i(ast->ioregs, base, index);
321 }
322
ast_get_index_reg_mask(struct ast_device * ast,u32 base,u8 index,u8 preserve_mask)323 static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
324 u8 preserve_mask)
325 {
326 return __ast_read8_i_masked(ast->ioregs, base, index, preserve_mask);
327 }
328
ast_set_index_reg(struct ast_device * ast,u32 base,u8 index,u8 val)329 static inline void ast_set_index_reg(struct ast_device *ast, u32 base, u8 index, u8 val)
330 {
331 __ast_write8_i(ast->ioregs, base, index, val);
332 }
333
ast_set_index_reg_mask(struct ast_device * ast,u32 base,u8 index,u8 preserve_mask,u8 val)334 static inline void ast_set_index_reg_mask(struct ast_device *ast, u32 base, u8 index,
335 u8 preserve_mask, u8 val)
336 {
337 __ast_write8_i_masked(ast->ioregs, base, index, preserve_mask, val);
338 }
339
340 #define AST_VIDMEM_SIZE_8M 0x00800000
341 #define AST_VIDMEM_SIZE_16M 0x01000000
342 #define AST_VIDMEM_SIZE_32M 0x02000000
343 #define AST_VIDMEM_SIZE_64M 0x04000000
344 #define AST_VIDMEM_SIZE_128M 0x08000000
345
346 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
347
348 struct ast_vbios_stdtable {
349 u8 misc;
350 u8 seq[4];
351 u8 crtc[25];
352 u8 ar[20];
353 u8 gr[9];
354 };
355
356 struct ast_vbios_enhtable {
357 u32 ht;
358 u32 hde;
359 u32 hfp;
360 u32 hsync;
361 u32 vt;
362 u32 vde;
363 u32 vfp;
364 u32 vsync;
365 u32 dclk_index;
366 u32 flags;
367 u32 refresh_rate;
368 u32 refresh_rate_index;
369 u32 mode_id;
370 };
371
372 struct ast_vbios_dclk_info {
373 u8 param1;
374 u8 param2;
375 u8 param3;
376 };
377
378 struct ast_vbios_mode_info {
379 const struct ast_vbios_stdtable *std_table;
380 const struct ast_vbios_enhtable *enh_table;
381 };
382
383 struct ast_crtc_state {
384 struct drm_crtc_state base;
385
386 /* Last known format of primary plane */
387 const struct drm_format_info *format;
388
389 struct ast_vbios_mode_info vbios_mode_info;
390 };
391
392 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
393
394 int ast_mode_config_init(struct ast_device *ast);
395
396 #define AST_MM_ALIGN_SHIFT 4
397 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
398
399 #define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
400 #define AST_DP501_FW_VERSION_1 BIT(4)
401 #define AST_DP501_PNP_CONNECTED BIT(1)
402
403 #define AST_DP501_DEFAULT_DCLK 65
404
405 #define AST_DP501_GBL_VERSION 0xf000
406 #define AST_DP501_PNPMONITOR 0xf010
407 #define AST_DP501_LINKRATE 0xf014
408 #define AST_DP501_EDID_DATA 0xf020
409
410 #define AST_DP_POWER_ON true
411 #define AST_DP_POWER_OFF false
412
413 /*
414 * ASTDP resoultion table:
415 * EX: ASTDP_A_B_C:
416 * A: Resolution
417 * B: Refresh Rate
418 * C: Misc information, such as CVT, Reduce Blanked
419 */
420 #define ASTDP_640x480_60 0x00
421 #define ASTDP_640x480_72 0x01
422 #define ASTDP_640x480_75 0x02
423 #define ASTDP_640x480_85 0x03
424 #define ASTDP_800x600_56 0x04
425 #define ASTDP_800x600_60 0x05
426 #define ASTDP_800x600_72 0x06
427 #define ASTDP_800x600_75 0x07
428 #define ASTDP_800x600_85 0x08
429 #define ASTDP_1024x768_60 0x09
430 #define ASTDP_1024x768_70 0x0A
431 #define ASTDP_1024x768_75 0x0B
432 #define ASTDP_1024x768_85 0x0C
433 #define ASTDP_1280x1024_60 0x0D
434 #define ASTDP_1280x1024_75 0x0E
435 #define ASTDP_1280x1024_85 0x0F
436 #define ASTDP_1600x1200_60 0x10
437 #define ASTDP_320x240_60 0x11
438 #define ASTDP_400x300_60 0x12
439 #define ASTDP_512x384_60 0x13
440 #define ASTDP_1920x1200_60 0x14
441 #define ASTDP_1920x1080_60 0x15
442 #define ASTDP_1280x800_60 0x16
443 #define ASTDP_1280x800_60_RB 0x17
444 #define ASTDP_1440x900_60 0x18
445 #define ASTDP_1440x900_60_RB 0x19
446 #define ASTDP_1680x1050_60 0x1A
447 #define ASTDP_1680x1050_60_RB 0x1B
448 #define ASTDP_1600x900_60 0x1C
449 #define ASTDP_1600x900_60_RB 0x1D
450 #define ASTDP_1366x768_60 0x1E
451 #define ASTDP_1152x864_75 0x1F
452
453 int ast_mm_init(struct ast_device *ast);
454
455 /* ast post */
456 void ast_post_gpu(struct drm_device *dev);
457 u32 ast_mindwm(struct ast_device *ast, u32 r);
458 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
459 void ast_patch_ahb_2500(void __iomem *regs);
460
461 int ast_vga_output_init(struct ast_device *ast);
462 int ast_sil164_output_init(struct ast_device *ast);
463
464 /* ast dp501 */
465 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
466 void ast_init_3rdtx(struct drm_device *dev);
467 int ast_dp501_output_init(struct ast_device *ast);
468
469 /* aspeed DP */
470 int ast_dp_launch(struct ast_device *ast);
471 int ast_astdp_output_init(struct ast_device *ast);
472
473 #endif
474