1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 #ifndef ATH12K_PCI_H 7 #define ATH12K_PCI_H 8 9 #include <linux/mhi.h> 10 #include <linux/pci.h> 11 12 #include "core.h" 13 14 #define PCIE_SOC_GLOBAL_RESET 0x3008 15 #define PCIE_SOC_GLOBAL_RESET_V 1 16 17 #define WLAON_WARM_SW_ENTRY 0x1f80504 18 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c 19 20 #define PCIE_Q6_COOKIE_ADDR 0x01f80500 21 #define PCIE_Q6_COOKIE_DATA 0xc0000000 22 23 /* register to wake the UMAC from power collapse */ 24 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 25 26 /* register used for handshake mechanism to validate UMAC is awake */ 27 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 28 29 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0 30 #define PARM_LTSSM_VALUE 0x111 31 32 #define GCC_GCC_PCIE_HOT_RST(ab) \ 33 ((ab)->hal.regs->gcc_gcc_pcie_hot_rst) 34 35 #define GCC_GCC_PCIE_HOT_RST_VAL 0x10 36 37 #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228 38 #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2 39 #define PCIE_INT_CLEAR_ALL 0xffffffff 40 41 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab) \ 42 ((ab)->hal.regs->pcie_qserdes_sysclk_en_sel) 43 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10 44 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff 45 #define PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab) \ 46 ((ab)->hal.regs->pcie_pcs_osc_dtct_config_base) 47 #define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02 48 #define PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab) \ 49 ((ab)->hal.regs->pcie_pcs_osc_dtct_config_base + 0x4) 50 #define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52 51 #define PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab) \ 52 ((ab)->hal.regs->pcie_pcs_osc_dtct_config_base + 0xc) 53 #define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff 54 #define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff 55 56 #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c 57 #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 58 59 #define QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB 0x1E20338 60 #define OTP_BOARD_ID_MASK GENMASK(15, 0) 61 62 #define PCIE_LOCAL_REG_QRTR_NODE_ID(ab) \ 63 ((ab)->hal.regs->qrtr_node_id) 64 #define DOMAIN_NUMBER_MASK GENMASK(7, 4) 65 #define BUS_NUMBER_MASK GENMASK(3, 0) 66 67 #define PCI_BAR_WINDOW0_BASE 0x1E00000 68 #define PCI_BAR_WINDOW0_END 0x1E7FFFC 69 #define PCI_SOC_RANGE_MASK 0x3FFF 70 #define PCI_SOC_PCI_REG_BASE 0x1E04000 71 #define PCI_SOC_PCI_REG_END 0x1E07FFC 72 #define PCI_PARF_BASE 0x1E08000 73 #define PCI_PARF_END 0x1E0BFFC 74 #define PCI_MHIREGLEN_REG 0x1E0E100 75 #define PCI_MHI_REGION_END 0x1E0EFFC 76 #define QRTR_PCI_DOMAIN_NR_MASK GENMASK(7, 4) 77 #define QRTR_PCI_BUS_NUMBER_MASK GENMASK(3, 0) 78 79 struct ath12k_msi_user { 80 const char *name; 81 int num_vectors; 82 u32 base_vector; 83 }; 84 85 struct ath12k_msi_config { 86 int total_vectors; 87 int total_users; 88 const struct ath12k_msi_user *users; 89 }; 90 91 enum ath12k_pci_flags { 92 ATH12K_PCI_FLAG_INIT_DONE, 93 ATH12K_PCI_FLAG_IS_MSI_64, 94 ATH12K_PCI_ASPM_RESTORE, 95 ATH12K_PCI_FLAG_MULTI_MSI_VECTORS, 96 }; 97 98 struct ath12k_pci_ops { 99 int (*wakeup)(struct ath12k_base *ab); 100 void (*release)(struct ath12k_base *ab); 101 }; 102 103 struct ath12k_pci_device_family_ops { 104 int (*probe)(struct pci_dev *pdev, const struct pci_device_id *pci_dev); 105 int (*arch_init)(struct ath12k_base *ab); 106 void (*arch_deinit)(struct ath12k_base *ab); 107 }; 108 109 struct ath12k_pci_reg_base { 110 u32 umac_base; 111 u32 ce_reg_base; 112 }; 113 114 struct ath12k_pci { 115 struct pci_dev *pdev; 116 struct ath12k_base *ab; 117 u16 dev_id; 118 char amss_path[100]; 119 u32 msi_ep_base_data; 120 struct mhi_controller *mhi_ctrl; 121 const struct ath12k_msi_config *msi_config; 122 unsigned long mhi_state; 123 enum mhi_callback mhi_pre_cb; 124 u32 register_window; 125 126 /* protects register_window above */ 127 spinlock_t window_lock; 128 129 /* enum ath12k_pci_flags */ 130 unsigned long flags; 131 u16 link_ctl; 132 unsigned long irq_flags; 133 const struct ath12k_pci_ops *pci_ops; 134 u32 qmi_instance; 135 u64 dma_mask; 136 const struct ath12k_pci_device_family_ops *device_family_ops; 137 const struct ath12k_pci_reg_base *reg_base; 138 139 u32 window_reg_addr; 140 }; 141 142 struct ath12k_pci_driver { 143 const char *name; 144 const struct pci_device_id *id_table; 145 struct ath12k_pci_device_family_ops ops; 146 struct pci_driver driver; 147 const struct ath12k_pci_reg_base *reg_base; 148 }; 149 150 static inline struct ath12k_pci *ath12k_pci_priv(struct ath12k_base *ab) 151 { 152 return (struct ath12k_pci *)ab->drv_priv; 153 } 154 155 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, 156 int *num_vectors, u32 *user_base_data, 157 u32 *base_vector); 158 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector); 159 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value); 160 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset); 161 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, 162 u8 *ul_pipe, u8 *dl_pipe); 163 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, 164 u32 *msi_addr_hi); 165 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id, 166 u32 *msi_idx); 167 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab); 168 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab); 169 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab); 170 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab); 171 int ath12k_pci_hif_suspend(struct ath12k_base *ab); 172 int ath12k_pci_hif_resume(struct ath12k_base *ab); 173 void ath12k_pci_stop(struct ath12k_base *ab); 174 int ath12k_pci_start(struct ath12k_base *ab); 175 int ath12k_pci_power_up(struct ath12k_base *ab); 176 void ath12k_pci_power_down(struct ath12k_base *ab, bool is_suspend); 177 int ath12k_pci_register_driver(const enum ath12k_device_family device_id, 178 struct ath12k_pci_driver *driver); 179 void ath12k_pci_unregister_driver(const enum ath12k_device_family device_id); 180 #endif /* ATH12K_PCI_H */ 181