1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #include "amdgpu_ctx.h" 38 39 #include <linux/atomic.h> 40 #include <linux/wait.h> 41 #include <linux/list.h> 42 #include <linux/kref.h> 43 #include <linux/rbtree.h> 44 #include <linux/hashtable.h> 45 #include <linux/dma-fence.h> 46 #include <linux/pci.h> 47 48 #include <drm/ttm/ttm_bo.h> 49 #include <drm/ttm/ttm_placement.h> 50 51 #include <drm/amdgpu_drm.h> 52 #include <drm/drm_gem.h> 53 #include <drm/drm_ioctl.h> 54 55 #include <kgd_kfd_interface.h> 56 #include "dm_pp_interface.h" 57 #include "kgd_pp_interface.h" 58 59 #include "amd_shared.h" 60 #include "amdgpu_utils.h" 61 #include "amdgpu_mode.h" 62 #include "amdgpu_ih.h" 63 #include "amdgpu_irq.h" 64 #include "amdgpu_ucode.h" 65 #include "amdgpu_ttm.h" 66 #include "amdgpu_psp.h" 67 #include "amdgpu_gds.h" 68 #include "amdgpu_sync.h" 69 #include "amdgpu_ring.h" 70 #include "amdgpu_vm.h" 71 #include "amdgpu_dpm.h" 72 #include "amdgpu_acp.h" 73 #include "amdgpu_uvd.h" 74 #include "amdgpu_vce.h" 75 #include "amdgpu_vcn.h" 76 #include "amdgpu_jpeg.h" 77 #include "amdgpu_vpe.h" 78 #include "amdgpu_umsch_mm.h" 79 #include "amdgpu_gmc.h" 80 #include "amdgpu_gfx.h" 81 #include "amdgpu_sdma.h" 82 #include "amdgpu_lsdma.h" 83 #include "amdgpu_nbio.h" 84 #include "amdgpu_hdp.h" 85 #include "amdgpu_dm.h" 86 #include "amdgpu_virt.h" 87 #include "amdgpu_csa.h" 88 #include "amdgpu_mes_ctx.h" 89 #include "amdgpu_gart.h" 90 #include "amdgpu_debugfs.h" 91 #include "amdgpu_job.h" 92 #include "amdgpu_bo_list.h" 93 #include "amdgpu_gem.h" 94 #include "amdgpu_doorbell.h" 95 #include "amdgpu_amdkfd.h" 96 #include "amdgpu_discovery.h" 97 #include "amdgpu_mes.h" 98 #include "amdgpu_umc.h" 99 #include "amdgpu_mmhub.h" 100 #include "amdgpu_gfxhub.h" 101 #include "amdgpu_df.h" 102 #include "amdgpu_smuio.h" 103 #include "amdgpu_fdinfo.h" 104 #include "amdgpu_mca.h" 105 #include "amdgpu_aca.h" 106 #include "amdgpu_ras.h" 107 #include "amdgpu_cper.h" 108 #include "amdgpu_xcp.h" 109 #include "amdgpu_seq64.h" 110 #include "amdgpu_reg_state.h" 111 #include "amdgpu_userq.h" 112 #include "amdgpu_eviction_fence.h" 113 #include "amdgpu_ip.h" 114 #if defined(CONFIG_DRM_AMD_ISP) 115 #include "amdgpu_isp.h" 116 #endif 117 118 #define MAX_GPU_INSTANCE 64 119 120 #define GFX_SLICE_PERIOD_MS 250 121 122 struct amdgpu_gpu_instance { 123 struct amdgpu_device *adev; 124 int mgpu_fan_enabled; 125 }; 126 127 struct amdgpu_mgpu_info { 128 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 129 struct mutex mutex; 130 uint32_t num_gpu; 131 uint32_t num_dgpu; 132 uint32_t num_apu; 133 }; 134 135 enum amdgpu_ss { 136 AMDGPU_SS_DRV_LOAD, 137 AMDGPU_SS_DEV_D0, 138 AMDGPU_SS_DEV_D3, 139 AMDGPU_SS_DRV_UNLOAD 140 }; 141 142 struct amdgpu_hwip_reg_entry { 143 u32 hwip; 144 u32 inst; 145 u32 seg; 146 u32 reg_offset; 147 const char *reg_name; 148 }; 149 150 struct amdgpu_watchdog_timer { 151 bool timeout_fatal_disable; 152 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 153 }; 154 155 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 156 157 /* 158 * Modules parameters. 159 */ 160 extern int amdgpu_modeset; 161 extern unsigned int amdgpu_vram_limit; 162 extern int amdgpu_vis_vram_limit; 163 extern int amdgpu_gart_size; 164 extern int amdgpu_gtt_size; 165 extern int amdgpu_moverate; 166 extern int amdgpu_audio; 167 extern int amdgpu_disp_priority; 168 extern int amdgpu_hw_i2c; 169 extern int amdgpu_pcie_gen2; 170 extern int amdgpu_msi; 171 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 172 extern int amdgpu_dpm; 173 extern int amdgpu_fw_load_type; 174 extern int amdgpu_aspm; 175 extern int amdgpu_runtime_pm; 176 extern uint amdgpu_ip_block_mask; 177 extern int amdgpu_bapm; 178 extern int amdgpu_deep_color; 179 extern int amdgpu_vm_size; 180 extern int amdgpu_vm_block_size; 181 extern int amdgpu_vm_fragment_size; 182 extern int amdgpu_vm_fault_stop; 183 extern int amdgpu_vm_debug; 184 extern int amdgpu_vm_update_mode; 185 extern int amdgpu_exp_hw_support; 186 extern int amdgpu_dc; 187 extern int amdgpu_sched_jobs; 188 extern int amdgpu_sched_hw_submission; 189 extern uint amdgpu_pcie_gen_cap; 190 extern uint amdgpu_pcie_lane_cap; 191 extern u64 amdgpu_cg_mask; 192 extern uint amdgpu_pg_mask; 193 extern uint amdgpu_sdma_phase_quantum; 194 extern char *amdgpu_disable_cu; 195 extern char *amdgpu_virtual_display; 196 extern uint amdgpu_pp_feature_mask; 197 extern uint amdgpu_force_long_training; 198 extern int amdgpu_lbpw; 199 extern int amdgpu_compute_multipipe; 200 extern int amdgpu_gpu_recovery; 201 extern int amdgpu_emu_mode; 202 extern uint amdgpu_smu_memory_pool_size; 203 extern int amdgpu_smu_pptable_id; 204 extern uint amdgpu_dc_feature_mask; 205 extern uint amdgpu_freesync_vid_mode; 206 extern uint amdgpu_dc_debug_mask; 207 extern uint amdgpu_dc_visual_confirm; 208 extern int amdgpu_dm_abm_level; 209 extern int amdgpu_backlight; 210 extern int amdgpu_damage_clips; 211 extern struct amdgpu_mgpu_info mgpu_info; 212 extern int amdgpu_ras_enable; 213 extern uint amdgpu_ras_mask; 214 extern int amdgpu_bad_page_threshold; 215 extern bool amdgpu_ignore_bad_page_threshold; 216 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 217 extern int amdgpu_async_gfx_ring; 218 extern int amdgpu_mcbp; 219 extern int amdgpu_discovery; 220 extern int amdgpu_mes; 221 extern int amdgpu_mes_log_enable; 222 extern int amdgpu_mes_kiq; 223 extern int amdgpu_uni_mes; 224 extern int amdgpu_noretry; 225 extern int amdgpu_force_asic_type; 226 extern int amdgpu_smartshift_bias; 227 extern int amdgpu_use_xgmi_p2p; 228 extern int amdgpu_mtype_local; 229 extern int amdgpu_enforce_isolation; 230 #ifdef CONFIG_HSA_AMD 231 extern int sched_policy; 232 extern bool debug_evictions; 233 extern bool no_system_mem_limit; 234 extern int halt_if_hws_hang; 235 extern uint amdgpu_svm_default_granularity; 236 #else 237 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 238 static const bool __maybe_unused debug_evictions; /* = false */ 239 static const bool __maybe_unused no_system_mem_limit; 240 static const int __maybe_unused halt_if_hws_hang; 241 #endif 242 #ifdef CONFIG_HSA_AMD_P2P 243 extern bool pcie_p2p; 244 #endif 245 246 extern int amdgpu_tmz; 247 extern int amdgpu_reset_method; 248 249 #ifdef CONFIG_DRM_AMDGPU_SI 250 extern int amdgpu_si_support; 251 #endif 252 #ifdef CONFIG_DRM_AMDGPU_CIK 253 extern int amdgpu_cik_support; 254 #endif 255 extern int amdgpu_num_kcq; 256 257 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 258 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 259 extern int amdgpu_vcnfw_log; 260 extern int amdgpu_sg_display; 261 extern int amdgpu_umsch_mm; 262 extern int amdgpu_seamless; 263 extern int amdgpu_umsch_mm_fwlog; 264 265 extern int amdgpu_user_partt_mode; 266 extern int amdgpu_agp; 267 extern int amdgpu_rebar; 268 269 extern int amdgpu_wbrf; 270 extern int amdgpu_user_queue; 271 272 extern uint amdgpu_hdmi_hpd_debounce_delay_ms; 273 274 #define AMDGPU_VM_MAX_NUM_CTX 4096 275 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 276 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 277 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 278 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 279 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 280 #define AMDGPUFB_CONN_LIMIT 4 281 #define AMDGPU_BIOS_NUM_SCRATCH 16 282 283 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 284 285 /* hard reset data */ 286 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 287 288 /* reset flags */ 289 #define AMDGPU_RESET_GFX (1 << 0) 290 #define AMDGPU_RESET_COMPUTE (1 << 1) 291 #define AMDGPU_RESET_DMA (1 << 2) 292 #define AMDGPU_RESET_CP (1 << 3) 293 #define AMDGPU_RESET_GRBM (1 << 4) 294 #define AMDGPU_RESET_DMA1 (1 << 5) 295 #define AMDGPU_RESET_RLC (1 << 6) 296 #define AMDGPU_RESET_SEM (1 << 7) 297 #define AMDGPU_RESET_IH (1 << 8) 298 #define AMDGPU_RESET_VMC (1 << 9) 299 #define AMDGPU_RESET_MC (1 << 10) 300 #define AMDGPU_RESET_DISPLAY (1 << 11) 301 #define AMDGPU_RESET_UVD (1 << 12) 302 #define AMDGPU_RESET_VCE (1 << 13) 303 #define AMDGPU_RESET_VCE1 (1 << 14) 304 305 /* reset mask */ 306 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 307 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 308 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 309 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 310 311 /* max cursor sizes (in pixels) */ 312 #define CIK_CURSOR_WIDTH 128 313 #define CIK_CURSOR_HEIGHT 128 314 315 /* smart shift bias level limits */ 316 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 317 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 318 319 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 320 #define AMDGPU_SWCTF_EXTRA_DELAY 50 321 322 struct amdgpu_xcp_mgr; 323 struct amdgpu_device; 324 struct amdgpu_irq_src; 325 struct amdgpu_fpriv; 326 struct amdgpu_bo_va_mapping; 327 struct kfd_vm_fault_info; 328 struct amdgpu_hive_info; 329 struct amdgpu_reset_context; 330 struct amdgpu_reset_control; 331 332 enum amdgpu_cp_irq { 333 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 334 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 335 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 336 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 343 344 AMDGPU_CP_IRQ_LAST 345 }; 346 347 enum amdgpu_thermal_irq { 348 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 349 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 350 351 AMDGPU_THERMAL_IRQ_LAST 352 }; 353 354 enum amdgpu_kiq_irq { 355 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 356 AMDGPU_CP_KIQ_IRQ_LAST 357 }; 358 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 359 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 360 #define MAX_KIQ_REG_TRY 1000 361 362 /* 363 * BIOS. 364 */ 365 bool amdgpu_get_bios(struct amdgpu_device *adev); 366 bool amdgpu_read_bios(struct amdgpu_device *adev); 367 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 368 u8 *bios, u32 length_bytes); 369 void amdgpu_bios_release(struct amdgpu_device *adev); 370 /* 371 * Clocks 372 */ 373 374 #define AMDGPU_MAX_PPLL 3 375 376 struct amdgpu_clock { 377 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 378 struct amdgpu_pll spll; 379 struct amdgpu_pll mpll; 380 /* 10 Khz units */ 381 uint32_t default_mclk; 382 uint32_t default_sclk; 383 uint32_t default_dispclk; 384 uint32_t dp_extclk; 385 uint32_t max_pixel_clock; 386 }; 387 388 /* sub-allocation manager, it has to be protected by another lock. 389 * By conception this is an helper for other part of the driver 390 * like the indirect buffer or semaphore, which both have their 391 * locking. 392 * 393 * Principe is simple, we keep a list of sub allocation in offset 394 * order (first entry has offset == 0, last entry has the highest 395 * offset). 396 * 397 * When allocating new object we first check if there is room at 398 * the end total_size - (last_object_offset + last_object_size) >= 399 * alloc_size. If so we allocate new object there. 400 * 401 * When there is not enough room at the end, we start waiting for 402 * each sub object until we reach object_offset+object_size >= 403 * alloc_size, this object then become the sub object we return. 404 * 405 * Alignment can't be bigger than page size. 406 * 407 * Hole are not considered for allocation to keep things simple. 408 * Assumption is that there won't be hole (all object on same 409 * alignment). 410 */ 411 412 struct amdgpu_sa_manager { 413 struct drm_suballoc_manager base; 414 struct amdgpu_bo *bo; 415 uint64_t gpu_addr; 416 void *cpu_ptr; 417 }; 418 419 /* 420 * IRQS. 421 */ 422 423 struct amdgpu_flip_work { 424 struct delayed_work flip_work; 425 struct work_struct unpin_work; 426 struct amdgpu_device *adev; 427 int crtc_id; 428 u32 target_vblank; 429 uint64_t base; 430 struct drm_pending_vblank_event *event; 431 struct amdgpu_bo *old_abo; 432 unsigned shared_count; 433 struct dma_fence **shared; 434 struct dma_fence_cb cb; 435 bool async; 436 }; 437 438 /* 439 * file private structure 440 */ 441 442 struct amdgpu_fpriv { 443 struct amdgpu_vm vm; 444 struct amdgpu_bo_va *prt_va; 445 struct amdgpu_bo_va *csa_va; 446 struct amdgpu_bo_va *seq64_va; 447 struct mutex bo_list_lock; 448 struct idr bo_list_handles; 449 struct amdgpu_ctx_mgr ctx_mgr; 450 struct amdgpu_userq_mgr userq_mgr; 451 452 /* Eviction fence infra */ 453 struct amdgpu_eviction_fence_mgr evf_mgr; 454 455 /** GPU partition selection */ 456 uint32_t xcp_id; 457 }; 458 459 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 460 461 /* 462 * Writeback 463 */ 464 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 465 466 /** 467 * amdgpu_wb - This struct is used for small GPU memory allocation. 468 * 469 * This struct is used to allocate a small amount of GPU memory that can be 470 * used to shadow certain states into the memory. This is especially useful for 471 * providing easy CPU access to some states without requiring register access 472 * (e.g., if some block is power gated, reading register may be problematic). 473 * 474 * Note: the term writeback was initially used because many of the amdgpu 475 * components had some level of writeback memory, and this struct initially 476 * described those components. 477 */ 478 struct amdgpu_wb { 479 480 /** 481 * @wb_obj: 482 * 483 * Buffer Object used for the writeback memory. 484 */ 485 struct amdgpu_bo *wb_obj; 486 487 /** 488 * @wb: 489 * 490 * Pointer to the first writeback slot. In terms of CPU address 491 * this value can be accessed directly by using the offset as an index. 492 * For the GPU address, it is necessary to use gpu_addr and the offset. 493 */ 494 uint32_t *wb; 495 496 /** 497 * @gpu_addr: 498 * 499 * Writeback base address in the GPU. 500 */ 501 uint64_t gpu_addr; 502 503 /** 504 * @num_wb: 505 * 506 * Number of writeback slots reserved for amdgpu. 507 */ 508 u32 num_wb; 509 510 /** 511 * @used: 512 * 513 * Track the writeback slot already used. 514 */ 515 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 516 517 /** 518 * @lock: 519 * 520 * Protects read and write of the used field array. 521 */ 522 spinlock_t lock; 523 }; 524 525 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 526 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 527 528 /* 529 * Benchmarking 530 */ 531 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 532 533 /* 534 * ASIC specific register table accessible by UMD 535 */ 536 struct amdgpu_allowed_register_entry { 537 uint32_t reg_offset; 538 bool grbm_indexed; 539 }; 540 541 /** 542 * enum amd_reset_method - Methods for resetting AMD GPU devices 543 * 544 * @AMD_RESET_METHOD_NONE: The device will not be reset. 545 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 546 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 547 * any device. 548 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 549 * individually. Suitable only for some discrete GPU, not 550 * available for all ASICs. 551 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 552 * are reset depends on the ASIC. Notably doesn't reset IPs 553 * shared with the CPU on APUs or the memory controllers (so 554 * VRAM is not lost). Not available on all ASICs. 555 * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs 556 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 557 * but without powering off the PCI bus. Suitable only for 558 * discrete GPUs. 559 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 560 * and does a secondary bus reset or FLR, depending on what the 561 * underlying hardware supports. 562 * 563 * Methods available for AMD GPU driver for resetting the device. Not all 564 * methods are suitable for every device. User can override the method using 565 * module parameter `reset_method`. 566 */ 567 enum amd_reset_method { 568 AMD_RESET_METHOD_NONE = -1, 569 AMD_RESET_METHOD_LEGACY = 0, 570 AMD_RESET_METHOD_MODE0, 571 AMD_RESET_METHOD_MODE1, 572 AMD_RESET_METHOD_MODE2, 573 AMD_RESET_METHOD_LINK, 574 AMD_RESET_METHOD_BACO, 575 AMD_RESET_METHOD_PCI, 576 AMD_RESET_METHOD_ON_INIT, 577 }; 578 579 struct amdgpu_video_codec_info { 580 u32 codec_type; 581 u32 max_width; 582 u32 max_height; 583 u32 max_pixels_per_frame; 584 u32 max_level; 585 }; 586 587 #define codec_info_build(type, width, height, level) \ 588 .codec_type = type,\ 589 .max_width = width,\ 590 .max_height = height,\ 591 .max_pixels_per_frame = height * width,\ 592 .max_level = level, 593 594 struct amdgpu_video_codecs { 595 const u32 codec_count; 596 const struct amdgpu_video_codec_info *codec_array; 597 }; 598 599 /* 600 * ASIC specific functions. 601 */ 602 struct amdgpu_asic_funcs { 603 bool (*read_disabled_bios)(struct amdgpu_device *adev); 604 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 605 u8 *bios, u32 length_bytes); 606 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 607 u32 sh_num, u32 reg_offset, u32 *value); 608 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 609 int (*reset)(struct amdgpu_device *adev); 610 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 611 /* get the reference clock */ 612 u32 (*get_xclk)(struct amdgpu_device *adev); 613 /* MM block clocks */ 614 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 615 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 616 /* static power management */ 617 int (*get_pcie_lanes)(struct amdgpu_device *adev); 618 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 619 /* get config memsize register */ 620 u32 (*get_config_memsize)(struct amdgpu_device *adev); 621 /* flush hdp write queue */ 622 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 623 /* invalidate hdp read cache */ 624 void (*invalidate_hdp)(struct amdgpu_device *adev, 625 struct amdgpu_ring *ring); 626 /* check if the asic needs a full reset of if soft reset will work */ 627 bool (*need_full_reset)(struct amdgpu_device *adev); 628 /* initialize doorbell layout for specific asic*/ 629 void (*init_doorbell_index)(struct amdgpu_device *adev); 630 /* PCIe bandwidth usage */ 631 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 632 uint64_t *count1); 633 /* do we need to reset the asic at init time (e.g., kexec) */ 634 bool (*need_reset_on_init)(struct amdgpu_device *adev); 635 /* PCIe replay counter */ 636 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 637 /* device supports BACO */ 638 int (*supports_baco)(struct amdgpu_device *adev); 639 /* pre asic_init quirks */ 640 void (*pre_asic_init)(struct amdgpu_device *adev); 641 /* enter/exit umd stable pstate */ 642 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 643 /* query video codecs */ 644 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 645 const struct amdgpu_video_codecs **codecs); 646 /* encode "> 32bits" smn addressing */ 647 u64 (*encode_ext_smn_addressing)(int ext_id); 648 649 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 650 enum amdgpu_reg_state reg_state, void *buf, 651 size_t max_size); 652 }; 653 654 /* 655 * IOCTL. 656 */ 657 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 658 struct drm_file *filp); 659 660 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 661 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 662 struct drm_file *filp); 663 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 664 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 665 struct drm_file *filp); 666 667 /* VRAM scratch page for HDP bug, default vram page */ 668 struct amdgpu_mem_scratch { 669 struct amdgpu_bo *robj; 670 uint32_t *ptr; 671 u64 gpu_addr; 672 }; 673 674 /* 675 * CGS 676 */ 677 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 678 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 679 680 /* 681 * Core structure, functions and helpers. 682 */ 683 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 684 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 685 686 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 687 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 688 689 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 690 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 691 692 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 693 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 694 695 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 696 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 697 698 struct amdgpu_mmio_remap { 699 u32 reg_offset; 700 resource_size_t bus_addr; 701 struct amdgpu_bo *bo; 702 }; 703 704 enum amdgpu_uid_type { 705 AMDGPU_UID_TYPE_XCD, 706 AMDGPU_UID_TYPE_AID, 707 AMDGPU_UID_TYPE_SOC, 708 AMDGPU_UID_TYPE_MAX 709 }; 710 711 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 712 713 struct amdgpu_uid { 714 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 715 struct amdgpu_device *adev; 716 }; 717 718 #define MAX_UMA_OPTION_NAME 28 719 #define MAX_UMA_OPTION_ENTRIES 19 720 721 #define AMDGPU_UMA_FLAG_AUTO BIT(1) 722 #define AMDGPU_UMA_FLAG_CUSTOM BIT(0) 723 724 /** 725 * struct amdgpu_uma_carveout_option - single UMA carveout option 726 * @name: Name of the carveout option 727 * @memory_carved_mb: Amount of memory carved in MB 728 * @flags: ATCS flags supported by this option 729 */ 730 struct amdgpu_uma_carveout_option { 731 char name[MAX_UMA_OPTION_NAME]; 732 uint32_t memory_carved_mb; 733 uint8_t flags; 734 }; 735 736 /** 737 * struct amdgpu_uma_carveout_info - table of available UMA carveout options 738 * @num_entries: Number of available options 739 * @uma_option_index: The index of the option currently applied 740 * @update_lock: Lock to serialize changes to the option 741 * @entries: The array of carveout options 742 */ 743 struct amdgpu_uma_carveout_info { 744 uint8_t num_entries; 745 uint8_t uma_option_index; 746 struct mutex update_lock; 747 struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; 748 }; 749 750 struct amd_powerplay { 751 void *pp_handle; 752 const struct amd_pm_funcs *pp_funcs; 753 }; 754 755 /* polaris10 kickers */ 756 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 757 ((rid == 0xE3) || \ 758 (rid == 0xE4) || \ 759 (rid == 0xE5) || \ 760 (rid == 0xE7) || \ 761 (rid == 0xEF))) || \ 762 ((did == 0x6FDF) && \ 763 ((rid == 0xE7) || \ 764 (rid == 0xEF) || \ 765 (rid == 0xFF)))) 766 767 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 768 ((rid == 0xE1) || \ 769 (rid == 0xF7))) 770 771 /* polaris11 kickers */ 772 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 773 ((rid == 0xE0) || \ 774 (rid == 0xE5))) || \ 775 ((did == 0x67FF) && \ 776 ((rid == 0xCF) || \ 777 (rid == 0xEF) || \ 778 (rid == 0xFF)))) 779 780 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 781 ((rid == 0xE2))) 782 783 /* polaris12 kickers */ 784 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 785 ((rid == 0xC0) || \ 786 (rid == 0xC1) || \ 787 (rid == 0xC3) || \ 788 (rid == 0xC7))) || \ 789 ((did == 0x6981) && \ 790 ((rid == 0x00) || \ 791 (rid == 0x01) || \ 792 (rid == 0x10)))) 793 794 struct amdgpu_mqd_prop { 795 uint64_t mqd_gpu_addr; 796 uint64_t hqd_base_gpu_addr; 797 uint64_t rptr_gpu_addr; 798 uint64_t wptr_gpu_addr; 799 uint32_t queue_size; 800 bool use_doorbell; 801 uint32_t doorbell_index; 802 uint64_t eop_gpu_addr; 803 uint32_t hqd_pipe_priority; 804 uint32_t hqd_queue_priority; 805 uint32_t mqd_stride_size; 806 bool allow_tunneling; 807 bool hqd_active; 808 uint64_t shadow_addr; 809 uint64_t gds_bkup_addr; 810 uint64_t csa_addr; 811 uint64_t fence_address; 812 bool tmz_queue; 813 bool kernel_queue; 814 }; 815 816 struct amdgpu_mqd { 817 unsigned mqd_size; 818 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 819 struct amdgpu_mqd_prop *p); 820 }; 821 822 struct amdgpu_pcie_reset_ctx { 823 bool in_link_reset; 824 bool occurs_dpc; 825 bool audio_suspended; 826 struct pci_dev *swus; 827 struct pci_saved_state *swus_pcistate; 828 struct pci_saved_state *swds_pcistate; 829 }; 830 831 /* 832 * Custom Init levels could be defined for different situations where a full 833 * initialization of all hardware blocks are not expected. Sample cases are 834 * custom init sequences after resume after S0i3/S3, reset on initialization, 835 * partial reset of blocks etc. Presently, this defines only two levels. Levels 836 * are described in corresponding struct definitions - amdgpu_init_default, 837 * amdgpu_init_minimal_xgmi. 838 */ 839 enum amdgpu_init_lvl_id { 840 AMDGPU_INIT_LEVEL_DEFAULT, 841 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 842 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 843 }; 844 845 struct amdgpu_init_level { 846 enum amdgpu_init_lvl_id level; 847 uint32_t hwini_ip_block_mask; 848 }; 849 850 #define AMDGPU_RESET_MAGIC_NUM 64 851 #define AMDGPU_MAX_DF_PERFMONS 4 852 struct amdgpu_reset_domain; 853 struct amdgpu_fru_info; 854 855 enum amdgpu_enforce_isolation_mode { 856 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 857 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 858 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 859 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 860 }; 861 862 struct amdgpu_device { 863 struct device *dev; 864 struct pci_dev *pdev; 865 struct drm_device ddev; 866 867 #ifdef CONFIG_DRM_AMD_ACP 868 struct amdgpu_acp acp; 869 #endif 870 struct amdgpu_hive_info *hive; 871 struct amdgpu_xcp_mgr *xcp_mgr; 872 /* ASIC */ 873 enum amd_asic_type asic_type; 874 uint32_t family; 875 uint32_t rev_id; 876 uint32_t external_rev_id; 877 unsigned long flags; 878 unsigned long apu_flags; 879 int usec_timeout; 880 const struct amdgpu_asic_funcs *asic_funcs; 881 bool shutdown; 882 bool need_swiotlb; 883 bool accel_working; 884 struct notifier_block acpi_nb; 885 struct notifier_block pm_nb; 886 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 887 struct debugfs_blob_wrapper debugfs_vbios_blob; 888 struct mutex srbm_mutex; 889 /* GRBM index mutex. Protects concurrent access to GRBM index */ 890 struct mutex grbm_idx_mutex; 891 struct dev_pm_domain vga_pm_domain; 892 bool have_disp_power_ref; 893 bool have_atomics_support; 894 895 /* BIOS */ 896 bool is_atom_fw; 897 uint8_t *bios; 898 uint32_t bios_size; 899 uint32_t bios_scratch_reg_offset; 900 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 901 902 /* Register/doorbell mmio */ 903 resource_size_t rmmio_base; 904 resource_size_t rmmio_size; 905 void __iomem *rmmio; 906 /* protects concurrent MM_INDEX/DATA based register access */ 907 spinlock_t mmio_idx_lock; 908 struct amdgpu_mmio_remap rmmio_remap; 909 /* protects concurrent SMC based register access */ 910 spinlock_t smc_idx_lock; 911 amdgpu_rreg_t smc_rreg; 912 amdgpu_wreg_t smc_wreg; 913 /* protects concurrent PCIE register access */ 914 spinlock_t pcie_idx_lock; 915 amdgpu_rreg_t pcie_rreg; 916 amdgpu_wreg_t pcie_wreg; 917 amdgpu_rreg_t pciep_rreg; 918 amdgpu_wreg_t pciep_wreg; 919 amdgpu_rreg_ext_t pcie_rreg_ext; 920 amdgpu_wreg_ext_t pcie_wreg_ext; 921 amdgpu_rreg64_t pcie_rreg64; 922 amdgpu_wreg64_t pcie_wreg64; 923 amdgpu_rreg64_ext_t pcie_rreg64_ext; 924 amdgpu_wreg64_ext_t pcie_wreg64_ext; 925 /* protects concurrent UVD register access */ 926 spinlock_t uvd_ctx_idx_lock; 927 amdgpu_rreg_t uvd_ctx_rreg; 928 amdgpu_wreg_t uvd_ctx_wreg; 929 /* protects concurrent DIDT register access */ 930 spinlock_t didt_idx_lock; 931 amdgpu_rreg_t didt_rreg; 932 amdgpu_wreg_t didt_wreg; 933 /* protects concurrent gc_cac register access */ 934 spinlock_t gc_cac_idx_lock; 935 amdgpu_rreg_t gc_cac_rreg; 936 amdgpu_wreg_t gc_cac_wreg; 937 /* protects concurrent se_cac register access */ 938 spinlock_t se_cac_idx_lock; 939 amdgpu_rreg_t se_cac_rreg; 940 amdgpu_wreg_t se_cac_wreg; 941 /* protects concurrent ENDPOINT (audio) register access */ 942 spinlock_t audio_endpt_idx_lock; 943 amdgpu_block_rreg_t audio_endpt_rreg; 944 amdgpu_block_wreg_t audio_endpt_wreg; 945 struct amdgpu_doorbell doorbell; 946 947 /* clock/pll info */ 948 struct amdgpu_clock clock; 949 950 /* MC */ 951 struct amdgpu_gmc gmc; 952 struct amdgpu_gart gart; 953 dma_addr_t dummy_page_addr; 954 struct amdgpu_vm_manager vm_manager; 955 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 956 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 957 958 /* memory management */ 959 struct amdgpu_mman mman; 960 struct amdgpu_mem_scratch mem_scratch; 961 struct amdgpu_wb wb; 962 atomic64_t num_bytes_moved; 963 atomic64_t num_evictions; 964 atomic64_t num_vram_cpu_page_faults; 965 atomic_t gpu_reset_counter; 966 atomic_t vram_lost_counter; 967 968 /* data for buffer migration throttling */ 969 struct { 970 spinlock_t lock; 971 s64 last_update_us; 972 s64 accum_us; /* accumulated microseconds */ 973 s64 accum_us_vis; /* for visible VRAM */ 974 u32 log2_max_MBps; 975 } mm_stats; 976 977 /* discovery*/ 978 struct amdgpu_discovery_info discovery; 979 980 /* display */ 981 bool enable_virtual_display; 982 struct amdgpu_vkms_output *amdgpu_vkms_output; 983 struct amdgpu_mode_info mode_info; 984 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 985 struct delayed_work hotplug_work; 986 struct amdgpu_irq_src crtc_irq; 987 struct amdgpu_irq_src vline0_irq; 988 struct amdgpu_irq_src vupdate_irq; 989 struct amdgpu_irq_src pageflip_irq; 990 struct amdgpu_irq_src hpd_irq; 991 struct amdgpu_irq_src dmub_trace_irq; 992 struct amdgpu_irq_src dmub_outbox_irq; 993 994 /* rings */ 995 u64 fence_context; 996 unsigned num_rings; 997 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 998 struct dma_fence __rcu *gang_submit; 999 bool ib_pool_ready; 1000 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 1001 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 1002 1003 /* interrupts */ 1004 struct amdgpu_irq irq; 1005 1006 /* powerplay */ 1007 struct amd_powerplay powerplay; 1008 struct amdgpu_pm pm; 1009 u64 cg_flags; 1010 u32 pg_flags; 1011 1012 /* nbio */ 1013 struct amdgpu_nbio nbio; 1014 1015 /* hdp */ 1016 struct amdgpu_hdp hdp; 1017 1018 /* smuio */ 1019 struct amdgpu_smuio smuio; 1020 1021 /* mmhub */ 1022 struct amdgpu_mmhub mmhub; 1023 1024 /* gfxhub */ 1025 struct amdgpu_gfxhub gfxhub; 1026 1027 /* gfx */ 1028 struct amdgpu_gfx gfx; 1029 1030 /* sdma */ 1031 struct amdgpu_sdma sdma; 1032 1033 /* lsdma */ 1034 struct amdgpu_lsdma lsdma; 1035 1036 /* uvd */ 1037 struct amdgpu_uvd uvd; 1038 1039 /* vce */ 1040 struct amdgpu_vce vce; 1041 1042 /* vcn */ 1043 struct amdgpu_vcn vcn; 1044 1045 /* jpeg */ 1046 struct amdgpu_jpeg jpeg; 1047 1048 /* vpe */ 1049 struct amdgpu_vpe vpe; 1050 1051 /* umsch */ 1052 struct amdgpu_umsch_mm umsch_mm; 1053 bool enable_umsch_mm; 1054 1055 /* firmwares */ 1056 struct amdgpu_firmware firmware; 1057 1058 /* PSP */ 1059 struct psp_context psp; 1060 1061 /* GDS */ 1062 struct amdgpu_gds gds; 1063 1064 /* for userq and VM fences */ 1065 struct amdgpu_seq64 seq64; 1066 1067 /* UMC */ 1068 struct amdgpu_umc umc; 1069 1070 /* display related functionality */ 1071 struct amdgpu_display_manager dm; 1072 1073 #if defined(CONFIG_DRM_AMD_ISP) 1074 /* isp */ 1075 struct amdgpu_isp isp; 1076 #endif 1077 1078 /* mes */ 1079 bool enable_mes; 1080 bool enable_mes_kiq; 1081 bool enable_uni_mes; 1082 struct amdgpu_mes mes; 1083 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1084 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1085 1086 /* xarray used to retrieve the user queue fence driver reference 1087 * in the EOP interrupt handler to signal the particular user 1088 * queue fence. 1089 */ 1090 struct xarray userq_xa; 1091 /** 1092 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 1093 * Key: doorbell_index (unique global identifier for the queue) 1094 * Value: struct amdgpu_usermode_queue 1095 */ 1096 struct xarray userq_doorbell_xa; 1097 1098 /* df */ 1099 struct amdgpu_df df; 1100 1101 /* MCA */ 1102 struct amdgpu_mca mca; 1103 1104 /* ACA */ 1105 struct amdgpu_aca aca; 1106 1107 /* CPER */ 1108 struct amdgpu_cper cper; 1109 1110 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1111 uint32_t harvest_ip_mask; 1112 int num_ip_blocks; 1113 struct mutex mn_lock; 1114 DECLARE_HASHTABLE(mn_hash, 7); 1115 1116 /* tracking pinned memory */ 1117 atomic64_t vram_pin_size; 1118 atomic64_t visible_pin_size; 1119 atomic64_t gart_pin_size; 1120 1121 /* soc15 register offset based on ip, instance and segment */ 1122 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1123 struct amdgpu_ip_map_info ip_map; 1124 1125 /* delayed work_func for deferring clockgating during resume */ 1126 struct delayed_work delayed_init_work; 1127 1128 struct amdgpu_virt virt; 1129 1130 /* record hw reset is performed */ 1131 bool has_hw_reset; 1132 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1133 1134 /* s3/s4 mask */ 1135 bool in_suspend; 1136 bool in_s3; 1137 bool in_s4; 1138 bool in_s0ix; 1139 suspend_state_t last_suspend_state; 1140 1141 enum pp_mp1_state mp1_state; 1142 struct amdgpu_doorbell_index doorbell_index; 1143 1144 struct mutex notifier_lock; 1145 1146 int asic_reset_res; 1147 struct work_struct xgmi_reset_work; 1148 struct list_head reset_list; 1149 1150 long gfx_timeout; 1151 long sdma_timeout; 1152 long video_timeout; 1153 long compute_timeout; 1154 long psp_timeout; 1155 1156 uint64_t unique_id; 1157 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1158 1159 /* enable runtime pm on the device */ 1160 bool in_runpm; 1161 bool has_pr3; 1162 1163 bool ucode_sysfs_en; 1164 1165 struct amdgpu_fru_info *fru_info; 1166 atomic_t throttling_logging_enabled; 1167 struct ratelimit_state throttling_logging_rs; 1168 uint32_t ras_hw_enabled; 1169 uint32_t ras_enabled; 1170 bool ras_default_ecc_enabled; 1171 1172 bool no_hw_access; 1173 struct pci_saved_state *pci_state; 1174 pci_channel_state_t pci_channel_state; 1175 1176 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1177 1178 /* Track auto wait count on s_barrier settings */ 1179 bool barrier_has_auto_waitcnt; 1180 1181 struct amdgpu_reset_control *reset_cntl; 1182 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1183 1184 bool ram_is_direct_mapped; 1185 1186 struct list_head ras_list; 1187 1188 struct amdgpu_reset_domain *reset_domain; 1189 1190 struct mutex benchmark_mutex; 1191 1192 bool scpm_enabled; 1193 uint32_t scpm_status; 1194 1195 struct work_struct reset_work; 1196 1197 bool dc_enabled; 1198 /* Mask of active clusters */ 1199 uint32_t aid_mask; 1200 1201 /* Debug */ 1202 bool debug_vm; 1203 bool debug_largebar; 1204 bool debug_disable_soft_recovery; 1205 bool debug_use_vram_fw_buf; 1206 bool debug_enable_ras_aca; 1207 bool debug_exp_resets; 1208 bool debug_disable_gpu_ring_reset; 1209 bool debug_vm_userptr; 1210 bool debug_disable_ce_logs; 1211 bool debug_enable_ce_cs; 1212 1213 /* Protection for the following isolation structure */ 1214 struct mutex enforce_isolation_mutex; 1215 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1216 struct amdgpu_isolation { 1217 void *owner; 1218 struct dma_fence *spearhead; 1219 struct amdgpu_sync active; 1220 struct amdgpu_sync prev; 1221 } isolation[MAX_XCP]; 1222 1223 struct amdgpu_init_level *init_lvl; 1224 1225 /* This flag is used to determine how VRAM allocations are handled for APUs 1226 * in KFD: VRAM or GTT. 1227 */ 1228 bool apu_prefer_gtt; 1229 1230 bool userq_halt_for_enforce_isolation; 1231 struct work_struct userq_reset_work; 1232 struct amdgpu_uid *uid_info; 1233 1234 struct amdgpu_uma_carveout_info uma_info; 1235 1236 /* KFD 1237 * Must be last --ends in a flexible-array member. 1238 */ 1239 struct amdgpu_kfd_dev kfd; 1240 }; 1241 1242 /* 1243 * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) 1244 * as fence address and writes a 32 bit fence value to this address. 1245 * Driver needs to allocate at least 4 DWs extra memory in addition to 1246 * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. 1247 */ 1248 #define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) 1249 1250 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1251 uint8_t ip, uint8_t inst) 1252 { 1253 /* This considers only major/minor/rev and ignores 1254 * subrevision/variant fields. 1255 */ 1256 return adev->ip_versions[ip][inst] & ~0xFFU; 1257 } 1258 1259 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1260 uint8_t ip, uint8_t inst) 1261 { 1262 /* This returns full version - major/minor/rev/variant/subrevision */ 1263 return adev->ip_versions[ip][inst]; 1264 } 1265 1266 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1267 { 1268 return container_of(ddev, struct amdgpu_device, ddev); 1269 } 1270 1271 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1272 { 1273 return &adev->ddev; 1274 } 1275 1276 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1277 { 1278 return container_of(bdev, struct amdgpu_device, mman.bdev); 1279 } 1280 1281 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1282 { 1283 return !!adev->aid_mask; 1284 } 1285 1286 int amdgpu_device_init(struct amdgpu_device *adev, 1287 uint32_t flags); 1288 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1289 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1290 1291 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1292 1293 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1294 void *buf, size_t size, bool write); 1295 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1296 void *buf, size_t size, bool write); 1297 1298 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1299 void *buf, size_t size, bool write); 1300 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1301 uint32_t inst, uint32_t reg_addr, char reg_name[], 1302 uint32_t expected_value, uint32_t mask); 1303 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1304 uint32_t reg, uint32_t acc_flags); 1305 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1306 u64 reg_addr); 1307 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1308 uint32_t reg, uint32_t acc_flags, 1309 uint32_t xcc_id); 1310 void amdgpu_device_wreg(struct amdgpu_device *adev, 1311 uint32_t reg, uint32_t v, 1312 uint32_t acc_flags); 1313 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1314 u64 reg_addr, u32 reg_data); 1315 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1316 uint32_t reg, uint32_t v, 1317 uint32_t acc_flags, 1318 uint32_t xcc_id); 1319 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1320 uint32_t reg, uint32_t v, uint32_t xcc_id); 1321 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1322 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1323 1324 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1325 u32 reg_addr); 1326 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1327 u32 reg_addr); 1328 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1329 u64 reg_addr); 1330 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1331 u32 reg_addr, u32 reg_data); 1332 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1333 u32 reg_addr, u64 reg_data); 1334 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1335 u64 reg_addr, u64 reg_data); 1336 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1337 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1338 enum amd_asic_type asic_type); 1339 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1340 1341 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1342 1343 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1344 struct amdgpu_reset_context *reset_context); 1345 1346 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1347 struct amdgpu_reset_context *reset_context); 1348 1349 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1350 1351 int emu_soc_asic_init(struct amdgpu_device *adev); 1352 1353 /* 1354 * Registers read & write functions. 1355 */ 1356 #define AMDGPU_REGS_NO_KIQ (1<<1) 1357 #define AMDGPU_REGS_RLC (1<<2) 1358 1359 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1360 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1361 1362 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1363 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1364 1365 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1366 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1367 1368 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1369 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1370 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1371 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1372 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1373 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1374 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1375 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1376 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1377 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1378 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1379 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1380 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1381 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1382 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1383 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1384 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1385 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1386 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1387 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1388 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1389 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1390 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1391 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1392 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1393 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1394 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1395 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1396 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1397 #define WREG32_P(reg, val, mask) \ 1398 do { \ 1399 uint32_t tmp_ = RREG32(reg); \ 1400 tmp_ &= (mask); \ 1401 tmp_ |= ((val) & ~(mask)); \ 1402 WREG32(reg, tmp_); \ 1403 } while (0) 1404 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1405 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1406 #define WREG32_PLL_P(reg, val, mask) \ 1407 do { \ 1408 uint32_t tmp_ = RREG32_PLL(reg); \ 1409 tmp_ &= (mask); \ 1410 tmp_ |= ((val) & ~(mask)); \ 1411 WREG32_PLL(reg, tmp_); \ 1412 } while (0) 1413 1414 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1415 do { \ 1416 u32 tmp = RREG32_SMC(_Reg); \ 1417 tmp &= (_Mask); \ 1418 tmp |= ((_Val) & ~(_Mask)); \ 1419 WREG32_SMC(_Reg, tmp); \ 1420 } while (0) 1421 1422 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1423 1424 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1425 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1426 1427 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1428 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1429 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1430 1431 #define REG_GET_FIELD(value, reg, field) \ 1432 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1433 1434 #define WREG32_FIELD(reg, field, val) \ 1435 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1436 1437 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1438 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1439 1440 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1441 /* 1442 * BIOS helpers. 1443 */ 1444 #define RBIOS8(i) (adev->bios[i]) 1445 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1446 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1447 1448 /* 1449 * ASICs macro. 1450 */ 1451 #define amdgpu_asic_set_vga_state(adev, state) \ 1452 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1453 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1454 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1455 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1456 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1457 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1458 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1459 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1460 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1461 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1462 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1463 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1464 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1465 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1466 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1467 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1468 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1469 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1470 #define amdgpu_asic_supports_baco(adev) \ 1471 ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) 1472 #define amdgpu_asic_pre_asic_init(adev) \ 1473 { \ 1474 if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ 1475 (adev)->asic_funcs->pre_asic_init((adev)); \ 1476 } 1477 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1478 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1479 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1480 1481 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1482 1483 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1484 #define for_each_inst(i, inst_mask) \ 1485 for (i = ffs(inst_mask); i-- != 0; \ 1486 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1487 1488 /* Common functions */ 1489 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1490 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1491 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1492 struct amdgpu_job *job, 1493 struct amdgpu_reset_context *reset_context); 1494 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1495 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1496 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1497 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1498 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1499 1500 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1501 u64 num_vis_bytes); 1502 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1503 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1504 const u32 *registers, 1505 const u32 array_size); 1506 1507 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1508 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1509 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1510 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1511 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1512 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1513 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1514 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1515 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1516 struct amdgpu_device *peer_adev); 1517 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1518 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1519 1520 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1521 struct amdgpu_ring *ring); 1522 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1523 struct amdgpu_ring *ring); 1524 1525 void amdgpu_device_halt(struct amdgpu_device *adev); 1526 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1527 u32 reg); 1528 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1529 u32 reg, u32 v); 1530 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1531 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1532 struct dma_fence *gang); 1533 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1534 struct amdgpu_ring *ring, 1535 struct amdgpu_job *job); 1536 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1537 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1538 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1539 1540 /* atpx handler */ 1541 #if defined(CONFIG_VGA_SWITCHEROO) 1542 void amdgpu_register_atpx_handler(void); 1543 void amdgpu_unregister_atpx_handler(void); 1544 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1545 bool amdgpu_is_atpx_hybrid(void); 1546 bool amdgpu_has_atpx(void); 1547 #else 1548 static inline void amdgpu_register_atpx_handler(void) {} 1549 static inline void amdgpu_unregister_atpx_handler(void) {} 1550 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1551 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1552 static inline bool amdgpu_has_atpx(void) { return false; } 1553 #endif 1554 1555 /* 1556 * KMS 1557 */ 1558 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1559 extern const int amdgpu_max_kms_ioctl; 1560 1561 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1562 void amdgpu_driver_unload_kms(struct drm_device *dev); 1563 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1564 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1565 struct drm_file *file_priv); 1566 void amdgpu_driver_release_kms(struct drm_device *dev); 1567 1568 int amdgpu_device_prepare(struct drm_device *dev); 1569 void amdgpu_device_complete(struct drm_device *dev); 1570 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1571 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1572 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1573 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1574 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1575 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1576 struct drm_file *filp); 1577 1578 /* 1579 * functions used by amdgpu_encoder.c 1580 */ 1581 struct amdgpu_afmt_acr { 1582 u32 clock; 1583 1584 int n_32khz; 1585 int cts_32khz; 1586 1587 int n_44_1khz; 1588 int cts_44_1khz; 1589 1590 int n_48khz; 1591 int cts_48khz; 1592 1593 }; 1594 1595 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1596 1597 /* amdgpu_acpi.c */ 1598 1599 struct amdgpu_numa_info { 1600 uint64_t size; 1601 int pxm; 1602 int nid; 1603 }; 1604 1605 /* ATCS Device/Driver State */ 1606 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1607 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1608 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1609 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1610 1611 #if defined(CONFIG_ACPI) 1612 int amdgpu_acpi_init(struct amdgpu_device *adev); 1613 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1614 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1615 bool amdgpu_acpi_is_power_shift_control_supported(void); 1616 bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); 1617 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1618 u8 perf_req, bool advertise); 1619 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1620 u8 dev_state, bool drv_state); 1621 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1622 enum amdgpu_ss ss_state); 1623 int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); 1624 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1625 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1626 u64 *tmr_size); 1627 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1628 struct amdgpu_numa_info *numa_info); 1629 1630 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1631 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1632 void amdgpu_acpi_detect(void); 1633 void amdgpu_acpi_release(void); 1634 #else 1635 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1636 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1637 u64 *tmr_offset, u64 *tmr_size) 1638 { 1639 return -EINVAL; 1640 } 1641 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1642 int xcc_id, 1643 struct amdgpu_numa_info *numa_info) 1644 { 1645 return -EINVAL; 1646 } 1647 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1648 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1649 static inline void amdgpu_acpi_detect(void) { } 1650 static inline void amdgpu_acpi_release(void) { } 1651 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1652 static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } 1653 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1654 u8 dev_state, bool drv_state) { return 0; } 1655 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1656 enum amdgpu_ss ss_state) 1657 { 1658 return 0; 1659 } 1660 static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) 1661 { 1662 return -EINVAL; 1663 } 1664 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1665 #endif 1666 1667 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1668 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1669 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1670 #else 1671 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1672 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1673 #endif 1674 1675 #if defined(CONFIG_DRM_AMD_ISP) 1676 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1677 #endif 1678 1679 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1680 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1681 1682 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1683 pci_channel_state_t state); 1684 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1685 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1686 void amdgpu_pci_resume(struct pci_dev *pdev); 1687 1688 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1689 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1690 1691 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1692 1693 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1694 enum amd_clockgating_state state); 1695 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1696 enum amd_powergating_state state); 1697 1698 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1699 { 1700 return amdgpu_gpu_recovery != 0 && 1701 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1702 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1703 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1704 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1705 } 1706 1707 #include "amdgpu_object.h" 1708 1709 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1710 { 1711 return adev->gmc.tmz_enabled; 1712 } 1713 1714 int amdgpu_in_reset(struct amdgpu_device *adev); 1715 1716 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1717 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1718 extern const struct attribute_group amdgpu_flash_attr_group; 1719 1720 void amdgpu_set_init_level(struct amdgpu_device *adev, 1721 enum amdgpu_init_lvl_id lvl); 1722 1723 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1724 { 1725 u32 status; 1726 int r; 1727 1728 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1729 if (r || PCI_POSSIBLE_ERROR(status)) { 1730 dev_err(adev->dev, "device lost from bus!"); 1731 return -ENODEV; 1732 } 1733 1734 return 0; 1735 } 1736 1737 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1738 enum amdgpu_uid_type type, uint8_t inst, 1739 uint64_t uid); 1740 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1741 enum amdgpu_uid_type type, uint8_t inst); 1742 #endif 1743