xref: /linux/include/dt-bindings/clock/qcom,ipq9574-gcc.h (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3  * Copyright (c) 2018-2023 The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H
7 #define _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H
8 
9 #define GPLL0_MAIN					0
10 #define GPLL0						1
11 #define GPLL2_MAIN					2
12 #define GPLL2						3
13 #define GPLL4_MAIN					4
14 #define GPLL4						5
15 #define GCC_SLEEP_CLK_SRC				6
16 #define APSS_AHB_CLK_SRC				7
17 #define APSS_AXI_CLK_SRC				8
18 #define BLSP1_QUP1_I2C_APPS_CLK_SRC			9
19 #define BLSP1_QUP1_SPI_APPS_CLK_SRC			10
20 #define BLSP1_QUP2_I2C_APPS_CLK_SRC			11
21 #define BLSP1_QUP2_SPI_APPS_CLK_SRC			12
22 #define BLSP1_QUP3_I2C_APPS_CLK_SRC			13
23 #define BLSP1_QUP3_SPI_APPS_CLK_SRC			14
24 #define BLSP1_QUP4_I2C_APPS_CLK_SRC			15
25 #define BLSP1_QUP4_SPI_APPS_CLK_SRC			16
26 #define BLSP1_QUP5_I2C_APPS_CLK_SRC			17
27 #define BLSP1_QUP5_SPI_APPS_CLK_SRC			18
28 #define BLSP1_QUP6_I2C_APPS_CLK_SRC			19
29 #define BLSP1_QUP6_SPI_APPS_CLK_SRC			20
30 #define BLSP1_UART1_APPS_CLK_SRC			21
31 #define BLSP1_UART2_APPS_CLK_SRC			22
32 #define BLSP1_UART3_APPS_CLK_SRC			23
33 #define BLSP1_UART4_APPS_CLK_SRC			24
34 #define BLSP1_UART5_APPS_CLK_SRC			25
35 #define BLSP1_UART6_APPS_CLK_SRC			26
36 #define GCC_APSS_AHB_CLK				27
37 #define GCC_APSS_AXI_CLK				28
38 #define GCC_BLSP1_QUP1_I2C_APPS_CLK			29
39 #define GCC_BLSP1_QUP1_SPI_APPS_CLK			30
40 #define GCC_BLSP1_QUP2_I2C_APPS_CLK			31
41 #define GCC_BLSP1_QUP2_SPI_APPS_CLK			32
42 #define GCC_BLSP1_QUP3_I2C_APPS_CLK			33
43 #define GCC_BLSP1_QUP3_SPI_APPS_CLK			34
44 #define GCC_BLSP1_QUP4_I2C_APPS_CLK			35
45 #define GCC_BLSP1_QUP4_SPI_APPS_CLK			36
46 #define GCC_BLSP1_QUP5_I2C_APPS_CLK			37
47 #define GCC_BLSP1_QUP5_SPI_APPS_CLK			38
48 #define GCC_BLSP1_QUP6_I2C_APPS_CLK			39
49 #define GCC_BLSP1_QUP6_SPI_APPS_CLK			40
50 #define GCC_BLSP1_UART1_APPS_CLK			41
51 #define GCC_BLSP1_UART2_APPS_CLK			42
52 #define GCC_BLSP1_UART3_APPS_CLK			43
53 #define GCC_BLSP1_UART4_APPS_CLK			44
54 #define GCC_BLSP1_UART5_APPS_CLK			45
55 #define GCC_BLSP1_UART6_APPS_CLK			46
56 #define PCIE0_AXI_M_CLK_SRC				47
57 #define GCC_PCIE0_AXI_M_CLK				48
58 #define PCIE1_AXI_M_CLK_SRC				49
59 #define GCC_PCIE1_AXI_M_CLK				50
60 #define PCIE2_AXI_M_CLK_SRC				51
61 #define GCC_PCIE2_AXI_M_CLK				52
62 #define PCIE3_AXI_M_CLK_SRC				53
63 #define GCC_PCIE3_AXI_M_CLK				54
64 #define PCIE0_AXI_S_CLK_SRC				55
65 #define GCC_PCIE0_AXI_S_BRIDGE_CLK			56
66 #define GCC_PCIE0_AXI_S_CLK				57
67 #define PCIE1_AXI_S_CLK_SRC				58
68 #define GCC_PCIE1_AXI_S_BRIDGE_CLK			59
69 #define GCC_PCIE1_AXI_S_CLK				60
70 #define PCIE2_AXI_S_CLK_SRC				61
71 #define GCC_PCIE2_AXI_S_BRIDGE_CLK			62
72 #define GCC_PCIE2_AXI_S_CLK				63
73 #define PCIE3_AXI_S_CLK_SRC				64
74 #define GCC_PCIE3_AXI_S_BRIDGE_CLK			65
75 #define GCC_PCIE3_AXI_S_CLK				66
76 #define PCIE0_PIPE_CLK_SRC				67
77 #define PCIE1_PIPE_CLK_SRC				68
78 #define PCIE2_PIPE_CLK_SRC				69
79 #define PCIE3_PIPE_CLK_SRC				70
80 #define PCIE_AUX_CLK_SRC				71
81 #define GCC_PCIE0_AUX_CLK				72
82 #define GCC_PCIE1_AUX_CLK				73
83 #define GCC_PCIE2_AUX_CLK				74
84 #define GCC_PCIE3_AUX_CLK				75
85 #define PCIE0_RCHNG_CLK_SRC				76
86 #define GCC_PCIE0_RCHNG_CLK				77
87 #define PCIE1_RCHNG_CLK_SRC				78
88 #define GCC_PCIE1_RCHNG_CLK				79
89 #define PCIE2_RCHNG_CLK_SRC				80
90 #define GCC_PCIE2_RCHNG_CLK				81
91 #define PCIE3_RCHNG_CLK_SRC				82
92 #define GCC_PCIE3_RCHNG_CLK				83
93 #define GCC_PCIE0_AHB_CLK				84
94 #define GCC_PCIE1_AHB_CLK				85
95 #define GCC_PCIE2_AHB_CLK				86
96 #define GCC_PCIE3_AHB_CLK				87
97 #define USB0_AUX_CLK_SRC				88
98 #define GCC_USB0_AUX_CLK				89
99 #define USB0_MASTER_CLK_SRC				90
100 #define GCC_USB0_MASTER_CLK				91
101 #define GCC_SNOC_USB_CLK				92
102 #define GCC_ANOC_USB_AXI_CLK				93
103 #define USB0_MOCK_UTMI_CLK_SRC				94
104 #define USB0_MOCK_UTMI_DIV_CLK_SRC			95
105 #define GCC_USB0_MOCK_UTMI_CLK				96
106 #define USB0_PIPE_CLK_SRC				97
107 #define GCC_USB0_PHY_CFG_AHB_CLK			98
108 #define SDCC1_APPS_CLK_SRC				99
109 #define GCC_SDCC1_APPS_CLK				100
110 #define SDCC1_ICE_CORE_CLK_SRC				101
111 #define GCC_SDCC1_ICE_CORE_CLK				102
112 #define GCC_SDCC1_AHB_CLK				103
113 #define PCNOC_BFDCD_CLK_SRC				104
114 #define GCC_NSSCFG_CLK					105
115 #define GCC_NSSNOC_NSSCC_CLK				106
116 #define GCC_NSSCC_CLK					107
117 #define GCC_NSSNOC_PCNOC_1_CLK				108
118 #define GCC_QDSS_DAP_AHB_CLK				109
119 #define GCC_QDSS_CFG_AHB_CLK				110
120 #define GCC_QPIC_AHB_CLK				111
121 #define GCC_QPIC_CLK					112
122 #define GCC_BLSP1_AHB_CLK				113
123 #define GCC_MDIO_AHB_CLK				114
124 #define GCC_PRNG_AHB_CLK				115
125 #define GCC_UNIPHY0_AHB_CLK				116
126 #define GCC_UNIPHY1_AHB_CLK				117
127 #define GCC_UNIPHY2_AHB_CLK				118
128 #define GCC_CMN_12GPLL_AHB_CLK				119
129 #define GCC_CMN_12GPLL_APU_CLK				120
130 #define SYSTEM_NOC_BFDCD_CLK_SRC			121
131 #define GCC_NSSNOC_SNOC_CLK				122
132 #define GCC_NSSNOC_SNOC_1_CLK				123
133 #define GCC_QDSS_ETR_USB_CLK				124
134 #define WCSS_AHB_CLK_SRC				125
135 #define GCC_Q6_AHB_CLK					126
136 #define GCC_Q6_AHB_S_CLK				127
137 #define GCC_WCSS_ECAHB_CLK				128
138 #define GCC_WCSS_ACMT_CLK				129
139 #define GCC_SYS_NOC_WCSS_AHB_CLK			130
140 #define WCSS_AXI_M_CLK_SRC				131
141 #define GCC_ANOC_WCSS_AXI_M_CLK				132
142 #define QDSS_AT_CLK_SRC					133
143 #define GCC_Q6SS_ATBM_CLK				134
144 #define GCC_WCSS_DBG_IFC_ATB_CLK			135
145 #define GCC_NSSNOC_ATB_CLK				136
146 #define GCC_QDSS_AT_CLK					137
147 #define GCC_SYS_NOC_AT_CLK				138
148 #define GCC_PCNOC_AT_CLK				139
149 #define GCC_USB0_EUD_AT_CLK				140
150 #define GCC_QDSS_EUD_AT_CLK				141
151 #define QDSS_STM_CLK_SRC				142
152 #define GCC_QDSS_STM_CLK				143
153 #define GCC_SYS_NOC_QDSS_STM_AXI_CLK			144
154 #define QDSS_TRACECLKIN_CLK_SRC				145
155 #define GCC_QDSS_TRACECLKIN_CLK				146
156 #define QDSS_TSCTR_CLK_SRC				147
157 #define GCC_Q6_TSCTR_1TO2_CLK				148
158 #define GCC_WCSS_DBG_IFC_NTS_CLK			149
159 #define GCC_QDSS_TSCTR_DIV2_CLK				150
160 #define GCC_QDSS_TS_CLK					151
161 #define GCC_QDSS_TSCTR_DIV4_CLK				152
162 #define GCC_NSS_TS_CLK					153
163 #define GCC_QDSS_TSCTR_DIV8_CLK				154
164 #define GCC_QDSS_TSCTR_DIV16_CLK			155
165 #define GCC_Q6SS_PCLKDBG_CLK				156
166 #define GCC_Q6SS_TRIG_CLK				157
167 #define GCC_WCSS_DBG_IFC_APB_CLK			158
168 #define GCC_WCSS_DBG_IFC_DAPBUS_CLK			159
169 #define GCC_QDSS_DAP_CLK				160
170 #define GCC_QDSS_APB2JTAG_CLK				161
171 #define GCC_QDSS_TSCTR_DIV3_CLK				162
172 #define QPIC_IO_MACRO_CLK_SRC				163
173 #define GCC_QPIC_IO_MACRO_CLK                           164
174 #define Q6_AXI_CLK_SRC					165
175 #define GCC_Q6_AXIM_CLK					166
176 #define GCC_WCSS_Q6_TBU_CLK				167
177 #define GCC_MEM_NOC_Q6_AXI_CLK				168
178 #define Q6_AXIM2_CLK_SRC				169
179 #define NSSNOC_MEMNOC_BFDCD_CLK_SRC			170
180 #define GCC_NSSNOC_MEMNOC_CLK				171
181 #define GCC_NSSNOC_MEM_NOC_1_CLK			172
182 #define GCC_NSS_TBU_CLK					173
183 #define GCC_MEM_NOC_NSSNOC_CLK				174
184 #define LPASS_AXIM_CLK_SRC				175
185 #define LPASS_SWAY_CLK_SRC				176
186 #define ADSS_PWM_CLK_SRC				177
187 #define GCC_ADSS_PWM_CLK				178
188 #define GP1_CLK_SRC					179
189 #define GP2_CLK_SRC					180
190 #define GP3_CLK_SRC					181
191 #define DDRSS_SMS_SLOW_CLK_SRC				182
192 #define GCC_XO_CLK_SRC					183
193 #define GCC_XO_CLK					184
194 #define GCC_NSSNOC_QOSGEN_REF_CLK			185
195 #define GCC_NSSNOC_TIMEOUT_REF_CLK			186
196 #define GCC_XO_DIV4_CLK					187
197 #define GCC_UNIPHY0_SYS_CLK				188
198 #define GCC_UNIPHY1_SYS_CLK				189
199 #define GCC_UNIPHY2_SYS_CLK				190
200 #define GCC_CMN_12GPLL_SYS_CLK				191
201 #define GCC_NSSNOC_XO_DCD_CLK				192
202 #define GCC_Q6SS_BOOT_CLK				193
203 #define UNIPHY_SYS_CLK_SRC				194
204 #define NSS_TS_CLK_SRC					195
205 #define GCC_ANOC_PCIE0_1LANE_M_CLK			196
206 #define GCC_ANOC_PCIE1_1LANE_M_CLK			197
207 #define GCC_ANOC_PCIE2_2LANE_M_CLK			198
208 #define GCC_ANOC_PCIE3_2LANE_M_CLK			199
209 #define GCC_SNOC_PCIE0_1LANE_S_CLK			200
210 #define GCC_SNOC_PCIE1_1LANE_S_CLK			201
211 #define GCC_SNOC_PCIE2_2LANE_S_CLK			202
212 #define GCC_SNOC_PCIE3_2LANE_S_CLK			203
213 #define GCC_CRYPTO_CLK_SRC				204
214 #define GCC_CRYPTO_CLK					205
215 #define GCC_CRYPTO_AXI_CLK				206
216 #define GCC_CRYPTO_AHB_CLK				207
217 #define GCC_USB0_PIPE_CLK				208
218 #define GCC_USB0_SLEEP_CLK				209
219 #define GCC_PCIE0_PIPE_CLK				210
220 #define GCC_PCIE1_PIPE_CLK				211
221 #define GCC_PCIE2_PIPE_CLK				212
222 #define GCC_PCIE3_PIPE_CLK				213
223 #endif
224