1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017~2018 NXP
5 *
6 */
7
8 #include <linux/bits.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/slab.h>
14
15 #include "../clk-fractional-divider.h"
16 #include "clk.h"
17
18 #define PCG_PR_MASK BIT(31)
19 #define PCG_PCS_SHIFT 24
20 #define PCG_PCS_MASK 0x7
21 #define PCG_CGC_SHIFT 30
22 #define PCG_FRAC_SHIFT 3
23 #define PCG_FRAC_WIDTH 1
24 #define PCG_PCD_SHIFT 0
25 #define PCG_PCD_WIDTH 3
26
27 #define SW_RST BIT(28)
28
pcc_gate_enable(struct clk_hw * hw)29 static int pcc_gate_enable(struct clk_hw *hw)
30 {
31 struct clk_gate *gate = to_clk_gate(hw);
32 unsigned long flags;
33 u32 val;
34 int ret;
35
36 ret = clk_gate_ops.enable(hw);
37 if (ret)
38 return ret;
39
40 /* Make sure the IP's clock is ready before release reset */
41 udelay(1);
42
43 spin_lock_irqsave(gate->lock, flags);
44 /*
45 * release the sw reset for peripherals associated with
46 * with this pcc clock.
47 */
48 val = readl(gate->reg);
49 val |= SW_RST;
50 writel(val, gate->reg);
51
52 spin_unlock_irqrestore(gate->lock, flags);
53
54 /*
55 * Read back the register to make sure the previous write has been
56 * done in the target HW register. For IP like GPU, after deassert
57 * the reset, need to wait for a while to make sure the sync reset
58 * is done
59 */
60 readl(gate->reg);
61 udelay(1);
62
63 return 0;
64 }
65
pcc_gate_disable(struct clk_hw * hw)66 static void pcc_gate_disable(struct clk_hw *hw)
67 {
68 clk_gate_ops.disable(hw);
69 }
70
pcc_gate_is_enabled(struct clk_hw * hw)71 static int pcc_gate_is_enabled(struct clk_hw *hw)
72 {
73 return clk_gate_ops.is_enabled(hw);
74 }
75
76 static const struct clk_ops pcc_gate_ops = {
77 .enable = pcc_gate_enable,
78 .disable = pcc_gate_disable,
79 .is_enabled = pcc_gate_is_enabled,
80 };
81
imx_ulp_clk_hw_composite(const char * name,const char * const * parent_names,int num_parents,bool mux_present,bool rate_present,bool gate_present,void __iomem * reg,bool has_swrst)82 static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,
83 const char * const *parent_names,
84 int num_parents, bool mux_present,
85 bool rate_present, bool gate_present,
86 void __iomem *reg, bool has_swrst)
87 {
88 struct clk_hw *mux_hw = NULL, *fd_hw = NULL, *gate_hw = NULL;
89 struct clk_fractional_divider *fd = NULL;
90 struct clk_gate *gate = NULL;
91 struct clk_mux *mux = NULL;
92 struct clk_hw *hw;
93 u32 val;
94
95 val = readl(reg);
96 if (!(val & PCG_PR_MASK)) {
97 pr_info("PCC PR is 0 for clk:%s, bypass\n", name);
98 return NULL;
99 }
100
101 if (mux_present) {
102 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
103 if (!mux)
104 return ERR_PTR(-ENOMEM);
105 mux_hw = &mux->hw;
106 mux->reg = reg;
107 mux->shift = PCG_PCS_SHIFT;
108 mux->mask = PCG_PCS_MASK;
109 if (has_swrst)
110 mux->lock = &imx_ccm_lock;
111 }
112
113 if (rate_present) {
114 fd = kzalloc(sizeof(*fd), GFP_KERNEL);
115 if (!fd) {
116 kfree(mux);
117 return ERR_PTR(-ENOMEM);
118 }
119 fd_hw = &fd->hw;
120 fd->reg = reg;
121 fd->mshift = PCG_FRAC_SHIFT;
122 fd->mwidth = PCG_FRAC_WIDTH;
123 fd->nshift = PCG_PCD_SHIFT;
124 fd->nwidth = PCG_PCD_WIDTH;
125 fd->flags = CLK_FRAC_DIVIDER_ZERO_BASED;
126 if (has_swrst)
127 fd->lock = &imx_ccm_lock;
128 }
129
130 if (gate_present) {
131 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
132 if (!gate) {
133 kfree(mux);
134 kfree(fd);
135 return ERR_PTR(-ENOMEM);
136 }
137 gate_hw = &gate->hw;
138 gate->reg = reg;
139 gate->bit_idx = PCG_CGC_SHIFT;
140 if (has_swrst)
141 gate->lock = &imx_ccm_lock;
142 /*
143 * make sure clock is gated during clock tree initialization,
144 * the HW ONLY allow clock parent/rate changed with clock gated,
145 * during clock tree initialization, clocks could be enabled
146 * by bootloader, so the HW status will mismatch with clock tree
147 * prepare count, then clock core driver will allow parent/rate
148 * change since the prepare count is zero, but HW actually
149 * prevent the parent/rate change due to the clock is enabled.
150 */
151 val = readl_relaxed(reg);
152 val &= ~(1 << PCG_CGC_SHIFT);
153 writel_relaxed(val, reg);
154 }
155
156 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
157 mux_hw, &clk_mux_ops, fd_hw,
158 &clk_fractional_divider_ops, gate_hw,
159 has_swrst ? &pcc_gate_ops : &clk_gate_ops, CLK_SET_RATE_GATE |
160 CLK_SET_PARENT_GATE | CLK_SET_RATE_NO_REPARENT);
161 if (IS_ERR(hw)) {
162 kfree(mux);
163 kfree(fd);
164 kfree(gate);
165 }
166
167 return hw;
168 }
169
imx7ulp_clk_hw_composite(const char * name,const char * const * parent_names,int num_parents,bool mux_present,bool rate_present,bool gate_present,void __iomem * reg)170 struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names,
171 int num_parents, bool mux_present, bool rate_present,
172 bool gate_present, void __iomem *reg)
173 {
174 return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present,
175 gate_present, reg, false);
176 }
177
imx8ulp_clk_hw_composite(const char * name,const char * const * parent_names,int num_parents,bool mux_present,bool rate_present,bool gate_present,void __iomem * reg,bool has_swrst)178 struct clk_hw *imx8ulp_clk_hw_composite(const char *name, const char * const *parent_names,
179 int num_parents, bool mux_present, bool rate_present,
180 bool gate_present, void __iomem *reg, bool has_swrst)
181 {
182 return imx_ulp_clk_hw_composite(name, parent_names, num_parents, mux_present, rate_present,
183 gate_present, reg, has_swrst);
184 }
185 EXPORT_SYMBOL_GPL(imx8ulp_clk_hw_composite);
186