1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: QPLib resource manager (header)
37 */
38
39 #ifndef __BNXT_QPLIB_RES_H__
40 #define __BNXT_QPLIB_RES_H__
41
42 #include "bnxt_ulp.h"
43
44 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
45
46 #define CHIP_NUM_57508 0x1750
47 #define CHIP_NUM_57504 0x1751
48 #define CHIP_NUM_57502 0x1752
49 #define CHIP_NUM_58818 0xd818
50 #define CHIP_NUM_57608 0x1760
51
52 #define BNXT_QPLIB_DBR_VALID (0x1UL << 26)
53 #define BNXT_QPLIB_DBR_EPOCH_SHIFT 24
54 #define BNXT_QPLIB_DBR_TOGGLE_SHIFT 25
55
56 struct bnxt_qplib_drv_modes {
57 u8 wqe_mode;
58 bool db_push;
59 bool dbr_pacing;
60 u32 toggle_bits;
61 };
62
63 enum bnxt_re_toggle_modes {
64 BNXT_QPLIB_CQ_TOGGLE_BIT = 0x1,
65 BNXT_QPLIB_SRQ_TOGGLE_BIT = 0x2,
66 };
67
68 struct bnxt_qplib_chip_ctx {
69 u16 chip_num;
70 u8 chip_rev;
71 u8 chip_metal;
72 u16 hw_stats_size;
73 u16 hwrm_cmd_max_timeout;
74 struct bnxt_qplib_drv_modes modes;
75 u64 hwrm_intf_ver;
76 u32 dbr_stat_db_fifo;
77 };
78
79 struct bnxt_qplib_db_pacing_data {
80 u32 do_pacing;
81 u32 pacing_th;
82 u32 alarm_th;
83 u32 fifo_max_depth;
84 u32 fifo_room_mask;
85 u32 fifo_room_shift;
86 u32 grc_reg_offset;
87 u32 dev_err_state;
88 };
89
90 #define BNXT_QPLIB_DBR_PF_DB_OFFSET 0x10000
91 #define BNXT_QPLIB_DBR_VF_DB_OFFSET 0x4000
92
93 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *))
94 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1)
95 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
96 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG)
97
98 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1))
99
100 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \
101 ((HWQ_CMP(hwq->prod, hwq)\
102 - HWQ_CMP(hwq->cons, hwq))\
103 & (hwq->max_elements - 1)))
104 enum bnxt_qplib_hwq_type {
105 HWQ_TYPE_CTX,
106 HWQ_TYPE_QUEUE,
107 HWQ_TYPE_L2_CMPL,
108 HWQ_TYPE_MR
109 };
110
111 #define MAX_PBL_LVL_0_PGS 1
112 #define MAX_PBL_LVL_1_PGS 512
113 #define MAX_PBL_LVL_1_PGS_SHIFT 9
114 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256
115 #define MAX_PBL_LVL_2_PGS (256 * 512)
116 #define MAX_PDL_LVL_SHIFT 9
117
118 enum bnxt_qplib_pbl_lvl {
119 PBL_LVL_0,
120 PBL_LVL_1,
121 PBL_LVL_2,
122 PBL_LVL_MAX
123 };
124
125 #define ROCE_PG_SIZE_4K (4 * 1024)
126 #define ROCE_PG_SIZE_8K (8 * 1024)
127 #define ROCE_PG_SIZE_64K (64 * 1024)
128 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024)
129 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024)
130 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024)
131
132 enum bnxt_qplib_hwrm_pg_size {
133 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0,
134 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1,
135 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2,
136 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3,
137 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4,
138 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5,
139 };
140
141 struct bnxt_qplib_reg_desc {
142 u8 bar_id;
143 resource_size_t bar_base;
144 unsigned long offset;
145 void __iomem *bar_reg;
146 size_t len;
147 };
148
149 struct bnxt_qplib_pbl {
150 u32 pg_count;
151 u32 pg_size;
152 void **pg_arr;
153 dma_addr_t *pg_map_arr;
154 };
155
156 struct bnxt_qplib_sg_info {
157 struct ib_umem *umem;
158 u32 npages;
159 u32 pgshft;
160 u32 pgsize;
161 bool nopte;
162 };
163
164 struct bnxt_qplib_hwq_attr {
165 struct bnxt_qplib_res *res;
166 struct bnxt_qplib_sg_info *sginfo;
167 enum bnxt_qplib_hwq_type type;
168 u32 depth;
169 u32 stride;
170 u32 aux_stride;
171 u32 aux_depth;
172 };
173
174 struct bnxt_qplib_hwq {
175 struct pci_dev *pdev;
176 /* lock to protect qplib_hwq */
177 spinlock_t lock;
178 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1];
179 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */
180 /* ptr for easy access to the PBL entries */
181 void **pbl_ptr;
182 /* ptr for easy access to the dma_addr */
183 dma_addr_t *pbl_dma_ptr;
184 u32 max_elements;
185 u32 depth;
186 u16 element_size; /* Size of each entry */
187 u16 qe_ppg; /* queue entry per page */
188
189 u32 prod; /* raw */
190 u32 cons; /* raw */
191 u8 cp_bit;
192 u8 is_user;
193 u64 *pad_pg;
194 u32 pad_stride;
195 u32 pad_pgofft;
196 };
197
198 struct bnxt_qplib_db_info {
199 void __iomem *db;
200 void __iomem *priv_db;
201 struct bnxt_qplib_hwq *hwq;
202 u32 xid;
203 u32 max_slot;
204 u32 flags;
205 u8 toggle;
206 };
207
208 enum bnxt_qplib_db_info_flags_mask {
209 BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT = 0x0UL,
210 BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT = 0x1UL,
211 BNXT_QPLIB_FLAG_EPOCH_CONS_MASK = 0x1UL,
212 BNXT_QPLIB_FLAG_EPOCH_PROD_MASK = 0x2UL,
213 };
214
215 enum bnxt_qplib_db_epoch_flag_shift {
216 BNXT_QPLIB_DB_EPOCH_CONS_SHIFT = BNXT_QPLIB_DBR_EPOCH_SHIFT,
217 BNXT_QPLIB_DB_EPOCH_PROD_SHIFT = (BNXT_QPLIB_DBR_EPOCH_SHIFT - 1),
218 };
219
220 /* Tables */
221 struct bnxt_qplib_pd_tbl {
222 unsigned long *tbl;
223 u32 max;
224 };
225
226 struct bnxt_qplib_sgid_tbl {
227 struct bnxt_qplib_gid_info *tbl;
228 u16 *hw_id;
229 u16 max;
230 u16 active;
231 void *ctx;
232 u8 *vlan;
233 };
234
235 enum {
236 BNXT_QPLIB_DPI_TYPE_KERNEL = 0,
237 BNXT_QPLIB_DPI_TYPE_UC = 1,
238 BNXT_QPLIB_DPI_TYPE_WC = 2
239 };
240
241 struct bnxt_qplib_dpi {
242 u32 dpi;
243 u32 bit;
244 void __iomem *dbr;
245 u64 umdbr;
246 u8 type;
247 };
248
249 struct bnxt_qplib_dpi_tbl {
250 void **app_tbl;
251 unsigned long *tbl;
252 u16 max;
253 struct bnxt_qplib_reg_desc ucreg; /* Hold entire DB bar. */
254 struct bnxt_qplib_reg_desc wcreg;
255 void __iomem *priv_db;
256 };
257
258 struct bnxt_qplib_stats {
259 dma_addr_t dma_map;
260 void *dma;
261 u32 size;
262 u32 fw_id;
263 };
264
265 struct bnxt_qplib_vf_res {
266 u32 max_qp_per_vf;
267 u32 max_mrw_per_vf;
268 u32 max_srq_per_vf;
269 u32 max_cq_per_vf;
270 u32 max_gid_per_vf;
271 };
272
273 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448
274 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64
275 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64
276 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128
277
278 #define MAX_TQM_ALLOC_REQ 48
279 #define MAX_TQM_ALLOC_BLK_SIZE 8
280 struct bnxt_qplib_tqm_ctx {
281 struct bnxt_qplib_hwq pde;
282 u8 pde_level; /* Original level */
283 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ];
284 u8 qcount[MAX_TQM_ALLOC_REQ];
285 };
286
287 struct bnxt_qplib_ctx {
288 u32 qpc_count;
289 struct bnxt_qplib_hwq qpc_tbl;
290 u32 mrw_count;
291 struct bnxt_qplib_hwq mrw_tbl;
292 u32 srqc_count;
293 struct bnxt_qplib_hwq srqc_tbl;
294 u32 cq_count;
295 struct bnxt_qplib_hwq cq_tbl;
296 struct bnxt_qplib_hwq tim_tbl;
297 struct bnxt_qplib_tqm_ctx tqm_ctx;
298 struct bnxt_qplib_stats stats;
299 struct bnxt_qplib_vf_res vf_res;
300 };
301
302 struct bnxt_qplib_res {
303 struct pci_dev *pdev;
304 struct bnxt_qplib_chip_ctx *cctx;
305 struct bnxt_qplib_dev_attr *dattr;
306 struct net_device *netdev;
307 struct bnxt_en_dev *en_dev;
308 struct bnxt_qplib_rcfw *rcfw;
309 struct bnxt_qplib_pd_tbl pd_tbl;
310 /* To protect the pd table bit map */
311 struct mutex pd_tbl_lock;
312 struct bnxt_qplib_sgid_tbl sgid_tbl;
313 struct bnxt_qplib_dpi_tbl dpi_tbl;
314 /* To protect the dpi table bit map */
315 struct mutex dpi_tbl_lock;
316 bool prio;
317 bool is_vf;
318 struct bnxt_qplib_db_pacing_data *pacing_data;
319 };
320
bnxt_qplib_is_chip_gen_p7(struct bnxt_qplib_chip_ctx * cctx)321 static inline bool bnxt_qplib_is_chip_gen_p7(struct bnxt_qplib_chip_ctx *cctx)
322 {
323 return (cctx->chip_num == CHIP_NUM_58818 ||
324 cctx->chip_num == CHIP_NUM_57608);
325 }
326
bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx * cctx)327 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
328 {
329 return (cctx->chip_num == CHIP_NUM_57508 ||
330 cctx->chip_num == CHIP_NUM_57504 ||
331 cctx->chip_num == CHIP_NUM_57502);
332 }
333
bnxt_qplib_is_chip_gen_p5_p7(struct bnxt_qplib_chip_ctx * cctx)334 static inline bool bnxt_qplib_is_chip_gen_p5_p7(struct bnxt_qplib_chip_ctx *cctx)
335 {
336 return bnxt_qplib_is_chip_gen_p5(cctx) || bnxt_qplib_is_chip_gen_p7(cctx);
337 }
338
bnxt_qplib_get_hwq_type(struct bnxt_qplib_res * res)339 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
340 {
341 return bnxt_qplib_is_chip_gen_p5_p7(res->cctx) ?
342 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
343 }
344
bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx * cctx)345 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
346 {
347 return bnxt_qplib_is_chip_gen_p5_p7(cctx) ?
348 RING_ALLOC_REQ_RING_TYPE_NQ :
349 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
350 }
351
bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq * hwq)352 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
353 {
354 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
355 struct bnxt_qplib_pbl *pbl;
356
357 pbl = &hwq->pbl[PBL_LVL_0];
358 switch (pbl->pg_size) {
359 case ROCE_PG_SIZE_4K:
360 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
361 break;
362 case ROCE_PG_SIZE_8K:
363 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
364 break;
365 case ROCE_PG_SIZE_64K:
366 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
367 break;
368 case ROCE_PG_SIZE_2M:
369 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
370 break;
371 case ROCE_PG_SIZE_8M:
372 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
373 break;
374 case ROCE_PG_SIZE_1G:
375 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
376 break;
377 default:
378 break;
379 }
380
381 return pg_size;
382 }
383
bnxt_qplib_get_qe(struct bnxt_qplib_hwq * hwq,u32 indx,u64 * pg)384 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
385 u32 indx, u64 *pg)
386 {
387 u32 pg_num, pg_idx;
388
389 pg_num = (indx / hwq->qe_ppg);
390 pg_idx = (indx % hwq->qe_ppg);
391 if (pg)
392 *pg = (u64)&hwq->pbl_ptr[pg_num];
393 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
394 }
395
bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq * hwq,u32 idx)396 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
397 {
398 idx += hwq->prod;
399 if (idx >= hwq->depth)
400 idx -= hwq->depth;
401 return bnxt_qplib_get_qe(hwq, idx, NULL);
402 }
403
404 #define to_bnxt_qplib(ptr, type, member) \
405 container_of(ptr, type, member)
406
407 struct bnxt_qplib_pd;
408 struct bnxt_qplib_dev_attr;
409
410 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
411 struct bnxt_qplib_hwq *hwq);
412 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
413 struct bnxt_qplib_hwq_attr *hwq_attr);
414 int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res,
415 struct bnxt_qplib_pd *pd);
416 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
417 struct bnxt_qplib_pd_tbl *pd_tbl,
418 struct bnxt_qplib_pd *pd);
419 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res,
420 struct bnxt_qplib_dpi *dpi,
421 void *app, u8 type);
422 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
423 struct bnxt_qplib_dpi *dpi);
424 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
425 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
426 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
427 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
428 struct net_device *netdev,
429 struct bnxt_qplib_dev_attr *dev_attr);
430 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
431 struct bnxt_qplib_ctx *ctx);
432 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
433 struct bnxt_qplib_ctx *ctx,
434 bool virt_fn, bool is_p5);
435 int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res);
436 void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res);
437
438 int bnxt_qplib_determine_atomics(struct pci_dev *dev);
439
bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info * dbinfo,struct bnxt_qplib_hwq * hwq,u32 cnt)440 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info *dbinfo,
441 struct bnxt_qplib_hwq *hwq, u32 cnt)
442 {
443 /* move prod and update toggle/epoch if wrap around */
444 hwq->prod += cnt;
445 if (hwq->prod >= hwq->depth) {
446 hwq->prod %= hwq->depth;
447 dbinfo->flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_PROD_SHIFT;
448 }
449 }
450
bnxt_qplib_hwq_incr_cons(u32 max_elements,u32 * cons,u32 cnt,u32 * dbinfo_flags)451 static inline void bnxt_qplib_hwq_incr_cons(u32 max_elements, u32 *cons, u32 cnt,
452 u32 *dbinfo_flags)
453 {
454 /* move cons and update toggle/epoch if wrap around */
455 *cons += cnt;
456 if (*cons >= max_elements) {
457 *cons %= max_elements;
458 *dbinfo_flags ^= 1UL << BNXT_QPLIB_FLAG_EPOCH_CONS_SHIFT;
459 }
460 }
461
bnxt_qplib_ring_db32(struct bnxt_qplib_db_info * info,bool arm)462 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
463 bool arm)
464 {
465 u32 key = 0;
466
467 key |= info->hwq->cons | (CMPL_DOORBELL_IDX_VALID |
468 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
469 if (!arm)
470 key |= CMPL_DOORBELL_MASK;
471 writel(key, info->db);
472 }
473
474 #define BNXT_QPLIB_INIT_DBHDR(xid, type, indx, toggle) \
475 (((u64)(((xid) & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | \
476 (type) | BNXT_QPLIB_DBR_VALID) << 32) | (indx) | \
477 (((u32)(toggle)) << (BNXT_QPLIB_DBR_TOGGLE_SHIFT)))
478
bnxt_qplib_ring_db(struct bnxt_qplib_db_info * info,u32 type)479 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
480 u32 type)
481 {
482 u64 key = 0;
483 u32 indx;
484 u8 toggle = 0;
485
486 if (type == DBC_DBC_TYPE_CQ_ARMALL ||
487 type == DBC_DBC_TYPE_CQ_ARMSE)
488 toggle = info->toggle;
489
490 indx = (info->hwq->cons & DBC_DBC_INDEX_MASK) |
491 ((info->flags & BNXT_QPLIB_FLAG_EPOCH_CONS_MASK) <<
492 BNXT_QPLIB_DB_EPOCH_CONS_SHIFT);
493
494 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, indx, toggle);
495 writeq(key, info->db);
496 }
497
bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info * info,u32 type)498 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
499 u32 type)
500 {
501 u64 key = 0;
502 u32 indx;
503
504 indx = (((info->hwq->prod / info->max_slot) & DBC_DBC_INDEX_MASK) |
505 ((info->flags & BNXT_QPLIB_FLAG_EPOCH_PROD_MASK) <<
506 BNXT_QPLIB_DB_EPOCH_PROD_SHIFT));
507 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, indx, 0);
508 writeq(key, info->db);
509 }
510
bnxt_qplib_armen_db(struct bnxt_qplib_db_info * info,u32 type)511 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
512 u32 type)
513 {
514 u64 key = 0;
515 u8 toggle = 0;
516
517 if (type == DBC_DBC_TYPE_CQ_ARMENA || type == DBC_DBC_TYPE_SRQ_ARMENA)
518 toggle = info->toggle;
519 /* Index always at 0 */
520 key = BNXT_QPLIB_INIT_DBHDR(info->xid, type, 0, toggle);
521 writeq(key, info->priv_db);
522 }
523
bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info * info,u32 th)524 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
525 u32 th)
526 {
527 u64 key = 0;
528
529 key = BNXT_QPLIB_INIT_DBHDR(info->xid, DBC_DBC_TYPE_SRQ_ARM, th, info->toggle);
530 writeq(key, info->priv_db);
531 }
532
bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info * info,struct bnxt_qplib_chip_ctx * cctx,bool arm)533 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
534 struct bnxt_qplib_chip_ctx *cctx,
535 bool arm)
536 {
537 u32 type;
538
539 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
540 if (bnxt_qplib_is_chip_gen_p5_p7(cctx))
541 bnxt_qplib_ring_db(info, type);
542 else
543 bnxt_qplib_ring_db32(info, arm);
544 }
545
_is_ext_stats_supported(u16 dev_cap_flags)546 static inline bool _is_ext_stats_supported(u16 dev_cap_flags)
547 {
548 return dev_cap_flags &
549 CREQ_QUERY_FUNC_RESP_SB_EXT_STATS;
550 }
551
_is_hw_retx_supported(u16 dev_cap_flags)552 static inline bool _is_hw_retx_supported(u16 dev_cap_flags)
553 {
554 return dev_cap_flags &
555 (CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED |
556 CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED);
557 }
558
559 #define BNXT_RE_HW_RETX(a) _is_hw_retx_supported((a))
560
_is_host_msn_table(u16 dev_cap_ext_flags2)561 static inline bool _is_host_msn_table(u16 dev_cap_ext_flags2)
562 {
563 return (dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK) ==
564 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE;
565 }
566
bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx * cctx)567 static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx)
568 {
569 return cctx->modes.dbr_pacing;
570 }
571
_is_alloc_mr_unified(u16 dev_cap_flags)572 static inline bool _is_alloc_mr_unified(u16 dev_cap_flags)
573 {
574 return dev_cap_flags & CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC;
575 }
576
_is_relaxed_ordering_supported(u16 dev_cap_ext_flags2)577 static inline bool _is_relaxed_ordering_supported(u16 dev_cap_ext_flags2)
578 {
579 return dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED;
580 }
581
_is_optimize_modify_qp_supported(u16 dev_cap_ext_flags2)582 static inline bool _is_optimize_modify_qp_supported(u16 dev_cap_ext_flags2)
583 {
584 return dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED;
585 }
586
_is_min_rnr_in_rtr_rts_mandatory(u16 dev_cap_ext_flags2)587 static inline bool _is_min_rnr_in_rtr_rts_mandatory(u16 dev_cap_ext_flags2)
588 {
589 return !!(dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_MIN_RNR_RTR_RTS_OPT_SUPPORTED);
590 }
591
_is_cq_coalescing_supported(u16 dev_cap_ext_flags2)592 static inline bool _is_cq_coalescing_supported(u16 dev_cap_ext_flags2)
593 {
594 return dev_cap_ext_flags2 & CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED;
595 }
596
597 #endif /* __BNXT_QPLIB_RES_H__ */
598