1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Socionext SPI flash controller F_OSPI driver 4 * Copyright (C) 2021 Socionext Inc. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/module.h> 12 #include <linux/mutex.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/spi/spi.h> 16 #include <linux/spi/spi-mem.h> 17 18 /* Registers */ 19 #define OSPI_PROT_CTL_INDIR 0x00 20 #define OSPI_PROT_MODE_DATA_MASK GENMASK(31, 30) 21 #define OSPI_PROT_MODE_ALT_MASK GENMASK(29, 28) 22 #define OSPI_PROT_MODE_ADDR_MASK GENMASK(27, 26) 23 #define OSPI_PROT_MODE_CODE_MASK GENMASK(25, 24) 24 #define OSPI_PROT_MODE_SINGLE 0 25 #define OSPI_PROT_MODE_DUAL 1 26 #define OSPI_PROT_MODE_QUAD 2 27 #define OSPI_PROT_MODE_OCTAL 3 28 #define OSPI_PROT_DATA_RATE_DATA BIT(23) 29 #define OSPI_PROT_DATA_RATE_ALT BIT(22) 30 #define OSPI_PROT_DATA_RATE_ADDR BIT(21) 31 #define OSPI_PROT_DATA_RATE_CODE BIT(20) 32 #define OSPI_PROT_SDR 0 33 #define OSPI_PROT_DDR 1 34 #define OSPI_PROT_BIT_POS_DATA BIT(19) 35 #define OSPI_PROT_BIT_POS_ALT BIT(18) 36 #define OSPI_PROT_BIT_POS_ADDR BIT(17) 37 #define OSPI_PROT_BIT_POS_CODE BIT(16) 38 #define OSPI_PROT_SAMP_EDGE BIT(12) 39 #define OSPI_PROT_DATA_UNIT_MASK GENMASK(11, 10) 40 #define OSPI_PROT_DATA_UNIT_1B 0 41 #define OSPI_PROT_DATA_UNIT_2B 1 42 #define OSPI_PROT_DATA_UNIT_4B 3 43 #define OSPI_PROT_TRANS_DIR_WRITE BIT(9) 44 #define OSPI_PROT_DATA_EN BIT(8) 45 #define OSPI_PROT_ALT_SIZE_MASK GENMASK(7, 5) 46 #define OSPI_PROT_ADDR_SIZE_MASK GENMASK(4, 2) 47 #define OSPI_PROT_CODE_SIZE_MASK GENMASK(1, 0) 48 49 #define OSPI_CLK_CTL 0x10 50 #define OSPI_CLK_CTL_BOOT_INT_CLK_EN BIT(16) 51 #define OSPI_CLK_CTL_PHA BIT(12) 52 #define OSPI_CLK_CTL_PHA_180 0 53 #define OSPI_CLK_CTL_PHA_90 1 54 #define OSPI_CLK_CTL_DIV GENMASK(9, 8) 55 #define OSPI_CLK_CTL_DIV_1 0 56 #define OSPI_CLK_CTL_DIV_2 1 57 #define OSPI_CLK_CTL_DIV_4 2 58 #define OSPI_CLK_CTL_DIV_8 3 59 #define OSPI_CLK_CTL_INT_CLK_EN BIT(0) 60 61 #define OSPI_CS_CTL1 0x14 62 #define OSPI_CS_CTL2 0x18 63 #define OSPI_SSEL 0x20 64 #define OSPI_CMD_IDX_INDIR 0x40 65 #define OSPI_ADDR 0x50 66 #define OSPI_ALT_INDIR 0x60 67 #define OSPI_DMY_INDIR 0x70 68 #define OSPI_DAT 0x80 69 #define OSPI_DAT_SWP_INDIR 0x90 70 71 #define OSPI_DAT_SIZE_INDIR 0xA0 72 #define OSPI_DAT_SIZE_EN BIT(15) 73 #define OSPI_DAT_SIZE_MASK GENMASK(10, 0) 74 #define OSPI_DAT_SIZE_MAX (OSPI_DAT_SIZE_MASK + 1) 75 76 #define OSPI_TRANS_CTL 0xC0 77 #define OSPI_TRANS_CTL_STOP_REQ BIT(1) /* RW1AC */ 78 #define OSPI_TRANS_CTL_START_REQ BIT(0) /* RW1AC */ 79 80 #define OSPI_ACC_MODE 0xC4 81 #define OSPI_ACC_MODE_BOOT_DISABLE BIT(0) 82 83 #define OSPI_SWRST 0xD0 84 #define OSPI_SWRST_INDIR_WRITE_FIFO BIT(9) /* RW1AC */ 85 #define OSPI_SWRST_INDIR_READ_FIFO BIT(8) /* RW1AC */ 86 87 #define OSPI_STAT 0xE0 88 #define OSPI_STAT_IS_AXI_WRITING BIT(10) 89 #define OSPI_STAT_IS_AXI_READING BIT(9) 90 #define OSPI_STAT_IS_SPI_INT_CLK_STOP BIT(4) 91 #define OSPI_STAT_IS_SPI_IDLE BIT(3) 92 93 #define OSPI_IRQ 0xF0 94 #define OSPI_IRQ_CS_DEASSERT BIT(8) 95 #define OSPI_IRQ_WRITE_BUF_READY BIT(2) 96 #define OSPI_IRQ_READ_BUF_READY BIT(1) 97 #define OSPI_IRQ_CS_TRANS_COMP BIT(0) 98 #define OSPI_IRQ_ALL \ 99 (OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_WRITE_BUF_READY \ 100 | OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP) 101 102 #define OSPI_IRQ_STAT_EN 0xF4 103 #define OSPI_IRQ_SIG_EN 0xF8 104 105 /* Parameters */ 106 #define OSPI_NUM_CS 4 107 #define OSPI_DUMMY_CYCLE_MAX 255 108 #define OSPI_WAIT_MAX_MSEC 100 109 110 struct f_ospi { 111 void __iomem *base; 112 struct device *dev; 113 struct clk *clk; 114 struct mutex mlock; 115 }; 116 117 static u32 f_ospi_get_dummy_cycle(const struct spi_mem_op *op) 118 { 119 if (!op->dummy.nbytes) 120 return 0; 121 122 return (op->dummy.nbytes * 8) / op->dummy.buswidth; 123 } 124 125 static void f_ospi_clear_irq(struct f_ospi *ospi) 126 { 127 writel(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_CS_TRANS_COMP, 128 ospi->base + OSPI_IRQ); 129 } 130 131 static void f_ospi_enable_irq_status(struct f_ospi *ospi, u32 irq_bits) 132 { 133 u32 val; 134 135 val = readl(ospi->base + OSPI_IRQ_STAT_EN); 136 val |= irq_bits; 137 writel(val, ospi->base + OSPI_IRQ_STAT_EN); 138 } 139 140 static void f_ospi_disable_irq_status(struct f_ospi *ospi, u32 irq_bits) 141 { 142 u32 val; 143 144 val = readl(ospi->base + OSPI_IRQ_STAT_EN); 145 val &= ~irq_bits; 146 writel(val, ospi->base + OSPI_IRQ_STAT_EN); 147 } 148 149 static void f_ospi_disable_irq_output(struct f_ospi *ospi, u32 irq_bits) 150 { 151 u32 val; 152 153 val = readl(ospi->base + OSPI_IRQ_SIG_EN); 154 val &= ~irq_bits; 155 writel(val, ospi->base + OSPI_IRQ_SIG_EN); 156 } 157 158 static int f_ospi_prepare_config(struct f_ospi *ospi) 159 { 160 u32 val, stat0, stat1; 161 162 /* G4: Disable internal clock */ 163 val = readl(ospi->base + OSPI_CLK_CTL); 164 val &= ~(OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN); 165 writel(val, ospi->base + OSPI_CLK_CTL); 166 167 /* G5: Wait for stop */ 168 stat0 = OSPI_STAT_IS_AXI_WRITING | OSPI_STAT_IS_AXI_READING; 169 stat1 = OSPI_STAT_IS_SPI_IDLE | OSPI_STAT_IS_SPI_INT_CLK_STOP; 170 171 return readl_poll_timeout(ospi->base + OSPI_STAT, 172 val, (val & (stat0 | stat1)) == stat1, 173 0, OSPI_WAIT_MAX_MSEC); 174 } 175 176 static int f_ospi_unprepare_config(struct f_ospi *ospi) 177 { 178 u32 val; 179 180 /* G11: Enable internal clock */ 181 val = readl(ospi->base + OSPI_CLK_CTL); 182 val |= OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN; 183 writel(val, ospi->base + OSPI_CLK_CTL); 184 185 /* G12: Wait for clock to start */ 186 return readl_poll_timeout(ospi->base + OSPI_STAT, 187 val, !(val & OSPI_STAT_IS_SPI_INT_CLK_STOP), 188 0, OSPI_WAIT_MAX_MSEC); 189 } 190 191 static void f_ospi_config_clk(struct f_ospi *ospi, u32 device_hz) 192 { 193 long rate_hz = clk_get_rate(ospi->clk); 194 u32 div = DIV_ROUND_UP(rate_hz, device_hz); 195 u32 div_reg; 196 u32 val; 197 198 if (rate_hz < device_hz) { 199 dev_warn(ospi->dev, "Device frequency too large: %d\n", 200 device_hz); 201 div_reg = OSPI_CLK_CTL_DIV_1; 202 } else { 203 if (div == 1) { 204 div_reg = OSPI_CLK_CTL_DIV_1; 205 } else if (div == 2) { 206 div_reg = OSPI_CLK_CTL_DIV_2; 207 } else if (div <= 4) { 208 div_reg = OSPI_CLK_CTL_DIV_4; 209 } else if (div <= 8) { 210 div_reg = OSPI_CLK_CTL_DIV_8; 211 } else { 212 dev_warn(ospi->dev, "Device frequency too small: %d\n", 213 device_hz); 214 div_reg = OSPI_CLK_CTL_DIV_8; 215 } 216 } 217 218 /* 219 * G7: Set clock mode 220 * clock phase is fixed at 180 degrees and configure edge direction 221 * instead. 222 */ 223 val = readl(ospi->base + OSPI_CLK_CTL); 224 225 FIELD_MODIFY(OSPI_CLK_CTL_PHA, &val, OSPI_CLK_CTL_PHA_180); 226 FIELD_MODIFY(OSPI_CLK_CTL_DIV, &val, div_reg); 227 228 writel(val, ospi->base + OSPI_CLK_CTL); 229 } 230 231 static void f_ospi_config_dll(struct f_ospi *ospi) 232 { 233 /* G8: Configure DLL, nothing */ 234 } 235 236 static u8 f_ospi_get_mode(struct f_ospi *ospi, int width, int data_size) 237 { 238 u8 mode = OSPI_PROT_MODE_SINGLE; 239 240 switch (width) { 241 case 1: 242 mode = OSPI_PROT_MODE_SINGLE; 243 break; 244 case 2: 245 mode = OSPI_PROT_MODE_DUAL; 246 break; 247 case 4: 248 mode = OSPI_PROT_MODE_QUAD; 249 break; 250 case 8: 251 mode = OSPI_PROT_MODE_OCTAL; 252 break; 253 default: 254 if (data_size) 255 dev_err(ospi->dev, "Invalid buswidth: %d\n", width); 256 break; 257 } 258 259 return mode; 260 } 261 262 static void f_ospi_config_indir_protocol(struct f_ospi *ospi, 263 struct spi_mem *mem, 264 const struct spi_mem_op *op) 265 { 266 struct spi_device *spi = mem->spi; 267 u8 mode; 268 u32 prot = 0, val; 269 int unit; 270 271 /* Set one chip select */ 272 writel(BIT(spi_get_chipselect(spi, 0)), ospi->base + OSPI_SSEL); 273 274 mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1); 275 prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode); 276 277 mode = f_ospi_get_mode(ospi, op->addr.buswidth, op->addr.nbytes); 278 prot |= FIELD_PREP(OSPI_PROT_MODE_ADDR_MASK, mode); 279 280 mode = f_ospi_get_mode(ospi, op->data.buswidth, op->data.nbytes); 281 prot |= FIELD_PREP(OSPI_PROT_MODE_DATA_MASK, mode); 282 283 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_DATA, OSPI_PROT_SDR); 284 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ALT, OSPI_PROT_SDR); 285 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ADDR, OSPI_PROT_SDR); 286 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_CODE, OSPI_PROT_SDR); 287 288 if (spi->mode & SPI_LSB_FIRST) 289 prot |= OSPI_PROT_BIT_POS_DATA | OSPI_PROT_BIT_POS_ALT 290 | OSPI_PROT_BIT_POS_ADDR | OSPI_PROT_BIT_POS_CODE; 291 292 if (spi->mode & SPI_CPHA) 293 prot |= OSPI_PROT_SAMP_EDGE; 294 295 /* Examine nbytes % 4 */ 296 switch (op->data.nbytes & 0x3) { 297 case 0: 298 unit = OSPI_PROT_DATA_UNIT_4B; 299 val = 0; 300 break; 301 case 2: 302 unit = OSPI_PROT_DATA_UNIT_2B; 303 val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1); 304 break; 305 default: 306 unit = OSPI_PROT_DATA_UNIT_1B; 307 val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1); 308 break; 309 } 310 prot |= FIELD_PREP(OSPI_PROT_DATA_UNIT_MASK, unit); 311 312 switch (op->data.dir) { 313 case SPI_MEM_DATA_IN: 314 prot |= OSPI_PROT_DATA_EN; 315 break; 316 317 case SPI_MEM_DATA_OUT: 318 prot |= OSPI_PROT_TRANS_DIR_WRITE | OSPI_PROT_DATA_EN; 319 break; 320 321 case SPI_MEM_NO_DATA: 322 prot |= OSPI_PROT_TRANS_DIR_WRITE; 323 break; 324 325 default: 326 dev_warn(ospi->dev, "Unsupported direction"); 327 break; 328 } 329 330 prot |= FIELD_PREP(OSPI_PROT_ADDR_SIZE_MASK, op->addr.nbytes); 331 prot |= FIELD_PREP(OSPI_PROT_CODE_SIZE_MASK, 1); /* 1byte */ 332 333 writel(prot, ospi->base + OSPI_PROT_CTL_INDIR); 334 writel(val, ospi->base + OSPI_DAT_SIZE_INDIR); 335 } 336 337 static int f_ospi_indir_prepare_op(struct f_ospi *ospi, struct spi_mem *mem, 338 const struct spi_mem_op *op) 339 { 340 u32 irq_stat_en; 341 int ret; 342 343 ret = f_ospi_prepare_config(ospi); 344 if (ret) 345 return ret; 346 347 f_ospi_config_clk(ospi, op->max_freq); 348 349 f_ospi_config_indir_protocol(ospi, mem, op); 350 351 writel(f_ospi_get_dummy_cycle(op), ospi->base + OSPI_DMY_INDIR); 352 writel(op->addr.val, ospi->base + OSPI_ADDR); 353 writel(op->cmd.opcode, ospi->base + OSPI_CMD_IDX_INDIR); 354 355 f_ospi_clear_irq(ospi); 356 357 switch (op->data.dir) { 358 case SPI_MEM_DATA_IN: 359 irq_stat_en = OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP; 360 break; 361 362 case SPI_MEM_DATA_OUT: 363 irq_stat_en = OSPI_IRQ_WRITE_BUF_READY | OSPI_IRQ_CS_TRANS_COMP; 364 break; 365 366 case SPI_MEM_NO_DATA: 367 irq_stat_en = OSPI_IRQ_CS_TRANS_COMP; 368 break; 369 370 default: 371 dev_warn(ospi->dev, "Unsupported direction"); 372 irq_stat_en = 0; 373 } 374 375 f_ospi_disable_irq_status(ospi, ~irq_stat_en); 376 f_ospi_enable_irq_status(ospi, irq_stat_en); 377 378 return f_ospi_unprepare_config(ospi); 379 } 380 381 static void f_ospi_indir_start_xfer(struct f_ospi *ospi) 382 { 383 /* Write only 1, auto cleared */ 384 writel(OSPI_TRANS_CTL_START_REQ, ospi->base + OSPI_TRANS_CTL); 385 } 386 387 static void f_ospi_indir_stop_xfer(struct f_ospi *ospi) 388 { 389 /* Write only 1, auto cleared */ 390 writel(OSPI_TRANS_CTL_STOP_REQ, ospi->base + OSPI_TRANS_CTL); 391 } 392 393 static int f_ospi_indir_wait_xfer_complete(struct f_ospi *ospi) 394 { 395 u32 val; 396 397 return readl_poll_timeout(ospi->base + OSPI_IRQ, val, 398 val & OSPI_IRQ_CS_TRANS_COMP, 399 0, OSPI_WAIT_MAX_MSEC); 400 } 401 402 static int f_ospi_indir_read(struct f_ospi *ospi, struct spi_mem *mem, 403 const struct spi_mem_op *op) 404 { 405 u8 *buf = op->data.buf.in; 406 u32 val; 407 int i, ret; 408 409 mutex_lock(&ospi->mlock); 410 411 /* E1-2: Prepare transfer operation */ 412 ret = f_ospi_indir_prepare_op(ospi, mem, op); 413 if (ret) 414 goto out; 415 416 f_ospi_indir_start_xfer(ospi); 417 418 /* E3-4: Wait for ready and read data */ 419 for (i = 0; i < op->data.nbytes; i++) { 420 ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val, 421 val & OSPI_IRQ_READ_BUF_READY, 422 0, OSPI_WAIT_MAX_MSEC); 423 if (ret) 424 goto out; 425 426 buf[i] = readl(ospi->base + OSPI_DAT) & 0xFF; 427 } 428 429 /* E5-6: Stop transfer if data size is nothing */ 430 if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)) 431 f_ospi_indir_stop_xfer(ospi); 432 433 /* E7-8: Wait for completion and clear */ 434 ret = f_ospi_indir_wait_xfer_complete(ospi); 435 if (ret) 436 goto out; 437 438 writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ); 439 440 /* E9: Do nothing if data size is valid */ 441 if (readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN) 442 goto out; 443 444 /* E10-11: Reset and check read fifo */ 445 writel(OSPI_SWRST_INDIR_READ_FIFO, ospi->base + OSPI_SWRST); 446 447 ret = readl_poll_timeout(ospi->base + OSPI_SWRST, val, 448 !(val & OSPI_SWRST_INDIR_READ_FIFO), 449 0, OSPI_WAIT_MAX_MSEC); 450 out: 451 mutex_unlock(&ospi->mlock); 452 453 return ret; 454 } 455 456 static int f_ospi_indir_write(struct f_ospi *ospi, struct spi_mem *mem, 457 const struct spi_mem_op *op) 458 { 459 u8 *buf = (u8 *)op->data.buf.out; 460 u32 val; 461 int i, ret; 462 463 mutex_lock(&ospi->mlock); 464 465 /* F1-3: Prepare transfer operation */ 466 ret = f_ospi_indir_prepare_op(ospi, mem, op); 467 if (ret) 468 goto out; 469 470 f_ospi_indir_start_xfer(ospi); 471 472 if (!(readl(ospi->base + OSPI_PROT_CTL_INDIR) & OSPI_PROT_DATA_EN)) 473 goto nodata; 474 475 /* F4-5: Wait for buffer ready and write data */ 476 for (i = 0; i < op->data.nbytes; i++) { 477 ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val, 478 val & OSPI_IRQ_WRITE_BUF_READY, 479 0, OSPI_WAIT_MAX_MSEC); 480 if (ret) 481 goto out; 482 483 writel(buf[i], ospi->base + OSPI_DAT); 484 } 485 486 /* F6-7: Stop transfer if data size is nothing */ 487 if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)) 488 f_ospi_indir_stop_xfer(ospi); 489 490 nodata: 491 /* F8-9: Wait for completion and clear */ 492 ret = f_ospi_indir_wait_xfer_complete(ospi); 493 if (ret) 494 goto out; 495 496 writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ); 497 out: 498 mutex_unlock(&ospi->mlock); 499 500 return ret; 501 } 502 503 static int f_ospi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 504 { 505 struct f_ospi *ospi = spi_controller_get_devdata(mem->spi->controller); 506 int err = 0; 507 508 switch (op->data.dir) { 509 case SPI_MEM_DATA_IN: 510 err = f_ospi_indir_read(ospi, mem, op); 511 break; 512 513 case SPI_MEM_DATA_OUT: 514 fallthrough; 515 case SPI_MEM_NO_DATA: 516 err = f_ospi_indir_write(ospi, mem, op); 517 break; 518 519 default: 520 dev_warn(ospi->dev, "Unsupported direction"); 521 err = -EOPNOTSUPP; 522 } 523 524 return err; 525 } 526 527 static bool f_ospi_supports_op_width(struct spi_mem *mem, 528 const struct spi_mem_op *op) 529 { 530 static const u8 width_available[] = { 0, 1, 2, 4, 8 }; 531 u8 width_op[] = { op->cmd.buswidth, op->addr.buswidth, 532 op->dummy.buswidth, op->data.buswidth }; 533 bool is_match_found; 534 int i, j; 535 536 for (i = 0; i < ARRAY_SIZE(width_op); i++) { 537 is_match_found = false; 538 539 for (j = 0; j < ARRAY_SIZE(width_available); j++) { 540 if (width_op[i] == width_available[j]) { 541 is_match_found = true; 542 break; 543 } 544 } 545 546 if (!is_match_found) 547 return false; 548 } 549 550 return true; 551 } 552 553 static bool f_ospi_supports_op(struct spi_mem *mem, 554 const struct spi_mem_op *op) 555 { 556 if (f_ospi_get_dummy_cycle(op) > OSPI_DUMMY_CYCLE_MAX) 557 return false; 558 559 if (op->addr.nbytes > 4) 560 return false; 561 562 if (!f_ospi_supports_op_width(mem, op)) 563 return false; 564 565 return spi_mem_default_supports_op(mem, op); 566 } 567 568 static int f_ospi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 569 { 570 op->data.nbytes = min_t(int, op->data.nbytes, OSPI_DAT_SIZE_MAX); 571 572 return 0; 573 } 574 575 static const struct spi_controller_mem_ops f_ospi_mem_ops = { 576 .adjust_op_size = f_ospi_adjust_op_size, 577 .supports_op = f_ospi_supports_op, 578 .exec_op = f_ospi_exec_op, 579 }; 580 581 static const struct spi_controller_mem_caps f_ospi_mem_caps = { 582 .per_op_freq = true, 583 }; 584 585 static int f_ospi_init(struct f_ospi *ospi) 586 { 587 int ret; 588 589 ret = f_ospi_prepare_config(ospi); 590 if (ret) 591 return ret; 592 593 /* Disable boot signal */ 594 writel(OSPI_ACC_MODE_BOOT_DISABLE, ospi->base + OSPI_ACC_MODE); 595 596 f_ospi_config_dll(ospi); 597 598 /* Disable IRQ */ 599 f_ospi_clear_irq(ospi); 600 f_ospi_disable_irq_status(ospi, OSPI_IRQ_ALL); 601 f_ospi_disable_irq_output(ospi, OSPI_IRQ_ALL); 602 603 return f_ospi_unprepare_config(ospi); 604 } 605 606 static int f_ospi_probe(struct platform_device *pdev) 607 { 608 struct spi_controller *ctlr; 609 struct device *dev = &pdev->dev; 610 struct f_ospi *ospi; 611 u32 num_cs = OSPI_NUM_CS; 612 int ret; 613 614 ctlr = devm_spi_alloc_host(dev, sizeof(*ospi)); 615 if (!ctlr) 616 return -ENOMEM; 617 618 ctlr->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL 619 | SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL 620 | SPI_MODE_0 | SPI_MODE_1 | SPI_LSB_FIRST; 621 ctlr->mem_ops = &f_ospi_mem_ops; 622 ctlr->mem_caps = &f_ospi_mem_caps; 623 ctlr->bus_num = -1; 624 of_property_read_u32(dev->of_node, "num-cs", &num_cs); 625 if (num_cs > OSPI_NUM_CS) { 626 dev_err(dev, "num-cs too large: %d\n", num_cs); 627 return -EINVAL; 628 } 629 ctlr->num_chipselect = num_cs; 630 631 ospi = spi_controller_get_devdata(ctlr); 632 ospi->dev = dev; 633 634 platform_set_drvdata(pdev, ospi); 635 636 ospi->base = devm_platform_ioremap_resource(pdev, 0); 637 if (IS_ERR(ospi->base)) 638 return PTR_ERR(ospi->base); 639 640 ospi->clk = devm_clk_get_enabled(dev, NULL); 641 if (IS_ERR(ospi->clk)) 642 return PTR_ERR(ospi->clk); 643 644 ret = devm_mutex_init(dev, &ospi->mlock); 645 if (ret) 646 return ret; 647 648 ret = f_ospi_init(ospi); 649 if (ret) 650 return ret; 651 652 return devm_spi_register_controller(dev, ctlr); 653 } 654 655 static const struct of_device_id f_ospi_dt_ids[] = { 656 { .compatible = "socionext,f-ospi" }, 657 {} 658 }; 659 MODULE_DEVICE_TABLE(of, f_ospi_dt_ids); 660 661 static struct platform_driver f_ospi_driver = { 662 .driver = { 663 .name = "socionext,f-ospi", 664 .of_match_table = f_ospi_dt_ids, 665 }, 666 .probe = f_ospi_probe, 667 }; 668 module_platform_driver(f_ospi_driver); 669 670 MODULE_DESCRIPTION("Socionext F_OSPI controller driver"); 671 MODULE_AUTHOR("Socionext Inc."); 672 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 673 MODULE_LICENSE("GPL"); 674