1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_HW_SEQUENCER_H__ 27 #define __DC_HW_SEQUENCER_H__ 28 #include "dc_types.h" 29 #include "inc/clock_source.h" 30 #include "inc/hw/timing_generator.h" 31 #include "inc/hw/opp.h" 32 #include "inc/hw/link_encoder.h" 33 #include "inc/core_status.h" 34 #include "inc/hw/hw_shared.h" 35 #include "dsc/dsc.h" 36 37 struct pipe_ctx; 38 struct dc_state; 39 struct dc_stream_status; 40 struct dc_writeback_info; 41 struct dchub_init_data; 42 struct dc_static_screen_params; 43 struct resource_pool; 44 struct dc_phy_addr_space_config; 45 struct dc_virtual_addr_space_config; 46 struct dpp; 47 struct dce_hwseq; 48 struct link_resource; 49 struct dc_dmub_cmd; 50 struct pg_block_update; 51 struct drr_params; 52 struct dc_underflow_debug_data; 53 struct dsc_optc_config; 54 struct vm_system_aperture_param; 55 struct memory_qos; 56 struct subvp_pipe_control_lock_fast_params { 57 struct dc *dc; 58 bool lock; 59 bool subvp_immediate_flip; 60 }; 61 62 struct pipe_control_lock_params { 63 struct dc *dc; 64 struct pipe_ctx *pipe_ctx; 65 bool lock; 66 }; 67 68 struct set_flip_control_gsl_params { 69 struct hubp *hubp; 70 bool flip_immediate; 71 }; 72 73 struct program_triplebuffer_params { 74 const struct dc *dc; 75 struct pipe_ctx *pipe_ctx; 76 bool enableTripleBuffer; 77 }; 78 79 struct update_plane_addr_params { 80 struct dc *dc; 81 struct pipe_ctx *pipe_ctx; 82 }; 83 84 struct set_input_transfer_func_params { 85 struct dc *dc; 86 struct pipe_ctx *pipe_ctx; 87 struct dc_plane_state *plane_state; 88 }; 89 90 struct program_gamut_remap_params { 91 struct pipe_ctx *pipe_ctx; 92 }; 93 94 struct program_manual_trigger_params { 95 struct pipe_ctx *pipe_ctx; 96 }; 97 98 struct send_dmcub_cmd_params { 99 struct dc_context *ctx; 100 union dmub_rb_cmd *cmd; 101 enum dm_dmub_wait_type wait_type; 102 }; 103 104 struct setup_dpp_params { 105 struct pipe_ctx *pipe_ctx; 106 }; 107 108 struct program_bias_and_scale_params { 109 struct pipe_ctx *pipe_ctx; 110 }; 111 112 struct set_output_transfer_func_params { 113 struct dc *dc; 114 struct pipe_ctx *pipe_ctx; 115 const struct dc_stream_state *stream; 116 }; 117 118 struct update_visual_confirm_params { 119 struct dc *dc; 120 struct pipe_ctx *pipe_ctx; 121 int mpcc_id; 122 }; 123 124 struct power_on_mpc_mem_pwr_params { 125 struct mpc *mpc; 126 int mpcc_id; 127 bool power_on; 128 }; 129 130 struct set_output_csc_params { 131 struct mpc *mpc; 132 int opp_id; 133 const uint16_t *regval; 134 enum mpc_output_csc_mode ocsc_mode; 135 }; 136 137 struct set_ocsc_default_params { 138 struct mpc *mpc; 139 int opp_id; 140 enum dc_color_space color_space; 141 enum mpc_output_csc_mode ocsc_mode; 142 }; 143 144 struct subvp_save_surf_addr { 145 struct dc_dmub_srv *dc_dmub_srv; 146 const struct dc_plane_address *addr; 147 uint8_t subvp_index; 148 }; 149 150 struct wait_for_dcc_meta_propagation_params { 151 const struct dc *dc; 152 const struct pipe_ctx *top_pipe_to_program; 153 }; 154 155 struct dmub_hw_control_lock_fast_params { 156 struct dc *dc; 157 bool is_required; 158 bool lock; 159 }; 160 161 struct program_surface_config_params { 162 struct hubp *hubp; 163 enum surface_pixel_format format; 164 struct dc_tiling_info *tiling_info; 165 struct plane_size plane_size; 166 enum dc_rotation_angle rotation; 167 struct dc_plane_dcc_param *dcc; 168 bool horizontal_mirror; 169 int compat_level; 170 }; 171 172 struct program_mcache_id_and_split_coordinate { 173 struct hubp *hubp; 174 struct dml2_hubp_pipe_mcache_regs *mcache_regs; 175 }; 176 177 struct program_cursor_update_now_params { 178 struct dc *dc; 179 struct pipe_ctx *pipe_ctx; 180 }; 181 182 struct hubp_wait_pipe_read_start_params { 183 struct hubp *hubp; 184 }; 185 186 struct apply_update_flags_for_phantom_params { 187 struct pipe_ctx *pipe_ctx; 188 }; 189 190 struct update_phantom_vp_position_params { 191 struct dc *dc; 192 struct pipe_ctx *pipe_ctx; 193 struct dc_state *context; 194 }; 195 196 struct set_odm_combine_params { 197 struct timing_generator *tg; 198 int opp_inst[MAX_PIPES]; 199 int opp_head_count; 200 int odm_slice_width; 201 int last_odm_slice_width; 202 }; 203 204 struct set_odm_bypass_params { 205 struct timing_generator *tg; 206 const struct dc_crtc_timing *timing; 207 }; 208 209 struct opp_pipe_clock_control_params { 210 struct output_pixel_processor *opp; 211 bool enable; 212 }; 213 214 struct opp_program_left_edge_extra_pixel_params { 215 struct output_pixel_processor *opp; 216 enum dc_pixel_encoding pixel_encoding; 217 bool is_otg_master; 218 }; 219 220 struct dccg_set_dto_dscclk_params { 221 struct dccg *dccg; 222 int inst; 223 int num_slices_h; 224 }; 225 226 struct dsc_set_config_params { 227 struct display_stream_compressor *dsc; 228 struct dsc_config *dsc_cfg; 229 struct dsc_optc_config *dsc_optc_cfg; 230 }; 231 232 struct dsc_enable_params { 233 struct display_stream_compressor *dsc; 234 int opp_inst; 235 }; 236 237 struct tg_set_dsc_config_params { 238 struct timing_generator *tg; 239 struct dsc_optc_config *dsc_optc_cfg; 240 bool enable; 241 }; 242 243 struct dsc_disconnect_params { 244 struct display_stream_compressor *dsc; 245 }; 246 247 struct dsc_read_state_params { 248 struct display_stream_compressor *dsc; 249 struct dcn_dsc_state *dsc_state; 250 }; 251 252 struct dsc_calculate_and_set_config_params { 253 struct pipe_ctx *pipe_ctx; 254 struct dsc_optc_config dsc_optc_cfg; 255 bool enable; 256 int opp_cnt; 257 }; 258 259 struct dsc_enable_with_opp_params { 260 struct pipe_ctx *pipe_ctx; 261 }; 262 263 struct program_tg_params { 264 struct dc *dc; 265 struct pipe_ctx *pipe_ctx; 266 struct dc_state *context; 267 }; 268 269 struct tg_program_global_sync_params { 270 struct timing_generator *tg; 271 int vready_offset; 272 unsigned int vstartup_lines; 273 unsigned int vupdate_offset_pixels; 274 unsigned int vupdate_vupdate_width_pixels; 275 unsigned int pstate_keepout_start_lines; 276 }; 277 278 struct tg_wait_for_state_params { 279 struct timing_generator *tg; 280 enum crtc_state state; 281 }; 282 283 struct tg_set_vtg_params_params { 284 struct timing_generator *tg; 285 struct dc_crtc_timing *timing; 286 bool program_fp2; 287 }; 288 289 struct tg_set_gsl_params { 290 struct timing_generator *tg; 291 struct gsl_params gsl; 292 }; 293 294 struct tg_set_gsl_source_select_params { 295 struct timing_generator *tg; 296 int group_idx; 297 uint32_t gsl_ready_signal; 298 }; 299 300 struct setup_vupdate_interrupt_params { 301 struct dc *dc; 302 struct pipe_ctx *pipe_ctx; 303 }; 304 305 struct tg_setup_vertical_interrupt2_params { 306 struct timing_generator *tg; 307 int start_line; 308 }; 309 310 struct dpp_set_hdr_multiplier_params { 311 struct dpp *dpp; 312 uint32_t hw_mult; 313 }; 314 315 struct program_det_size_params { 316 struct hubbub *hubbub; 317 unsigned int hubp_inst; 318 unsigned int det_buffer_size_kb; 319 }; 320 321 struct program_det_segments_params { 322 struct hubbub *hubbub; 323 unsigned int hubp_inst; 324 unsigned int det_size; 325 }; 326 327 struct update_dchubp_dpp_params { 328 struct dc *dc; 329 struct pipe_ctx *pipe_ctx; 330 struct dc_state *context; 331 }; 332 333 struct opp_set_dyn_expansion_params { 334 struct output_pixel_processor *opp; 335 enum dc_color_space color_space; 336 enum dc_color_depth color_depth; 337 enum signal_type signal; 338 }; 339 340 struct opp_program_fmt_params { 341 struct output_pixel_processor *opp; 342 struct bit_depth_reduction_params *fmt_bit_depth; 343 struct clamping_and_pixel_encoding_params *clamping; 344 }; 345 346 struct opp_program_bit_depth_reduction_params { 347 struct output_pixel_processor *opp; 348 bool use_default_params; 349 struct pipe_ctx *pipe_ctx; 350 }; 351 352 struct opp_set_disp_pattern_generator_params { 353 struct output_pixel_processor *opp; 354 enum controller_dp_test_pattern test_pattern; 355 enum controller_dp_color_space color_space; 356 enum dc_color_depth color_depth; 357 struct tg_color solid_color; 358 bool use_solid_color; 359 int width; 360 int height; 361 int offset; 362 }; 363 364 struct set_abm_pipe_params { 365 struct dc *dc; 366 struct pipe_ctx *pipe_ctx; 367 }; 368 369 struct set_abm_level_params { 370 struct abm *abm; 371 unsigned int abm_level; 372 }; 373 374 struct set_abm_immediate_disable_params { 375 struct dc *dc; 376 struct pipe_ctx *pipe_ctx; 377 }; 378 379 struct set_disp_pattern_generator_params { 380 struct dc *dc; 381 struct pipe_ctx *pipe_ctx; 382 enum controller_dp_test_pattern test_pattern; 383 enum controller_dp_color_space color_space; 384 enum dc_color_depth color_depth; 385 const struct tg_color *solid_color; 386 int width; 387 int height; 388 int offset; 389 }; 390 391 struct mpc_update_blending_params { 392 struct mpc *mpc; 393 struct mpcc_blnd_cfg blnd_cfg; 394 int mpcc_id; 395 }; 396 397 struct mpc_assert_idle_mpcc_params { 398 struct mpc *mpc; 399 int mpcc_id; 400 }; 401 402 struct mpc_insert_plane_params { 403 struct mpc *mpc; 404 struct mpc_tree *mpc_tree_params; 405 struct mpcc_blnd_cfg blnd_cfg; 406 struct mpcc_sm_cfg *sm_cfg; 407 struct mpcc *insert_above_mpcc; 408 int dpp_id; 409 int mpcc_id; 410 }; 411 412 struct mpc_remove_mpcc_params { 413 struct mpc *mpc; 414 struct mpc_tree *mpc_tree_params; 415 struct mpcc *mpcc_to_remove; 416 }; 417 418 struct opp_set_mpcc_disconnect_pending_params { 419 struct output_pixel_processor *opp; 420 int mpcc_inst; 421 bool pending; 422 }; 423 424 struct dc_set_optimized_required_params { 425 struct dc *dc; 426 bool optimized_required; 427 }; 428 429 struct hubp_disconnect_params { 430 struct hubp *hubp; 431 }; 432 433 struct hubbub_force_pstate_change_control_params { 434 struct hubbub *hubbub; 435 bool enable; 436 bool wait; 437 }; 438 439 struct tg_enable_crtc_params { 440 struct timing_generator *tg; 441 }; 442 443 struct hubp_wait_flip_pending_params { 444 struct hubp *hubp; 445 unsigned int timeout_us; 446 unsigned int polling_interval_us; 447 }; 448 449 struct tg_wait_double_buffer_pending_params { 450 struct timing_generator *tg; 451 unsigned int timeout_us; 452 unsigned int polling_interval_us; 453 }; 454 455 struct update_force_pstate_params { 456 struct dc *dc; 457 struct dc_state *context; 458 }; 459 460 struct hubbub_apply_dedcn21_147_wa_params { 461 struct hubbub *hubbub; 462 }; 463 464 struct hubbub_allow_self_refresh_control_params { 465 struct hubbub *hubbub; 466 bool allow; 467 bool *disallow_self_refresh_applied; 468 }; 469 470 struct tg_get_frame_count_params { 471 struct timing_generator *tg; 472 unsigned int *frame_count; 473 }; 474 475 struct mpc_set_dwb_mux_params { 476 struct mpc *mpc; 477 int dwb_id; 478 int mpcc_id; 479 }; 480 481 struct mpc_disable_dwb_mux_params { 482 struct mpc *mpc; 483 unsigned int dwb_id; 484 }; 485 486 struct mcif_wb_config_buf_params { 487 struct mcif_wb *mcif_wb; 488 struct mcif_buf_params *mcif_buf_params; 489 unsigned int dest_height; 490 }; 491 492 struct mcif_wb_config_arb_params { 493 struct mcif_wb *mcif_wb; 494 struct mcif_arb_params *mcif_arb_params; 495 }; 496 497 struct mcif_wb_enable_params { 498 struct mcif_wb *mcif_wb; 499 }; 500 501 struct mcif_wb_disable_params { 502 struct mcif_wb *mcif_wb; 503 }; 504 505 struct dwbc_enable_params { 506 struct dwbc *dwb; 507 struct dc_dwb_params *dwb_params; 508 }; 509 510 struct dwbc_disable_params { 511 struct dwbc *dwb; 512 }; 513 514 struct dwbc_update_params { 515 struct dwbc *dwb; 516 struct dc_dwb_params *dwb_params; 517 }; 518 519 struct hubp_update_mall_sel_params { 520 struct hubp *hubp; 521 uint32_t mall_sel; 522 bool cache_cursor; 523 }; 524 525 struct hubp_prepare_subvp_buffering_params { 526 struct hubp *hubp; 527 bool enable; 528 }; 529 530 struct hubp_set_blank_en_params { 531 struct hubp *hubp; 532 bool enable; 533 }; 534 535 struct hubp_disable_control_params { 536 struct hubp *hubp; 537 bool disable; 538 }; 539 540 struct hubbub_soft_reset_params { 541 struct hubbub *hubbub; 542 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset); 543 bool reset; 544 }; 545 546 struct hubp_clk_cntl_params { 547 struct hubp *hubp; 548 bool enable; 549 }; 550 551 struct hubp_init_params { 552 struct hubp *hubp; 553 }; 554 555 struct hubp_set_vm_system_aperture_settings_params { 556 struct hubp *hubp; 557 //struct vm_system_aperture_param apt; 558 PHYSICAL_ADDRESS_LOC sys_default; 559 PHYSICAL_ADDRESS_LOC sys_low; 560 PHYSICAL_ADDRESS_LOC sys_high; 561 }; 562 563 struct hubp_set_flip_int_params { 564 struct hubp *hubp; 565 }; 566 567 struct dpp_dppclk_control_params { 568 struct dpp *dpp; 569 bool dppclk_div; 570 bool enable; 571 }; 572 573 struct disable_phantom_crtc_params { 574 struct timing_generator *tg; 575 }; 576 577 struct dpp_pg_control_params { 578 struct dce_hwseq *hws; 579 unsigned int dpp_inst; 580 bool power_on; 581 }; 582 583 struct hubp_pg_control_params { 584 struct dce_hwseq *hws; 585 unsigned int hubp_inst; 586 bool power_on; 587 }; 588 589 struct hubp_reset_params { 590 struct hubp *hubp; 591 }; 592 593 struct dpp_reset_params { 594 struct dpp *dpp; 595 }; 596 597 struct dpp_root_clock_control_params { 598 struct dce_hwseq *hws; 599 unsigned int dpp_inst; 600 bool clock_on; 601 }; 602 603 struct dc_ip_request_cntl_params { 604 struct dc *dc; 605 bool enable; 606 }; 607 608 struct dsc_pg_status_params { 609 struct dce_hwseq *hws; 610 int dsc_inst; 611 bool is_ungated; 612 }; 613 614 struct dsc_wait_disconnect_pending_clear_params { 615 struct display_stream_compressor *dsc; 616 bool *is_ungated; 617 }; 618 619 struct dsc_disable_params { 620 struct display_stream_compressor *dsc; 621 bool *is_ungated; 622 }; 623 624 struct dccg_set_ref_dscclk_params { 625 struct dccg *dccg; 626 int dsc_inst; 627 bool *is_ungated; 628 }; 629 630 struct dccg_update_dpp_dto_params { 631 struct dccg *dccg; 632 int dpp_inst; 633 int dppclk_khz; 634 }; 635 636 struct hubp_vtg_sel_params { 637 struct hubp *hubp; 638 uint32_t otg_inst; 639 }; 640 641 struct hubp_setup2_params { 642 struct hubp *hubp; 643 struct dml2_dchub_per_pipe_register_set *hubp_regs; 644 union dml2_global_sync_programming *global_sync; 645 struct dc_crtc_timing *timing; 646 }; 647 648 struct hubp_setup_params { 649 struct hubp *hubp; 650 struct _vcs_dpi_display_dlg_regs_st *dlg_regs; 651 struct _vcs_dpi_display_ttu_regs_st *ttu_regs; 652 struct _vcs_dpi_display_rq_regs_st *rq_regs; 653 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest; 654 }; 655 656 struct hubp_set_unbounded_requesting_params { 657 struct hubp *hubp; 658 bool unbounded_req; 659 }; 660 661 struct hubp_setup_interdependent2_params { 662 struct hubp *hubp; 663 struct dml2_dchub_per_pipe_register_set *hubp_regs; 664 }; 665 666 struct hubp_setup_interdependent_params { 667 struct hubp *hubp; 668 struct _vcs_dpi_display_dlg_regs_st *dlg_regs; 669 struct _vcs_dpi_display_ttu_regs_st *ttu_regs; 670 }; 671 672 struct dpp_set_cursor_matrix_params { 673 struct dpp *dpp; 674 enum dc_color_space color_space; 675 struct dc_csc_transform *cursor_csc_color_matrix; 676 }; 677 678 struct mpc_update_mpcc_params { 679 struct dc *dc; 680 struct pipe_ctx *pipe_ctx; 681 }; 682 683 struct dpp_set_scaler_params { 684 struct dpp *dpp; 685 const struct scaler_data *scl_data; 686 }; 687 688 struct hubp_mem_program_viewport_params { 689 struct hubp *hubp; 690 const struct rect *viewport; 691 const struct rect *viewport_c; 692 }; 693 694 struct hubp_program_mcache_id_and_split_coordinate_params { 695 struct hubp *hubp; 696 struct mcache_regs_struct *mcache_regs; 697 }; 698 699 struct abort_cursor_offload_update_params { 700 struct dc *dc; 701 struct pipe_ctx *pipe_ctx; 702 }; 703 704 struct set_cursor_attribute_params { 705 struct dc *dc; 706 struct pipe_ctx *pipe_ctx; 707 }; 708 709 struct set_cursor_position_params { 710 struct dc *dc; 711 struct pipe_ctx *pipe_ctx; 712 }; 713 714 struct set_cursor_sdr_white_level_params { 715 struct dc *dc; 716 struct pipe_ctx *pipe_ctx; 717 }; 718 719 struct program_output_csc_params { 720 struct dc *dc; 721 struct pipe_ctx *pipe_ctx; 722 enum dc_color_space colorspace; 723 uint16_t *matrix; 724 int opp_id; 725 }; 726 727 struct hubp_set_blank_params { 728 struct hubp *hubp; 729 bool blank; 730 }; 731 732 struct phantom_hubp_post_enable_params { 733 struct hubp *hubp; 734 }; 735 736 union block_sequence_params { 737 struct update_plane_addr_params update_plane_addr_params; 738 struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; 739 struct pipe_control_lock_params pipe_control_lock_params; 740 struct set_flip_control_gsl_params set_flip_control_gsl_params; 741 struct program_triplebuffer_params program_triplebuffer_params; 742 struct set_input_transfer_func_params set_input_transfer_func_params; 743 struct program_gamut_remap_params program_gamut_remap_params; 744 struct program_manual_trigger_params program_manual_trigger_params; 745 struct send_dmcub_cmd_params send_dmcub_cmd_params; 746 struct setup_dpp_params setup_dpp_params; 747 struct program_bias_and_scale_params program_bias_and_scale_params; 748 struct set_output_transfer_func_params set_output_transfer_func_params; 749 struct update_visual_confirm_params update_visual_confirm_params; 750 struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; 751 struct set_output_csc_params set_output_csc_params; 752 struct set_ocsc_default_params set_ocsc_default_params; 753 struct subvp_save_surf_addr subvp_save_surf_addr; 754 struct wait_for_dcc_meta_propagation_params wait_for_dcc_meta_propagation_params; 755 struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; 756 struct program_surface_config_params program_surface_config_params; 757 struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate; 758 struct program_cursor_update_now_params program_cursor_update_now_params; 759 struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params; 760 struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params; 761 struct update_phantom_vp_position_params update_phantom_vp_position_params; 762 struct set_odm_combine_params set_odm_combine_params; 763 struct set_odm_bypass_params set_odm_bypass_params; 764 struct opp_pipe_clock_control_params opp_pipe_clock_control_params; 765 struct opp_program_left_edge_extra_pixel_params opp_program_left_edge_extra_pixel_params; 766 struct dccg_set_dto_dscclk_params dccg_set_dto_dscclk_params; 767 struct dsc_set_config_params dsc_set_config_params; 768 struct dsc_enable_params dsc_enable_params; 769 struct tg_set_dsc_config_params tg_set_dsc_config_params; 770 struct dsc_disconnect_params dsc_disconnect_params; 771 struct dsc_read_state_params dsc_read_state_params; 772 struct dsc_calculate_and_set_config_params dsc_calculate_and_set_config_params; 773 struct dsc_enable_with_opp_params dsc_enable_with_opp_params; 774 struct program_tg_params program_tg_params; 775 struct tg_program_global_sync_params tg_program_global_sync_params; 776 struct tg_wait_for_state_params tg_wait_for_state_params; 777 struct tg_set_vtg_params_params tg_set_vtg_params_params; 778 struct tg_setup_vertical_interrupt2_params tg_setup_vertical_interrupt2_params; 779 struct dpp_set_hdr_multiplier_params dpp_set_hdr_multiplier_params; 780 struct tg_set_gsl_params tg_set_gsl_params; 781 struct tg_set_gsl_source_select_params tg_set_gsl_source_select_params; 782 struct setup_vupdate_interrupt_params setup_vupdate_interrupt_params; 783 struct program_det_size_params program_det_size_params; 784 struct program_det_segments_params program_det_segments_params; 785 struct update_dchubp_dpp_params update_dchubp_dpp_params; 786 struct opp_set_dyn_expansion_params opp_set_dyn_expansion_params; 787 struct opp_program_fmt_params opp_program_fmt_params; 788 struct opp_program_bit_depth_reduction_params opp_program_bit_depth_reduction_params; 789 struct opp_set_disp_pattern_generator_params opp_set_disp_pattern_generator_params; 790 struct set_abm_pipe_params set_abm_pipe_params; 791 struct set_abm_level_params set_abm_level_params; 792 struct set_abm_immediate_disable_params set_abm_immediate_disable_params; 793 struct set_disp_pattern_generator_params set_disp_pattern_generator_params; 794 struct mpc_remove_mpcc_params mpc_remove_mpcc_params; 795 struct opp_set_mpcc_disconnect_pending_params opp_set_mpcc_disconnect_pending_params; 796 struct dc_set_optimized_required_params dc_set_optimized_required_params; 797 struct hubp_disconnect_params hubp_disconnect_params; 798 struct hubbub_force_pstate_change_control_params hubbub_force_pstate_change_control_params; 799 struct tg_enable_crtc_params tg_enable_crtc_params; 800 struct hubp_wait_flip_pending_params hubp_wait_flip_pending_params; 801 struct tg_wait_double_buffer_pending_params tg_wait_double_buffer_pending_params; 802 struct update_force_pstate_params update_force_pstate_params; 803 struct hubbub_apply_dedcn21_147_wa_params hubbub_apply_dedcn21_147_wa_params; 804 struct hubbub_allow_self_refresh_control_params hubbub_allow_self_refresh_control_params; 805 struct tg_get_frame_count_params tg_get_frame_count_params; 806 struct mpc_set_dwb_mux_params mpc_set_dwb_mux_params; 807 struct mpc_disable_dwb_mux_params mpc_disable_dwb_mux_params; 808 struct mcif_wb_config_buf_params mcif_wb_config_buf_params; 809 struct mcif_wb_config_arb_params mcif_wb_config_arb_params; 810 struct mcif_wb_enable_params mcif_wb_enable_params; 811 struct mcif_wb_disable_params mcif_wb_disable_params; 812 struct dwbc_enable_params dwbc_enable_params; 813 struct dwbc_disable_params dwbc_disable_params; 814 struct dwbc_update_params dwbc_update_params; 815 struct hubp_update_mall_sel_params hubp_update_mall_sel_params; 816 struct hubp_prepare_subvp_buffering_params hubp_prepare_subvp_buffering_params; 817 struct hubp_set_blank_en_params hubp_set_blank_en_params; 818 struct hubp_disable_control_params hubp_disable_control_params; 819 struct hubbub_soft_reset_params hubbub_soft_reset_params; 820 struct hubp_clk_cntl_params hubp_clk_cntl_params; 821 struct hubp_init_params hubp_init_params; 822 struct hubp_set_vm_system_aperture_settings_params hubp_set_vm_system_aperture_settings_params; 823 struct hubp_set_flip_int_params hubp_set_flip_int_params; 824 struct dpp_dppclk_control_params dpp_dppclk_control_params; 825 struct disable_phantom_crtc_params disable_phantom_crtc_params; 826 struct dpp_pg_control_params dpp_pg_control_params; 827 struct hubp_pg_control_params hubp_pg_control_params; 828 struct hubp_reset_params hubp_reset_params; 829 struct dpp_reset_params dpp_reset_params; 830 struct dpp_root_clock_control_params dpp_root_clock_control_params; 831 struct dc_ip_request_cntl_params dc_ip_request_cntl_params; 832 struct dsc_pg_status_params dsc_pg_status_params; 833 struct dsc_wait_disconnect_pending_clear_params dsc_wait_disconnect_pending_clear_params; 834 struct dsc_disable_params dsc_disable_params; 835 struct dccg_set_ref_dscclk_params dccg_set_ref_dscclk_params; 836 struct dccg_update_dpp_dto_params dccg_update_dpp_dto_params; 837 struct hubp_vtg_sel_params hubp_vtg_sel_params; 838 struct hubp_setup2_params hubp_setup2_params; 839 struct hubp_setup_params hubp_setup_params; 840 struct hubp_set_unbounded_requesting_params hubp_set_unbounded_requesting_params; 841 struct hubp_setup_interdependent2_params hubp_setup_interdependent2_params; 842 struct hubp_setup_interdependent_params hubp_setup_interdependent_params; 843 struct dpp_set_cursor_matrix_params dpp_set_cursor_matrix_params; 844 struct mpc_update_mpcc_params mpc_update_mpcc_params; 845 struct mpc_update_blending_params mpc_update_blending_params; 846 struct mpc_assert_idle_mpcc_params mpc_assert_idle_mpcc_params; 847 struct mpc_insert_plane_params mpc_insert_plane_params; 848 struct dpp_set_scaler_params dpp_set_scaler_params; 849 struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params; 850 struct abort_cursor_offload_update_params abort_cursor_offload_update_params; 851 struct set_cursor_attribute_params set_cursor_attribute_params; 852 struct set_cursor_position_params set_cursor_position_params; 853 struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params; 854 struct program_output_csc_params program_output_csc_params; 855 struct hubp_set_blank_params hubp_set_blank_params; 856 struct phantom_hubp_post_enable_params phantom_hubp_post_enable_params; 857 }; 858 859 enum block_sequence_func { 860 DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, 861 OPTC_PIPE_CONTROL_LOCK, 862 HUBP_SET_FLIP_CONTROL_GSL, 863 HUBP_PROGRAM_TRIPLEBUFFER, 864 HUBP_UPDATE_PLANE_ADDR, 865 DPP_SET_INPUT_TRANSFER_FUNC, 866 DPP_PROGRAM_GAMUT_REMAP, 867 OPTC_PROGRAM_MANUAL_TRIGGER, 868 DMUB_SEND_DMCUB_CMD, 869 DPP_SETUP_DPP, 870 DPP_PROGRAM_BIAS_AND_SCALE, 871 DPP_SET_OUTPUT_TRANSFER_FUNC, 872 DPP_SET_HDR_MULTIPLIER, 873 MPC_UPDATE_VISUAL_CONFIRM, 874 MPC_POWER_ON_MPC_MEM_PWR, 875 MPC_SET_OUTPUT_CSC, 876 MPC_SET_OCSC_DEFAULT, 877 DMUB_SUBVP_SAVE_SURF_ADDR, 878 HUBP_WAIT_FOR_DCC_META_PROP, 879 DMUB_HW_CONTROL_LOCK_FAST, 880 HUBP_PROGRAM_SURFACE_CONFIG, 881 HUBP_PROGRAM_MCACHE_ID, 882 PROGRAM_CURSOR_UPDATE_NOW, 883 HUBP_WAIT_PIPE_READ_START, 884 HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM, 885 HWS_UPDATE_PHANTOM_VP_POSITION, 886 OPTC_SET_ODM_COMBINE, 887 OPTC_SET_ODM_BYPASS, 888 OPP_PIPE_CLOCK_CONTROL, 889 OPP_PROGRAM_LEFT_EDGE_EXTRA_PIXEL, 890 DCCG_SET_DTO_DSCCLK, 891 DSC_SET_CONFIG, 892 DSC_ENABLE, 893 TG_SET_DSC_CONFIG, 894 DSC_DISCONNECT, 895 DSC_READ_STATE, 896 DSC_CALCULATE_AND_SET_CONFIG, 897 DSC_ENABLE_WITH_OPP, 898 TG_PROGRAM_GLOBAL_SYNC, 899 TG_WAIT_FOR_STATE, 900 TG_SET_VTG_PARAMS, 901 TG_SETUP_VERTICAL_INTERRUPT2, 902 HUBP_PROGRAM_DET_SIZE, 903 HUBP_PROGRAM_DET_SEGMENTS, 904 OPP_SET_DYN_EXPANSION, 905 OPP_PROGRAM_FMT, 906 OPP_PROGRAM_BIT_DEPTH_REDUCTION, 907 OPP_SET_DISP_PATTERN_GENERATOR, 908 ABM_SET_PIPE, 909 ABM_SET_LEVEL, 910 ABM_SET_IMMEDIATE_DISABLE, 911 MPC_REMOVE_MPCC, 912 OPP_SET_MPCC_DISCONNECT_PENDING, 913 DC_SET_OPTIMIZED_REQUIRED, 914 HUBP_DISCONNECT, 915 HUBBUB_FORCE_PSTATE_CHANGE_CONTROL, 916 TG_ENABLE_CRTC, 917 TG_SET_GSL, 918 TG_SET_GSL_SOURCE_SELECT, 919 HUBP_WAIT_FLIP_PENDING, 920 TG_WAIT_DOUBLE_BUFFER_PENDING, 921 UPDATE_FORCE_PSTATE, 922 PROGRAM_MALL_PIPE_CONFIG, 923 HUBBUB_APPLY_DEDCN21_147_WA, 924 HUBBUB_ALLOW_SELF_REFRESH_CONTROL, 925 TG_GET_FRAME_COUNT, 926 MPC_SET_DWB_MUX, 927 MPC_DISABLE_DWB_MUX, 928 MCIF_WB_CONFIG_BUF, 929 MCIF_WB_CONFIG_ARB, 930 MCIF_WB_ENABLE, 931 MCIF_WB_DISABLE, 932 DWBC_ENABLE, 933 DWBC_DISABLE, 934 DWBC_UPDATE, 935 HUBP_UPDATE_MALL_SEL, 936 HUBP_PREPARE_SUBVP_BUFFERING, 937 HUBP_SET_BLANK_EN, 938 HUBP_DISABLE_CONTROL, 939 HUBBUB_SOFT_RESET, 940 HUBP_CLK_CNTL, 941 HUBP_INIT, 942 HUBP_SET_VM_SYSTEM_APERTURE_SETTINGS, 943 HUBP_SET_FLIP_INT, 944 DPP_DPPCLK_CONTROL, 945 DISABLE_PHANTOM_CRTC, 946 DSC_PG_STATUS, 947 DSC_WAIT_DISCONNECT_PENDING_CLEAR, 948 DSC_DISABLE, 949 DCCG_SET_REF_DSCCLK, 950 DPP_PG_CONTROL, 951 HUBP_PG_CONTROL, 952 HUBP_RESET, 953 DPP_RESET, 954 DPP_ROOT_CLOCK_CONTROL, 955 DC_IP_REQUEST_CNTL, 956 DCCG_UPDATE_DPP_DTO, 957 HUBP_VTG_SEL, 958 HUBP_SETUP2, 959 HUBP_SETUP, 960 HUBP_SET_UNBOUNDED_REQUESTING, 961 HUBP_SETUP_INTERDEPENDENT2, 962 HUBP_SETUP_INTERDEPENDENT, 963 DPP_SET_CURSOR_MATRIX, 964 MPC_UPDATE_BLENDING, 965 MPC_ASSERT_IDLE_MPCC, 966 MPC_INSERT_PLANE, 967 DPP_SET_SCALER, 968 HUBP_MEM_PROGRAM_VIEWPORT, 969 ABORT_CURSOR_OFFLOAD_UPDATE, 970 SET_CURSOR_ATTRIBUTE, 971 SET_CURSOR_POSITION, 972 SET_CURSOR_SDR_WHITE_LEVEL, 973 PROGRAM_OUTPUT_CSC, 974 HUBP_SET_LEGACY_TILING_COMPAT_LEVEL, 975 HUBP_SET_BLANK, 976 PHANTOM_HUBP_POST_ENABLE, 977 /* This must be the last value in this enum, add new ones above */ 978 HWSS_BLOCK_SEQUENCE_FUNC_COUNT 979 }; 980 981 struct block_sequence { 982 union block_sequence_params params; 983 enum block_sequence_func func; 984 }; 985 986 struct block_sequence_state { 987 struct block_sequence *steps; 988 unsigned int *num_steps; 989 }; 990 991 #define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES) 992 993 struct hw_sequencer_funcs { 994 void (*hardware_release)(struct dc *dc); 995 /* Embedded Display Related */ 996 void (*edp_power_control)(struct dc_link *link, bool enable); 997 void (*edp_wait_for_hpd_ready)(struct dc_link *link, bool power_up); 998 void (*edp_wait_for_T12)(struct dc_link *link); 999 1000 /* Pipe Programming Related */ 1001 void (*init_hw)(struct dc *dc); 1002 void (*power_down_on_boot)(struct dc *dc); 1003 void (*enable_accelerated_mode)(struct dc *dc, 1004 struct dc_state *context); 1005 enum dc_status (*apply_ctx_to_hw)(struct dc *dc, 1006 struct dc_state *context); 1007 void (*disable_plane)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx); 1008 void (*disable_plane_sequence)(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx, 1009 struct block_sequence_state *seq_state); 1010 void (*disable_pixel_data)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank); 1011 void (*apply_ctx_for_surface)(struct dc *dc, 1012 const struct dc_stream_state *stream, 1013 int num_planes, struct dc_state *context); 1014 void (*program_front_end_for_ctx)(struct dc *dc, 1015 struct dc_state *context); 1016 void (*wait_for_pending_cleared)(struct dc *dc, 1017 struct dc_state *context); 1018 void (*post_unlock_program_front_end)(struct dc *dc, 1019 struct dc_state *context); 1020 void (*update_plane_addr)(const struct dc *dc, 1021 struct pipe_ctx *pipe_ctx); 1022 void (*update_dchub)(struct dce_hwseq *hws, 1023 struct dchub_init_data *dh_data); 1024 void (*wait_for_mpcc_disconnect)(struct dc *dc, 1025 struct resource_pool *res_pool, 1026 struct pipe_ctx *pipe_ctx); 1027 void (*wait_for_mpcc_disconnect_sequence)(struct dc *dc, 1028 struct resource_pool *res_pool, 1029 struct pipe_ctx *pipe_ctx, 1030 struct block_sequence_state *seq_state); 1031 void (*edp_backlight_control)( 1032 struct dc_link *link, 1033 bool enable); 1034 void (*program_triplebuffer)(const struct dc *dc, 1035 struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 1036 void (*update_pending_status)(struct pipe_ctx *pipe_ctx); 1037 void (*update_dsc_pg)(struct dc *dc, struct dc_state *context, bool safe_to_disable); 1038 void (*clear_surface_dcc_and_tiling)(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); 1039 1040 /* Pipe Lock Related */ 1041 void (*pipe_control_lock)(struct dc *dc, 1042 struct pipe_ctx *pipe, bool lock); 1043 void (*interdependent_update_lock)(struct dc *dc, 1044 struct dc_state *context, bool lock); 1045 void (*set_flip_control_gsl)(struct pipe_ctx *pipe_ctx, 1046 bool flip_immediate); 1047 void (*cursor_lock)(struct dc *dc, struct pipe_ctx *pipe, bool lock); 1048 1049 /* Timing Related */ 1050 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes, 1051 struct crtc_position *position); 1052 int (*get_vupdate_offset_from_vsync)(struct pipe_ctx *pipe_ctx); 1053 void (*calc_vupdate_position)( 1054 struct dc *dc, 1055 struct pipe_ctx *pipe_ctx, 1056 uint32_t *start_line, 1057 uint32_t *end_line); 1058 void (*enable_per_frame_crtc_position_reset)(struct dc *dc, 1059 int group_size, struct pipe_ctx *grouped_pipes[]); 1060 void (*enable_timing_synchronization)(struct dc *dc, 1061 struct dc_state *state, 1062 int group_index, int group_size, 1063 struct pipe_ctx *grouped_pipes[]); 1064 void (*enable_vblanks_synchronization)(struct dc *dc, 1065 int group_index, int group_size, 1066 struct pipe_ctx *grouped_pipes[]); 1067 void (*setup_periodic_interrupt)(struct dc *dc, 1068 struct pipe_ctx *pipe_ctx); 1069 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, 1070 struct dc_crtc_timing_adjust adjust); 1071 void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, 1072 int num_pipes, 1073 const struct dc_static_screen_params *events); 1074 1075 /* Stream Related */ 1076 void (*enable_stream)(struct pipe_ctx *pipe_ctx); 1077 void (*disable_stream)(struct pipe_ctx *pipe_ctx); 1078 void (*blank_stream)(struct pipe_ctx *pipe_ctx); 1079 void (*unblank_stream)(struct pipe_ctx *pipe_ctx, 1080 struct dc_link_settings *link_settings); 1081 1082 /* Bandwidth Related */ 1083 void (*prepare_bandwidth)(struct dc *dc, struct dc_state *context); 1084 bool (*update_bandwidth)(struct dc *dc, struct dc_state *context); 1085 void (*optimize_bandwidth)(struct dc *dc, struct dc_state *context); 1086 1087 /* Infopacket Related */ 1088 void (*set_avmute)(struct pipe_ctx *pipe_ctx, bool enable); 1089 void (*send_immediate_sdp_message)( 1090 struct pipe_ctx *pipe_ctx, 1091 const uint8_t *custom_sdp_message, 1092 unsigned int sdp_message_size); 1093 void (*update_info_frame)(struct pipe_ctx *pipe_ctx); 1094 void (*set_dmdata_attributes)(struct pipe_ctx *pipe); 1095 void (*program_dmdata_engine)(struct pipe_ctx *pipe_ctx); 1096 bool (*dmdata_status_done)(struct pipe_ctx *pipe_ctx); 1097 1098 /* Cursor Related */ 1099 void (*set_cursor_position)(struct pipe_ctx *pipe); 1100 void (*set_cursor_attribute)(struct pipe_ctx *pipe); 1101 void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe); 1102 void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1103 void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1104 void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe); 1105 void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe); 1106 void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context, 1107 const struct dc_stream_state *stream); 1108 void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe); 1109 1110 /* Colour Related */ 1111 void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); 1112 void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, 1113 enum dc_color_space colorspace, 1114 uint16_t *matrix, int opp_id); 1115 void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); 1116 1117 /* VM Related */ 1118 int (*init_sys_ctx)(struct dce_hwseq *hws, 1119 struct dc *dc, 1120 struct dc_phy_addr_space_config *pa_config); 1121 void (*init_vm_ctx)(struct dce_hwseq *hws, 1122 struct dc *dc, 1123 struct dc_virtual_addr_space_config *va_config, 1124 int vmid); 1125 1126 /* Writeback Related */ 1127 void (*update_writeback)(struct dc *dc, 1128 struct dc_writeback_info *wb_info, 1129 struct dc_state *context); 1130 void (*enable_writeback)(struct dc *dc, 1131 struct dc_writeback_info *wb_info, 1132 struct dc_state *context); 1133 void (*disable_writeback)(struct dc *dc, 1134 unsigned int dwb_pipe_inst); 1135 1136 /* Clock Related */ 1137 enum dc_status (*set_clock)(struct dc *dc, 1138 enum dc_clock_type clock_type, 1139 uint32_t clk_khz, uint32_t stepping); 1140 void (*get_clock)(struct dc *dc, enum dc_clock_type clock_type, 1141 struct dc_clock_config *clock_cfg); 1142 void (*optimize_pwr_state)(const struct dc *dc, 1143 struct dc_state *context); 1144 void (*exit_optimized_pwr_state)(const struct dc *dc, 1145 struct dc_state *context); 1146 void (*calculate_pix_rate_divider)(struct dc *dc, 1147 struct dc_state *context, 1148 const struct dc_stream_state *stream); 1149 1150 /* Audio Related */ 1151 void (*enable_audio_stream)(struct pipe_ctx *pipe_ctx); 1152 void (*disable_audio_stream)(struct pipe_ctx *pipe_ctx); 1153 1154 /* Stereo 3D Related */ 1155 void (*setup_stereo)(struct pipe_ctx *pipe_ctx, struct dc *dc); 1156 1157 /* HW State Logging Related */ 1158 void (*log_hw_state)(struct dc *dc, struct dc_log_buffer_ctx *log_ctx); 1159 void (*log_color_state)(struct dc *dc, 1160 struct dc_log_buffer_ctx *log_ctx); 1161 void (*get_hw_state)(struct dc *dc, char *pBuf, 1162 unsigned int bufSize, unsigned int mask); 1163 void (*clear_status_bits)(struct dc *dc, unsigned int mask); 1164 1165 bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, 1166 struct set_backlight_level_params *params); 1167 1168 void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); 1169 1170 void (*set_pipe)(struct pipe_ctx *pipe_ctx); 1171 1172 void (*enable_dp_link_output)(struct dc_link *link, 1173 const struct link_resource *link_res, 1174 enum signal_type signal, 1175 enum clock_source_id clock_source, 1176 const struct dc_link_settings *link_settings); 1177 void (*enable_tmds_link_output)(struct dc_link *link, 1178 const struct link_resource *link_res, 1179 enum signal_type signal, 1180 enum clock_source_id clock_source, 1181 enum dc_color_depth color_depth, 1182 uint32_t pixel_clock); 1183 void (*enable_lvds_link_output)(struct dc_link *link, 1184 const struct link_resource *link_res, 1185 enum clock_source_id clock_source, 1186 uint32_t pixel_clock); 1187 void (*disable_link_output)(struct dc_link *link, 1188 const struct link_resource *link_res, 1189 enum signal_type signal); 1190 1191 void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); 1192 1193 /* Idle Optimization Related */ 1194 bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable); 1195 1196 bool (*does_plane_fit_in_mall)(struct dc *dc, 1197 unsigned int pitch, 1198 unsigned int height, 1199 enum surface_pixel_format format, 1200 struct dc_cursor_attributes *cursor_attr); 1201 void (*commit_subvp_config)(struct dc *dc, struct dc_state *context); 1202 void (*enable_phantom_streams)(struct dc *dc, struct dc_state *context); 1203 void (*disable_phantom_streams)(struct dc *dc, struct dc_state *context); 1204 void (*subvp_pipe_control_lock)(struct dc *dc, 1205 struct dc_state *context, 1206 bool lock, 1207 bool should_lock_all_pipes, 1208 struct pipe_ctx *top_pipe_to_program, 1209 bool subvp_prev_use); 1210 void (*subvp_pipe_control_lock_fast)(union block_sequence_params *params); 1211 1212 void (*z10_restore)(const struct dc *dc); 1213 void (*z10_save_init)(struct dc *dc); 1214 bool (*is_abm_supported)(struct dc *dc, 1215 struct dc_state *context, struct dc_stream_state *stream); 1216 1217 void (*set_disp_pattern_generator)(const struct dc *dc, 1218 struct pipe_ctx *pipe_ctx, 1219 enum controller_dp_test_pattern test_pattern, 1220 enum controller_dp_color_space color_space, 1221 enum dc_color_depth color_depth, 1222 const struct tg_color *solid_color, 1223 int width, int height, int offset); 1224 void (*blank_phantom)(struct dc *dc, 1225 struct timing_generator *tg, 1226 int width, 1227 int height); 1228 void (*update_visual_confirm_color)(struct dc *dc, 1229 struct pipe_ctx *pipe_ctx, 1230 int mpcc_id); 1231 void (*update_phantom_vp_position)(struct dc *dc, 1232 struct dc_state *context, 1233 struct pipe_ctx *phantom_pipe); 1234 void (*apply_update_flags_for_phantom)(struct pipe_ctx *phantom_pipe); 1235 1236 void (*calc_blocks_to_gate)(struct dc *dc, struct dc_state *context, 1237 struct pg_block_update *update_state); 1238 void (*calc_blocks_to_ungate)(struct dc *dc, struct dc_state *context, 1239 struct pg_block_update *update_state); 1240 void (*hw_block_power_up)(struct dc *dc, 1241 struct pg_block_update *update_state); 1242 void (*hw_block_power_down)(struct dc *dc, 1243 struct pg_block_update *update_state); 1244 void (*root_clock_control)(struct dc *dc, 1245 struct pg_block_update *update_state, bool power_on); 1246 bool (*is_pipe_topology_transition_seamless)(struct dc *dc, 1247 const struct dc_state *cur_ctx, 1248 const struct dc_state *new_ctx); 1249 void (*wait_for_dcc_meta_propagation)(const struct dc *dc, 1250 const struct pipe_ctx *top_pipe_to_program); 1251 void (*dmub_hw_control_lock)(struct dc *dc, 1252 struct dc_state *context, 1253 bool lock); 1254 void (*fams2_update_config)(struct dc *dc, 1255 struct dc_state *context, 1256 bool enable); 1257 void (*dmub_hw_control_lock_fast)(union block_sequence_params *params); 1258 void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); 1259 void (*program_outstanding_updates)(struct dc *dc, 1260 struct dc_state *context); 1261 void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); 1262 void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); 1263 void (*detect_pipe_changes)(struct dc_state *old_state, 1264 struct dc_state *new_state, 1265 struct pipe_ctx *old_pipe, 1266 struct pipe_ctx *new_pipe); 1267 void (*enable_plane)(struct dc *dc, 1268 struct pipe_ctx *pipe_ctx, 1269 struct dc_state *context); 1270 void (*enable_plane_sequence)(struct dc *dc, 1271 struct pipe_ctx *pipe_ctx, 1272 struct dc_state *context, 1273 struct block_sequence_state *seq_state); 1274 void (*update_dchubp_dpp)(struct dc *dc, 1275 struct pipe_ctx *pipe_ctx, 1276 struct dc_state *context); 1277 void (*update_dchubp_dpp_sequence)(struct dc *dc, 1278 struct pipe_ctx *pipe_ctx, 1279 struct dc_state *context, 1280 struct block_sequence_state *seq_state); 1281 void (*post_unlock_reset_opp)(struct dc *dc, 1282 struct pipe_ctx *opp_head); 1283 void (*post_unlock_reset_opp_sequence)( 1284 struct dc *dc, 1285 struct pipe_ctx *opp_head, 1286 struct block_sequence_state *seq_state); 1287 void (*get_underflow_debug_data)(const struct dc *dc, 1288 struct timing_generator *tg, 1289 struct dc_underflow_debug_data *out_data); 1290 1291 /** 1292 * measure_memory_qos - Measure memory QoS metrics 1293 * @dc: DC structure 1294 * @qos: Pointer to memory_qos struct to populate with measured values 1295 * 1296 * Populates the provided memory_qos struct with peak bandwidth, average bandwidth, 1297 * max latency, min latency, and average latency from hardware performance counters. 1298 */ 1299 void (*measure_memory_qos)(struct dc *dc, struct memory_qos *qos); 1300 1301 }; 1302 1303 void color_space_to_black_color( 1304 const struct dc *dc, 1305 enum dc_color_space colorspace, 1306 struct tg_color *black_color); 1307 1308 bool hwss_wait_for_blank_complete( 1309 struct timing_generator *tg); 1310 1311 const uint16_t *find_color_matrix( 1312 enum dc_color_space color_space, 1313 uint32_t *array_size); 1314 1315 void get_surface_tile_visual_confirm_color( 1316 struct pipe_ctx *pipe_ctx, 1317 struct tg_color *color); 1318 void get_surface_visual_confirm_color( 1319 const struct pipe_ctx *pipe_ctx, 1320 struct tg_color *color); 1321 1322 void get_hdr_visual_confirm_color( 1323 struct pipe_ctx *pipe_ctx, 1324 struct tg_color *color); 1325 void get_mpctree_visual_confirm_color( 1326 struct pipe_ctx *pipe_ctx, 1327 struct tg_color *color); 1328 void get_smartmux_visual_confirm_color( 1329 struct dc *dc, 1330 struct tg_color *color); 1331 void get_vabc_visual_confirm_color( 1332 struct pipe_ctx *pipe_ctx, 1333 struct tg_color *color); 1334 void get_subvp_visual_confirm_color( 1335 struct pipe_ctx *pipe_ctx, 1336 struct tg_color *color); 1337 void get_fams2_visual_confirm_color( 1338 struct dc *dc, 1339 struct dc_state *context, 1340 struct pipe_ctx *pipe_ctx, 1341 struct tg_color *color); 1342 1343 void get_mclk_switch_visual_confirm_color( 1344 struct pipe_ctx *pipe_ctx, 1345 struct tg_color *color); 1346 1347 void get_cursor_visual_confirm_color( 1348 struct pipe_ctx *pipe_ctx, 1349 struct tg_color *color); 1350 1351 void get_dcc_visual_confirm_color( 1352 struct dc *dc, 1353 struct pipe_ctx *pipe_ctx, 1354 struct tg_color *color); 1355 1356 void set_p_state_switch_method( 1357 struct dc *dc, 1358 struct dc_state *context, 1359 struct pipe_ctx *pipe_ctx); 1360 1361 void set_drr_and_clear_adjust_pending( 1362 struct pipe_ctx *pipe_ctx, 1363 struct dc_stream_state *stream, 1364 struct drr_params *params); 1365 1366 void hwss_execute_sequence(struct dc *dc, 1367 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 1368 int num_steps); 1369 1370 void hwss_build_fast_sequence(struct dc *dc, 1371 struct dc_dmub_cmd *dc_dmub_cmd, 1372 unsigned int dmub_cmd_count, 1373 struct block_sequence block_sequence[MAX_HWSS_BLOCK_SEQUENCE_SIZE], 1374 unsigned int *num_steps, 1375 struct pipe_ctx *pipe_ctx, 1376 struct dc_stream_status *stream_status, 1377 struct dc_state *context); 1378 1379 void hwss_wait_for_all_blank_complete(struct dc *dc, 1380 struct dc_state *context); 1381 1382 void hwss_wait_for_odm_update_pending_complete(struct dc *dc, 1383 struct dc_state *context); 1384 1385 void hwss_wait_for_no_pipes_pending(struct dc *dc, 1386 struct dc_state *context); 1387 1388 void hwss_wait_for_outstanding_hw_updates(struct dc *dc, 1389 struct dc_state *dc_context); 1390 1391 void hwss_process_outstanding_hw_updates(struct dc *dc, 1392 struct dc_state *dc_context); 1393 1394 void hwss_send_dmcub_cmd(union block_sequence_params *params); 1395 1396 void hwss_program_manual_trigger(union block_sequence_params *params); 1397 1398 void hwss_setup_dpp(union block_sequence_params *params); 1399 1400 void hwss_program_bias_and_scale(union block_sequence_params *params); 1401 1402 void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params); 1403 1404 void hwss_set_output_csc(union block_sequence_params *params); 1405 1406 void hwss_set_ocsc_default(union block_sequence_params *params); 1407 1408 void hwss_subvp_save_surf_addr(union block_sequence_params *params); 1409 1410 void hwss_program_surface_config(union block_sequence_params *params); 1411 1412 void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params); 1413 1414 void hwss_set_odm_combine(union block_sequence_params *params); 1415 1416 void hwss_set_odm_bypass(union block_sequence_params *params); 1417 1418 void hwss_opp_pipe_clock_control(union block_sequence_params *params); 1419 1420 void hwss_opp_program_left_edge_extra_pixel(union block_sequence_params *params); 1421 1422 void hwss_blank_pixel_data(union block_sequence_params *params); 1423 1424 void hwss_dccg_set_dto_dscclk(union block_sequence_params *params); 1425 1426 void hwss_dsc_set_config(union block_sequence_params *params); 1427 1428 void hwss_dsc_enable(union block_sequence_params *params); 1429 1430 void hwss_tg_set_dsc_config(union block_sequence_params *params); 1431 1432 void hwss_dsc_disconnect(union block_sequence_params *params); 1433 1434 void hwss_dsc_read_state(union block_sequence_params *params); 1435 1436 void hwss_dsc_calculate_and_set_config(union block_sequence_params *params); 1437 1438 void hwss_dsc_enable_with_opp(union block_sequence_params *params); 1439 1440 void hwss_program_tg(union block_sequence_params *params); 1441 1442 void hwss_tg_program_global_sync(union block_sequence_params *params); 1443 1444 void hwss_tg_wait_for_state(union block_sequence_params *params); 1445 1446 void hwss_tg_set_vtg_params(union block_sequence_params *params); 1447 1448 void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params); 1449 1450 void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params); 1451 1452 void hwss_program_det_size(union block_sequence_params *params); 1453 1454 void hwss_program_det_segments(union block_sequence_params *params); 1455 1456 void hwss_opp_set_dyn_expansion(union block_sequence_params *params); 1457 1458 void hwss_opp_program_fmt(union block_sequence_params *params); 1459 1460 void hwss_opp_program_bit_depth_reduction(union block_sequence_params *params); 1461 1462 void hwss_opp_set_disp_pattern_generator(union block_sequence_params *params); 1463 1464 void hwss_set_abm_pipe(union block_sequence_params *params); 1465 1466 void hwss_set_abm_level(union block_sequence_params *params); 1467 1468 void hwss_set_abm_immediate_disable(union block_sequence_params *params); 1469 1470 void hwss_mpc_remove_mpcc(union block_sequence_params *params); 1471 1472 void hwss_opp_set_mpcc_disconnect_pending(union block_sequence_params *params); 1473 1474 void hwss_dc_set_optimized_required(union block_sequence_params *params); 1475 1476 void hwss_hubp_disconnect(union block_sequence_params *params); 1477 1478 void hwss_hubbub_force_pstate_change_control(union block_sequence_params *params); 1479 1480 void hwss_tg_enable_crtc(union block_sequence_params *params); 1481 1482 void hwss_tg_set_gsl(union block_sequence_params *params); 1483 1484 void hwss_tg_set_gsl_source_select(union block_sequence_params *params); 1485 1486 void hwss_hubp_wait_flip_pending(union block_sequence_params *params); 1487 1488 void hwss_tg_wait_double_buffer_pending(union block_sequence_params *params); 1489 1490 void hwss_update_force_pstate(union block_sequence_params *params); 1491 1492 void hwss_hubbub_apply_dedcn21_147_wa(union block_sequence_params *params); 1493 1494 void hwss_hubbub_allow_self_refresh_control(union block_sequence_params *params); 1495 1496 void hwss_tg_get_frame_count(union block_sequence_params *params); 1497 1498 void hwss_mpc_set_dwb_mux(union block_sequence_params *params); 1499 1500 void hwss_mpc_disable_dwb_mux(union block_sequence_params *params); 1501 1502 void hwss_mcif_wb_config_buf(union block_sequence_params *params); 1503 1504 void hwss_mcif_wb_config_arb(union block_sequence_params *params); 1505 1506 void hwss_mcif_wb_enable(union block_sequence_params *params); 1507 1508 void hwss_mcif_wb_disable(union block_sequence_params *params); 1509 1510 void hwss_dwbc_enable(union block_sequence_params *params); 1511 1512 void hwss_dwbc_disable(union block_sequence_params *params); 1513 1514 void hwss_dwbc_update(union block_sequence_params *params); 1515 1516 void hwss_hubp_update_mall_sel(union block_sequence_params *params); 1517 1518 void hwss_hubp_prepare_subvp_buffering(union block_sequence_params *params); 1519 1520 void hwss_hubp_set_blank_en(union block_sequence_params *params); 1521 1522 void hwss_hubp_disable_control(union block_sequence_params *params); 1523 1524 void hwss_hubbub_soft_reset(union block_sequence_params *params); 1525 1526 void hwss_hubp_clk_cntl(union block_sequence_params *params); 1527 1528 void hwss_hubp_init(union block_sequence_params *params); 1529 1530 void hwss_hubp_set_vm_system_aperture_settings(union block_sequence_params *params); 1531 1532 void hwss_hubp_set_flip_int(union block_sequence_params *params); 1533 1534 void hwss_dpp_dppclk_control(union block_sequence_params *params); 1535 1536 void hwss_disable_phantom_crtc(union block_sequence_params *params); 1537 1538 void hwss_dsc_pg_status(union block_sequence_params *params); 1539 1540 void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params); 1541 1542 void hwss_dsc_disable(union block_sequence_params *params); 1543 1544 void hwss_dccg_set_ref_dscclk(union block_sequence_params *params); 1545 1546 void hwss_dpp_pg_control(union block_sequence_params *params); 1547 1548 void hwss_hubp_pg_control(union block_sequence_params *params); 1549 1550 void hwss_hubp_reset(union block_sequence_params *params); 1551 1552 void hwss_dpp_reset(union block_sequence_params *params); 1553 1554 void hwss_dpp_root_clock_control(union block_sequence_params *params); 1555 1556 void hwss_dc_ip_request_cntl(union block_sequence_params *params); 1557 1558 void hwss_dccg_update_dpp_dto(union block_sequence_params *params); 1559 1560 void hwss_hubp_vtg_sel(union block_sequence_params *params); 1561 1562 void hwss_hubp_setup2(union block_sequence_params *params); 1563 1564 void hwss_hubp_setup(union block_sequence_params *params); 1565 1566 void hwss_hubp_set_unbounded_requesting(union block_sequence_params *params); 1567 1568 void hwss_hubp_setup_interdependent2(union block_sequence_params *params); 1569 1570 void hwss_hubp_setup_interdependent(union block_sequence_params *params); 1571 1572 void hwss_dpp_set_cursor_matrix(union block_sequence_params *params); 1573 1574 void hwss_mpc_update_mpcc(union block_sequence_params *params); 1575 1576 void hwss_mpc_update_blending(union block_sequence_params *params); 1577 1578 void hwss_mpc_assert_idle_mpcc(union block_sequence_params *params); 1579 1580 void hwss_mpc_insert_plane(union block_sequence_params *params); 1581 1582 void hwss_dpp_set_scaler(union block_sequence_params *params); 1583 1584 void hwss_hubp_mem_program_viewport(union block_sequence_params *params); 1585 1586 void hwss_abort_cursor_offload_update(union block_sequence_params *params); 1587 1588 void hwss_set_cursor_attribute(union block_sequence_params *params); 1589 1590 void hwss_set_cursor_position(union block_sequence_params *params); 1591 1592 void hwss_set_cursor_sdr_white_level(union block_sequence_params *params); 1593 1594 void hwss_program_output_csc(union block_sequence_params *params); 1595 1596 void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params); 1597 1598 void hwss_hubp_set_blank(union block_sequence_params *params); 1599 1600 void hwss_phantom_hubp_post_enable(union block_sequence_params *params); 1601 1602 void hwss_add_optc_pipe_control_lock(struct block_sequence_state *seq_state, 1603 struct dc *dc, struct pipe_ctx *pipe_ctx, bool lock); 1604 1605 void hwss_add_hubp_set_flip_control_gsl(struct block_sequence_state *seq_state, 1606 struct hubp *hubp, bool flip_immediate); 1607 1608 void hwss_add_hubp_program_triplebuffer(struct block_sequence_state *seq_state, 1609 struct dc *dc, struct pipe_ctx *pipe_ctx, bool enableTripleBuffer); 1610 1611 void hwss_add_hubp_update_plane_addr(struct block_sequence_state *seq_state, 1612 struct dc *dc, struct pipe_ctx *pipe_ctx); 1613 1614 void hwss_add_dpp_set_input_transfer_func(struct block_sequence_state *seq_state, 1615 struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state); 1616 1617 void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, 1618 struct pipe_ctx *pipe_ctx); 1619 1620 void hwss_add_dpp_program_bias_and_scale(struct block_sequence_state *seq_state, 1621 struct pipe_ctx *pipe_ctx); 1622 1623 void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state, 1624 struct pipe_ctx *pipe_ctx); 1625 1626 void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state, 1627 struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream); 1628 1629 void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state, 1630 struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id); 1631 1632 void hwss_add_mpc_power_on_mpc_mem_pwr(struct block_sequence_state *seq_state, 1633 struct mpc *mpc, int mpcc_id, bool power_on); 1634 1635 void hwss_add_mpc_set_output_csc(struct block_sequence_state *seq_state, 1636 struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); 1637 1638 void hwss_add_mpc_set_ocsc_default(struct block_sequence_state *seq_state, 1639 struct mpc *mpc, int opp_id, enum dc_color_space colorspace, enum mpc_output_csc_mode ocsc_mode); 1640 1641 void hwss_add_dmub_send_dmcub_cmd(struct block_sequence_state *seq_state, 1642 struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type); 1643 1644 void hwss_add_dmub_subvp_save_surf_addr(struct block_sequence_state *seq_state, 1645 struct dc_dmub_srv *dc_dmub_srv, struct dc_plane_address *addr, uint8_t subvp_index); 1646 1647 void hwss_add_hubp_wait_for_dcc_meta_prop(struct block_sequence_state *seq_state, 1648 struct dc *dc, struct pipe_ctx *top_pipe_to_program); 1649 1650 void hwss_add_hubp_wait_pipe_read_start(struct block_sequence_state *seq_state, 1651 struct hubp *hubp); 1652 1653 void hwss_add_hws_apply_update_flags_for_phantom(struct block_sequence_state *seq_state, 1654 struct pipe_ctx *pipe_ctx); 1655 1656 void hwss_add_hws_update_phantom_vp_position(struct block_sequence_state *seq_state, 1657 struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); 1658 1659 void hwss_add_optc_set_odm_combine(struct block_sequence_state *seq_state, 1660 struct timing_generator *tg, int opp_inst[MAX_PIPES], int opp_head_count, 1661 int odm_slice_width, int last_odm_slice_width); 1662 1663 void hwss_add_optc_set_odm_bypass(struct block_sequence_state *seq_state, 1664 struct timing_generator *optc, struct dc_crtc_timing *timing); 1665 1666 void hwss_add_tg_program_global_sync(struct block_sequence_state *seq_state, 1667 struct timing_generator *tg, 1668 int vready_offset, 1669 unsigned int vstartup_lines, 1670 unsigned int vupdate_offset_pixels, 1671 unsigned int vupdate_vupdate_width_pixels, 1672 unsigned int pstate_keepout_start_lines); 1673 1674 void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state, 1675 struct timing_generator *tg, enum crtc_state state); 1676 1677 void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state, 1678 struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 1679 1680 void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state, 1681 struct timing_generator *tg, int start_line); 1682 1683 void hwss_add_dpp_set_hdr_multiplier(struct block_sequence_state *seq_state, 1684 struct dpp *dpp, uint32_t hw_mult); 1685 1686 void hwss_add_hubp_program_det_size(struct block_sequence_state *seq_state, 1687 struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_buffer_size_kb); 1688 1689 void hwss_add_hubp_program_mcache_id(struct block_sequence_state *seq_state, 1690 struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); 1691 1692 void hwss_add_hubbub_force_pstate_change_control(struct block_sequence_state *seq_state, 1693 struct hubbub *hubbub, bool enable, bool wait); 1694 1695 void hwss_add_hubp_program_det_segments(struct block_sequence_state *seq_state, 1696 struct hubbub *hubbub, unsigned int hubp_inst, unsigned int det_size); 1697 1698 void hwss_add_opp_set_dyn_expansion(struct block_sequence_state *seq_state, 1699 struct output_pixel_processor *opp, enum dc_color_space color_sp, 1700 enum dc_color_depth color_dpth, enum signal_type signal); 1701 1702 void hwss_add_opp_program_fmt(struct block_sequence_state *seq_state, 1703 struct output_pixel_processor *opp, struct bit_depth_reduction_params *fmt_bit_depth, 1704 struct clamping_and_pixel_encoding_params *clamping); 1705 1706 void hwss_add_abm_set_pipe(struct block_sequence_state *seq_state, 1707 struct dc *dc, struct pipe_ctx *pipe_ctx); 1708 1709 void hwss_add_abm_set_level(struct block_sequence_state *seq_state, 1710 struct abm *abm, uint32_t abm_level); 1711 1712 void hwss_add_tg_enable_crtc(struct block_sequence_state *seq_state, 1713 struct timing_generator *tg); 1714 1715 void hwss_add_hubp_wait_flip_pending(struct block_sequence_state *seq_state, 1716 struct hubp *hubp, unsigned int timeout_us, unsigned int polling_interval_us); 1717 1718 void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_state, 1719 struct timing_generator *tg, unsigned int timeout_us, unsigned int polling_interval_us); 1720 1721 void hwss_add_dccg_set_dto_dscclk(struct block_sequence_state *seq_state, 1722 struct dccg *dccg, int inst, int num_slices_h); 1723 1724 void hwss_add_dsc_calculate_and_set_config(struct block_sequence_state *seq_state, 1725 struct pipe_ctx *pipe_ctx, bool enable, int opp_cnt); 1726 1727 void hwss_add_mpc_remove_mpcc(struct block_sequence_state *seq_state, 1728 struct mpc *mpc, struct mpc_tree *mpc_tree_params, struct mpcc *mpcc_to_remove); 1729 1730 void hwss_add_opp_set_mpcc_disconnect_pending(struct block_sequence_state *seq_state, 1731 struct output_pixel_processor *opp, int mpcc_inst, bool pending); 1732 1733 void hwss_add_hubp_disconnect(struct block_sequence_state *seq_state, 1734 struct hubp *hubp); 1735 1736 void hwss_add_dsc_enable_with_opp(struct block_sequence_state *seq_state, 1737 struct pipe_ctx *pipe_ctx); 1738 1739 void hwss_add_dsc_disconnect(struct block_sequence_state *seq_state, 1740 struct display_stream_compressor *dsc); 1741 1742 void hwss_add_dc_set_optimized_required(struct block_sequence_state *seq_state, 1743 struct dc *dc, bool optimized_required); 1744 1745 void hwss_add_abm_set_immediate_disable(struct block_sequence_state *seq_state, 1746 struct dc *dc, struct pipe_ctx *pipe_ctx); 1747 1748 void hwss_add_opp_set_disp_pattern_generator(struct block_sequence_state *seq_state, 1749 struct output_pixel_processor *opp, 1750 enum controller_dp_test_pattern test_pattern, 1751 enum controller_dp_color_space color_space, 1752 enum dc_color_depth color_depth, 1753 struct tg_color solid_color, 1754 bool use_solid_color, 1755 int width, 1756 int height, 1757 int offset); 1758 1759 void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_state, 1760 struct output_pixel_processor *opp, 1761 bool use_default_params, 1762 struct pipe_ctx *pipe_ctx); 1763 1764 void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, 1765 struct dc *dc, 1766 bool enable); 1767 1768 void hwss_add_dwbc_update(struct block_sequence_state *seq_state, 1769 struct dwbc *dwb, 1770 struct dc_dwb_params *dwb_params); 1771 1772 void hwss_add_mcif_wb_config_buf(struct block_sequence_state *seq_state, 1773 struct mcif_wb *mcif_wb, 1774 struct mcif_buf_params *mcif_buf_params, 1775 unsigned int dest_height); 1776 1777 void hwss_add_mcif_wb_config_arb(struct block_sequence_state *seq_state, 1778 struct mcif_wb *mcif_wb, 1779 struct mcif_arb_params *mcif_arb_params); 1780 1781 void hwss_add_mcif_wb_enable(struct block_sequence_state *seq_state, 1782 struct mcif_wb *mcif_wb); 1783 1784 void hwss_add_mcif_wb_disable(struct block_sequence_state *seq_state, 1785 struct mcif_wb *mcif_wb); 1786 1787 void hwss_add_mpc_set_dwb_mux(struct block_sequence_state *seq_state, 1788 struct mpc *mpc, 1789 int dwb_id, 1790 int mpcc_id); 1791 1792 void hwss_add_mpc_disable_dwb_mux(struct block_sequence_state *seq_state, 1793 struct mpc *mpc, 1794 unsigned int dwb_id); 1795 1796 void hwss_add_dwbc_enable(struct block_sequence_state *seq_state, 1797 struct dwbc *dwb, 1798 struct dc_dwb_params *dwb_params); 1799 1800 void hwss_add_dwbc_disable(struct block_sequence_state *seq_state, 1801 struct dwbc *dwb); 1802 1803 void hwss_add_tg_set_gsl(struct block_sequence_state *seq_state, 1804 struct timing_generator *tg, 1805 struct gsl_params gsl); 1806 1807 void hwss_add_tg_set_gsl_source_select(struct block_sequence_state *seq_state, 1808 struct timing_generator *tg, 1809 int group_idx, 1810 uint32_t gsl_ready_signal); 1811 1812 void hwss_add_hubp_update_mall_sel(struct block_sequence_state *seq_state, 1813 struct hubp *hubp, 1814 uint32_t mall_sel, 1815 bool cache_cursor); 1816 1817 void hwss_add_hubp_prepare_subvp_buffering(struct block_sequence_state *seq_state, 1818 struct hubp *hubp, 1819 bool enable); 1820 1821 void hwss_add_hubp_set_blank_en(struct block_sequence_state *seq_state, 1822 struct hubp *hubp, 1823 bool enable); 1824 1825 void hwss_add_hubp_disable_control(struct block_sequence_state *seq_state, 1826 struct hubp *hubp, 1827 bool disable); 1828 1829 void hwss_add_hubbub_soft_reset(struct block_sequence_state *seq_state, 1830 struct hubbub *hubbub, 1831 void (*hubbub_soft_reset)(struct hubbub *hubbub, bool reset), 1832 bool reset); 1833 1834 void hwss_add_hubp_clk_cntl(struct block_sequence_state *seq_state, 1835 struct hubp *hubp, 1836 bool enable); 1837 1838 void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, 1839 struct dpp *dpp, 1840 bool dppclk_div, 1841 bool enable); 1842 1843 void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, 1844 struct timing_generator *tg); 1845 1846 void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, 1847 struct dce_hwseq *hws, 1848 int dsc_inst, 1849 bool is_ungated); 1850 1851 void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, 1852 struct display_stream_compressor *dsc, 1853 bool *is_ungated); 1854 1855 void hwss_add_dsc_disable(struct block_sequence_state *seq_state, 1856 struct display_stream_compressor *dsc, 1857 bool *is_ungated); 1858 1859 void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, 1860 struct dccg *dccg, 1861 int dsc_inst, 1862 bool *is_ungated); 1863 1864 void hwss_add_dpp_root_clock_control(struct block_sequence_state *seq_state, 1865 struct dce_hwseq *hws, 1866 unsigned int dpp_inst, 1867 bool clock_on); 1868 1869 void hwss_add_dpp_pg_control(struct block_sequence_state *seq_state, 1870 struct dce_hwseq *hws, 1871 unsigned int dpp_inst, 1872 bool power_on); 1873 1874 void hwss_add_hubp_pg_control(struct block_sequence_state *seq_state, 1875 struct dce_hwseq *hws, 1876 unsigned int hubp_inst, 1877 bool power_on); 1878 1879 void hwss_add_hubp_set_blank(struct block_sequence_state *seq_state, 1880 struct hubp *hubp, 1881 bool blank); 1882 1883 void hwss_add_hubp_init(struct block_sequence_state *seq_state, 1884 struct hubp *hubp); 1885 1886 void hwss_add_hubp_reset(struct block_sequence_state *seq_state, 1887 struct hubp *hubp); 1888 1889 void hwss_add_dpp_reset(struct block_sequence_state *seq_state, 1890 struct dpp *dpp); 1891 1892 void hwss_add_opp_pipe_clock_control(struct block_sequence_state *seq_state, 1893 struct output_pixel_processor *opp, 1894 bool enable); 1895 1896 void hwss_add_hubp_set_vm_system_aperture_settings(struct block_sequence_state *seq_state, 1897 struct hubp *hubp, 1898 uint64_t sys_default, 1899 uint64_t sys_low, 1900 uint64_t sys_high); 1901 1902 void hwss_add_hubp_set_flip_int(struct block_sequence_state *seq_state, 1903 struct hubp *hubp); 1904 1905 void hwss_add_dccg_update_dpp_dto(struct block_sequence_state *seq_state, 1906 struct dccg *dccg, 1907 int dpp_inst, 1908 int dppclk_khz); 1909 1910 void hwss_add_hubp_vtg_sel(struct block_sequence_state *seq_state, 1911 struct hubp *hubp, 1912 uint32_t otg_inst); 1913 1914 void hwss_add_hubp_setup2(struct block_sequence_state *seq_state, 1915 struct hubp *hubp, 1916 struct dml2_dchub_per_pipe_register_set *hubp_regs, 1917 union dml2_global_sync_programming *global_sync, 1918 struct dc_crtc_timing *timing); 1919 1920 void hwss_add_hubp_setup(struct block_sequence_state *seq_state, 1921 struct hubp *hubp, 1922 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 1923 struct _vcs_dpi_display_ttu_regs_st *ttu_regs, 1924 struct _vcs_dpi_display_rq_regs_st *rq_regs, 1925 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); 1926 1927 void hwss_add_hubp_set_unbounded_requesting(struct block_sequence_state *seq_state, 1928 struct hubp *hubp, 1929 bool unbounded_req); 1930 1931 void hwss_add_hubp_setup_interdependent2(struct block_sequence_state *seq_state, 1932 struct hubp *hubp, 1933 struct dml2_dchub_per_pipe_register_set *hubp_regs); 1934 1935 void hwss_add_hubp_setup_interdependent(struct block_sequence_state *seq_state, 1936 struct hubp *hubp, 1937 struct _vcs_dpi_display_dlg_regs_st *dlg_regs, 1938 struct _vcs_dpi_display_ttu_regs_st *ttu_regs); 1939 void hwss_add_hubp_program_surface_config(struct block_sequence_state *seq_state, 1940 struct hubp *hubp, 1941 enum surface_pixel_format format, 1942 struct dc_tiling_info *tiling_info, 1943 struct plane_size plane_size, 1944 enum dc_rotation_angle rotation, 1945 struct dc_plane_dcc_param *dcc, 1946 bool horizontal_mirror, 1947 int compat_level); 1948 1949 void hwss_add_dpp_setup_dpp(struct block_sequence_state *seq_state, 1950 struct pipe_ctx *pipe_ctx); 1951 1952 void hwss_add_dpp_set_cursor_matrix(struct block_sequence_state *seq_state, 1953 struct dpp *dpp, 1954 enum dc_color_space color_space, 1955 struct dc_csc_transform *cursor_csc_color_matrix); 1956 1957 void hwss_add_mpc_update_blending(struct block_sequence_state *seq_state, 1958 struct mpc *mpc, 1959 struct mpcc_blnd_cfg blnd_cfg, 1960 int mpcc_id); 1961 1962 void hwss_add_mpc_assert_idle_mpcc(struct block_sequence_state *seq_state, 1963 struct mpc *mpc, 1964 int mpcc_id); 1965 1966 void hwss_add_mpc_insert_plane(struct block_sequence_state *seq_state, 1967 struct mpc *mpc, 1968 struct mpc_tree *mpc_tree_params, 1969 struct mpcc_blnd_cfg blnd_cfg, 1970 struct mpcc_sm_cfg *sm_cfg, 1971 struct mpcc *insert_above_mpcc, 1972 int dpp_id, 1973 int mpcc_id); 1974 1975 void hwss_add_dpp_set_scaler(struct block_sequence_state *seq_state, 1976 struct dpp *dpp, 1977 const struct scaler_data *scl_data); 1978 1979 void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state, 1980 struct hubp *hubp, 1981 const struct rect *viewport, 1982 const struct rect *viewport_c); 1983 1984 void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state, 1985 struct dc *dc, 1986 struct pipe_ctx *pipe_ctx); 1987 1988 void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state, 1989 struct dc *dc, 1990 struct pipe_ctx *pipe_ctx); 1991 1992 void hwss_add_set_cursor_position(struct block_sequence_state *seq_state, 1993 struct dc *dc, 1994 struct pipe_ctx *pipe_ctx); 1995 1996 void hwss_add_set_cursor_sdr_white_level(struct block_sequence_state *seq_state, 1997 struct dc *dc, 1998 struct pipe_ctx *pipe_ctx); 1999 2000 void hwss_add_program_output_csc(struct block_sequence_state *seq_state, 2001 struct dc *dc, 2002 struct pipe_ctx *pipe_ctx, 2003 enum dc_color_space colorspace, 2004 uint16_t *matrix, 2005 int opp_id); 2006 2007 void hwss_add_phantom_hubp_post_enable(struct block_sequence_state *seq_state, 2008 struct hubp *hubp); 2009 2010 void hwss_add_update_force_pstate(struct block_sequence_state *seq_state, 2011 struct dc *dc, 2012 struct dc_state *context); 2013 2014 void hwss_add_hubbub_apply_dedcn21_147_wa(struct block_sequence_state *seq_state, 2015 struct hubbub *hubbub); 2016 2017 void hwss_add_hubbub_allow_self_refresh_control(struct block_sequence_state *seq_state, 2018 struct hubbub *hubbub, 2019 bool allow, 2020 bool *disallow_self_refresh_applied); 2021 2022 void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, 2023 struct timing_generator *tg, 2024 unsigned int *frame_count); 2025 2026 void hwss_add_tg_set_dsc_config(struct block_sequence_state *seq_state, 2027 struct timing_generator *tg, 2028 struct dsc_optc_config *dsc_optc_cfg, 2029 bool enable); 2030 2031 void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq_state, 2032 struct output_pixel_processor *opp, 2033 enum dc_pixel_encoding pixel_encoding, 2034 bool is_otg_master); 2035 2036 #endif /* __DC_HW_SEQUENCER_H__ */ 2037