xref: /linux/include/linux/can/platform/sja1000.h (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _CAN_PLATFORM_SJA1000_H
3 #define _CAN_PLATFORM_SJA1000_H
4 
5 /* clock divider register */
6 #define CDR_CLKOUT_MASK 0x07
7 #define CDR_CLK_OFF	0x08 /* Clock off (CLKOUT pin) */
8 #define CDR_RXINPEN	0x20 /* TX1 output is RX irq output */
9 #define CDR_CBP		0x40 /* CAN input comparator bypass */
10 #define CDR_PELICAN	0x80 /* PeliCAN mode */
11 
12 /* output control register */
13 #define OCR_MODE_BIPHASE  0x00
14 #define OCR_MODE_TEST     0x01
15 #define OCR_MODE_NORMAL   0x02
16 #define OCR_MODE_CLOCK    0x03
17 #define OCR_MODE_MASK     0x03
18 #define OCR_TX0_INVERT    0x04
19 #define OCR_TX0_PULLDOWN  0x08
20 #define OCR_TX0_PULLUP    0x10
21 #define OCR_TX0_PUSHPULL  0x18
22 #define OCR_TX1_INVERT    0x20
23 #define OCR_TX1_PULLDOWN  0x40
24 #define OCR_TX1_PULLUP    0x80
25 #define OCR_TX1_PUSHPULL  0xc0
26 #define OCR_TX_MASK       0xfc
27 #define OCR_TX_SHIFT      2
28 
29 struct sja1000_platform_data {
30 	u32 osc_freq;	/* CAN bus oscillator frequency in Hz */
31 
32 	u8 ocr;		/* output control register */
33 	u8 cdr;		/* clock divider register */
34 };
35 
36 #endif	/* !_CAN_PLATFORM_SJA1000_H */
37