| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.h | 57 const TargetRegisterClass *NewRC = nullptr; variable
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| H A D | CriticalAntiDepBreaker.cpp | 186 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
314 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
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| H A D | MachineRegisterInfo.cpp | 75 const TargetRegisterClass *NewRC = in constrainRegClass() local
126 const TargetRegisterClass *NewRC = in recomputeRegClass() local
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| H A D | PeepholeOptimizer.cpp | 823 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI() local
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| H A D | RegisterCoalescer.cpp | 1382 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 316 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | LazyCallGraph.cpp | 1659 RefSCC *NewRC = OriginalRC; in addSplitFunction() local
1684 RefSCC *NewRC = createRefSCC(*this); in addSplitFunction() local
1733 RefSCC *NewRC; in addSplitRefRecursiveFunctions() local
1955 RefSCC *NewRC = createRefSCC(*this); in buildRefSCCs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 356 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
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| H A D | HexagonVLIWPacketizer.cpp | 361 const TargetRegisterClass *NewRC) { in isNewifiable()
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| H A D | HexagonBitSimplify.cpp | 2654 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2722 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
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| H A D | HexagonFrameLowering.cpp | 2197 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { in optimizeSpillSlots()
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| H A D | HexagonConstPropagation.cpp | 2897 const TargetRegisterClass *NewRC; rewriteHexConstDefs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 451 auto *NewRC = getMinSizeReg(RC, SubRegs); in rewriteReg() local
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| H A D | SIRegisterInfo.cpp | 3032 const TargetRegisterClass *NewRC, in shouldCoalesce()
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| H A D | SIInstrInfo.cpp | 2612 const TargetRegisterClass *NewRC = in reMaterialize() local
7232 const TargetRegisterClass *NewRC = in moveToVALUImpl() local
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| H A D | SIISelLowering.cpp | 15250 auto *NewRC = TRI->getEquivalentVGPRClass(RC); in AdjustInstrPostInstrSelection() local
15265 auto *NewRC = TRI->getEquivalentAGPRClass(RC); in AdjustInstrPostInstrSelection() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 384 const TargetRegisterClass *NewRC, in shouldCoalesce() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.cpp | 1069 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 882 const TargetRegisterClass *NewRC, in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 1118 const TargetRegisterClass *NewRC, in shouldCoalesce()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 5091 const TargetRegisterClass *NewRC = in transformToImmFormFedByLI() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 7134 auto *NewRC = MRI.constrainRegClass( in updateOperandRegConstraints() local
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaTemplate.cpp | 7744 const Expr *NewRC = New->getRequiresClause(); in TemplateParameterListsAreEqual() local
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| H A D | SemaOverload.cpp | 1507 Expr *NewRC = New->getTrailingRequiresClause(), in IsOverloadOrOverrideImpl() local
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