| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupInstTuning.cpp | 107 bool ReplaceInTie = true) -> bool { in processInstruction()
133 auto ProcessVPERMILPDri = [&](unsigned NewOpc) -> bool { in processInstruction()
148 auto ProcessVPERMILPSri = [&](unsigned NewOpc) -> bool { in processInstruction()
162 auto ProcessVPERMILPSmi = [&](unsigned NewOpc) -> bool { in processInstruction()
186 auto ProcessUNPCK = [&](unsigned NewOpc, unsigned MaskImm) -> bool { in processInstruction()
195 auto ProcessUNPCKToIntDomain = [&](unsigned NewOpc) -> bool { in processInstruction()
207 unsigned NewOpc) -> bool { in processInstruction()
213 unsigned NewOpc) -> bool { in processInstruction()
223 auto ProcessUNPCKPS = [&](unsigned NewOpc) -> bool { in processInstruction()
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| H A D | X86EvexToVex.cpp | |
| H A D | X86CompressEVEX.cpp | 117 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { in performCustomAdjustments()
243 unsigned NewOpc = IsRedundantNDD in CompressEVEXImpl() local
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| H A D | X86FixupLEAs.cpp | 809 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); processInstrForSlow3OpLEA() local
847 unsigned NewOpc = processInstrForSlow3OpLEA() local
853 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); processInstrForSlow3OpLEA() local
881 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); processInstrForSlow3OpLEA() local
904 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); processInstrForSlow3OpLEA() local
[all...] |
| H A D | X86InstructionSelector.cpp | |
| H A D | X86ISelDAGToDAG.cpp | 1134 unsigned NewOpc; in PreprocessISelDAG() local
1167 unsigned NewOpc; in PreprocessISelDAG() local
1189 unsigned NewOpc; in PreprocessISelDAG() local
1606 unsigned NewOpc; in PostprocessISelDAG() local
1668 unsigned NewOpc; in PostprocessISelDAG() local
3630 unsigned NewOpc = SelectOpcode(X86::NEG64m, X86::NEG32m, X86::NEG16m, in foldLoadStoreIntoMemOperand() local
3645 unsigned NewOpc = in foldLoadStoreIntoMemOperand() local
3715 unsigned NewOpc = SelectRegOpcode(Opc); in foldLoadStoreIntoMemOperand() local
4165 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; in matchBEXTRFromAndImm() local
4183 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; in matchBEXTRFromAndImm() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86EncodingOptimization.cpp | 25 unsigned NewOpc = 0; in optimizeInstFromVEX3ToVEX2() local
105 unsigned NewOpc; in optimizeShiftRotateWithImmediateOne() local
277 unsigned NewOpc; in optimizeVPCMPWithImmediateOneOrSix() local
290 unsigned NewOpc; in optimizeMOVSX() local
314 unsigned NewOpc; in optimizeINCDEC() local
342 unsigned NewOpc; in optimizeMOV() local
397 unsigned NewOpc; in optimizeToFixedRegisterForm() local
474 unsigned NewOpc; in optimizeToShortImmediateForm() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMemAbsolute.cpp | 113 int NewOpc; in runOnMachineFunction() local
217 bool HexagonGenMemAbsolute::isValidIndexedLoad(int &Opc, int &NewOpc) { in isValidIndexedLoad()
246 bool HexagonGenMemAbsolute::isValidIndexedStore(int &Opc, int &NewOpc) { in isValidIndexedStore()
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| H A D | HexagonRDFOpt.cpp | 229 unsigned OpNum, NewOpc; in rewrite() local
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| H A D | HexagonGenPredicate.cpp | 387 unsigned NewOpc = getPredForm(Opc); in convertToPredForm() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 876 unsigned NewOpc = in ExpandMQQPRLoadStore() local
2144 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; in ExpandMI() local
2154 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; in ExpandMI() local
2164 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; in ExpandMI() local
2440 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI() local
2482 unsigned NewOpc; in ExpandMI() local
2776 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
2807 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local
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| H A D | ARMLoadStoreOptimizer.cpp | 1349 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1501 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1638 unsigned NewOpc; in MergeBaseUpdateLSDouble() local
1735 bool isDef, unsigned NewOpc, unsigned Reg, in InsertLDR_STR()
1807 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1831 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
2059 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM() local
2256 MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, in CanFormLdStDWord()
2420 unsigned NewOpc = 0; in RescheduleOps() local
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| H A D | Thumb2InstrInfo.cpp | 610 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex() local
643 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
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| H A D | ARMConstantIslandPass.cpp | 1845 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1896 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1930 unsigned NewOpc = 0; in optimizeThumb2Branches() member
1944 unsigned NewOpc = 0; in optimizeThumb2Branches() local
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| H A D | ARMInstructionSelector.cpp | 910 unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize); in select() local
1106 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize); in select() local
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| H A D | ThumbRegisterInfo.cpp | 418 unsigned NewOpc = convertToNonSPOpcode(Opcode); rewriteFrameIndex() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CondBrTuning.cpp | 98 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode()); in convertToFlagSetting() local
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| H A D | AArch64AdvSIMDScalarPass.cpp | 292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVVectorPeephole.cpp | 165 unsigned NewOpc; in convertVMergeToVMv() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostSelectOptimize.cpp | 270 unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); in optimizeNZCVDefs() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 590 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlign()); in selectLoadStoreOp() local
655 unsigned NewOpc = getLeaOP(Ty, STI); in selectFrameIndexOrGep() local
706 unsigned NewOpc = getLeaOP(Ty, STI); in selectGlobalValue() local
738 unsigned NewOpc; in selectConstant() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); insertMergedInstruction() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 477 const unsigned NewOpc = TryAK ? AMDGPU::S_FMAAK_F32 : AMDGPU::S_FMAMK_F32; in tryAddToFoldList() local
514 unsigned NewOpc = macToMad(Opc); in tryAddToFoldList() local
826 unsigned NewOpc = AMDGPU::getFlatScratchInstSSfromSV(Opc); in foldOperand() local
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| H A D | SIInstrInfo.cpp | 1148 int NewOpc; in commuteOpcode() local
3460 unsigned NewOpc = isVGPRCopy ? Is64Bit ? AMDGPU::V_MOV_B64_PSEUDO in foldImmediate() local
3553 unsigned NewOpc = in foldImmediate() local
3632 unsigned NewOpc = in foldImmediate() local
3861 unsigned NewOpc = AMDGPU::mapWMMA2AddrTo3AddrOpcode(MI.getOpcode()); in convertToThreeAddress() local
3964 unsigned NewOpc = in convertToThreeAddress() local
3983 unsigned NewOpc = in convertToThreeAddress() local
4033 unsigned NewOpc = IsFMA ? IsF16 ? AMDGPU::V_FMA_F16_gfx9_e64 in convertToThreeAddress() local
6126 int NewOpc = AMDGPU::getGlobalVaddrOp(Opc); in moveFlatAddrToVGPR() local
7523 unsigned NewOpc = Opc == AMDGPU::S_ADD_I32 ? in moveScalarAddSub() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 685 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc()
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