1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2026, NVIDIA CORPORATION & AFFILIATES. All rights reserved. 4 */ 5 #ifndef _NV_FALCON_HW_H_ 6 #define _NV_FALCON_HW_H_ 7 8 #include <linux/types.h> 9 10 /* PMC (Power Management Controller) Registers */ 11 #define NV_PMC_BOOT_0 0x00000000 12 #define NV_PMC_ENABLE 0x00000200 13 #define NV_PMC_ENABLE_PWR 0x00002000 14 #define NV_PMC_ENABLE_HUB 0x20000000 15 16 /* Falcon Base Pages for Different Engines */ 17 #define NV_PPWR_FALCON_BASE 0x10a000 18 #define NV_PGSP_FALCON_BASE 0x110000 19 20 /* Falcon Common Register Offsets (relative to base_page) */ 21 #define NV_FALCON_DMACTL_OFFSET 0x010c 22 #define NV_FALCON_ENGINE_RESET_OFFSET 0x03c0 23 24 /* DMEM Control Register Flags */ 25 #define NV_PPWR_FALCON_DMEMC_AINCR_TRUE 0x01000000 26 #define NV_PPWR_FALCON_DMEMC_AINCW_TRUE 0x02000000 27 28 /* Falcon DMEM port offsets (for port 0) */ 29 #define NV_FALCON_DMEMC_OFFSET 0x1c0 30 #define NV_FALCON_DMEMD_OFFSET 0x1c4 31 32 /* DMA Register Offsets (relative to base_page) */ 33 #define NV_FALCON_DMA_ADDR_LOW_OFFSET 0x110 34 #define NV_FALCON_DMA_MEM_OFFSET 0x114 35 #define NV_FALCON_DMA_CMD_OFFSET 0x118 36 #define NV_FALCON_DMA_BLOCK_OFFSET 0x11c 37 #define NV_FALCON_DMA_ADDR_HIGH_OFFSET 0x128 38 39 /* DMA Global Address Top Bits Register */ 40 #define NV_GPU_DMA_ADDR_TOP_BITS_REG 0x100f04 41 42 /* DMA Command Register Bit Definitions */ 43 #define NV_FALCON_DMA_CMD_WRITE_BIT 0x20 44 #define NV_FALCON_DMA_CMD_SIZE_SHIFT 8 45 #define NV_FALCON_DMA_CMD_DONE_BIT 0x2 46 47 /* 48 * Falcon DMA is synchronous, so a transfer size and count larger than 49 * its per-operation maximum adds no value. 50 */ 51 52 /* DMA block size and alignment */ 53 #define NV_FALCON_DMA_MIN_TRANSFER_SIZE 4 54 #define NV_FALCON_DMA_MAX_TRANSFER_SIZE 256 55 #define NV_FALCON_DMA_BLOCK_SIZE 256 56 #define NV_FALCON_DMA_MAX_TRANSFER_COUNT 1 57 58 /* DMACTL register bits */ 59 #define NV_FALCON_DMACTL_DMEM_SCRUBBING 0x1 60 #define NV_FALCON_DMACTL_READY_MASK 0x6 61 62 /* Falcon Core Selection Register */ 63 #define NV_FALCON_CORE_SELECT_OFFSET 0x1668 64 #define NV_FALCON_CORE_SELECT_MASK 0x30 65 66 /* Falcon mailbox register (for Ada+ reset check) */ 67 #define NV_FALCON_MAILBOX_TEST_OFFSET 0x40c 68 #define NV_FALCON_MAILBOX_RESET_MAGIC 0xbadf5620 69 70 /* Falcon Message Queue Register Offsets (relative to base_page) */ 71 #define NV_FALCON_QUEUE_HEAD_BASE_OFFSET 0x2c00 72 #define NV_FALCON_QUEUE_TAIL_BASE_OFFSET 0x2c04 73 #define NV_FALCON_QUEUE_STRIDE 0x8 74 #define NV_FALCON_MSG_QUEUE_HEAD_BASE_OFFSET 0x2c80 75 #define NV_FALCON_MSG_QUEUE_TAIL_BASE_OFFSET 0x2c84 76 77 /* FSP Falcon Base Pages */ 78 #define NV_FSP_FALCON_BASE 0x8f0100 79 /* base_page = cpuctl & ~0xfff */ 80 #define NV_FSP_FALCON_BASE_PAGE 0x8f0000 81 #define NV_FSP_EMEM_BASE 0x8f2000 82 83 /* FSP EMEM Port Offsets (relative to FSP EMEM base) */ 84 #define NV_FSP_EMEMC_OFFSET 0xac0 85 #define NV_FSP_EMEMD_OFFSET 0xac4 86 #define NV_FSP_EMEM_PORT_STRIDE 0x8 87 88 /* EMEM Control Register Flags (same as DMEM) */ 89 #define NV_FALCON_EMEMC_AINCR 0x01000000 90 #define NV_FALCON_EMEMC_AINCW 0x02000000 91 92 /* FSP RPC channel configuration */ 93 #define NV_FSP_RPC_CHANNEL_SIZE 1024 94 #define NV_FSP_RPC_MAX_PACKET_SIZE 1024 95 #define NV_FSP_RPC_CHANNEL_HOPPER 2 96 #define NV_FSP_RPC_EMEM_BASE \ 97 (NV_FSP_RPC_CHANNEL_HOPPER * NV_FSP_RPC_CHANNEL_SIZE) 98 99 /* FSP EMEM port 2 registers (pre-computed for Hopper channel 2) */ 100 #define NV_FSP_EMEM_PORT2_CTRL (NV_FSP_EMEM_BASE + NV_FSP_EMEMC_OFFSET + \ 101 NV_FSP_RPC_CHANNEL_HOPPER * NV_FSP_EMEM_PORT_STRIDE) 102 #define NV_FSP_EMEM_PORT2_DATA (NV_FSP_EMEM_BASE + NV_FSP_EMEMD_OFFSET + \ 103 NV_FSP_RPC_CHANNEL_HOPPER * NV_FSP_EMEM_PORT_STRIDE) 104 105 /* FSP queue register offsets (pre-computed for Hopper channel 2) */ 106 #define NV_FSP_QUEUE_HEAD \ 107 (NV_FSP_FALCON_BASE_PAGE + NV_FALCON_QUEUE_HEAD_BASE_OFFSET + \ 108 NV_FSP_RPC_CHANNEL_HOPPER * NV_FALCON_QUEUE_STRIDE) 109 #define NV_FSP_QUEUE_TAIL \ 110 (NV_FSP_FALCON_BASE_PAGE + NV_FALCON_QUEUE_TAIL_BASE_OFFSET + \ 111 NV_FSP_RPC_CHANNEL_HOPPER * NV_FALCON_QUEUE_STRIDE) 112 #define NV_FSP_MSG_QUEUE_HEAD \ 113 (NV_FSP_FALCON_BASE_PAGE + NV_FALCON_MSG_QUEUE_HEAD_BASE_OFFSET + \ 114 NV_FSP_RPC_CHANNEL_HOPPER * NV_FALCON_QUEUE_STRIDE) 115 #define NV_FSP_MSG_QUEUE_TAIL \ 116 (NV_FSP_FALCON_BASE_PAGE + NV_FALCON_MSG_QUEUE_TAIL_BASE_OFFSET + \ 117 NV_FSP_RPC_CHANNEL_HOPPER * NV_FALCON_QUEUE_STRIDE) 118 119 /* MCTP Header */ 120 #define NV_MCTP_HDR_SEID_SHIFT 16 121 #define NV_MCTP_HDR_SEID_MASK 0xff 122 #define NV_MCTP_HDR_SEQ_SHIFT 28 123 #define NV_MCTP_HDR_SEQ_MASK 0x3 124 #define NV_MCTP_HDR_EOM_BIT 0x40000000 125 #define NV_MCTP_HDR_SOM_BIT 0x80000000 126 127 /* MCTP Message Header */ 128 #define NV_MCTP_MSG_TYPE_SHIFT 0 129 #define NV_MCTP_MSG_TYPE_MASK 0x7f 130 #define NV_MCTP_MSG_TYPE_VENDOR_DEFINED 0x7e 131 #define NV_MCTP_MSG_VENDOR_ID_SHIFT 8 132 #define NV_MCTP_MSG_VENDOR_ID_MASK 0xffff 133 #define NV_MCTP_MSG_VENDOR_ID_NVIDIA 0x10de 134 #define NV_MCTP_MSG_NVDM_TYPE_SHIFT 24 135 #define NV_MCTP_MSG_NVDM_TYPE_MASK 0xff 136 137 /* NVDM response type */ 138 #define NV_NVDM_TYPE_RESPONSE 0x15 139 140 /* Minimum response size: mctp_hdr + msg_hdr + status_hdr + type + status */ 141 #define NV_FSP_RPC_MIN_RESPONSE_WORDS 5 142 143 /* FBIF (Frame Buffer Interface) Registers */ 144 /* Legacy PMU FBIF offsets (Kepler, Maxwell Gen1) */ 145 #define NV_PMU_LEGACY_FBIF_CTL_OFFSET 0x624 146 #define NV_PMU_LEGACY_FBIF_TRANSCFG_OFFSET 0x600 147 148 /* PMU FBIF offsets */ 149 #define NV_PMU_FBIF_CTL_OFFSET 0xe24 150 #define NV_PMU_FBIF_TRANSCFG_OFFSET 0xe00 151 152 /* GSP FBIF offsets */ 153 #define NV_GSP_FBIF_CTL_OFFSET 0x624 154 #define NV_GSP_FBIF_TRANSCFG_OFFSET 0x600 155 156 /* OFA Falcon Base Page and FBIF offsets (used for Hopper+ DMA) */ 157 #define NV_OFA_FALCON_BASE 0x844000 158 #define NV_OFA_FBIF_CTL_OFFSET 0x424 159 #define NV_OFA_FBIF_TRANSCFG_OFFSET 0x400 160 161 /* OFA DMA support check register (Hopper+) */ 162 #define NV_OFA_DMA_SUPPORT_CHECK_REG 0x8443c0 163 164 /* FSP NVDM command types */ 165 #define NV_NVDM_TYPE_FBDMA 0x22 166 #define NV_FBDMA_SUBCMD_ENABLE 0x1 167 168 /* FBIF CTL2 offset (relative to fbif_ctl) */ 169 #define NV_FBIF_CTL2_OFFSET 0x60 170 171 /* FBIF TRANSCFG register bits */ 172 #define NV_FBIF_TRANSCFG_TARGET_MASK 0x3 173 #define NV_FBIF_TRANSCFG_SYSMEM_DEFAULT 0x5 174 175 /* FBIF CTL register bits */ 176 #define NV_FBIF_CTL_ALLOW_PHYS_MODE 0x10 177 #define NV_FBIF_CTL_ALLOW_FULL_PHYS_MODE 0x80 178 179 /* Memory clear register offsets */ 180 #define NV_MEM_CLEAR_OFFSET 0x100b20 181 #define NV_BOOT_COMPLETE_OFFSET 0x118234 182 #define NV_BOOT_COMPLETE_SUCCESS 0x3ff 183 184 /* FSP boot complete register (Hopper+) */ 185 #define NV_FSP_BOOT_COMPLETE_OFFSET 0x200bc 186 #define NV_FSP_BOOT_COMPLETE_SUCCESS 0xff 187 188 enum gpu_arch { 189 GPU_ARCH_UNKNOWN = -1, 190 GPU_ARCH_KEPLER = 0, 191 GPU_ARCH_MAXWELL_GEN1, 192 GPU_ARCH_MAXWELL_GEN2, 193 GPU_ARCH_PASCAL, 194 GPU_ARCH_PASCAL_10X, 195 GPU_ARCH_VOLTA, 196 GPU_ARCH_TURING, 197 GPU_ARCH_AMPERE, 198 GPU_ARCH_ADA, 199 GPU_ARCH_HOPPER, 200 }; 201 202 enum falcon_type { 203 FALCON_TYPE_PMU_LEGACY = 0, 204 FALCON_TYPE_PMU, 205 FALCON_TYPE_GSP, 206 FALCON_TYPE_OFA, 207 }; 208 209 struct falcon { 210 u32 base_page; 211 u32 dmactl; 212 u32 engine_reset; 213 u32 fbif_ctl; 214 u32 fbif_ctl2; 215 u32 fbif_transcfg; 216 u32 dmem_control_reg; 217 u32 dmem_data_reg; 218 bool no_outside_reset; 219 }; 220 221 struct gpu_properties { 222 u32 pmc_enable_mask; 223 bool memory_clear_supported; 224 enum falcon_type falcon_type; 225 }; 226 227 static const u32 verified_gpu_map[] = { 228 0x0e40a0a2, /* K520 */ 229 0x0e6000a1, /* GTX660 */ 230 0x0e63a0a1, /* K4000 */ 231 0x0f22d0a1, /* K80 */ 232 0x108000a1, /* GT635 */ 233 0x117010a2, /* GTX750 */ 234 0x117020a2, /* GTX745 */ 235 0x124320a1, /* M60 */ 236 0x130000a1, /* P100 */ 237 0x134000a1, /* P4 */ 238 0x132000a1, /* P40 */ 239 0x140000a1, /* V100 */ 240 0x164000a1, /* T4 */ 241 0xb77000a1, /* A16 */ 242 0x170000a1, /* A100 */ 243 0xb72000a1, /* A10 */ 244 0x180000a1, /* H100 */ 245 0x194000a1, /* L4 */ 246 0x192000a1, /* L40S */ 247 }; 248 249 #define VERIFIED_GPU_MAP_SIZE ARRAY_SIZE(verified_gpu_map) 250 251 static const struct gpu_properties gpu_properties_map[] = { 252 [GPU_ARCH_KEPLER] = { 253 .pmc_enable_mask = NV_PMC_ENABLE_PWR | NV_PMC_ENABLE_HUB, 254 .memory_clear_supported = false, 255 .falcon_type = FALCON_TYPE_PMU_LEGACY, 256 }, 257 [GPU_ARCH_MAXWELL_GEN1] = { 258 .pmc_enable_mask = NV_PMC_ENABLE_PWR | NV_PMC_ENABLE_HUB, 259 .memory_clear_supported = false, 260 .falcon_type = FALCON_TYPE_PMU_LEGACY, 261 }, 262 [GPU_ARCH_MAXWELL_GEN2] = { 263 .pmc_enable_mask = NV_PMC_ENABLE_PWR, 264 .memory_clear_supported = false, 265 .falcon_type = FALCON_TYPE_PMU, 266 }, 267 [GPU_ARCH_PASCAL] = { 268 .pmc_enable_mask = NV_PMC_ENABLE_PWR, 269 .memory_clear_supported = false, 270 .falcon_type = FALCON_TYPE_PMU, 271 }, 272 [GPU_ARCH_PASCAL_10X] = { 273 .pmc_enable_mask = 0, 274 .memory_clear_supported = false, 275 .falcon_type = FALCON_TYPE_PMU, 276 }, 277 [GPU_ARCH_VOLTA] = { 278 .pmc_enable_mask = 0, 279 .memory_clear_supported = false, 280 .falcon_type = FALCON_TYPE_GSP, 281 }, 282 [GPU_ARCH_TURING] = { 283 .pmc_enable_mask = 0, 284 .memory_clear_supported = true, 285 .falcon_type = FALCON_TYPE_GSP, 286 }, 287 [GPU_ARCH_AMPERE] = { 288 .pmc_enable_mask = 0, 289 .memory_clear_supported = true, 290 .falcon_type = FALCON_TYPE_GSP, 291 }, 292 [GPU_ARCH_ADA] = { 293 .pmc_enable_mask = 0, 294 .memory_clear_supported = true, 295 .falcon_type = FALCON_TYPE_PMU, 296 }, 297 [GPU_ARCH_HOPPER] = { 298 .pmc_enable_mask = 0, 299 .memory_clear_supported = true, 300 .falcon_type = FALCON_TYPE_OFA, 301 }, 302 }; 303 304 static const struct falcon falcon_map[] = { 305 [FALCON_TYPE_PMU_LEGACY] = { 306 .base_page = NV_PPWR_FALCON_BASE, 307 .dmactl = NV_PPWR_FALCON_BASE + NV_FALCON_DMACTL_OFFSET, 308 .engine_reset = NV_PPWR_FALCON_BASE + NV_FALCON_ENGINE_RESET_OFFSET, 309 .fbif_ctl = NV_PPWR_FALCON_BASE + NV_PMU_LEGACY_FBIF_CTL_OFFSET, 310 .fbif_ctl2 = NV_PPWR_FALCON_BASE + 311 NV_PMU_LEGACY_FBIF_CTL_OFFSET + NV_FBIF_CTL2_OFFSET, 312 .fbif_transcfg = NV_PPWR_FALCON_BASE + NV_PMU_LEGACY_FBIF_TRANSCFG_OFFSET, 313 .dmem_control_reg = NV_PPWR_FALCON_BASE + NV_FALCON_DMEMC_OFFSET, 314 .dmem_data_reg = NV_PPWR_FALCON_BASE + NV_FALCON_DMEMD_OFFSET, 315 .no_outside_reset = false, 316 }, 317 [FALCON_TYPE_PMU] = { 318 .base_page = NV_PPWR_FALCON_BASE, 319 .dmactl = NV_PPWR_FALCON_BASE + NV_FALCON_DMACTL_OFFSET, 320 .engine_reset = NV_PPWR_FALCON_BASE + NV_FALCON_ENGINE_RESET_OFFSET, 321 .fbif_ctl = NV_PPWR_FALCON_BASE + NV_PMU_FBIF_CTL_OFFSET, 322 .fbif_ctl2 = NV_PPWR_FALCON_BASE + NV_PMU_FBIF_CTL_OFFSET + NV_FBIF_CTL2_OFFSET, 323 .fbif_transcfg = NV_PPWR_FALCON_BASE + NV_PMU_FBIF_TRANSCFG_OFFSET, 324 .dmem_control_reg = NV_PPWR_FALCON_BASE + NV_FALCON_DMEMC_OFFSET, 325 .dmem_data_reg = NV_PPWR_FALCON_BASE + NV_FALCON_DMEMD_OFFSET, 326 .no_outside_reset = false, 327 }, 328 [FALCON_TYPE_GSP] = { 329 .base_page = NV_PGSP_FALCON_BASE, 330 .dmactl = NV_PGSP_FALCON_BASE + NV_FALCON_DMACTL_OFFSET, 331 .engine_reset = NV_PGSP_FALCON_BASE + NV_FALCON_ENGINE_RESET_OFFSET, 332 .fbif_ctl = NV_PGSP_FALCON_BASE + NV_GSP_FBIF_CTL_OFFSET, 333 .fbif_ctl2 = NV_PGSP_FALCON_BASE + NV_GSP_FBIF_CTL_OFFSET + NV_FBIF_CTL2_OFFSET, 334 .fbif_transcfg = NV_PGSP_FALCON_BASE + NV_GSP_FBIF_TRANSCFG_OFFSET, 335 .dmem_control_reg = NV_PGSP_FALCON_BASE + NV_FALCON_DMEMC_OFFSET, 336 .dmem_data_reg = NV_PGSP_FALCON_BASE + NV_FALCON_DMEMD_OFFSET, 337 .no_outside_reset = false, 338 }, 339 [FALCON_TYPE_OFA] = { 340 .base_page = NV_OFA_FALCON_BASE, 341 .dmactl = NV_OFA_FALCON_BASE + NV_FALCON_DMACTL_OFFSET, 342 .engine_reset = NV_OFA_FALCON_BASE + NV_FALCON_ENGINE_RESET_OFFSET, 343 .fbif_ctl = NV_OFA_FALCON_BASE + NV_OFA_FBIF_CTL_OFFSET, 344 .fbif_ctl2 = NV_OFA_FALCON_BASE + NV_OFA_FBIF_CTL_OFFSET + NV_FBIF_CTL2_OFFSET, 345 .fbif_transcfg = NV_OFA_FALCON_BASE + NV_OFA_FBIF_TRANSCFG_OFFSET, 346 .dmem_control_reg = NV_OFA_FALCON_BASE + NV_FALCON_DMEMC_OFFSET, 347 .dmem_data_reg = NV_OFA_FALCON_BASE + NV_FALCON_DMEMD_OFFSET, 348 .no_outside_reset = true, 349 }, 350 }; 351 352 #endif /* _NV_FALCON_HW_H_ */ 353