1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2024 Intel Corporation. */ 3 4 #ifndef _IXGBE_TYPE_E610_H_ 5 #define _IXGBE_TYPE_E610_H_ 6 7 #include <linux/net/intel/libie/adminq.h> 8 9 #define BYTES_PER_DWORD 4 10 11 /* General E610 defines */ 12 #define IXGBE_MAX_VSI 768 13 14 /* Checksum and Shadow RAM pointers */ 15 #define IXGBE_E610_SR_NVM_CTRL_WORD 0x00 16 #define IXGBE_E610_SR_PBA_BLOCK_PTR 0x16 17 #define IXGBE_E610_SR_PBA_BLOCK_MASK GENMASK(15, 8) 18 #define IXGBE_E610_SR_NVM_DEV_STARTER_VER 0x18 19 #define IXGBE_E610_SR_NVM_EETRACK_LO 0x2D 20 #define IXGBE_E610_SR_NVM_EETRACK_HI 0x2E 21 #define IXGBE_E610_NVM_VER_LO_MASK GENMASK(7, 0) 22 #define IXGBE_E610_NVM_VER_HI_MASK GENMASK(15, 12) 23 #define IXGBE_E610_SR_SW_CHECKSUM_WORD 0x3F 24 #define IXGBE_E610_SR_PFA_PTR 0x40 25 #define IXGBE_E610_SR_1ST_NVM_BANK_PTR 0x42 26 #define IXGBE_E610_SR_NVM_BANK_SIZE 0x43 27 #define IXGBE_E610_SR_1ST_OROM_BANK_PTR 0x44 28 #define IXGBE_E610_SR_OROM_BANK_SIZE 0x45 29 #define IXGBE_E610_SR_NETLIST_BANK_PTR 0x46 30 #define IXGBE_E610_SR_NETLIST_BANK_SIZE 0x47 31 32 /* The OROM version topology */ 33 #define IXGBE_OROM_VER_PATCH_MASK GENMASK_ULL(7, 0) 34 #define IXGBE_OROM_VER_BUILD_MASK GENMASK_ULL(23, 8) 35 #define IXGBE_OROM_VER_MASK GENMASK_ULL(31, 24) 36 37 /* CSS Header words */ 38 #define IXGBE_NVM_CSS_HDR_LEN_L 0x02 39 #define IXGBE_NVM_CSS_HDR_LEN_H 0x03 40 #define IXGBE_NVM_CSS_SREV_L 0x14 41 #define IXGBE_NVM_CSS_SREV_H 0x15 42 43 #define IXGBE_HDR_LEN_ROUNDUP 32 44 45 /* Length of Authentication header section in words */ 46 #define IXGBE_NVM_AUTH_HEADER_LEN 0x08 47 48 /* Shadow RAM related */ 49 #define IXGBE_SR_WORDS_IN_1KB 512 50 51 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 52 #define IXGBE_NETLIST_ID_BLK_SIZE 0x30 53 #define IXGBE_NETLIST_ID_BLK_OFFSET(n) IXGBE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 54 55 /* netlist ID block field offsets (word offsets) */ 56 #define IXGBE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 57 #define IXGBE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 58 #define IXGBE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 59 #define IXGBE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 60 #define IXGBE_NETLIST_ID_BLK_TYPE_LOW 0x06 61 #define IXGBE_NETLIST_ID_BLK_TYPE_HIGH 0x07 62 #define IXGBE_NETLIST_ID_BLK_REV_LOW 0x08 63 #define IXGBE_NETLIST_ID_BLK_REV_HIGH 0x09 64 #define IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 65 #define IXGBE_NETLIST_ID_BLK_CUST_VER 0x2F 66 67 /* The Link Topology Netlist section is stored as a series of words. It is 68 * stored in the NVM as a TLV, with the first two words containing the type 69 * and length. 70 */ 71 #define IXGBE_NETLIST_LINK_TOPO_MOD_ID 0x011B 72 #define IXGBE_NETLIST_TYPE_OFFSET 0x0000 73 #define IXGBE_NETLIST_LEN_OFFSET 0x0001 74 75 /* The Link Topology section follows the TLV header. When reading the netlist 76 * using ixgbe_read_netlist_module, we need to account for the 2-word TLV 77 * header. 78 */ 79 #define IXGBE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 80 #define IXGBE_LINK_TOPO_MODULE_LEN IXGBE_NETLIST_LINK_TOPO_OFFSET(0x0000) 81 #define IXGBE_LINK_TOPO_NODE_COUNT IXGBE_NETLIST_LINK_TOPO_OFFSET(0x0001) 82 #define IXGBE_LINK_TOPO_NODE_COUNT_M GENMASK_ULL(9, 0) 83 84 /* Firmware Status Register (GL_FWSTS) */ 85 #define GL_FWSTS 0x00083048 /* Reset Source: POR */ 86 #define GL_FWSTS_EP_PF0 BIT(24) 87 #define GL_FWSTS_EP_PF1 BIT(25) 88 89 /* Global NVM General Status Register */ 90 #define GLNVM_GENS 0x000B6100 /* Reset Source: POR */ 91 #define GLNVM_GENS_SR_SIZE_M GENMASK(7, 5) 92 93 #define IXGBE_GL_MNG_FWSM 0x000B6134 /* Reset Source: POR */ 94 #define IXGBE_GL_MNG_FWSM_RECOVERY_M BIT(1) 95 #define IXGBE_GL_MNG_FWSM_ROLLBACK_M BIT(2) 96 97 /* Flash Access Register */ 98 #define IXGBE_GLNVM_FLA 0x000B6108 /* Reset Source: POR */ 99 #define IXGBE_GLNVM_FLA_LOCKED_S 6 100 #define IXGBE_GLNVM_FLA_LOCKED_M BIT(6) 101 102 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 103 #define IXGBE_SR_CTRL_WORD_1_M GENMASK(7, 6) 104 #define IXGBE_SR_CTRL_WORD_VALID BIT(0) 105 #define IXGBE_SR_CTRL_WORD_OROM_BANK BIT(3) 106 #define IXGBE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 107 #define IXGBE_SR_CTRL_WORD_NVM_BANK BIT(5) 108 #define IXGBE_SR_NVM_PTR_4KB_UNITS BIT(15) 109 110 /* Admin Command Interface (ACI) registers */ 111 #define IXGBE_PF_HIDA(_i) (0x00085000 + ((_i) * 4)) 112 #define IXGBE_PF_HIDA_2(_i) (0x00085020 + ((_i) * 4)) 113 #define IXGBE_PF_HIBA(_i) (0x00084000 + ((_i) * 4)) 114 #define IXGBE_PF_HICR 0x00082048 115 116 #define IXGBE_PF_HICR_EN BIT(0) 117 #define IXGBE_PF_HICR_C BIT(1) 118 #define IXGBE_PF_HICR_SV BIT(2) 119 #define IXGBE_PF_HICR_EV BIT(3) 120 121 #define IXGBE_FW_API_VER_MAJOR 0x01 122 #define IXGBE_FW_API_VER_MINOR 0x07 123 #define IXGBE_FW_API_VER_DIFF_ALLOWED 0x02 124 125 #define IXGBE_ACI_DESC_SIZE 32 126 #define IXGBE_ACI_DESC_SIZE_IN_DWORDS (IXGBE_ACI_DESC_SIZE / BYTES_PER_DWORD) 127 128 #define IXGBE_ACI_MAX_BUFFER_SIZE 4096 /* Size in bytes */ 129 #define IXGBE_ACI_SEND_DELAY_TIME_MS 10 130 #define IXGBE_ACI_SEND_MAX_EXECUTE 3 131 #define IXGBE_ACI_SEND_TIMEOUT_MS \ 132 (IXGBE_ACI_SEND_MAX_EXECUTE * IXGBE_ACI_SEND_DELAY_TIME_MS) 133 /* [ms] timeout of waiting for sync response */ 134 #define IXGBE_ACI_SYNC_RESPONSE_TIMEOUT 100000 135 /* [ms] timeout of waiting for async response */ 136 #define IXGBE_ACI_ASYNC_RESPONSE_TIMEOUT 150000 137 /* [ms] timeout of waiting for resource release */ 138 #define IXGBE_ACI_RELEASE_RES_TIMEOUT 10000 139 140 /* Admin Command Interface (ACI) opcodes */ 141 enum ixgbe_aci_opc { 142 ixgbe_aci_opc_get_ver = 0x0001, 143 ixgbe_aci_opc_driver_ver = 0x0002, 144 ixgbe_aci_opc_get_exp_err = 0x0005, 145 146 /* resource ownership */ 147 ixgbe_aci_opc_req_res = 0x0008, 148 ixgbe_aci_opc_release_res = 0x0009, 149 150 /* device/function capabilities */ 151 ixgbe_aci_opc_list_func_caps = 0x000A, 152 ixgbe_aci_opc_list_dev_caps = 0x000B, 153 154 /* safe disable of RXEN */ 155 ixgbe_aci_opc_disable_rxen = 0x000C, 156 157 /* FW events */ 158 ixgbe_aci_opc_get_fw_event = 0x0014, 159 160 /* PHY commands */ 161 ixgbe_aci_opc_get_phy_caps = 0x0600, 162 ixgbe_aci_opc_set_phy_cfg = 0x0601, 163 ixgbe_aci_opc_restart_an = 0x0605, 164 ixgbe_aci_opc_get_link_status = 0x0607, 165 ixgbe_aci_opc_set_event_mask = 0x0613, 166 ixgbe_aci_opc_get_link_topo = 0x06E0, 167 ixgbe_aci_opc_get_link_topo_pin = 0x06E1, 168 ixgbe_aci_opc_read_i2c = 0x06E2, 169 ixgbe_aci_opc_write_i2c = 0x06E3, 170 ixgbe_aci_opc_read_mdio = 0x06E4, 171 ixgbe_aci_opc_write_mdio = 0x06E5, 172 ixgbe_aci_opc_set_gpio_by_func = 0x06E6, 173 ixgbe_aci_opc_get_gpio_by_func = 0x06E7, 174 ixgbe_aci_opc_set_port_id_led = 0x06E9, 175 ixgbe_aci_opc_set_gpio = 0x06EC, 176 ixgbe_aci_opc_get_gpio = 0x06ED, 177 ixgbe_aci_opc_sff_eeprom = 0x06EE, 178 ixgbe_aci_opc_prog_topo_dev_nvm = 0x06F2, 179 ixgbe_aci_opc_read_topo_dev_nvm = 0x06F3, 180 181 /* NVM commands */ 182 ixgbe_aci_opc_nvm_read = 0x0701, 183 ixgbe_aci_opc_nvm_erase = 0x0702, 184 ixgbe_aci_opc_nvm_write = 0x0703, 185 ixgbe_aci_opc_nvm_cfg_read = 0x0704, 186 ixgbe_aci_opc_nvm_cfg_write = 0x0705, 187 ixgbe_aci_opc_nvm_checksum = 0x0706, 188 ixgbe_aci_opc_nvm_write_activate = 0x0707, 189 ixgbe_aci_opc_nvm_sr_dump = 0x0707, 190 ixgbe_aci_opc_nvm_save_factory_settings = 0x0708, 191 ixgbe_aci_opc_nvm_update_empr = 0x0709, 192 ixgbe_aci_opc_nvm_pkg_data = 0x070A, 193 ixgbe_aci_opc_nvm_pass_component_tbl = 0x070B, 194 195 /* Alternate Structure Commands */ 196 ixgbe_aci_opc_write_alt_direct = 0x0900, 197 ixgbe_aci_opc_write_alt_indirect = 0x0901, 198 ixgbe_aci_opc_read_alt_direct = 0x0902, 199 ixgbe_aci_opc_read_alt_indirect = 0x0903, 200 ixgbe_aci_opc_done_alt_write = 0x0904, 201 ixgbe_aci_opc_clear_port_alt_write = 0x0906, 202 203 /* TCA Events */ 204 ixgbe_aci_opc_temp_tca_event = 0x0C94, 205 206 /* debug commands */ 207 ixgbe_aci_opc_debug_dump_internals = 0xFF08, 208 209 /* SystemDiagnostic commands */ 210 ixgbe_aci_opc_set_health_status_config = 0xFF20, 211 ixgbe_aci_opc_get_supported_health_status_codes = 0xFF21, 212 ixgbe_aci_opc_get_health_status = 0xFF22, 213 ixgbe_aci_opc_clear_health_status = 0xFF23, 214 }; 215 216 #define IXGBE_DRV_VER_STR_LEN_E610 32 217 218 /* Get Expanded Error Code (0x0005, direct) */ 219 struct ixgbe_aci_cmd_get_exp_err { 220 __le32 reason; 221 #define IXGBE_ACI_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 222 __le32 identifier; 223 u8 rsvd[8]; 224 }; 225 226 /* FW update timeout definitions are in milliseconds */ 227 #define IXGBE_NVM_TIMEOUT 180000 228 229 /* Disable RXEN (direct 0x000C) */ 230 struct ixgbe_aci_cmd_disable_rxen { 231 u8 lport_num; 232 u8 reserved[15]; 233 }; 234 235 /* Get PHY capabilities (indirect 0x0600) */ 236 struct ixgbe_aci_cmd_get_phy_caps { 237 u8 lport_num; 238 u8 reserved; 239 __le16 param0; 240 /* 18.0 - Report qualified modules */ 241 #define IXGBE_ACI_GET_PHY_RQM BIT(0) 242 /* 18.1 - 18.3 : Report mode 243 * 000b - Report topology capabilities, without media 244 * 001b - Report topology capabilities, with media 245 * 010b - Report Active configuration 246 * 011b - Report PHY Type and FEC mode capabilities 247 * 100b - Report Default capabilities 248 */ 249 #define IXGBE_ACI_REPORT_MODE_M GENMASK(3, 1) 250 #define IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA 0 251 #define IXGBE_ACI_REPORT_TOPO_CAP_MEDIA BIT(1) 252 #define IXGBE_ACI_REPORT_ACTIVE_CFG BIT(2) 253 #define IXGBE_ACI_REPORT_DFLT_CFG BIT(3) 254 __le32 reserved1; 255 __le32 addr_high; 256 __le32 addr_low; 257 }; 258 259 /* This is #define of PHY type (Extended): 260 * The first set of defines is for phy_type_low. 261 */ 262 #define IXGBE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 263 #define IXGBE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 264 #define IXGBE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 265 #define IXGBE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 266 #define IXGBE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 267 #define IXGBE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 268 #define IXGBE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 269 #define IXGBE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 270 #define IXGBE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 271 #define IXGBE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 272 #define IXGBE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 273 #define IXGBE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 274 #define IXGBE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 275 #define IXGBE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 276 #define IXGBE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 277 #define IXGBE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 278 #define IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 279 #define IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 280 #define IXGBE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 281 #define IXGBE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 282 #define IXGBE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 283 #define IXGBE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 284 #define IXGBE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 285 #define IXGBE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 286 #define IXGBE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 287 #define IXGBE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 288 #define IXGBE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 289 #define IXGBE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 290 #define IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 291 #define IXGBE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 292 #define IXGBE_PHY_TYPE_LOW_MAX_INDEX 29 293 /* The second set of defines is for phy_type_high. */ 294 #define IXGBE_PHY_TYPE_HIGH_10BASE_T BIT_ULL(1) 295 #define IXGBE_PHY_TYPE_HIGH_10M_SGMII BIT_ULL(2) 296 #define IXGBE_PHY_TYPE_HIGH_2500M_SGMII BIT_ULL(56) 297 #define IXGBE_PHY_TYPE_HIGH_100M_USXGMII BIT_ULL(57) 298 #define IXGBE_PHY_TYPE_HIGH_1G_USXGMII BIT_ULL(58) 299 #define IXGBE_PHY_TYPE_HIGH_2500M_USXGMII BIT_ULL(59) 300 #define IXGBE_PHY_TYPE_HIGH_5G_USXGMII BIT_ULL(60) 301 #define IXGBE_PHY_TYPE_HIGH_10G_USXGMII BIT_ULL(61) 302 #define IXGBE_PHY_TYPE_HIGH_MAX_INDEX 61 303 304 struct ixgbe_aci_cmd_get_phy_caps_data { 305 __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 306 __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 307 u8 caps; 308 #define IXGBE_ACI_PHY_EN_TX_LINK_PAUSE BIT(0) 309 #define IXGBE_ACI_PHY_EN_RX_LINK_PAUSE BIT(1) 310 #define IXGBE_ACI_PHY_LOW_POWER_MODE BIT(2) 311 #define IXGBE_ACI_PHY_EN_LINK BIT(3) 312 #define IXGBE_ACI_PHY_AN_MODE BIT(4) 313 #define IXGBE_ACI_PHY_EN_MOD_QUAL BIT(5) 314 #define IXGBE_ACI_PHY_EN_LESM BIT(6) 315 #define IXGBE_ACI_PHY_EN_AUTO_FEC BIT(7) 316 #define IXGBE_ACI_PHY_CAPS_MASK GENMASK(7, 0) 317 u8 low_power_ctrl_an; 318 #define IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 319 #define IXGBE_ACI_PHY_AN_EN_CLAUSE28 BIT(1) 320 #define IXGBE_ACI_PHY_AN_EN_CLAUSE73 BIT(2) 321 #define IXGBE_ACI_PHY_AN_EN_CLAUSE37 BIT(3) 322 __le16 eee_cap; 323 #define IXGBE_ACI_PHY_EEE_EN_100BASE_TX BIT(0) 324 #define IXGBE_ACI_PHY_EEE_EN_1000BASE_T BIT(1) 325 #define IXGBE_ACI_PHY_EEE_EN_10GBASE_T BIT(2) 326 #define IXGBE_ACI_PHY_EEE_EN_5GBASE_T BIT(11) 327 #define IXGBE_ACI_PHY_EEE_EN_2_5GBASE_T BIT(12) 328 __le16 eeer_value; 329 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 330 u8 phy_fw_ver[8]; 331 u8 link_fec_options; 332 #define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 333 #define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 334 #define IXGBE_ACI_PHY_FEC_25G_RS_528_REQ BIT(2) 335 #define IXGBE_ACI_PHY_FEC_25G_KR_REQ BIT(3) 336 #define IXGBE_ACI_PHY_FEC_25G_RS_544_REQ BIT(4) 337 #define IXGBE_ACI_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 338 #define IXGBE_ACI_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 339 #define IXGBE_ACI_PHY_FEC_MASK 0xdf 340 u8 module_compliance_enforcement; 341 #define IXGBE_ACI_MOD_ENFORCE_STRICT_MODE BIT(0) 342 u8 extended_compliance_code; 343 #define IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE 3 344 u8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE]; 345 #define IXGBE_ACI_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 346 #define IXGBE_ACI_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 347 #define IXGBE_ACI_MOD_TYPE_IDENT 1 348 #define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 349 #define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 350 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 351 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 352 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 353 #define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 354 #define IXGBE_ACI_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 355 #define IXGBE_ACI_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 356 u8 qualified_module_count; 357 u8 rsvd2; 358 __le16 eee_entry_delay; 359 u8 rsvd3[4]; 360 #define IXGBE_ACI_QUAL_MOD_COUNT_MAX 16 361 struct { 362 u8 v_oui[3]; 363 u8 rsvd3; 364 u8 v_part[16]; 365 __le32 v_rev; 366 __le64 rsvd4; 367 } qual_modules[IXGBE_ACI_QUAL_MOD_COUNT_MAX]; 368 }; 369 370 /* Set PHY capabilities (direct 0x0601) 371 * NOTE: This command must be followed by setup link and restart auto-neg 372 */ 373 struct ixgbe_aci_cmd_set_phy_cfg { 374 u8 lport_num; 375 u8 reserved[7]; 376 __le32 addr_high; 377 __le32 addr_low; 378 }; 379 380 /* Set PHY config command data structure */ 381 struct ixgbe_aci_cmd_set_phy_cfg_data { 382 __le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */ 383 __le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */ 384 u8 caps; 385 u8 low_power_ctrl_an; 386 __le16 eee_cap; /* Value from ixgbe_aci_get_phy_caps */ 387 __le16 eeer_value; /* Use defines from ixgbe_aci_get_phy_caps */ 388 u8 link_fec_opt; /* Use defines from ixgbe_aci_get_phy_caps */ 389 u8 module_compliance_enforcement; 390 __le16 eee_entry_delay; 391 } __packed; 392 393 /* Set PHY config capabilities (@caps) defines */ 394 #define IXGBE_ACI_PHY_ENA_VALID_MASK 0xef 395 #define IXGBE_ACI_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 396 #define IXGBE_ACI_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 397 #define IXGBE_ACI_PHY_ENA_LOW_POWER BIT(2) 398 #define IXGBE_ACI_PHY_ENA_LINK BIT(3) 399 #define IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT BIT(5) 400 #define IXGBE_ACI_PHY_ENA_LESM BIT(6) 401 #define IXGBE_ACI_PHY_ENA_AUTO_FEC BIT(7) 402 403 /* Restart AN command data structure (direct 0x0605) 404 * Also used for response, with only the lport_num field present. 405 */ 406 struct ixgbe_aci_cmd_restart_an { 407 u8 lport_num; 408 u8 reserved; 409 u8 cmd_flags; 410 #define IXGBE_ACI_RESTART_AN_LINK_RESTART BIT(1) 411 #define IXGBE_ACI_RESTART_AN_LINK_ENABLE BIT(2) 412 u8 reserved2[13]; 413 }; 414 415 /* Get link status (indirect 0x0607), also used for Link Status Event */ 416 struct ixgbe_aci_cmd_get_link_status { 417 u8 lport_num; 418 u8 reserved; 419 __le16 cmd_flags; 420 #define IXGBE_ACI_LSE_M GENMASK(1, 0) 421 #define IXGBE_ACI_LSE_NOP 0x0 422 #define IXGBE_ACI_LSE_DIS 0x2 423 #define IXGBE_ACI_LSE_ENA 0x3 424 /* only response uses this flag */ 425 #define IXGBE_ACI_LSE_IS_ENABLED 0x1 426 __le32 reserved2; 427 __le32 addr_high; 428 __le32 addr_low; 429 }; 430 431 /* Get link status response data structure, also used for Link Status Event */ 432 struct ixgbe_aci_cmd_get_link_status_data { 433 u8 topo_media_conflict; 434 #define IXGBE_ACI_LINK_TOPO_CONFLICT BIT(0) 435 #define IXGBE_ACI_LINK_MEDIA_CONFLICT BIT(1) 436 #define IXGBE_ACI_LINK_TOPO_CORRUPT BIT(2) 437 #define IXGBE_ACI_LINK_TOPO_UNREACH_PRT BIT(4) 438 #define IXGBE_ACI_LINK_TOPO_UNDRUTIL_PRT BIT(5) 439 #define IXGBE_ACI_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 440 #define IXGBE_ACI_LINK_TOPO_UNSUPP_MEDIA BIT(7) 441 u8 link_cfg_err; 442 #define IXGBE_ACI_LINK_CFG_ERR BIT(0) 443 #define IXGBE_ACI_LINK_CFG_COMPLETED BIT(1) 444 #define IXGBE_ACI_LINK_ACT_PORT_OPT_INVAL BIT(2) 445 #define IXGBE_ACI_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 446 #define IXGBE_ACI_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 447 #define IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 448 #define IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 449 #define IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 450 u8 link_info; 451 #define IXGBE_ACI_LINK_UP BIT(0) /* Link Status */ 452 #define IXGBE_ACI_LINK_FAULT BIT(1) 453 #define IXGBE_ACI_LINK_FAULT_TX BIT(2) 454 #define IXGBE_ACI_LINK_FAULT_RX BIT(3) 455 #define IXGBE_ACI_LINK_FAULT_REMOTE BIT(4) 456 #define IXGBE_ACI_LINK_UP_PORT BIT(5) /* External Port Link Status */ 457 #define IXGBE_ACI_MEDIA_AVAILABLE BIT(6) 458 #define IXGBE_ACI_SIGNAL_DETECT BIT(7) 459 u8 an_info; 460 #define IXGBE_ACI_AN_COMPLETED BIT(0) 461 #define IXGBE_ACI_LP_AN_ABILITY BIT(1) 462 #define IXGBE_ACI_PD_FAULT BIT(2) /* Parallel Detection Fault */ 463 #define IXGBE_ACI_FEC_EN BIT(3) 464 #define IXGBE_ACI_PHY_LOW_POWER BIT(4) /* Low Power State */ 465 #define IXGBE_ACI_LINK_PAUSE_TX BIT(5) 466 #define IXGBE_ACI_LINK_PAUSE_RX BIT(6) 467 #define IXGBE_ACI_QUALIFIED_MODULE BIT(7) 468 u8 ext_info; 469 #define IXGBE_ACI_LINK_PHY_TEMP_ALARM BIT(0) 470 #define IXGBE_ACI_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 471 /* Port Tx Suspended */ 472 #define IXGBE_ACI_LINK_TX_ACTIVE 0 473 #define IXGBE_ACI_LINK_TX_DRAINED 1 474 #define IXGBE_ACI_LINK_TX_FLUSHED 3 475 u8 lb_status; 476 #define IXGBE_ACI_LINK_LB_PHY_LCL BIT(0) 477 #define IXGBE_ACI_LINK_LB_PHY_RMT BIT(1) 478 #define IXGBE_ACI_LINK_LB_MAC_LCL BIT(2) 479 __le16 max_frame_size; 480 u8 cfg; 481 #define IXGBE_ACI_LINK_25G_KR_FEC_EN BIT(0) 482 #define IXGBE_ACI_LINK_25G_RS_528_FEC_EN BIT(1) 483 #define IXGBE_ACI_LINK_25G_RS_544_FEC_EN BIT(2) 484 #define IXGBE_ACI_FEC_MASK GENMASK(2, 0) 485 /* Pacing Config */ 486 #define IXGBE_ACI_CFG_PACING_M GENMASK(6, 3) 487 #define IXGBE_ACI_CFG_PACING_TYPE_M BIT(7) 488 #define IXGBE_ACI_CFG_PACING_TYPE_AVG 0 489 #define IXGBE_ACI_CFG_PACING_TYPE_FIXED IXGBE_ACI_CFG_PACING_TYPE_M 490 /* External Device Power Ability */ 491 u8 power_desc; 492 #define IXGBE_ACI_PWR_CLASS_M GENMASK(5, 0) 493 #define IXGBE_ACI_LINK_PWR_BASET_LOW_HIGH 0 494 #define IXGBE_ACI_LINK_PWR_BASET_HIGH 1 495 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_1 0 496 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_2 1 497 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_3 2 498 #define IXGBE_ACI_LINK_PWR_QSFP_CLASS_4 3 499 __le16 link_speed; 500 #define IXGBE_ACI_LINK_SPEED_M GENMASK(10, 0) 501 #define IXGBE_ACI_LINK_SPEED_10MB BIT(0) 502 #define IXGBE_ACI_LINK_SPEED_100MB BIT(1) 503 #define IXGBE_ACI_LINK_SPEED_1000MB BIT(2) 504 #define IXGBE_ACI_LINK_SPEED_2500MB BIT(3) 505 #define IXGBE_ACI_LINK_SPEED_5GB BIT(4) 506 #define IXGBE_ACI_LINK_SPEED_10GB BIT(5) 507 #define IXGBE_ACI_LINK_SPEED_20GB BIT(6) 508 #define IXGBE_ACI_LINK_SPEED_25GB BIT(7) 509 #define IXGBE_ACI_LINK_SPEED_40GB BIT(8) 510 #define IXGBE_ACI_LINK_SPEED_50GB BIT(9) 511 #define IXGBE_ACI_LINK_SPEED_100GB BIT(10) 512 #define IXGBE_ACI_LINK_SPEED_200GB BIT(11) 513 #define IXGBE_ACI_LINK_SPEED_UNKNOWN BIT(15) 514 __le16 reserved3; 515 u8 eee_status; 516 #define IXGBE_ACI_LINK_EEE_ENABLED BIT(2) 517 #define IXGBE_ACI_LINK_EEE_ACTIVE BIT(3) 518 u8 reserved4; 519 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 520 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 521 /* Get link status version 2 link partner data */ 522 __le64 lp_phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 523 __le64 lp_phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 524 u8 lp_fec_adv; 525 #define IXGBE_ACI_LINK_LP_10G_KR_FEC_CAP BIT(0) 526 #define IXGBE_ACI_LINK_LP_25G_KR_FEC_CAP BIT(1) 527 #define IXGBE_ACI_LINK_LP_RS_528_FEC_CAP BIT(2) 528 #define IXGBE_ACI_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 529 #define IXGBE_ACI_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 530 #define IXGBE_ACI_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 531 u8 lp_fec_req; 532 #define IXGBE_ACI_LINK_LP_10G_KR_FEC_REQ BIT(0) 533 #define IXGBE_ACI_LINK_LP_25G_KR_FEC_REQ BIT(1) 534 #define IXGBE_ACI_LINK_LP_RS_528_FEC_REQ BIT(2) 535 #define IXGBE_ACI_LINK_LP_KR_272_FEC_REQ BIT(3) 536 u8 lp_flowcontrol; 537 #define IXGBE_ACI_LINK_LP_PAUSE_ADV BIT(0) 538 #define IXGBE_ACI_LINK_LP_ASM_DIR_ADV BIT(1) 539 u8 reserved5[5]; 540 } __packed; 541 542 /* Set event mask command (direct 0x0613) */ 543 struct ixgbe_aci_cmd_set_event_mask { 544 u8 lport_num; 545 u8 reserved[7]; 546 __le16 event_mask; 547 #define IXGBE_ACI_LINK_EVENT_UPDOWN BIT(1) 548 #define IXGBE_ACI_LINK_EVENT_MEDIA_NA BIT(2) 549 #define IXGBE_ACI_LINK_EVENT_LINK_FAULT BIT(3) 550 #define IXGBE_ACI_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 551 #define IXGBE_ACI_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 552 #define IXGBE_ACI_LINK_EVENT_SIGNAL_DETECT BIT(6) 553 #define IXGBE_ACI_LINK_EVENT_AN_COMPLETED BIT(7) 554 #define IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 555 #define IXGBE_ACI_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 556 #define IXGBE_ACI_LINK_EVENT_TOPO_CONFLICT BIT(10) 557 #define IXGBE_ACI_LINK_EVENT_MEDIA_CONFLICT BIT(11) 558 #define IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 559 u8 reserved1[6]; 560 }; 561 562 struct ixgbe_aci_cmd_link_topo_params { 563 u8 lport_num; 564 u8 lport_num_valid; 565 #define IXGBE_ACI_LINK_TOPO_PORT_NUM_VALID BIT(0) 566 u8 node_type_ctx; 567 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_M GENMASK(3, 0) 568 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_PHY 0 569 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 570 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 571 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED_CTRL 3 572 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED 4 573 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_THERMAL 5 574 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE 6 575 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MEZZ 7 576 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 577 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CLK_CTRL 9 578 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CLK_MUX 10 579 #define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPS 11 580 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_S 4 581 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_M GENMASK(7, 4) 582 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_GLOBAL 0 583 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_BOARD 1 584 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT 2 585 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE 3 586 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE 4 587 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_DIRECT_BUS_ACCESS 5 588 #define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE_BUS_ADDRESS 6 589 u8 index; 590 }; 591 592 struct ixgbe_aci_cmd_link_topo_addr { 593 struct ixgbe_aci_cmd_link_topo_params topo_params; 594 __le16 handle; 595 /* Used to decode the handle field */ 596 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 597 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 598 #define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 599 }; 600 601 /* Get Link Topology Handle (direct, 0x06E0) */ 602 struct ixgbe_aci_cmd_get_link_topo { 603 struct ixgbe_aci_cmd_link_topo_addr addr; 604 u8 node_part_num; 605 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 606 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_ZL30632_80032 0x24 607 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_SI5384 0x25 608 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_C827 0x31 609 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_GEN_CLK_MUX 0x47 610 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48 611 #define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_E610_PTC 0x49 612 u8 rsvd[9]; 613 }; 614 615 /* Get Link Topology Pin (direct, 0x06E1) */ 616 struct ixgbe_aci_cmd_get_link_topo_pin { 617 struct ixgbe_aci_cmd_link_topo_addr addr; 618 u8 input_io_params; 619 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_GPIO 0 620 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RESET_N 1 621 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_INT_N 2 622 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_PRESENT_N 3 623 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_TX_DIS 4 624 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_MODSEL_N 5 625 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_LPMODE 6 626 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_TX_FAULT 7 627 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RX_LOSS 8 628 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RS0 9 629 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RS1 10 630 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_EEPROM_WP 11 631 /* 12 repeats intentionally due to two different uses depending on context */ 632 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_LED 12 633 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_RED_LED 12 634 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_GREEN_LED 13 635 #define IXGBE_ACI_LINK_TOPO_IO_FUNC_BLUE_LED 14 636 #define IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_GPIO 3 637 /* Use IXGBE_ACI_LINK_TOPO_NODE_TYPE_* for the type values */ 638 u8 output_io_params; 639 /* Use IXGBE_ACI_LINK_TOPO_NODE_TYPE_* for the type values */ 640 u8 output_io_flags; 641 #define IXGBE_ACI_LINK_TOPO_OUTPUT_POLARITY BIT(5) 642 #define IXGBE_ACI_LINK_TOPO_OUTPUT_VALUE BIT(6) 643 #define IXGBE_ACI_LINK_TOPO_OUTPUT_DRIVEN BIT(7) 644 u8 rsvd[7]; 645 }; 646 647 /* Set Port Identification LED (direct, 0x06E9) */ 648 struct ixgbe_aci_cmd_set_port_id_led { 649 u8 lport_num; 650 u8 lport_num_valid; 651 u8 ident_mode; 652 u8 rsvd[13]; 653 }; 654 655 #define IXGBE_ACI_PORT_ID_PORT_NUM_VALID BIT(0) 656 #define IXGBE_ACI_PORT_IDENT_LED_ORIG 0 657 #define IXGBE_ACI_PORT_IDENT_LED_BLINK BIT(0) 658 659 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 660 struct ixgbe_aci_cmd_sff_eeprom { 661 u8 lport_num; 662 u8 lport_num_valid; 663 #define IXGBE_ACI_SFF_PORT_NUM_VALID BIT(0) 664 __le16 i2c_bus_addr; 665 #define IXGBE_ACI_SFF_I2CBUS_7BIT_M GENMASK(6, 0) 666 #define IXGBE_ACI_SFF_I2CBUS_10BIT_M GENMASK(9, 0) 667 #define IXGBE_ACI_SFF_I2CBUS_TYPE_M BIT(10) 668 #define IXGBE_ACI_SFF_I2CBUS_TYPE_7BIT 0 669 #define IXGBE_ACI_SFF_I2CBUS_TYPE_10BIT IXGBE_ACI_SFF_I2CBUS_TYPE_M 670 #define IXGBE_ACI_SFF_NO_PAGE_BANK_UPDATE 0 671 #define IXGBE_ACI_SFF_UPDATE_PAGE 1 672 #define IXGBE_ACI_SFF_UPDATE_BANK 2 673 #define IXGBE_ACI_SFF_UPDATE_PAGE_BANK 3 674 #define IXGBE_ACI_SFF_IS_WRITE BIT(15) 675 __le16 i2c_offset; 676 u8 module_bank; 677 u8 module_page; 678 __le32 addr_high; 679 __le32 addr_low; 680 }; 681 682 /* NVM Read command (indirect 0x0701) 683 * NVM Erase commands (direct 0x0702) 684 * NVM Write commands (indirect 0x0703) 685 * NVM Write Activate commands (direct 0x0707) 686 * NVM Shadow RAM Dump commands (direct 0x0707) 687 */ 688 struct ixgbe_aci_cmd_nvm { 689 #define IXGBE_ACI_NVM_MAX_OFFSET 0xFFFFFF 690 __le16 offset_low; 691 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 692 #define IXGBE_ACI_NVM_OFFSET_HI_A_MASK GENMASK(15, 8) 693 #define IXGBE_ACI_NVM_OFFSET_HI_U_MASK GENMASK(23, 16) 694 u8 cmd_flags; 695 #define IXGBE_ACI_NVM_LAST_CMD BIT(0) 696 #define IXGBE_ACI_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 697 #define IXGBE_ACI_NVM_PRESERVE_ALL BIT(1) 698 #define IXGBE_ACI_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 699 #define IXGBE_ACI_NVM_ACTIV_SEL_OROM BIT(4) 700 #define IXGBE_ACI_NVM_ACTIV_SEL_NETLIST BIT(5) 701 #define IXGBE_ACI_NVM_SPECIAL_UPDATE BIT(6) 702 #define IXGBE_ACI_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 703 #define IXGBE_ACI_NVM_FLASH_ONLY BIT(7) 704 #define IXGBE_ACI_NVM_RESET_LVL_M GENMASK(1, 0) /* Write reply only */ 705 #define IXGBE_ACI_NVM_POR_FLAG 0 706 #define IXGBE_ACI_NVM_PERST_FLAG 1 707 #define IXGBE_ACI_NVM_EMPR_FLAG 2 708 #define IXGBE_ACI_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 709 #define IXGBE_ACI_NVM_NO_PRESERVATION 0x0 710 #define IXGBE_ACI_NVM_PRESERVE_SELECTED 0x6 711 712 /* For Write Activate, several flags are sent as part of a separate 713 * flags2 field using a separate byte. For simplicity of the software 714 * interface, we pass the flags as a 16 bit value so these flags are 715 * all offset by 8 bits 716 */ 717 #define IXGBE_ACI_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 718 __le16 module_typeid; 719 __le16 length; 720 #define IXGBE_ACI_NVM_ERASE_LEN 0xFFFF 721 __le32 addr_high; 722 __le32 addr_low; 723 }; 724 725 /* NVM Module_Type ID, needed offset and read_len for 726 * struct ixgbe_aci_cmd_nvm. 727 */ 728 #define IXGBE_ACI_NVM_START_POINT 0 729 730 /* NVM Checksum Command (direct, 0x0706) */ 731 struct ixgbe_aci_cmd_nvm_checksum { 732 u8 flags; 733 #define IXGBE_ACI_NVM_CHECKSUM_VERIFY BIT(0) 734 #define IXGBE_ACI_NVM_CHECKSUM_RECALC BIT(1) 735 u8 rsvd; 736 __le16 checksum; /* Used only by response */ 737 #define IXGBE_ACI_NVM_CHECKSUM_CORRECT 0xBABA 738 u8 rsvd2[12]; 739 }; 740 741 /* Used for NVM Set Package Data command - 0x070A */ 742 struct ixgbe_aci_cmd_nvm_pkg_data { 743 u8 reserved[3]; 744 u8 cmd_flags; 745 #define IXGBE_ACI_NVM_PKG_DELETE BIT(0) /* used for command call */ 746 747 u32 reserved1; 748 __le32 addr_high; 749 __le32 addr_low; 750 }; 751 752 /* Used for Pass Component Table command - 0x070B */ 753 struct ixgbe_aci_cmd_nvm_pass_comp_tbl { 754 u8 component_response; /* Response only */ 755 #define IXGBE_ACI_NVM_PASS_COMP_CAN_BE_UPDATED 0x0 756 #define IXGBE_ACI_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1 757 #define IXGBE_ACI_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2 758 #define IXGBE_ACI_NVM_PASS_COMP_PARTIAL_CHECK 0x3 759 u8 component_response_code; /* Response only */ 760 #define IXGBE_ACI_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0 761 #define IXGBE_ACI_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1 762 #define IXGBE_ACI_NVM_PASS_COMP_STAMP_LOWER 0x2 763 #define IXGBE_ACI_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3 764 #define IXGBE_ACI_NVM_PASS_COMP_CONFLICT_CODE 0x4 765 #define IXGBE_ACI_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5 766 #define IXGBE_ACI_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6 767 #define IXGBE_ACI_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7 768 #define IXGBE_ACI_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8 769 #define IXGBE_ACI_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA 770 #define IXGBE_ACI_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB 771 u8 reserved; 772 u8 transfer_flag; 773 __le32 reserved1; 774 __le32 addr_high; 775 __le32 addr_low; 776 }; 777 778 struct ixgbe_aci_cmd_nvm_comp_tbl { 779 __le16 comp_class; 780 #define NVM_COMP_CLASS_ALL_FW 0x000A 781 782 __le16 comp_id; 783 #define NVM_COMP_ID_OROM 0x5 784 #define NVM_COMP_ID_NVM 0x6 785 #define NVM_COMP_ID_NETLIST 0x8 786 787 u8 comp_class_idx; 788 #define FWU_COMP_CLASS_IDX_NOT_USE 0x0 789 790 __le32 comp_cmp_stamp; 791 u8 cvs_type; 792 #define NVM_CVS_TYPE_ASCII 0x1 793 794 u8 cvs_len; 795 u8 cvs[]; /* Component Version String */ 796 } __packed; 797 798 /* E610-specific adapter context structures */ 799 800 struct ixgbe_link_status { 801 /* Refer to ixgbe_aci_phy_type for bits definition */ 802 u64 phy_type_low; 803 u64 phy_type_high; 804 u16 max_frame_size; 805 u16 link_speed; 806 u16 req_speeds; 807 u8 topo_media_conflict; 808 u8 link_cfg_err; 809 u8 lse_ena; /* Link Status Event notification */ 810 u8 link_info; 811 u8 an_info; 812 u8 ext_info; 813 u8 fec_info; 814 u8 pacing; 815 /* Refer to #define from module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE] 816 * of ixgbe_aci_get_phy_caps structure 817 */ 818 u8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE]; 819 u8 eee_status; 820 }; 821 822 /* Common HW capabilities for SW use */ 823 struct ixgbe_hw_caps { 824 /* Write CSR protection */ 825 u64 wr_csr_prot; 826 u32 switching_mode; 827 /* switching mode supported - EVB switching (including cloud) */ 828 #define IXGBE_NVM_IMAGE_TYPE_EVB 0x0 829 830 /* Manageability mode & supported protocols over MCTP */ 831 u32 mgmt_mode; 832 #define IXGBE_MGMT_MODE_PASS_THRU_MODE_M GENMASK(3, 0) 833 #define IXGBE_MGMT_MODE_CTL_INTERFACE_M GENMASK(7, 4) 834 #define IXGBE_MGMT_MODE_REDIR_SB_INTERFACE_M GENMASK(11, 8) 835 836 u32 mgmt_protocols_mctp; 837 #define IXGBE_MGMT_MODE_PROTO_RSVD BIT(0) 838 #define IXGBE_MGMT_MODE_PROTO_PLDM BIT(1) 839 #define IXGBE_MGMT_MODE_PROTO_OEM BIT(2) 840 #define IXGBE_MGMT_MODE_PROTO_NC_SI BIT(3) 841 842 u32 os2bmc; 843 u32 valid_functions; 844 /* DCB capabilities */ 845 u32 active_tc_bitmap; 846 u32 maxtc; 847 848 /* RSS related capabilities */ 849 u32 rss_table_size; /* 512 for PFs and 64 for VFs */ 850 u32 rss_table_entry_width; /* RSS Entry width in bits */ 851 852 /* Tx/Rx queues */ 853 u32 num_rxq; /* Number/Total Rx queues */ 854 u32 rxq_first_id; /* First queue ID for Rx queues */ 855 u32 num_txq; /* Number/Total Tx queues */ 856 u32 txq_first_id; /* First queue ID for Tx queues */ 857 858 /* MSI-X vectors */ 859 u32 num_msix_vectors; 860 u32 msix_vector_first_id; 861 862 /* Max MTU for function or device */ 863 u32 max_mtu; 864 865 /* WOL related */ 866 u32 num_wol_proxy_fltr; 867 u32 wol_proxy_vsi_seid; 868 869 /* LED/SDP pin count */ 870 u32 led_pin_num; 871 u32 sdp_pin_num; 872 873 /* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */ 874 #define IXGBE_MAX_SUPPORTED_GPIO_LED 12 875 #define IXGBE_MAX_SUPPORTED_GPIO_SDP 8 876 u8 led[IXGBE_MAX_SUPPORTED_GPIO_LED]; 877 u8 sdp[IXGBE_MAX_SUPPORTED_GPIO_SDP]; 878 /* SR-IOV virtualization */ 879 u8 sr_iov_1_1; /* SR-IOV enabled */ 880 /* VMDQ */ 881 u8 vmdq; /* VMDQ supported */ 882 883 /* EVB capabilities */ 884 u8 evb_802_1_qbg; /* Edge Virtual Bridging */ 885 u8 evb_802_1_qbh; /* Bridge Port Extension */ 886 887 u8 dcb; 888 u8 iscsi; 889 u8 ieee_1588; 890 u8 mgmt_cem; 891 892 /* WoL and APM support */ 893 #define IXGBE_WOL_SUPPORT_M BIT(0) 894 #define IXGBE_ACPI_PROG_MTHD_M BIT(1) 895 #define IXGBE_PROXY_SUPPORT_M BIT(2) 896 u8 apm_wol_support; 897 u8 acpi_prog_mthd; 898 u8 proxy_support; 899 u8 eee_support; 900 bool nvm_update_pending_nvm; 901 bool nvm_update_pending_orom; 902 bool nvm_update_pending_netlist; 903 #define IXGBE_NVM_PENDING_NVM_IMAGE BIT(0) 904 #define IXGBE_NVM_PENDING_OROM BIT(1) 905 #define IXGBE_NVM_PENDING_NETLIST BIT(2) 906 bool sec_rev_disabled; 907 bool update_disabled; 908 bool nvm_unified_update; 909 bool netlist_auth; 910 #define IXGBE_NVM_MGMT_SEC_REV_DISABLED BIT(0) 911 #define IXGBE_NVM_MGMT_UPDATE_DISABLED BIT(1) 912 #define IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 913 #define IXGBE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5) 914 bool no_drop_policy_support; 915 /* PCIe reset avoidance */ 916 bool pcie_reset_avoidance; /* false: not supported, true: supported */ 917 /* Post update reset restriction */ 918 bool reset_restrict_support; /* false: not supported, true: supported */ 919 920 /* External topology device images within the NVM */ 921 #define IXGBE_EXT_TOPO_DEV_IMG_COUNT 4 922 u32 ext_topo_dev_img_ver_high[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 923 u32 ext_topo_dev_img_ver_low[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 924 u8 ext_topo_dev_img_part_num[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 925 #define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S 8 926 #define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M GENMASK(15, 8) 927 bool ext_topo_dev_img_load_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 928 #define IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN BIT(0) 929 bool ext_topo_dev_img_prog_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT]; 930 #define IXGBE_EXT_TOPO_DEV_IMG_PROG_EN BIT(1) 931 } __packed; 932 933 #define IXGBE_OROM_CIV_SIGNATURE "$CIV" 934 935 struct ixgbe_orom_civd_info { 936 u8 signature[4]; /* Must match ASCII '$CIV' characters */ 937 u8 checksum; /* Simple modulo 256 sum of all structure bytes must equal 0 */ 938 __le32 combo_ver; /* Combo Image Version number */ 939 u8 combo_name_len; /* Length of the unicode combo image version string, max of 32 */ 940 __le16 combo_name[32]; /* Unicode string representing the Combo Image version */ 941 } __packed; 942 943 /* Function specific capabilities */ 944 struct ixgbe_hw_func_caps { 945 u32 num_allocd_vfs; /* Number of allocated VFs */ 946 u32 vf_base_id; /* Logical ID of the first VF */ 947 u32 guar_num_vsi; 948 struct ixgbe_hw_caps common_cap; 949 bool no_drop_policy_ena; 950 }; 951 952 /* Device wide capabilities */ 953 struct ixgbe_hw_dev_caps { 954 struct ixgbe_hw_caps common_cap; 955 u32 num_vfs_exposed; /* Total number of VFs exposed */ 956 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 957 u32 num_flow_director_fltr; /* Number of FD filters available */ 958 u32 num_funcs; 959 }; 960 961 /* ACI event information */ 962 struct ixgbe_aci_event { 963 struct libie_aq_desc desc; 964 u8 *msg_buf; 965 u16 msg_len; 966 u16 buf_len; 967 }; 968 969 struct ixgbe_aci_info { 970 struct mutex lock; /* admin command interface lock */ 971 enum libie_aq_err last_status; /* last status of sent admin command */ 972 }; 973 974 enum ixgbe_bank_select { 975 IXGBE_ACTIVE_FLASH_BANK, 976 IXGBE_INACTIVE_FLASH_BANK, 977 }; 978 979 /* Option ROM version information */ 980 struct ixgbe_orom_info { 981 u8 major; /* Major version of OROM */ 982 u8 patch; /* Patch version of OROM */ 983 u16 build; /* Build version of OROM */ 984 u32 srev; /* Security revision */ 985 }; 986 987 /* NVM version information */ 988 struct ixgbe_nvm_info { 989 u32 eetrack; 990 u32 srev; 991 u8 major; 992 u8 minor; 993 } __packed; 994 995 /* netlist version information */ 996 struct ixgbe_netlist_info { 997 u32 major; /* major high/low */ 998 u32 minor; /* minor high/low */ 999 u32 type; /* type high/low */ 1000 u32 rev; /* revision high/low */ 1001 u32 hash; /* SHA-1 hash word */ 1002 u16 cust_ver; /* customer version */ 1003 } __packed; 1004 1005 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 1006 * of the flash image. 1007 */ 1008 enum ixgbe_flash_bank { 1009 IXGBE_INVALID_FLASH_BANK, 1010 IXGBE_1ST_FLASH_BANK, 1011 IXGBE_2ND_FLASH_BANK, 1012 }; 1013 1014 /* information for accessing NVM, OROM, and Netlist flash banks */ 1015 struct ixgbe_bank_info { 1016 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 1017 u32 nvm_size; /* Size of NVM bank */ 1018 u32 orom_ptr; /* Pointer to 1st OROM bank */ 1019 u32 orom_size; /* Size of OROM bank */ 1020 u32 netlist_ptr; /* Ptr to 1st Netlist bank */ 1021 u32 netlist_size; /* Size of Netlist bank */ 1022 enum ixgbe_flash_bank nvm_bank; /* Active NVM bank */ 1023 enum ixgbe_flash_bank orom_bank; /* Active OROM bank */ 1024 enum ixgbe_flash_bank netlist_bank; /* Active Netlist bank */ 1025 }; 1026 1027 /* Flash Chip Information */ 1028 struct ixgbe_flash_info { 1029 struct ixgbe_orom_info orom; /* Option ROM version info */ 1030 u32 flash_size; /* Available flash size in bytes */ 1031 struct ixgbe_nvm_info nvm; /* NVM version information */ 1032 struct ixgbe_netlist_info netlist; /* Netlist version info */ 1033 struct ixgbe_bank_info banks; /* Flash Bank information */ 1034 u16 sr_words; /* Shadow RAM size in words */ 1035 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 1036 }; 1037 1038 #endif /* _IXGBE_TYPE_E610_H_ */ 1039