1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
13
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
16
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
19
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23
24 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25
26 #define NVME_NSID_ALL 0xffffffff
27
28 /* Special NSSR value, 'NVMe' */
29 #define NVME_SUBSYS_RESET 0x4E564D65
30
31 enum nvme_subsys_type {
32 /* Referral to another discovery type target subsystem */
33 NVME_NQN_DISC = 1,
34
35 /* NVME type target subsystem */
36 NVME_NQN_NVME = 2,
37
38 /* Current discovery type target subsystem */
39 NVME_NQN_CURR = 3,
40 };
41
42 enum nvme_ctrl_type {
43 NVME_CTRL_IO = 1, /* I/O controller */
44 NVME_CTRL_DISC = 2, /* Discovery controller */
45 NVME_CTRL_ADMIN = 3, /* Administrative controller */
46 };
47
48 enum nvme_dctype {
49 NVME_DCTYPE_NOT_REPORTED = 0,
50 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
51 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
52 };
53
54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
55 enum {
56 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
57 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
58 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
59 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
60 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
61 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
62 NVMF_ADDR_FAMILY_MAX,
63 };
64
65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
66 enum {
67 NVMF_TRTYPE_RDMA = 1, /* RDMA */
68 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
69 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
70 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
71 NVMF_TRTYPE_MAX,
72 };
73
74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
75 enum {
76 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
77 NVMF_TREQ_REQUIRED = 1, /* Required */
78 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
79 #define NVME_TREQ_SECURE_CHANNEL_MASK \
80 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
81
82 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
83 };
84
85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
86 * RDMA_QPTYPE field
87 */
88 enum {
89 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
90 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
91 NVMF_RDMA_QPTYPE_INVALID = 0xff,
92 };
93
94 /* RDMA Provider Type codes for Discovery Log Page entry TSAS
95 * RDMA_PRTYPE field
96 */
97 enum {
98 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
99 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
100 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
101 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
102 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
103 };
104
105 /* RDMA Connection Management Service Type codes for Discovery Log Page
106 * entry TSAS RDMA_CMS field
107 */
108 enum {
109 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
110 };
111
112 /* TSAS SECTYPE for TCP transport */
113 enum {
114 NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
115 NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
116 NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
117 NVMF_TCP_SECTYPE_INVALID = 0xff,
118 };
119
120 #define NVME_AQ_DEPTH 32
121 #define NVME_NR_AEN_COMMANDS 1
122 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
123
124 /*
125 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
126 * NVM-Express 1.2 specification, section 4.1.2.
127 */
128 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
129
130 enum {
131 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
132 NVME_REG_VS = 0x0008, /* Version */
133 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
134 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
135 NVME_REG_CC = 0x0014, /* Controller Configuration */
136 NVME_REG_CSTS = 0x001c, /* Controller Status */
137 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
138 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
139 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
140 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
141 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
142 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
143 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
144 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
145 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
146 * Location
147 */
148 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
149 * Space Control
150 */
151 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
152 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
153 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
154 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
155 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
156 * Buffer Size
157 */
158 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
159 * Write Throughput
160 */
161 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
162 };
163
164 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
165 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
166 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
167 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
168 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
169 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
170 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
171 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
172
173 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
174 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
175
176 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
177 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
178
179 enum {
180 NVME_CMBSZ_SQS = 1 << 0,
181 NVME_CMBSZ_CQS = 1 << 1,
182 NVME_CMBSZ_LISTS = 1 << 2,
183 NVME_CMBSZ_RDS = 1 << 3,
184 NVME_CMBSZ_WDS = 1 << 4,
185
186 NVME_CMBSZ_SZ_SHIFT = 12,
187 NVME_CMBSZ_SZ_MASK = 0xfffff,
188
189 NVME_CMBSZ_SZU_SHIFT = 8,
190 NVME_CMBSZ_SZU_MASK = 0xf,
191 };
192
193 /*
194 * Submission and Completion Queue Entry Sizes for the NVM command set.
195 * (In bytes and specified as a power of two (2^n)).
196 */
197 #define NVME_ADM_SQES 6
198 #define NVME_NVM_IOSQES 6
199 #define NVME_NVM_IOCQES 4
200
201 enum {
202 NVME_CC_ENABLE = 1 << 0,
203 NVME_CC_EN_SHIFT = 0,
204 NVME_CC_CSS_SHIFT = 4,
205 NVME_CC_MPS_SHIFT = 7,
206 NVME_CC_AMS_SHIFT = 11,
207 NVME_CC_SHN_SHIFT = 14,
208 NVME_CC_IOSQES_SHIFT = 16,
209 NVME_CC_IOCQES_SHIFT = 20,
210 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
211 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
212 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
213 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
214 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
215 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
216 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
217 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
218 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
219 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
220 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
221 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
222 NVME_CC_CRIME = 1 << 24,
223 };
224
225 enum {
226 NVME_CSTS_RDY = 1 << 0,
227 NVME_CSTS_CFS = 1 << 1,
228 NVME_CSTS_NSSRO = 1 << 4,
229 NVME_CSTS_PP = 1 << 5,
230 NVME_CSTS_SHST_NORMAL = 0 << 2,
231 NVME_CSTS_SHST_OCCUR = 1 << 2,
232 NVME_CSTS_SHST_CMPLT = 2 << 2,
233 NVME_CSTS_SHST_MASK = 3 << 2,
234 };
235
236 enum {
237 NVME_CMBMSC_CRE = 1 << 0,
238 NVME_CMBMSC_CMSE = 1 << 1,
239 };
240
241 enum {
242 NVME_CAP_CSS_NVM = 1 << 0,
243 NVME_CAP_CSS_CSI = 1 << 6,
244 };
245
246 enum {
247 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
248 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
249 };
250
251 struct nvme_id_power_state {
252 __le16 max_power; /* centiwatts */
253 __u8 rsvd2;
254 __u8 flags;
255 __le32 entry_lat; /* microseconds */
256 __le32 exit_lat; /* microseconds */
257 __u8 read_tput;
258 __u8 read_lat;
259 __u8 write_tput;
260 __u8 write_lat;
261 __le16 idle_power;
262 __u8 idle_scale;
263 __u8 rsvd19;
264 __le16 active_power;
265 __u8 active_work_scale;
266 __u8 rsvd23[9];
267 };
268
269 enum {
270 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
271 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
272 };
273
274 enum nvme_ctrl_attr {
275 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
276 NVME_CTRL_ATTR_TBKAS = (1 << 6),
277 NVME_CTRL_ATTR_ELBAS = (1 << 15),
278 };
279
280 struct nvme_id_ctrl {
281 __le16 vid;
282 __le16 ssvid;
283 char sn[20];
284 char mn[40];
285 char fr[8];
286 __u8 rab;
287 __u8 ieee[3];
288 __u8 cmic;
289 __u8 mdts;
290 __le16 cntlid;
291 __le32 ver;
292 __le32 rtd3r;
293 __le32 rtd3e;
294 __le32 oaes;
295 __le32 ctratt;
296 __u8 rsvd100[11];
297 __u8 cntrltype;
298 __u8 fguid[16];
299 __le16 crdt1;
300 __le16 crdt2;
301 __le16 crdt3;
302 __u8 rsvd134[122];
303 __le16 oacs;
304 __u8 acl;
305 __u8 aerl;
306 __u8 frmw;
307 __u8 lpa;
308 __u8 elpe;
309 __u8 npss;
310 __u8 avscc;
311 __u8 apsta;
312 __le16 wctemp;
313 __le16 cctemp;
314 __le16 mtfa;
315 __le32 hmpre;
316 __le32 hmmin;
317 __u8 tnvmcap[16];
318 __u8 unvmcap[16];
319 __le32 rpmbs;
320 __le16 edstt;
321 __u8 dsto;
322 __u8 fwug;
323 __le16 kas;
324 __le16 hctma;
325 __le16 mntmt;
326 __le16 mxtmt;
327 __le32 sanicap;
328 __le32 hmminds;
329 __le16 hmmaxd;
330 __le16 nvmsetidmax;
331 __le16 endgidmax;
332 __u8 anatt;
333 __u8 anacap;
334 __le32 anagrpmax;
335 __le32 nanagrpid;
336 __u8 rsvd352[160];
337 __u8 sqes;
338 __u8 cqes;
339 __le16 maxcmd;
340 __le32 nn;
341 __le16 oncs;
342 __le16 fuses;
343 __u8 fna;
344 __u8 vwc;
345 __le16 awun;
346 __le16 awupf;
347 __u8 nvscc;
348 __u8 nwpc;
349 __le16 acwu;
350 __u8 rsvd534[2];
351 __le32 sgls;
352 __le32 mnan;
353 __u8 rsvd544[224];
354 char subnqn[256];
355 __u8 rsvd1024[768];
356 __le32 ioccsz;
357 __le32 iorcsz;
358 __le16 icdoff;
359 __u8 ctrattr;
360 __u8 msdbd;
361 __u8 rsvd1804[2];
362 __u8 dctype;
363 __u8 rsvd1807[241];
364 struct nvme_id_power_state psd[32];
365 __u8 vs[1024];
366 };
367
368 enum {
369 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
370 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
371 NVME_CTRL_CMIC_ANA = 1 << 3,
372 NVME_CTRL_ONCS_COMPARE = 1 << 0,
373 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
374 NVME_CTRL_ONCS_DSM = 1 << 2,
375 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
376 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
377 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
378 NVME_CTRL_VWC_PRESENT = 1 << 0,
379 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
380 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
381 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
382 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
383 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
384 NVME_CTRL_CTRATT_128_ID = 1 << 0,
385 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
386 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
387 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
388 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
389 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
390 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
391 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
392 NVME_CTRL_SGLS_BYTE_ALIGNED = 1,
393 NVME_CTRL_SGLS_DWORD_ALIGNED = 2,
394 NVME_CTRL_SGLS_KSDBDS = 1 << 2,
395 NVME_CTRL_SGLS_MSDS = 1 << 19,
396 NVME_CTRL_SGLS_SAOS = 1 << 20,
397 };
398
399 struct nvme_lbaf {
400 __le16 ms;
401 __u8 ds;
402 __u8 rp;
403 };
404
405 struct nvme_id_ns {
406 __le64 nsze;
407 __le64 ncap;
408 __le64 nuse;
409 __u8 nsfeat;
410 __u8 nlbaf;
411 __u8 flbas;
412 __u8 mc;
413 __u8 dpc;
414 __u8 dps;
415 __u8 nmic;
416 __u8 rescap;
417 __u8 fpi;
418 __u8 dlfeat;
419 __le16 nawun;
420 __le16 nawupf;
421 __le16 nacwu;
422 __le16 nabsn;
423 __le16 nabo;
424 __le16 nabspf;
425 __le16 noiob;
426 __u8 nvmcap[16];
427 __le16 npwg;
428 __le16 npwa;
429 __le16 npdg;
430 __le16 npda;
431 __le16 nows;
432 __u8 rsvd74[18];
433 __le32 anagrpid;
434 __u8 rsvd96[3];
435 __u8 nsattr;
436 __le16 nvmsetid;
437 __le16 endgid;
438 __u8 nguid[16];
439 __u8 eui64[8];
440 struct nvme_lbaf lbaf[64];
441 __u8 vs[3712];
442 };
443
444 /* I/O Command Set Independent Identify Namespace Data Structure */
445 struct nvme_id_ns_cs_indep {
446 __u8 nsfeat;
447 __u8 nmic;
448 __u8 rescap;
449 __u8 fpi;
450 __le32 anagrpid;
451 __u8 nsattr;
452 __u8 rsvd9;
453 __le16 nvmsetid;
454 __le16 endgid;
455 __u8 nstat;
456 __u8 rsvd15[4081];
457 };
458
459 struct nvme_zns_lbafe {
460 __le64 zsze;
461 __u8 zdes;
462 __u8 rsvd9[7];
463 };
464
465 struct nvme_id_ns_zns {
466 __le16 zoc;
467 __le16 ozcs;
468 __le32 mar;
469 __le32 mor;
470 __le32 rrl;
471 __le32 frl;
472 __u8 rsvd20[2796];
473 struct nvme_zns_lbafe lbafe[64];
474 __u8 vs[256];
475 };
476
477 struct nvme_id_ctrl_zns {
478 __u8 zasl;
479 __u8 rsvd1[4095];
480 };
481
482 struct nvme_id_ns_nvm {
483 __le64 lbstm;
484 __u8 pic;
485 __u8 rsvd9[3];
486 __le32 elbaf[64];
487 __u8 rsvd268[3828];
488 };
489
490 enum {
491 NVME_ID_NS_NVM_STS_MASK = 0x7f,
492 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
493 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
494 NVME_ID_NS_NVM_QPIF_SHIFT = 9,
495 NVME_ID_NS_NVM_QPIF_MASK = 0xf,
496 NVME_ID_NS_NVM_QPIFS = 1 << 3,
497 };
498
nvme_elbaf_sts(__u32 elbaf)499 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
500 {
501 return elbaf & NVME_ID_NS_NVM_STS_MASK;
502 }
503
nvme_elbaf_guard_type(__u32 elbaf)504 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
505 {
506 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
507 }
508
nvme_elbaf_qualified_guard_type(__u32 elbaf)509 static inline __u8 nvme_elbaf_qualified_guard_type(__u32 elbaf)
510 {
511 return (elbaf >> NVME_ID_NS_NVM_QPIF_SHIFT) & NVME_ID_NS_NVM_QPIF_MASK;
512 }
513
514 struct nvme_id_ctrl_nvm {
515 __u8 vsl;
516 __u8 wzsl;
517 __u8 wusl;
518 __u8 dmrl;
519 __le32 dmrsl;
520 __le64 dmsl;
521 __u8 rsvd16[4080];
522 };
523
524 enum {
525 NVME_ID_CNS_NS = 0x00,
526 NVME_ID_CNS_CTRL = 0x01,
527 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
528 NVME_ID_CNS_NS_DESC_LIST = 0x03,
529 NVME_ID_CNS_CS_NS = 0x05,
530 NVME_ID_CNS_CS_CTRL = 0x06,
531 NVME_ID_CNS_NS_ACTIVE_LIST_CS = 0x07,
532 NVME_ID_CNS_NS_CS_INDEP = 0x08,
533 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
534 NVME_ID_CNS_NS_PRESENT = 0x11,
535 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
536 NVME_ID_CNS_CTRL_LIST = 0x13,
537 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
538 NVME_ID_CNS_NS_GRANULARITY = 0x16,
539 NVME_ID_CNS_UUID_LIST = 0x17,
540 NVME_ID_CNS_ENDGRP_LIST = 0x19,
541 };
542
543 enum {
544 NVME_CSI_NVM = 0,
545 NVME_CSI_ZNS = 2,
546 };
547
548 enum {
549 NVME_DIR_IDENTIFY = 0x00,
550 NVME_DIR_STREAMS = 0x01,
551 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
552 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
553 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
554 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
555 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
556 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
557 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
558 NVME_DIR_ENDIR = 0x01,
559 };
560
561 enum {
562 NVME_NS_FEAT_THIN = 1 << 0,
563 NVME_NS_FEAT_ATOMICS = 1 << 1,
564 NVME_NS_FEAT_IO_OPT = 1 << 4,
565 NVME_NS_ATTR_RO = 1 << 0,
566 NVME_NS_FLBAS_LBA_MASK = 0xf,
567 NVME_NS_FLBAS_LBA_UMASK = 0x60,
568 NVME_NS_FLBAS_LBA_SHIFT = 1,
569 NVME_NS_FLBAS_META_EXT = 0x10,
570 NVME_NS_NMIC_SHARED = 1 << 0,
571 NVME_NS_ROTATIONAL = 1 << 4,
572 NVME_NS_VWC_NOT_PRESENT = 1 << 5,
573 NVME_LBAF_RP_BEST = 0,
574 NVME_LBAF_RP_BETTER = 1,
575 NVME_LBAF_RP_GOOD = 2,
576 NVME_LBAF_RP_DEGRADED = 3,
577 NVME_NS_DPC_PI_LAST = 1 << 4,
578 NVME_NS_DPC_PI_FIRST = 1 << 3,
579 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
580 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
581 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
582 NVME_NS_DPS_PI_FIRST = 1 << 3,
583 NVME_NS_DPS_PI_MASK = 0x7,
584 NVME_NS_DPS_PI_TYPE1 = 1,
585 NVME_NS_DPS_PI_TYPE2 = 2,
586 NVME_NS_DPS_PI_TYPE3 = 3,
587 };
588
589 enum {
590 NVME_NSTAT_NRDY = 1 << 0,
591 };
592
593 enum {
594 NVME_NVM_NS_16B_GUARD = 0,
595 NVME_NVM_NS_32B_GUARD = 1,
596 NVME_NVM_NS_64B_GUARD = 2,
597 NVME_NVM_NS_QTYPE_GUARD = 3,
598 };
599
nvme_lbaf_index(__u8 flbas)600 static inline __u8 nvme_lbaf_index(__u8 flbas)
601 {
602 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
603 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
604 }
605
606 /* Identify Namespace Metadata Capabilities (MC): */
607 enum {
608 NVME_MC_EXTENDED_LBA = (1 << 0),
609 NVME_MC_METADATA_PTR = (1 << 1),
610 };
611
612 struct nvme_ns_id_desc {
613 __u8 nidt;
614 __u8 nidl;
615 __le16 reserved;
616 };
617
618 #define NVME_NIDT_EUI64_LEN 8
619 #define NVME_NIDT_NGUID_LEN 16
620 #define NVME_NIDT_UUID_LEN 16
621 #define NVME_NIDT_CSI_LEN 1
622
623 enum {
624 NVME_NIDT_EUI64 = 0x01,
625 NVME_NIDT_NGUID = 0x02,
626 NVME_NIDT_UUID = 0x03,
627 NVME_NIDT_CSI = 0x04,
628 };
629
630 struct nvme_endurance_group_log {
631 __u8 egcw;
632 __u8 egfeat;
633 __u8 rsvd2;
634 __u8 avsp;
635 __u8 avspt;
636 __u8 pused;
637 __le16 did;
638 __u8 rsvd8[24];
639 __u8 ee[16];
640 __u8 dur[16];
641 __u8 duw[16];
642 __u8 muw[16];
643 __u8 hrc[16];
644 __u8 hwc[16];
645 __u8 mdie[16];
646 __u8 neile[16];
647 __u8 tegcap[16];
648 __u8 uegcap[16];
649 __u8 rsvd192[320];
650 };
651
652 struct nvme_rotational_media_log {
653 __le16 endgid;
654 __le16 numa;
655 __le16 nrs;
656 __u8 rsvd6[2];
657 __le32 spinc;
658 __le32 fspinc;
659 __le32 ldc;
660 __le32 fldc;
661 __u8 rsvd24[488];
662 };
663
664 struct nvme_smart_log {
665 __u8 critical_warning;
666 __u8 temperature[2];
667 __u8 avail_spare;
668 __u8 spare_thresh;
669 __u8 percent_used;
670 __u8 endu_grp_crit_warn_sumry;
671 __u8 rsvd7[25];
672 __u8 data_units_read[16];
673 __u8 data_units_written[16];
674 __u8 host_reads[16];
675 __u8 host_writes[16];
676 __u8 ctrl_busy_time[16];
677 __u8 power_cycles[16];
678 __u8 power_on_hours[16];
679 __u8 unsafe_shutdowns[16];
680 __u8 media_errors[16];
681 __u8 num_err_log_entries[16];
682 __le32 warning_temp_time;
683 __le32 critical_comp_time;
684 __le16 temp_sensor[8];
685 __le32 thm_temp1_trans_count;
686 __le32 thm_temp2_trans_count;
687 __le32 thm_temp1_total_time;
688 __le32 thm_temp2_total_time;
689 __u8 rsvd232[280];
690 };
691
692 struct nvme_fw_slot_info_log {
693 __u8 afi;
694 __u8 rsvd1[7];
695 __le64 frs[7];
696 __u8 rsvd64[448];
697 };
698
699 enum {
700 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
701 NVME_CMD_EFFECTS_LBCC = 1 << 1,
702 NVME_CMD_EFFECTS_NCC = 1 << 2,
703 NVME_CMD_EFFECTS_NIC = 1 << 3,
704 NVME_CMD_EFFECTS_CCC = 1 << 4,
705 NVME_CMD_EFFECTS_CSER_MASK = GENMASK(15, 14),
706 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
707 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
708 NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20),
709 };
710
711 struct nvme_effects_log {
712 __le32 acs[256];
713 __le32 iocs[256];
714 __u8 resv[2048];
715 };
716
717 enum nvme_ana_state {
718 NVME_ANA_OPTIMIZED = 0x01,
719 NVME_ANA_NONOPTIMIZED = 0x02,
720 NVME_ANA_INACCESSIBLE = 0x03,
721 NVME_ANA_PERSISTENT_LOSS = 0x04,
722 NVME_ANA_CHANGE = 0x0f,
723 };
724
725 struct nvme_ana_group_desc {
726 __le32 grpid;
727 __le32 nnsids;
728 __le64 chgcnt;
729 __u8 state;
730 __u8 rsvd17[15];
731 __le32 nsids[];
732 };
733
734 /* flag for the log specific field of the ANA log */
735 #define NVME_ANA_LOG_RGO (1 << 0)
736
737 struct nvme_ana_rsp_hdr {
738 __le64 chgcnt;
739 __le16 ngrps;
740 __le16 rsvd10[3];
741 };
742
743 struct nvme_zone_descriptor {
744 __u8 zt;
745 __u8 zs;
746 __u8 za;
747 __u8 rsvd3[5];
748 __le64 zcap;
749 __le64 zslba;
750 __le64 wp;
751 __u8 rsvd32[32];
752 };
753
754 enum {
755 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
756 };
757
758 struct nvme_zone_report {
759 __le64 nr_zones;
760 __u8 resv8[56];
761 struct nvme_zone_descriptor entries[];
762 };
763
764 enum {
765 NVME_SMART_CRIT_SPARE = 1 << 0,
766 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
767 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
768 NVME_SMART_CRIT_MEDIA = 1 << 3,
769 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
770 };
771
772 enum {
773 NVME_AER_ERROR = 0,
774 NVME_AER_SMART = 1,
775 NVME_AER_NOTICE = 2,
776 NVME_AER_CSS = 6,
777 NVME_AER_VS = 7,
778 };
779
780 enum {
781 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
782 };
783
784 enum {
785 NVME_AER_NOTICE_NS_CHANGED = 0x00,
786 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
787 NVME_AER_NOTICE_ANA = 0x03,
788 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
789 };
790
791 enum {
792 NVME_AEN_BIT_NS_ATTR = 8,
793 NVME_AEN_BIT_FW_ACT = 9,
794 NVME_AEN_BIT_ANA_CHANGE = 11,
795 NVME_AEN_BIT_DISC_CHANGE = 31,
796 };
797
798 enum {
799 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
800 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
801 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
802 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
803 };
804
805 struct nvme_lba_range_type {
806 __u8 type;
807 __u8 attributes;
808 __u8 rsvd2[14];
809 __le64 slba;
810 __le64 nlb;
811 __u8 guid[16];
812 __u8 rsvd48[16];
813 };
814
815 enum {
816 NVME_LBART_TYPE_FS = 0x01,
817 NVME_LBART_TYPE_RAID = 0x02,
818 NVME_LBART_TYPE_CACHE = 0x03,
819 NVME_LBART_TYPE_SWAP = 0x04,
820
821 NVME_LBART_ATTRIB_TEMP = 1 << 0,
822 NVME_LBART_ATTRIB_HIDE = 1 << 1,
823 };
824
825 enum nvme_pr_type {
826 NVME_PR_WRITE_EXCLUSIVE = 1,
827 NVME_PR_EXCLUSIVE_ACCESS = 2,
828 NVME_PR_WRITE_EXCLUSIVE_REG_ONLY = 3,
829 NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY = 4,
830 NVME_PR_WRITE_EXCLUSIVE_ALL_REGS = 5,
831 NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS = 6,
832 };
833
834 enum nvme_eds {
835 NVME_EXTENDED_DATA_STRUCT = 0x1,
836 };
837
838 struct nvme_registered_ctrl {
839 __le16 cntlid;
840 __u8 rcsts;
841 __u8 rsvd3[5];
842 __le64 hostid;
843 __le64 rkey;
844 };
845
846 struct nvme_reservation_status {
847 __le32 gen;
848 __u8 rtype;
849 __u8 regctl[2];
850 __u8 resv5[2];
851 __u8 ptpls;
852 __u8 resv10[14];
853 struct nvme_registered_ctrl regctl_ds[];
854 };
855
856 struct nvme_registered_ctrl_ext {
857 __le16 cntlid;
858 __u8 rcsts;
859 __u8 rsvd3[5];
860 __le64 rkey;
861 __u8 hostid[16];
862 __u8 rsvd32[32];
863 };
864
865 struct nvme_reservation_status_ext {
866 __le32 gen;
867 __u8 rtype;
868 __u8 regctl[2];
869 __u8 resv5[2];
870 __u8 ptpls;
871 __u8 resv10[14];
872 __u8 rsvd24[40];
873 struct nvme_registered_ctrl_ext regctl_eds[];
874 };
875
876 /* I/O commands */
877
878 enum nvme_opcode {
879 nvme_cmd_flush = 0x00,
880 nvme_cmd_write = 0x01,
881 nvme_cmd_read = 0x02,
882 nvme_cmd_write_uncor = 0x04,
883 nvme_cmd_compare = 0x05,
884 nvme_cmd_write_zeroes = 0x08,
885 nvme_cmd_dsm = 0x09,
886 nvme_cmd_verify = 0x0c,
887 nvme_cmd_resv_register = 0x0d,
888 nvme_cmd_resv_report = 0x0e,
889 nvme_cmd_resv_acquire = 0x11,
890 nvme_cmd_resv_release = 0x15,
891 nvme_cmd_zone_mgmt_send = 0x79,
892 nvme_cmd_zone_mgmt_recv = 0x7a,
893 nvme_cmd_zone_append = 0x7d,
894 nvme_cmd_vendor_start = 0x80,
895 };
896
897 #define nvme_opcode_name(opcode) { opcode, #opcode }
898 #define show_nvm_opcode_name(val) \
899 __print_symbolic(val, \
900 nvme_opcode_name(nvme_cmd_flush), \
901 nvme_opcode_name(nvme_cmd_write), \
902 nvme_opcode_name(nvme_cmd_read), \
903 nvme_opcode_name(nvme_cmd_write_uncor), \
904 nvme_opcode_name(nvme_cmd_compare), \
905 nvme_opcode_name(nvme_cmd_write_zeroes), \
906 nvme_opcode_name(nvme_cmd_dsm), \
907 nvme_opcode_name(nvme_cmd_verify), \
908 nvme_opcode_name(nvme_cmd_resv_register), \
909 nvme_opcode_name(nvme_cmd_resv_report), \
910 nvme_opcode_name(nvme_cmd_resv_acquire), \
911 nvme_opcode_name(nvme_cmd_resv_release), \
912 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
913 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
914 nvme_opcode_name(nvme_cmd_zone_append))
915
916
917
918 /*
919 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
920 *
921 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
922 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
923 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
924 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
925 * request subtype
926 */
927 enum {
928 NVME_SGL_FMT_ADDRESS = 0x00,
929 NVME_SGL_FMT_OFFSET = 0x01,
930 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
931 NVME_SGL_FMT_INVALIDATE = 0x0f,
932 };
933
934 /*
935 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
936 *
937 * For struct nvme_sgl_desc:
938 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
939 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
940 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
941 *
942 * For struct nvme_keyed_sgl_desc:
943 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
944 *
945 * Transport-specific SGL types:
946 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
947 */
948 enum {
949 NVME_SGL_FMT_DATA_DESC = 0x00,
950 NVME_SGL_FMT_SEG_DESC = 0x02,
951 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
952 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
953 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
954 };
955
956 struct nvme_sgl_desc {
957 __le64 addr;
958 __le32 length;
959 __u8 rsvd[3];
960 __u8 type;
961 };
962
963 struct nvme_keyed_sgl_desc {
964 __le64 addr;
965 __u8 length[3];
966 __u8 key[4];
967 __u8 type;
968 };
969
970 union nvme_data_ptr {
971 struct {
972 __le64 prp1;
973 __le64 prp2;
974 };
975 struct nvme_sgl_desc sgl;
976 struct nvme_keyed_sgl_desc ksgl;
977 };
978
979 /*
980 * Lowest two bits of our flags field (FUSE field in the spec):
981 *
982 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
983 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
984 *
985 * Highest two bits in our flags field (PSDT field in the spec):
986 *
987 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
988 * If used, MPTR contains addr of single physical buffer (byte aligned).
989 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
990 * If used, MPTR contains an address of an SGL segment containing
991 * exactly 1 SGL descriptor (qword aligned).
992 */
993 enum {
994 NVME_CMD_FUSE_FIRST = (1 << 0),
995 NVME_CMD_FUSE_SECOND = (1 << 1),
996
997 NVME_CMD_SGL_METABUF = (1 << 6),
998 NVME_CMD_SGL_METASEG = (1 << 7),
999 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
1000 };
1001
1002 struct nvme_common_command {
1003 __u8 opcode;
1004 __u8 flags;
1005 __u16 command_id;
1006 __le32 nsid;
1007 __le32 cdw2[2];
1008 __le64 metadata;
1009 union nvme_data_ptr dptr;
1010 struct_group(cdws,
1011 __le32 cdw10;
1012 __le32 cdw11;
1013 __le32 cdw12;
1014 __le32 cdw13;
1015 __le32 cdw14;
1016 __le32 cdw15;
1017 );
1018 };
1019
1020 struct nvme_rw_command {
1021 __u8 opcode;
1022 __u8 flags;
1023 __u16 command_id;
1024 __le32 nsid;
1025 __le32 cdw2;
1026 __le32 cdw3;
1027 __le64 metadata;
1028 union nvme_data_ptr dptr;
1029 __le64 slba;
1030 __le16 length;
1031 __le16 control;
1032 __le32 dsmgmt;
1033 __le32 reftag;
1034 __le16 lbat;
1035 __le16 lbatm;
1036 };
1037
1038 enum {
1039 NVME_RW_LR = 1 << 15,
1040 NVME_RW_FUA = 1 << 14,
1041 NVME_RW_APPEND_PIREMAP = 1 << 9,
1042 NVME_RW_DSM_FREQ_UNSPEC = 0,
1043 NVME_RW_DSM_FREQ_TYPICAL = 1,
1044 NVME_RW_DSM_FREQ_RARE = 2,
1045 NVME_RW_DSM_FREQ_READS = 3,
1046 NVME_RW_DSM_FREQ_WRITES = 4,
1047 NVME_RW_DSM_FREQ_RW = 5,
1048 NVME_RW_DSM_FREQ_ONCE = 6,
1049 NVME_RW_DSM_FREQ_PREFETCH = 7,
1050 NVME_RW_DSM_FREQ_TEMP = 8,
1051 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
1052 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
1053 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
1054 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
1055 NVME_RW_DSM_SEQ_REQ = 1 << 6,
1056 NVME_RW_DSM_COMPRESSED = 1 << 7,
1057 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
1058 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
1059 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
1060 NVME_RW_PRINFO_PRACT = 1 << 13,
1061 NVME_RW_DTYPE_STREAMS = 1 << 4,
1062 NVME_WZ_DEAC = 1 << 9,
1063 };
1064
1065 struct nvme_dsm_cmd {
1066 __u8 opcode;
1067 __u8 flags;
1068 __u16 command_id;
1069 __le32 nsid;
1070 __u64 rsvd2[2];
1071 union nvme_data_ptr dptr;
1072 __le32 nr;
1073 __le32 attributes;
1074 __u32 rsvd12[4];
1075 };
1076
1077 enum {
1078 NVME_DSMGMT_IDR = 1 << 0,
1079 NVME_DSMGMT_IDW = 1 << 1,
1080 NVME_DSMGMT_AD = 1 << 2,
1081 };
1082
1083 #define NVME_DSM_MAX_RANGES 256
1084
1085 struct nvme_dsm_range {
1086 __le32 cattr;
1087 __le32 nlb;
1088 __le64 slba;
1089 };
1090
1091 struct nvme_write_zeroes_cmd {
1092 __u8 opcode;
1093 __u8 flags;
1094 __u16 command_id;
1095 __le32 nsid;
1096 __u64 rsvd2;
1097 __le64 metadata;
1098 union nvme_data_ptr dptr;
1099 __le64 slba;
1100 __le16 length;
1101 __le16 control;
1102 __le32 dsmgmt;
1103 __le32 reftag;
1104 __le16 lbat;
1105 __le16 lbatm;
1106 };
1107
1108 enum nvme_zone_mgmt_action {
1109 NVME_ZONE_CLOSE = 0x1,
1110 NVME_ZONE_FINISH = 0x2,
1111 NVME_ZONE_OPEN = 0x3,
1112 NVME_ZONE_RESET = 0x4,
1113 NVME_ZONE_OFFLINE = 0x5,
1114 NVME_ZONE_SET_DESC_EXT = 0x10,
1115 };
1116
1117 struct nvme_zone_mgmt_send_cmd {
1118 __u8 opcode;
1119 __u8 flags;
1120 __u16 command_id;
1121 __le32 nsid;
1122 __le32 cdw2[2];
1123 __le64 metadata;
1124 union nvme_data_ptr dptr;
1125 __le64 slba;
1126 __le32 cdw12;
1127 __u8 zsa;
1128 __u8 select_all;
1129 __u8 rsvd13[2];
1130 __le32 cdw14[2];
1131 };
1132
1133 struct nvme_zone_mgmt_recv_cmd {
1134 __u8 opcode;
1135 __u8 flags;
1136 __u16 command_id;
1137 __le32 nsid;
1138 __le64 rsvd2[2];
1139 union nvme_data_ptr dptr;
1140 __le64 slba;
1141 __le32 numd;
1142 __u8 zra;
1143 __u8 zrasf;
1144 __u8 pr;
1145 __u8 rsvd13;
1146 __le32 cdw14[2];
1147 };
1148
1149 enum {
1150 NVME_ZRA_ZONE_REPORT = 0,
1151 NVME_ZRASF_ZONE_REPORT_ALL = 0,
1152 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1153 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1154 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1155 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1156 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1157 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1158 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
1159 NVME_REPORT_ZONE_PARTIAL = 1,
1160 };
1161
1162 /* Features */
1163
1164 enum {
1165 NVME_TEMP_THRESH_MASK = 0xffff,
1166 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1167 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1168 };
1169
1170 struct nvme_feat_auto_pst {
1171 __le64 entries[32];
1172 };
1173
1174 enum {
1175 NVME_HOST_MEM_ENABLE = (1 << 0),
1176 NVME_HOST_MEM_RETURN = (1 << 1),
1177 };
1178
1179 struct nvme_feat_host_behavior {
1180 __u8 acre;
1181 __u8 etdas;
1182 __u8 lbafee;
1183 __u8 resv1[509];
1184 };
1185
1186 enum {
1187 NVME_ENABLE_ACRE = 1,
1188 NVME_ENABLE_LBAFEE = 1,
1189 };
1190
1191 /* Admin commands */
1192
1193 enum nvme_admin_opcode {
1194 nvme_admin_delete_sq = 0x00,
1195 nvme_admin_create_sq = 0x01,
1196 nvme_admin_get_log_page = 0x02,
1197 nvme_admin_delete_cq = 0x04,
1198 nvme_admin_create_cq = 0x05,
1199 nvme_admin_identify = 0x06,
1200 nvme_admin_abort_cmd = 0x08,
1201 nvme_admin_set_features = 0x09,
1202 nvme_admin_get_features = 0x0a,
1203 nvme_admin_async_event = 0x0c,
1204 nvme_admin_ns_mgmt = 0x0d,
1205 nvme_admin_activate_fw = 0x10,
1206 nvme_admin_download_fw = 0x11,
1207 nvme_admin_dev_self_test = 0x14,
1208 nvme_admin_ns_attach = 0x15,
1209 nvme_admin_keep_alive = 0x18,
1210 nvme_admin_directive_send = 0x19,
1211 nvme_admin_directive_recv = 0x1a,
1212 nvme_admin_virtual_mgmt = 0x1c,
1213 nvme_admin_nvme_mi_send = 0x1d,
1214 nvme_admin_nvme_mi_recv = 0x1e,
1215 nvme_admin_dbbuf = 0x7C,
1216 nvme_admin_format_nvm = 0x80,
1217 nvme_admin_security_send = 0x81,
1218 nvme_admin_security_recv = 0x82,
1219 nvme_admin_sanitize_nvm = 0x84,
1220 nvme_admin_get_lba_status = 0x86,
1221 nvme_admin_vendor_start = 0xC0,
1222 };
1223
1224 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1225 #define show_admin_opcode_name(val) \
1226 __print_symbolic(val, \
1227 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1228 nvme_admin_opcode_name(nvme_admin_create_sq), \
1229 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1230 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1231 nvme_admin_opcode_name(nvme_admin_create_cq), \
1232 nvme_admin_opcode_name(nvme_admin_identify), \
1233 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1234 nvme_admin_opcode_name(nvme_admin_set_features), \
1235 nvme_admin_opcode_name(nvme_admin_get_features), \
1236 nvme_admin_opcode_name(nvme_admin_async_event), \
1237 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1238 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1239 nvme_admin_opcode_name(nvme_admin_download_fw), \
1240 nvme_admin_opcode_name(nvme_admin_dev_self_test), \
1241 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1242 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1243 nvme_admin_opcode_name(nvme_admin_directive_send), \
1244 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1245 nvme_admin_opcode_name(nvme_admin_virtual_mgmt), \
1246 nvme_admin_opcode_name(nvme_admin_nvme_mi_send), \
1247 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv), \
1248 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1249 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1250 nvme_admin_opcode_name(nvme_admin_security_send), \
1251 nvme_admin_opcode_name(nvme_admin_security_recv), \
1252 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1253 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1254
1255 enum {
1256 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1257 NVME_CQ_IRQ_ENABLED = (1 << 1),
1258 NVME_SQ_PRIO_URGENT = (0 << 1),
1259 NVME_SQ_PRIO_HIGH = (1 << 1),
1260 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1261 NVME_SQ_PRIO_LOW = (3 << 1),
1262 NVME_FEAT_ARBITRATION = 0x01,
1263 NVME_FEAT_POWER_MGMT = 0x02,
1264 NVME_FEAT_LBA_RANGE = 0x03,
1265 NVME_FEAT_TEMP_THRESH = 0x04,
1266 NVME_FEAT_ERR_RECOVERY = 0x05,
1267 NVME_FEAT_VOLATILE_WC = 0x06,
1268 NVME_FEAT_NUM_QUEUES = 0x07,
1269 NVME_FEAT_IRQ_COALESCE = 0x08,
1270 NVME_FEAT_IRQ_CONFIG = 0x09,
1271 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1272 NVME_FEAT_ASYNC_EVENT = 0x0b,
1273 NVME_FEAT_AUTO_PST = 0x0c,
1274 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1275 NVME_FEAT_TIMESTAMP = 0x0e,
1276 NVME_FEAT_KATO = 0x0f,
1277 NVME_FEAT_HCTM = 0x10,
1278 NVME_FEAT_NOPSC = 0x11,
1279 NVME_FEAT_RRL = 0x12,
1280 NVME_FEAT_PLM_CONFIG = 0x13,
1281 NVME_FEAT_PLM_WINDOW = 0x14,
1282 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1283 NVME_FEAT_SANITIZE = 0x17,
1284 NVME_FEAT_SW_PROGRESS = 0x80,
1285 NVME_FEAT_HOST_ID = 0x81,
1286 NVME_FEAT_RESV_MASK = 0x82,
1287 NVME_FEAT_RESV_PERSIST = 0x83,
1288 NVME_FEAT_WRITE_PROTECT = 0x84,
1289 NVME_FEAT_VENDOR_START = 0xC0,
1290 NVME_FEAT_VENDOR_END = 0xFF,
1291 NVME_LOG_SUPPORTED = 0x00,
1292 NVME_LOG_ERROR = 0x01,
1293 NVME_LOG_SMART = 0x02,
1294 NVME_LOG_FW_SLOT = 0x03,
1295 NVME_LOG_CHANGED_NS = 0x04,
1296 NVME_LOG_CMD_EFFECTS = 0x05,
1297 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1298 NVME_LOG_TELEMETRY_HOST = 0x07,
1299 NVME_LOG_TELEMETRY_CTRL = 0x08,
1300 NVME_LOG_ENDURANCE_GROUP = 0x09,
1301 NVME_LOG_ANA = 0x0c,
1302 NVME_LOG_FEATURES = 0x12,
1303 NVME_LOG_RMI = 0x16,
1304 NVME_LOG_DISC = 0x70,
1305 NVME_LOG_RESERVATION = 0x80,
1306 NVME_FWACT_REPL = (0 << 3),
1307 NVME_FWACT_REPL_ACTV = (1 << 3),
1308 NVME_FWACT_ACTV = (2 << 3),
1309 };
1310
1311 struct nvme_supported_log {
1312 __le32 lids[256];
1313 };
1314
1315 enum {
1316 NVME_LIDS_LSUPP = 1 << 0,
1317 };
1318
1319 struct nvme_supported_features_log {
1320 __le32 fis[256];
1321 };
1322
1323 enum {
1324 NVME_FIS_FSUPP = 1 << 0,
1325 NVME_FIS_NSCPE = 1 << 20,
1326 NVME_FIS_CSCPE = 1 << 21,
1327 };
1328
1329 /* NVMe Namespace Write Protect State */
1330 enum {
1331 NVME_NS_NO_WRITE_PROTECT = 0,
1332 NVME_NS_WRITE_PROTECT,
1333 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1334 NVME_NS_WRITE_PROTECT_PERMANENT,
1335 };
1336
1337 #define NVME_MAX_CHANGED_NAMESPACES 1024
1338
1339 struct nvme_identify {
1340 __u8 opcode;
1341 __u8 flags;
1342 __u16 command_id;
1343 __le32 nsid;
1344 __u64 rsvd2[2];
1345 union nvme_data_ptr dptr;
1346 __u8 cns;
1347 __u8 rsvd3;
1348 __le16 ctrlid;
1349 __le16 cnssid;
1350 __u8 rsvd11;
1351 __u8 csi;
1352 __u32 rsvd12[4];
1353 };
1354
1355 #define NVME_IDENTIFY_DATA_SIZE 4096
1356
1357 struct nvme_features {
1358 __u8 opcode;
1359 __u8 flags;
1360 __u16 command_id;
1361 __le32 nsid;
1362 __u64 rsvd2[2];
1363 union nvme_data_ptr dptr;
1364 __le32 fid;
1365 __le32 dword11;
1366 __le32 dword12;
1367 __le32 dword13;
1368 __le32 dword14;
1369 __le32 dword15;
1370 };
1371
1372 struct nvme_host_mem_buf_desc {
1373 __le64 addr;
1374 __le32 size;
1375 __u32 rsvd;
1376 };
1377
1378 struct nvme_create_cq {
1379 __u8 opcode;
1380 __u8 flags;
1381 __u16 command_id;
1382 __u32 rsvd1[5];
1383 __le64 prp1;
1384 __u64 rsvd8;
1385 __le16 cqid;
1386 __le16 qsize;
1387 __le16 cq_flags;
1388 __le16 irq_vector;
1389 __u32 rsvd12[4];
1390 };
1391
1392 struct nvme_create_sq {
1393 __u8 opcode;
1394 __u8 flags;
1395 __u16 command_id;
1396 __u32 rsvd1[5];
1397 __le64 prp1;
1398 __u64 rsvd8;
1399 __le16 sqid;
1400 __le16 qsize;
1401 __le16 sq_flags;
1402 __le16 cqid;
1403 __u32 rsvd12[4];
1404 };
1405
1406 struct nvme_delete_queue {
1407 __u8 opcode;
1408 __u8 flags;
1409 __u16 command_id;
1410 __u32 rsvd1[9];
1411 __le16 qid;
1412 __u16 rsvd10;
1413 __u32 rsvd11[5];
1414 };
1415
1416 struct nvme_abort_cmd {
1417 __u8 opcode;
1418 __u8 flags;
1419 __u16 command_id;
1420 __u32 rsvd1[9];
1421 __le16 sqid;
1422 __u16 cid;
1423 __u32 rsvd11[5];
1424 };
1425
1426 struct nvme_download_firmware {
1427 __u8 opcode;
1428 __u8 flags;
1429 __u16 command_id;
1430 __u32 rsvd1[5];
1431 union nvme_data_ptr dptr;
1432 __le32 numd;
1433 __le32 offset;
1434 __u32 rsvd12[4];
1435 };
1436
1437 struct nvme_format_cmd {
1438 __u8 opcode;
1439 __u8 flags;
1440 __u16 command_id;
1441 __le32 nsid;
1442 __u64 rsvd2[4];
1443 __le32 cdw10;
1444 __u32 rsvd11[5];
1445 };
1446
1447 struct nvme_get_log_page_command {
1448 __u8 opcode;
1449 __u8 flags;
1450 __u16 command_id;
1451 __le32 nsid;
1452 __u64 rsvd2[2];
1453 union nvme_data_ptr dptr;
1454 __u8 lid;
1455 __u8 lsp; /* upper 4 bits reserved */
1456 __le16 numdl;
1457 __le16 numdu;
1458 __le16 lsi;
1459 union {
1460 struct {
1461 __le32 lpol;
1462 __le32 lpou;
1463 };
1464 __le64 lpo;
1465 };
1466 __u8 rsvd14[3];
1467 __u8 csi;
1468 __u32 rsvd15;
1469 };
1470
1471 struct nvme_directive_cmd {
1472 __u8 opcode;
1473 __u8 flags;
1474 __u16 command_id;
1475 __le32 nsid;
1476 __u64 rsvd2[2];
1477 union nvme_data_ptr dptr;
1478 __le32 numd;
1479 __u8 doper;
1480 __u8 dtype;
1481 __le16 dspec;
1482 __u8 endir;
1483 __u8 tdtype;
1484 __u16 rsvd15;
1485
1486 __u32 rsvd16[3];
1487 };
1488
1489 /*
1490 * Fabrics subcommands.
1491 */
1492 enum nvmf_fabrics_opcode {
1493 nvme_fabrics_command = 0x7f,
1494 };
1495
1496 enum nvmf_capsule_command {
1497 nvme_fabrics_type_property_set = 0x00,
1498 nvme_fabrics_type_connect = 0x01,
1499 nvme_fabrics_type_property_get = 0x04,
1500 nvme_fabrics_type_auth_send = 0x05,
1501 nvme_fabrics_type_auth_receive = 0x06,
1502 };
1503
1504 #define nvme_fabrics_type_name(type) { type, #type }
1505 #define show_fabrics_type_name(type) \
1506 __print_symbolic(type, \
1507 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1508 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1509 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1510 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1511 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1512
1513 /*
1514 * If not fabrics command, fctype will be ignored.
1515 */
1516 #define show_opcode_name(qid, opcode, fctype) \
1517 ((opcode) == nvme_fabrics_command ? \
1518 show_fabrics_type_name(fctype) : \
1519 ((qid) ? \
1520 show_nvm_opcode_name(opcode) : \
1521 show_admin_opcode_name(opcode)))
1522
1523 struct nvmf_common_command {
1524 __u8 opcode;
1525 __u8 resv1;
1526 __u16 command_id;
1527 __u8 fctype;
1528 __u8 resv2[35];
1529 __u8 ts[24];
1530 };
1531
1532 /*
1533 * The legal cntlid range a NVMe Target will provide.
1534 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1535 * Devices based on earlier specs did not have the subsystem concept;
1536 * therefore, those devices had their cntlid value set to 0 as a result.
1537 */
1538 #define NVME_CNTLID_MIN 1
1539 #define NVME_CNTLID_MAX 0xffef
1540 #define NVME_CNTLID_DYNAMIC 0xffff
1541
1542 #define MAX_DISC_LOGS 255
1543
1544 /* Discovery log page entry flags (EFLAGS): */
1545 enum {
1546 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1547 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1548 };
1549
1550 /* Discovery log page entry */
1551 struct nvmf_disc_rsp_page_entry {
1552 __u8 trtype;
1553 __u8 adrfam;
1554 __u8 subtype;
1555 __u8 treq;
1556 __le16 portid;
1557 __le16 cntlid;
1558 __le16 asqsz;
1559 __le16 eflags;
1560 __u8 resv10[20];
1561 char trsvcid[NVMF_TRSVCID_SIZE];
1562 __u8 resv64[192];
1563 char subnqn[NVMF_NQN_FIELD_LEN];
1564 char traddr[NVMF_TRADDR_SIZE];
1565 union tsas {
1566 char common[NVMF_TSAS_SIZE];
1567 struct rdma {
1568 __u8 qptype;
1569 __u8 prtype;
1570 __u8 cms;
1571 __u8 resv3[5];
1572 __u16 pkey;
1573 __u8 resv10[246];
1574 } rdma;
1575 struct tcp {
1576 __u8 sectype;
1577 } tcp;
1578 } tsas;
1579 };
1580
1581 /* Discovery log page header */
1582 struct nvmf_disc_rsp_page_hdr {
1583 __le64 genctr;
1584 __le64 numrec;
1585 __le16 recfmt;
1586 __u8 resv14[1006];
1587 struct nvmf_disc_rsp_page_entry entries[];
1588 };
1589
1590 enum {
1591 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1592 };
1593
1594 struct nvmf_connect_command {
1595 __u8 opcode;
1596 __u8 resv1;
1597 __u16 command_id;
1598 __u8 fctype;
1599 __u8 resv2[19];
1600 union nvme_data_ptr dptr;
1601 __le16 recfmt;
1602 __le16 qid;
1603 __le16 sqsize;
1604 __u8 cattr;
1605 __u8 resv3;
1606 __le32 kato;
1607 __u8 resv4[12];
1608 };
1609
1610 enum {
1611 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1612 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
1613 };
1614
1615 struct nvmf_connect_data {
1616 uuid_t hostid;
1617 __le16 cntlid;
1618 char resv4[238];
1619 char subsysnqn[NVMF_NQN_FIELD_LEN];
1620 char hostnqn[NVMF_NQN_FIELD_LEN];
1621 char resv5[256];
1622 };
1623
1624 struct nvmf_property_set_command {
1625 __u8 opcode;
1626 __u8 resv1;
1627 __u16 command_id;
1628 __u8 fctype;
1629 __u8 resv2[35];
1630 __u8 attrib;
1631 __u8 resv3[3];
1632 __le32 offset;
1633 __le64 value;
1634 __u8 resv4[8];
1635 };
1636
1637 struct nvmf_property_get_command {
1638 __u8 opcode;
1639 __u8 resv1;
1640 __u16 command_id;
1641 __u8 fctype;
1642 __u8 resv2[35];
1643 __u8 attrib;
1644 __u8 resv3[3];
1645 __le32 offset;
1646 __u8 resv4[16];
1647 };
1648
1649 struct nvmf_auth_common_command {
1650 __u8 opcode;
1651 __u8 resv1;
1652 __u16 command_id;
1653 __u8 fctype;
1654 __u8 resv2[19];
1655 union nvme_data_ptr dptr;
1656 __u8 resv3;
1657 __u8 spsp0;
1658 __u8 spsp1;
1659 __u8 secp;
1660 __le32 al_tl;
1661 __u8 resv4[16];
1662 };
1663
1664 struct nvmf_auth_send_command {
1665 __u8 opcode;
1666 __u8 resv1;
1667 __u16 command_id;
1668 __u8 fctype;
1669 __u8 resv2[19];
1670 union nvme_data_ptr dptr;
1671 __u8 resv3;
1672 __u8 spsp0;
1673 __u8 spsp1;
1674 __u8 secp;
1675 __le32 tl;
1676 __u8 resv4[16];
1677 };
1678
1679 struct nvmf_auth_receive_command {
1680 __u8 opcode;
1681 __u8 resv1;
1682 __u16 command_id;
1683 __u8 fctype;
1684 __u8 resv2[19];
1685 union nvme_data_ptr dptr;
1686 __u8 resv3;
1687 __u8 spsp0;
1688 __u8 spsp1;
1689 __u8 secp;
1690 __le32 al;
1691 __u8 resv4[16];
1692 };
1693
1694 /* Value for secp */
1695 enum {
1696 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1697 };
1698
1699 /* Defined value for auth_type */
1700 enum {
1701 NVME_AUTH_COMMON_MESSAGES = 0x00,
1702 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1703 };
1704
1705 /* Defined messages for auth_id */
1706 enum {
1707 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1708 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1709 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1710 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1711 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1712 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1713 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1714 };
1715
1716 struct nvmf_auth_dhchap_protocol_descriptor {
1717 __u8 authid;
1718 __u8 rsvd;
1719 __u8 halen;
1720 __u8 dhlen;
1721 __u8 idlist[60];
1722 };
1723
1724 enum {
1725 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1726 };
1727
1728 /* Defined hash functions for DH-HMAC-CHAP authentication */
1729 enum {
1730 NVME_AUTH_HASH_SHA256 = 0x01,
1731 NVME_AUTH_HASH_SHA384 = 0x02,
1732 NVME_AUTH_HASH_SHA512 = 0x03,
1733 NVME_AUTH_HASH_INVALID = 0xff,
1734 };
1735
1736 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1737 enum {
1738 NVME_AUTH_DHGROUP_NULL = 0x00,
1739 NVME_AUTH_DHGROUP_2048 = 0x01,
1740 NVME_AUTH_DHGROUP_3072 = 0x02,
1741 NVME_AUTH_DHGROUP_4096 = 0x03,
1742 NVME_AUTH_DHGROUP_6144 = 0x04,
1743 NVME_AUTH_DHGROUP_8192 = 0x05,
1744 NVME_AUTH_DHGROUP_INVALID = 0xff,
1745 };
1746
1747 union nvmf_auth_protocol {
1748 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1749 };
1750
1751 struct nvmf_auth_dhchap_negotiate_data {
1752 __u8 auth_type;
1753 __u8 auth_id;
1754 __le16 rsvd;
1755 __le16 t_id;
1756 __u8 sc_c;
1757 __u8 napd;
1758 union nvmf_auth_protocol auth_protocol[];
1759 };
1760
1761 struct nvmf_auth_dhchap_challenge_data {
1762 __u8 auth_type;
1763 __u8 auth_id;
1764 __u16 rsvd1;
1765 __le16 t_id;
1766 __u8 hl;
1767 __u8 rsvd2;
1768 __u8 hashid;
1769 __u8 dhgid;
1770 __le16 dhvlen;
1771 __le32 seqnum;
1772 /* 'hl' bytes of challenge value */
1773 __u8 cval[];
1774 /* followed by 'dhvlen' bytes of DH value */
1775 };
1776
1777 struct nvmf_auth_dhchap_reply_data {
1778 __u8 auth_type;
1779 __u8 auth_id;
1780 __le16 rsvd1;
1781 __le16 t_id;
1782 __u8 hl;
1783 __u8 rsvd2;
1784 __u8 cvalid;
1785 __u8 rsvd3;
1786 __le16 dhvlen;
1787 __le32 seqnum;
1788 /* 'hl' bytes of response data */
1789 __u8 rval[];
1790 /* followed by 'hl' bytes of Challenge value */
1791 /* followed by 'dhvlen' bytes of DH value */
1792 };
1793
1794 enum {
1795 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1796 };
1797
1798 struct nvmf_auth_dhchap_success1_data {
1799 __u8 auth_type;
1800 __u8 auth_id;
1801 __le16 rsvd1;
1802 __le16 t_id;
1803 __u8 hl;
1804 __u8 rsvd2;
1805 __u8 rvalid;
1806 __u8 rsvd3[7];
1807 /* 'hl' bytes of response value */
1808 __u8 rval[];
1809 };
1810
1811 struct nvmf_auth_dhchap_success2_data {
1812 __u8 auth_type;
1813 __u8 auth_id;
1814 __le16 rsvd1;
1815 __le16 t_id;
1816 __u8 rsvd2[10];
1817 };
1818
1819 struct nvmf_auth_dhchap_failure_data {
1820 __u8 auth_type;
1821 __u8 auth_id;
1822 __le16 rsvd1;
1823 __le16 t_id;
1824 __u8 rescode;
1825 __u8 rescode_exp;
1826 };
1827
1828 enum {
1829 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1830 };
1831
1832 enum {
1833 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1834 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1835 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1836 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1837 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1838 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1839 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1840 };
1841
1842
1843 struct nvme_dbbuf {
1844 __u8 opcode;
1845 __u8 flags;
1846 __u16 command_id;
1847 __u32 rsvd1[5];
1848 __le64 prp1;
1849 __le64 prp2;
1850 __u32 rsvd12[6];
1851 };
1852
1853 struct streams_directive_params {
1854 __le16 msl;
1855 __le16 nssa;
1856 __le16 nsso;
1857 __u8 rsvd[10];
1858 __le32 sws;
1859 __le16 sgs;
1860 __le16 nsa;
1861 __le16 nso;
1862 __u8 rsvd2[6];
1863 };
1864
1865 struct nvme_command {
1866 union {
1867 struct nvme_common_command common;
1868 struct nvme_rw_command rw;
1869 struct nvme_identify identify;
1870 struct nvme_features features;
1871 struct nvme_create_cq create_cq;
1872 struct nvme_create_sq create_sq;
1873 struct nvme_delete_queue delete_queue;
1874 struct nvme_download_firmware dlfw;
1875 struct nvme_format_cmd format;
1876 struct nvme_dsm_cmd dsm;
1877 struct nvme_write_zeroes_cmd write_zeroes;
1878 struct nvme_zone_mgmt_send_cmd zms;
1879 struct nvme_zone_mgmt_recv_cmd zmr;
1880 struct nvme_abort_cmd abort;
1881 struct nvme_get_log_page_command get_log_page;
1882 struct nvmf_common_command fabrics;
1883 struct nvmf_connect_command connect;
1884 struct nvmf_property_set_command prop_set;
1885 struct nvmf_property_get_command prop_get;
1886 struct nvmf_auth_common_command auth_common;
1887 struct nvmf_auth_send_command auth_send;
1888 struct nvmf_auth_receive_command auth_receive;
1889 struct nvme_dbbuf dbbuf;
1890 struct nvme_directive_cmd directive;
1891 };
1892 };
1893
nvme_is_fabrics(const struct nvme_command * cmd)1894 static inline bool nvme_is_fabrics(const struct nvme_command *cmd)
1895 {
1896 return cmd->common.opcode == nvme_fabrics_command;
1897 }
1898
1899 struct nvme_error_slot {
1900 __le64 error_count;
1901 __le16 sqid;
1902 __le16 cmdid;
1903 __le16 status_field;
1904 __le16 param_error_location;
1905 __le64 lba;
1906 __le32 nsid;
1907 __u8 vs;
1908 __u8 resv[3];
1909 __le64 cs;
1910 __u8 resv2[24];
1911 };
1912
nvme_is_write(const struct nvme_command * cmd)1913 static inline bool nvme_is_write(const struct nvme_command *cmd)
1914 {
1915 /*
1916 * What a mess...
1917 *
1918 * Why can't we simply have a Fabrics In and Fabrics out command?
1919 */
1920 if (unlikely(nvme_is_fabrics(cmd)))
1921 return cmd->fabrics.fctype & 1;
1922 return cmd->common.opcode & 1;
1923 }
1924
1925 enum {
1926 /*
1927 * Generic Command Status:
1928 */
1929 NVME_SCT_GENERIC = 0x0,
1930 NVME_SC_SUCCESS = 0x0,
1931 NVME_SC_INVALID_OPCODE = 0x1,
1932 NVME_SC_INVALID_FIELD = 0x2,
1933 NVME_SC_CMDID_CONFLICT = 0x3,
1934 NVME_SC_DATA_XFER_ERROR = 0x4,
1935 NVME_SC_POWER_LOSS = 0x5,
1936 NVME_SC_INTERNAL = 0x6,
1937 NVME_SC_ABORT_REQ = 0x7,
1938 NVME_SC_ABORT_QUEUE = 0x8,
1939 NVME_SC_FUSED_FAIL = 0x9,
1940 NVME_SC_FUSED_MISSING = 0xa,
1941 NVME_SC_INVALID_NS = 0xb,
1942 NVME_SC_CMD_SEQ_ERROR = 0xc,
1943 NVME_SC_SGL_INVALID_LAST = 0xd,
1944 NVME_SC_SGL_INVALID_COUNT = 0xe,
1945 NVME_SC_SGL_INVALID_DATA = 0xf,
1946 NVME_SC_SGL_INVALID_METADATA = 0x10,
1947 NVME_SC_SGL_INVALID_TYPE = 0x11,
1948 NVME_SC_CMB_INVALID_USE = 0x12,
1949 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1950 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1951 NVME_SC_OP_DENIED = 0x15,
1952 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1953 NVME_SC_RESERVED = 0x17,
1954 NVME_SC_HOST_ID_INCONSIST = 0x18,
1955 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1956 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1957 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1958 NVME_SC_SANITIZE_FAILED = 0x1C,
1959 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1960 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1961 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1962 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1963 NVME_SC_CMD_INTERRUPTED = 0x21,
1964 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1965 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1966 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1967
1968 NVME_SC_LBA_RANGE = 0x80,
1969 NVME_SC_CAP_EXCEEDED = 0x81,
1970 NVME_SC_NS_NOT_READY = 0x82,
1971 NVME_SC_RESERVATION_CONFLICT = 0x83,
1972 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1973
1974 /*
1975 * Command Specific Status:
1976 */
1977 NVME_SCT_COMMAND_SPECIFIC = 0x100,
1978 NVME_SC_CQ_INVALID = 0x100,
1979 NVME_SC_QID_INVALID = 0x101,
1980 NVME_SC_QUEUE_SIZE = 0x102,
1981 NVME_SC_ABORT_LIMIT = 0x103,
1982 NVME_SC_ABORT_MISSING = 0x104,
1983 NVME_SC_ASYNC_LIMIT = 0x105,
1984 NVME_SC_FIRMWARE_SLOT = 0x106,
1985 NVME_SC_FIRMWARE_IMAGE = 0x107,
1986 NVME_SC_INVALID_VECTOR = 0x108,
1987 NVME_SC_INVALID_LOG_PAGE = 0x109,
1988 NVME_SC_INVALID_FORMAT = 0x10a,
1989 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1990 NVME_SC_INVALID_QUEUE = 0x10c,
1991 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1992 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1993 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1994 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1995 NVME_SC_FW_NEEDS_RESET = 0x111,
1996 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1997 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1998 NVME_SC_OVERLAPPING_RANGE = 0x114,
1999 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
2000 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
2001 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
2002 NVME_SC_NS_IS_PRIVATE = 0x119,
2003 NVME_SC_NS_NOT_ATTACHED = 0x11a,
2004 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
2005 NVME_SC_CTRL_LIST_INVALID = 0x11c,
2006 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
2007 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
2008 NVME_SC_CTRL_ID_INVALID = 0x11f,
2009 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
2010 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
2011 NVME_SC_RES_ID_INVALID = 0x122,
2012 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
2013 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
2014 NVME_SC_ANA_ATTACH_FAILED = 0x125,
2015
2016 /*
2017 * I/O Command Set Specific - NVM commands:
2018 */
2019 NVME_SC_BAD_ATTRIBUTES = 0x180,
2020 NVME_SC_INVALID_PI = 0x181,
2021 NVME_SC_READ_ONLY = 0x182,
2022 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
2023
2024 /*
2025 * I/O Command Set Specific - Fabrics commands:
2026 */
2027 NVME_SC_CONNECT_FORMAT = 0x180,
2028 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
2029 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
2030 NVME_SC_CONNECT_RESTART_DISC = 0x183,
2031 NVME_SC_CONNECT_INVALID_HOST = 0x184,
2032
2033 NVME_SC_DISCOVERY_RESTART = 0x190,
2034 NVME_SC_AUTH_REQUIRED = 0x191,
2035
2036 /*
2037 * I/O Command Set Specific - Zoned commands:
2038 */
2039 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
2040 NVME_SC_ZONE_FULL = 0x1b9,
2041 NVME_SC_ZONE_READ_ONLY = 0x1ba,
2042 NVME_SC_ZONE_OFFLINE = 0x1bb,
2043 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
2044 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
2045 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
2046 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
2047
2048 /*
2049 * Media and Data Integrity Errors:
2050 */
2051 NVME_SCT_MEDIA_ERROR = 0x200,
2052 NVME_SC_WRITE_FAULT = 0x280,
2053 NVME_SC_READ_ERROR = 0x281,
2054 NVME_SC_GUARD_CHECK = 0x282,
2055 NVME_SC_APPTAG_CHECK = 0x283,
2056 NVME_SC_REFTAG_CHECK = 0x284,
2057 NVME_SC_COMPARE_FAILED = 0x285,
2058 NVME_SC_ACCESS_DENIED = 0x286,
2059 NVME_SC_UNWRITTEN_BLOCK = 0x287,
2060
2061 /*
2062 * Path-related Errors:
2063 */
2064 NVME_SCT_PATH = 0x300,
2065 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
2066 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
2067 NVME_SC_ANA_INACCESSIBLE = 0x302,
2068 NVME_SC_ANA_TRANSITION = 0x303,
2069 NVME_SC_CTRL_PATH_ERROR = 0x360,
2070 NVME_SC_HOST_PATH_ERROR = 0x370,
2071 NVME_SC_HOST_ABORTED_CMD = 0x371,
2072
2073 NVME_SC_MASK = 0x00ff, /* Status Code */
2074 NVME_SCT_MASK = 0x0700, /* Status Code Type */
2075 NVME_SCT_SC_MASK = NVME_SCT_MASK | NVME_SC_MASK,
2076
2077 NVME_STATUS_CRD = 0x1800, /* Command Retry Delayed */
2078 NVME_STATUS_MORE = 0x2000,
2079 NVME_STATUS_DNR = 0x4000, /* Do Not Retry */
2080 };
2081
2082 #define NVME_SCT(status) ((status) >> 8 & 7)
2083
2084 struct nvme_completion {
2085 /*
2086 * Used by Admin and Fabrics commands to return data:
2087 */
2088 union nvme_result {
2089 __le16 u16;
2090 __le32 u32;
2091 __le64 u64;
2092 } result;
2093 __le16 sq_head; /* how much of this queue may be reclaimed */
2094 __le16 sq_id; /* submission queue that generated this entry */
2095 __u16 command_id; /* of the command which completed */
2096 __le16 status; /* did the command fail, and if so, why? */
2097 };
2098
2099 #define NVME_VS(major, minor, tertiary) \
2100 (((major) << 16) | ((minor) << 8) | (tertiary))
2101
2102 #define NVME_MAJOR(ver) ((ver) >> 16)
2103 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
2104 #define NVME_TERTIARY(ver) ((ver) & 0xff)
2105
2106 enum {
2107 NVME_AEN_RESV_LOG_PAGE_AVALIABLE = 0x00,
2108 };
2109
2110 enum {
2111 NVME_PR_LOG_EMPTY_LOG_PAGE = 0x00,
2112 NVME_PR_LOG_REGISTRATION_PREEMPTED = 0x01,
2113 NVME_PR_LOG_RESERVATION_RELEASED = 0x02,
2114 NVME_PR_LOG_RESERVATOIN_PREEMPTED = 0x03,
2115 };
2116
2117 enum {
2118 NVME_PR_NOTIFY_BIT_REG_PREEMPTED = 1,
2119 NVME_PR_NOTIFY_BIT_RESV_RELEASED = 2,
2120 NVME_PR_NOTIFY_BIT_RESV_PREEMPTED = 3,
2121 };
2122
2123 struct nvme_pr_log {
2124 __le64 count;
2125 __u8 type;
2126 __u8 nr_pages;
2127 __u8 rsvd1[2];
2128 __le32 nsid;
2129 __u8 rsvd2[48];
2130 };
2131
2132 struct nvmet_pr_register_data {
2133 __le64 crkey;
2134 __le64 nrkey;
2135 };
2136
2137 struct nvmet_pr_acquire_data {
2138 __le64 crkey;
2139 __le64 prkey;
2140 };
2141
2142 struct nvmet_pr_release_data {
2143 __le64 crkey;
2144 };
2145
2146 enum nvme_pr_capabilities {
2147 NVME_PR_SUPPORT_PTPL = 1,
2148 NVME_PR_SUPPORT_WRITE_EXCLUSIVE = 1 << 1,
2149 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS = 1 << 2,
2150 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_REG_ONLY = 1 << 3,
2151 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_REG_ONLY = 1 << 4,
2152 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_ALL_REGS = 1 << 5,
2153 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_ALL_REGS = 1 << 6,
2154 NVME_PR_SUPPORT_IEKEY_VER_1_3_DEF = 1 << 7,
2155 };
2156
2157 enum nvme_pr_register_action {
2158 NVME_PR_REGISTER_ACT_REG = 0,
2159 NVME_PR_REGISTER_ACT_UNREG = 1,
2160 NVME_PR_REGISTER_ACT_REPLACE = 1 << 1,
2161 };
2162
2163 enum nvme_pr_acquire_action {
2164 NVME_PR_ACQUIRE_ACT_ACQUIRE = 0,
2165 NVME_PR_ACQUIRE_ACT_PREEMPT = 1,
2166 NVME_PR_ACQUIRE_ACT_PREEMPT_AND_ABORT = 1 << 1,
2167 };
2168
2169 enum nvme_pr_release_action {
2170 NVME_PR_RELEASE_ACT_RELEASE = 0,
2171 NVME_PR_RELEASE_ACT_CLEAR = 1,
2172 };
2173
2174 enum nvme_pr_change_ptpl {
2175 NVME_PR_CPTPL_NO_CHANGE = 0,
2176 NVME_PR_CPTPL_RESV = 1 << 30,
2177 NVME_PR_CPTPL_CLEARED = 2 << 30,
2178 NVME_PR_CPTPL_PERSIST = 3 << 30,
2179 };
2180
2181 #define NVME_PR_IGNORE_KEY (1 << 3)
2182
2183 #endif /* _LINUX_NVME_H */
2184